./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.09.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 4fc63b2a Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24deb2f0-8b11-493f-9105-b37163521d7a/bin/uautomizer-verify-4GaUIPS5ZU/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24deb2f0-8b11-493f-9105-b37163521d7a/bin/uautomizer-verify-4GaUIPS5ZU/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24deb2f0-8b11-493f-9105-b37163521d7a/bin/uautomizer-verify-4GaUIPS5ZU/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24deb2f0-8b11-493f-9105-b37163521d7a/bin/uautomizer-verify-4GaUIPS5ZU/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.09.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24deb2f0-8b11-493f-9105-b37163521d7a/bin/uautomizer-verify-4GaUIPS5ZU/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24deb2f0-8b11-493f-9105-b37163521d7a/bin/uautomizer-verify-4GaUIPS5ZU --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 3945fa4b58cef50cb4b44b435a699812e99a1f6375664d08551274c6b50bee45 --- Real Ultimate output --- This is Ultimate 0.2.5-dev-4fc63b2 [2024-10-31 21:55:59,335 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-10-31 21:55:59,404 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24deb2f0-8b11-493f-9105-b37163521d7a/bin/uautomizer-verify-4GaUIPS5ZU/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-10-31 21:55:59,409 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-10-31 21:55:59,410 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-10-31 21:55:59,434 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-10-31 21:55:59,435 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-10-31 21:55:59,436 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-10-31 21:55:59,436 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-10-31 21:55:59,437 INFO L153 SettingsManager]: * Use memory slicer=true [2024-10-31 21:55:59,438 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-10-31 21:55:59,438 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-10-31 21:55:59,438 INFO L153 SettingsManager]: * Use SBE=true [2024-10-31 21:55:59,439 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-10-31 21:55:59,439 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-10-31 21:55:59,440 INFO L153 SettingsManager]: * Use old map elimination=false [2024-10-31 21:55:59,440 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-10-31 21:55:59,441 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-10-31 21:55:59,441 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-10-31 21:55:59,441 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-10-31 21:55:59,442 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-10-31 21:55:59,442 INFO L153 SettingsManager]: * sizeof long=4 [2024-10-31 21:55:59,443 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-10-31 21:55:59,443 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-10-31 21:55:59,444 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-10-31 21:55:59,444 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-10-31 21:55:59,444 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-10-31 21:55:59,445 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-10-31 21:55:59,445 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-10-31 21:55:59,445 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-10-31 21:55:59,446 INFO L153 SettingsManager]: * sizeof long double=12 [2024-10-31 21:55:59,446 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-10-31 21:55:59,446 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-10-31 21:55:59,447 INFO L153 SettingsManager]: * Use constant arrays=true [2024-10-31 21:55:59,447 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-10-31 21:55:59,448 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-10-31 21:55:59,448 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-10-31 21:55:59,448 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-10-31 21:55:59,449 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-10-31 21:55:59,449 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24deb2f0-8b11-493f-9105-b37163521d7a/bin/uautomizer-verify-4GaUIPS5ZU/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24deb2f0-8b11-493f-9105-b37163521d7a/bin/uautomizer-verify-4GaUIPS5ZU Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 3945fa4b58cef50cb4b44b435a699812e99a1f6375664d08551274c6b50bee45 [2024-10-31 21:55:59,723 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-10-31 21:55:59,747 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-10-31 21:55:59,751 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-10-31 21:55:59,752 INFO L270 PluginConnector]: Initializing CDTParser... [2024-10-31 21:55:59,753 INFO L274 PluginConnector]: CDTParser initialized [2024-10-31 21:55:59,754 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24deb2f0-8b11-493f-9105-b37163521d7a/bin/uautomizer-verify-4GaUIPS5ZU/../../sv-benchmarks/c/systemc/transmitter.09.cil.c Unable to find full path for "g++" [2024-10-31 21:56:01,971 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-10-31 21:56:02,290 INFO L384 CDTParser]: Found 1 translation units. [2024-10-31 21:56:02,291 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24deb2f0-8b11-493f-9105-b37163521d7a/sv-benchmarks/c/systemc/transmitter.09.cil.c [2024-10-31 21:56:02,317 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24deb2f0-8b11-493f-9105-b37163521d7a/bin/uautomizer-verify-4GaUIPS5ZU/data/1114bca1c/06b1ff972c954fa69b48abde46f97ccf/FLAG68506e6cc [2024-10-31 21:56:02,340 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24deb2f0-8b11-493f-9105-b37163521d7a/bin/uautomizer-verify-4GaUIPS5ZU/data/1114bca1c/06b1ff972c954fa69b48abde46f97ccf [2024-10-31 21:56:02,344 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-10-31 21:56:02,345 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-10-31 21:56:02,347 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-10-31 21:56:02,347 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-10-31 21:56:02,353 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-10-31 21:56:02,354 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 31.10 09:56:02" (1/1) ... [2024-10-31 21:56:02,355 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@4d08bcf4 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 09:56:02, skipping insertion in model container [2024-10-31 21:56:02,355 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 31.10 09:56:02" (1/1) ... [2024-10-31 21:56:02,410 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-10-31 21:56:02,887 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-10-31 21:56:02,906 INFO L200 MainTranslator]: Completed pre-run [2024-10-31 21:56:02,987 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-10-31 21:56:03,025 INFO L204 MainTranslator]: Completed translation [2024-10-31 21:56:03,025 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 09:56:03 WrapperNode [2024-10-31 21:56:03,026 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-10-31 21:56:03,027 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-10-31 21:56:03,027 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-10-31 21:56:03,027 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-10-31 21:56:03,036 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 09:56:03" (1/1) ... [2024-10-31 21:56:03,052 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 09:56:03" (1/1) ... [2024-10-31 21:56:03,207 INFO L138 Inliner]: procedures = 46, calls = 58, calls flagged for inlining = 53, calls inlined = 171, statements flattened = 2601 [2024-10-31 21:56:03,208 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-10-31 21:56:03,209 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-10-31 21:56:03,209 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-10-31 21:56:03,209 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-10-31 21:56:03,225 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 09:56:03" (1/1) ... [2024-10-31 21:56:03,225 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 09:56:03" (1/1) ... [2024-10-31 21:56:03,239 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 09:56:03" (1/1) ... [2024-10-31 21:56:03,289 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-10-31 21:56:03,289 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 09:56:03" (1/1) ... [2024-10-31 21:56:03,293 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 09:56:03" (1/1) ... [2024-10-31 21:56:03,344 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 09:56:03" (1/1) ... [2024-10-31 21:56:03,377 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 09:56:03" (1/1) ... [2024-10-31 21:56:03,386 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 09:56:03" (1/1) ... [2024-10-31 21:56:03,399 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 09:56:03" (1/1) ... [2024-10-31 21:56:03,463 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-10-31 21:56:03,464 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-10-31 21:56:03,465 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-10-31 21:56:03,469 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-10-31 21:56:03,470 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 09:56:03" (1/1) ... [2024-10-31 21:56:03,485 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-10-31 21:56:03,497 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24deb2f0-8b11-493f-9105-b37163521d7a/bin/uautomizer-verify-4GaUIPS5ZU/z3 [2024-10-31 21:56:03,511 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24deb2f0-8b11-493f-9105-b37163521d7a/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-10-31 21:56:03,514 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24deb2f0-8b11-493f-9105-b37163521d7a/bin/uautomizer-verify-4GaUIPS5ZU/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-10-31 21:56:03,578 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-10-31 21:56:03,579 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-10-31 21:56:03,579 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-10-31 21:56:03,579 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-10-31 21:56:03,729 INFO L238 CfgBuilder]: Building ICFG [2024-10-31 21:56:03,731 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-10-31 21:56:05,981 INFO L? ?]: Removed 524 outVars from TransFormulas that were not future-live. [2024-10-31 21:56:05,981 INFO L287 CfgBuilder]: Performing block encoding [2024-10-31 21:56:06,028 INFO L311 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-10-31 21:56:06,028 INFO L316 CfgBuilder]: Removed 13 assume(true) statements. [2024-10-31 21:56:06,032 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 31.10 09:56:06 BoogieIcfgContainer [2024-10-31 21:56:06,032 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-10-31 21:56:06,034 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-10-31 21:56:06,035 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-10-31 21:56:06,039 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-10-31 21:56:06,041 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-10-31 21:56:06,042 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 31.10 09:56:02" (1/3) ... [2024-10-31 21:56:06,043 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@3f685304 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 31.10 09:56:06, skipping insertion in model container [2024-10-31 21:56:06,043 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-10-31 21:56:06,043 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.10 09:56:03" (2/3) ... [2024-10-31 21:56:06,044 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@3f685304 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 31.10 09:56:06, skipping insertion in model container [2024-10-31 21:56:06,044 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-10-31 21:56:06,044 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 31.10 09:56:06" (3/3) ... [2024-10-31 21:56:06,046 INFO L332 chiAutomizerObserver]: Analyzing ICFG transmitter.09.cil.c [2024-10-31 21:56:06,160 INFO L300 stractBuchiCegarLoop]: Interprodecural is true [2024-10-31 21:56:06,161 INFO L301 stractBuchiCegarLoop]: Hoare is None [2024-10-31 21:56:06,161 INFO L302 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-10-31 21:56:06,161 INFO L303 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-10-31 21:56:06,162 INFO L304 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-10-31 21:56:06,162 INFO L305 stractBuchiCegarLoop]: Difference is false [2024-10-31 21:56:06,163 INFO L306 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-10-31 21:56:06,163 INFO L310 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-10-31 21:56:06,174 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1112 states, 1111 states have (on average 1.5085508550855085) internal successors, (1676), 1111 states have internal predecessors, (1676), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 21:56:06,254 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 983 [2024-10-31 21:56:06,254 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 21:56:06,254 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 21:56:06,266 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 21:56:06,266 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 21:56:06,266 INFO L332 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-10-31 21:56:06,269 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1112 states, 1111 states have (on average 1.5085508550855085) internal successors, (1676), 1111 states have internal predecessors, (1676), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 21:56:06,283 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 983 [2024-10-31 21:56:06,283 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 21:56:06,283 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 21:56:06,287 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 21:56:06,287 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 21:56:06,296 INFO L745 eck$LassoCheckResult]: Stem: 138#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 1013#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 813#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1008#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 733#L641true assume !(1 == ~m_i~0);~m_st~0 := 2; 786#L641-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 705#L646-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 495#L651-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 988#L656-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 333#L661-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 945#L666-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 869#L671-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 684#L676-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 382#L681-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 221#L686-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1102#L922true assume !(0 == ~M_E~0); 1041#L922-2true assume !(0 == ~T1_E~0); 1058#L927-1true assume !(0 == ~T2_E~0); 552#L932-1true assume !(0 == ~T3_E~0); 437#L937-1true assume 0 == ~T4_E~0;~T4_E~0 := 1; 494#L942-1true assume !(0 == ~T5_E~0); 736#L947-1true assume !(0 == ~T6_E~0); 556#L952-1true assume !(0 == ~T7_E~0); 627#L957-1true assume !(0 == ~T8_E~0); 982#L962-1true assume !(0 == ~T9_E~0); 420#L967-1true assume !(0 == ~E_1~0); 954#L972-1true assume !(0 == ~E_2~0); 715#L977-1true assume 0 == ~E_3~0;~E_3~0 := 1; 1050#L982-1true assume !(0 == ~E_4~0); 104#L987-1true assume !(0 == ~E_5~0); 107#L992-1true assume !(0 == ~E_6~0); 363#L997-1true assume !(0 == ~E_7~0); 900#L1002-1true assume !(0 == ~E_8~0); 354#L1007-1true assume !(0 == ~E_9~0); 6#L1012-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 891#L443true assume !(1 == ~m_pc~0); 571#L443-2true is_master_triggered_~__retres1~0#1 := 0; 562#L454true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 693#is_master_triggered_returnLabel#1true activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 187#L1140true assume !(0 != activate_threads_~tmp~1#1); 55#L1140-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 914#L462true assume 1 == ~t1_pc~0; 459#L463true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 961#L473true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 579#L1148true assume !(0 != activate_threads_~tmp___0~0#1); 318#L1148-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 995#L481true assume !(1 == ~t2_pc~0); 790#L481-2true is_transmit2_triggered_~__retres1~2#1 := 0; 543#L492true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 255#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 234#L1156true assume !(0 != activate_threads_~tmp___1~0#1); 299#L1156-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1094#L500true assume 1 == ~t3_pc~0; 474#L501true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 754#L511true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 781#L1164true assume !(0 != activate_threads_~tmp___2~0#1); 7#L1164-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 766#L519true assume 1 == ~t4_pc~0; 154#L520true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 298#L530true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 56#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 206#L1172true assume !(0 != activate_threads_~tmp___3~0#1); 515#L1172-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 87#L538true assume !(1 == ~t5_pc~0); 845#L538-2true is_transmit5_triggered_~__retres1~5#1 := 0; 36#L549true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 697#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 176#L1180true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 611#L1180-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1113#L557true assume 1 == ~t6_pc~0; 410#L558true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 824#L568true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 244#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 207#L1188true assume !(0 != activate_threads_~tmp___5~0#1); 948#L1188-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1065#L576true assume !(1 == ~t7_pc~0); 303#L576-2true is_transmit7_triggered_~__retres1~7#1 := 0; 409#L587true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1030#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1059#L1196true assume !(0 != activate_threads_~tmp___6~0#1); 670#L1196-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 257#L595true assume 1 == ~t8_pc~0; 1015#L596true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 700#L606true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 616#is_transmit8_triggered_returnLabel#1true activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 517#L1204true assume !(0 != activate_threads_~tmp___7~0#1); 952#L1204-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 151#L614true assume !(1 == ~t9_pc~0); 460#L614-2true is_transmit9_triggered_~__retres1~9#1 := 0; 99#L625true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 282#is_transmit9_triggered_returnLabel#1true activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 682#L1212true assume !(0 != activate_threads_~tmp___8~0#1); 236#L1212-2true havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 425#L1025true assume !(1 == ~M_E~0); 473#L1025-2true assume !(1 == ~T1_E~0); 603#L1030-1true assume 1 == ~T2_E~0;~T2_E~0 := 2; 761#L1035-1true assume !(1 == ~T3_E~0); 230#L1040-1true assume !(1 == ~T4_E~0); 740#L1045-1true assume !(1 == ~T5_E~0); 181#L1050-1true assume !(1 == ~T6_E~0); 292#L1055-1true assume !(1 == ~T7_E~0); 92#L1060-1true assume !(1 == ~T8_E~0); 123#L1065-1true assume !(1 == ~T9_E~0); 966#L1070-1true assume 1 == ~E_1~0;~E_1~0 := 2; 557#L1075-1true assume !(1 == ~E_2~0); 1098#L1080-1true assume !(1 == ~E_3~0); 549#L1085-1true assume !(1 == ~E_4~0); 858#L1090-1true assume !(1 == ~E_5~0); 980#L1095-1true assume !(1 == ~E_6~0); 586#L1100-1true assume !(1 == ~E_7~0); 591#L1105-1true assume !(1 == ~E_8~0); 79#L1110-1true assume 1 == ~E_9~0;~E_9~0 := 2; 262#L1115-1true assume { :end_inline_reset_delta_events } true; 202#L1396-2true [2024-10-31 21:56:06,299 INFO L747 eck$LassoCheckResult]: Loop: 202#L1396-2true assume !false; 967#L1397true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 946#L897-1true assume false; 621#eval_returnLabel#1true havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 387#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 349#L922-3true assume 0 == ~M_E~0;~M_E~0 := 1; 987#L922-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 172#L927-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 277#L932-3true assume !(0 == ~T3_E~0); 547#L937-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 75#L942-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 632#L947-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 278#L952-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 826#L957-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 850#L962-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 645#L967-3true assume 0 == ~E_1~0;~E_1~0 := 1; 875#L972-3true assume !(0 == ~E_2~0); 551#L977-3true assume 0 == ~E_3~0;~E_3~0 := 1; 1101#L982-3true assume 0 == ~E_4~0;~E_4~0 := 1; 1074#L987-3true assume 0 == ~E_5~0;~E_5~0 := 1; 243#L992-3true assume 0 == ~E_6~0;~E_6~0 := 1; 369#L997-3true assume 0 == ~E_7~0;~E_7~0 := 1; 241#L1002-3true assume 0 == ~E_8~0;~E_8~0 := 1; 507#L1007-3true assume 0 == ~E_9~0;~E_9~0 := 1; 93#L1012-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 269#L443-30true assume !(1 == ~m_pc~0); 691#L443-32true is_master_triggered_~__retres1~0#1 := 0; 260#L454-10true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 265#is_master_triggered_returnLabel#11true activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 964#L1140-30true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 721#L1140-32true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 339#L462-30true assume 1 == ~t1_pc~0; 225#L463-10true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 711#L473-10true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 435#is_transmit1_triggered_returnLabel#11true activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 757#L1148-30true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1079#L1148-32true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 329#L481-30true assume !(1 == ~t2_pc~0); 726#L481-32true is_transmit2_triggered_~__retres1~2#1 := 0; 679#L492-10true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 204#is_transmit2_triggered_returnLabel#11true activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 140#L1156-30true assume !(0 != activate_threads_~tmp___1~0#1); 302#L1156-32true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 567#L500-30true assume !(1 == ~t3_pc~0); 1080#L500-32true is_transmit3_triggered_~__retres1~3#1 := 0; 371#L511-10true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 414#is_transmit3_triggered_returnLabel#11true activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1040#L1164-30true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 290#L1164-32true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 651#L519-30true assume !(1 == ~t4_pc~0); 433#L519-32true is_transmit4_triggered_~__retres1~4#1 := 0; 415#L530-10true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 919#is_transmit4_triggered_returnLabel#11true activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 422#L1172-30true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 533#L1172-32true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 943#L538-30true assume 1 == ~t5_pc~0; 98#L539-10true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 280#L549-10true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 522#is_transmit5_triggered_returnLabel#11true activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 674#L1180-30true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 137#L1180-32true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 143#L557-30true assume 1 == ~t6_pc~0; 2#L558-10true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 399#L568-10true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 58#is_transmit6_triggered_returnLabel#11true activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1056#L1188-30true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 150#L1188-32true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 525#L576-30true assume 1 == ~t7_pc~0; 1044#L577-10true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 393#L587-10true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 578#is_transmit7_triggered_returnLabel#11true activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 855#L1196-30true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 231#L1196-32true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 211#L595-30true assume !(1 == ~t8_pc~0); 772#L595-32true is_transmit8_triggered_~__retres1~8#1 := 0; 178#L606-10true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1071#is_transmit8_triggered_returnLabel#11true activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 856#L1204-30true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1104#L1204-32true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 958#L614-30true assume !(1 == ~t9_pc~0); 788#L614-32true is_transmit9_triggered_~__retres1~9#1 := 0; 653#L625-10true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19#is_transmit9_triggered_returnLabel#11true activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 94#L1212-30true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 625#L1212-32true havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 508#L1025-3true assume 1 == ~M_E~0;~M_E~0 := 2; 321#L1025-5true assume !(1 == ~T1_E~0); 476#L1030-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 876#L1035-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 1033#L1040-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 1052#L1045-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 864#L1050-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 698#L1055-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 40#L1060-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 732#L1065-3true assume !(1 == ~T9_E~0); 723#L1070-3true assume 1 == ~E_1~0;~E_1~0 := 2; 536#L1075-3true assume 1 == ~E_2~0;~E_2~0 := 2; 877#L1080-3true assume 1 == ~E_3~0;~E_3~0 := 2; 959#L1085-3true assume 1 == ~E_4~0;~E_4~0 := 2; 708#L1090-3true assume 1 == ~E_5~0;~E_5~0 := 2; 1019#L1095-3true assume 1 == ~E_6~0;~E_6~0 := 2; 738#L1100-3true assume 1 == ~E_7~0;~E_7~0 := 2; 932#L1105-3true assume !(1 == ~E_8~0); 116#L1110-3true assume 1 == ~E_9~0;~E_9~0 := 2; 793#L1115-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 769#L699-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 120#L751-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 222#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 720#L1415true assume !(0 == start_simulation_~tmp~3#1); 419#L1415-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 986#L699-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 423#L751-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 24#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 1090#L1370true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1075#L1377true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 411#stop_simulation_returnLabel#1true start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 160#L1428true assume !(0 != start_simulation_~tmp___0~1#1); 202#L1396-2true [2024-10-31 21:56:06,306 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 21:56:06,306 INFO L85 PathProgramCache]: Analyzing trace with hash 1400170149, now seen corresponding path program 1 times [2024-10-31 21:56:06,319 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 21:56:06,320 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1174375440] [2024-10-31 21:56:06,321 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 21:56:06,324 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 21:56:06,494 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 21:56:06,752 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 21:56:06,753 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 21:56:06,753 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1174375440] [2024-10-31 21:56:06,754 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1174375440] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 21:56:06,754 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 21:56:06,754 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 21:56:06,756 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1039612532] [2024-10-31 21:56:06,757 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 21:56:06,763 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 21:56:06,764 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 21:56:06,764 INFO L85 PathProgramCache]: Analyzing trace with hash -541420616, now seen corresponding path program 1 times [2024-10-31 21:56:06,764 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 21:56:06,765 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1804164609] [2024-10-31 21:56:06,765 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 21:56:06,765 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 21:56:06,783 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 21:56:06,848 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 21:56:06,849 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 21:56:06,852 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1804164609] [2024-10-31 21:56:06,852 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1804164609] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 21:56:06,852 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 21:56:06,853 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-31 21:56:06,853 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [490711905] [2024-10-31 21:56:06,853 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 21:56:06,854 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 21:56:06,858 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 21:56:06,905 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 21:56:06,905 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 21:56:06,909 INFO L87 Difference]: Start difference. First operand has 1112 states, 1111 states have (on average 1.5085508550855085) internal successors, (1676), 1111 states have internal predecessors, (1676), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 21:56:07,002 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 21:56:07,003 INFO L93 Difference]: Finished difference Result 1110 states and 1646 transitions. [2024-10-31 21:56:07,004 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1110 states and 1646 transitions. [2024-10-31 21:56:07,015 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 979 [2024-10-31 21:56:07,030 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1110 states to 1104 states and 1640 transitions. [2024-10-31 21:56:07,033 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1104 [2024-10-31 21:56:07,035 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1104 [2024-10-31 21:56:07,036 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1104 states and 1640 transitions. [2024-10-31 21:56:07,044 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 21:56:07,044 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1104 states and 1640 transitions. [2024-10-31 21:56:07,069 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1104 states and 1640 transitions. [2024-10-31 21:56:07,111 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1104 to 1104. [2024-10-31 21:56:07,114 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1104 states, 1104 states have (on average 1.4855072463768115) internal successors, (1640), 1103 states have internal predecessors, (1640), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 21:56:07,118 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1104 states to 1104 states and 1640 transitions. [2024-10-31 21:56:07,119 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1104 states and 1640 transitions. [2024-10-31 21:56:07,123 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 21:56:07,128 INFO L425 stractBuchiCegarLoop]: Abstraction has 1104 states and 1640 transitions. [2024-10-31 21:56:07,129 INFO L332 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-10-31 21:56:07,130 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1104 states and 1640 transitions. [2024-10-31 21:56:07,137 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 979 [2024-10-31 21:56:07,137 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 21:56:07,137 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 21:56:07,143 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 21:56:07,143 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 21:56:07,144 INFO L745 eck$LassoCheckResult]: Stem: 2514#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 2515#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 3273#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3274#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3225#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 3226#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3208#L646-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 3030#L651-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3031#L656-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2839#L661-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2840#L666-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3294#L671-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 3200#L676-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 2899#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 2670#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2671#L922 assume !(0 == ~M_E~0); 3331#L922-2 assume !(0 == ~T1_E~0); 3332#L927-1 assume !(0 == ~T2_E~0); 3094#L932-1 assume !(0 == ~T3_E~0); 2969#L937-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2970#L942-1 assume !(0 == ~T5_E~0); 3029#L947-1 assume !(0 == ~T6_E~0); 3098#L952-1 assume !(0 == ~T7_E~0); 3099#L957-1 assume !(0 == ~T8_E~0); 3156#L962-1 assume !(0 == ~T9_E~0); 2948#L967-1 assume !(0 == ~E_1~0); 2949#L972-1 assume !(0 == ~E_2~0); 3212#L977-1 assume 0 == ~E_3~0;~E_3~0 := 1; 3213#L982-1 assume !(0 == ~E_4~0); 2447#L987-1 assume !(0 == ~E_5~0); 2448#L992-1 assume !(0 == ~E_6~0); 2454#L997-1 assume !(0 == ~E_7~0); 2875#L1002-1 assume !(0 == ~E_8~0); 2864#L1007-1 assume !(0 == ~E_9~0); 2241#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2242#L443 assume !(1 == ~m_pc~0); 3114#L443-2 is_master_triggered_~__retres1~0#1 := 0; 3106#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3107#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2609#L1140 assume !(0 != activate_threads_~tmp~1#1); 2346#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2347#L462 assume 1 == ~t1_pc~0; 2995#L463 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2961#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2283#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2284#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 2818#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2819#L481 assume !(1 == ~t2_pc~0); 2603#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2602#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2729#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2693#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 2694#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2786#L500 assume 1 == ~t3_pc~0; 3014#L501 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3015#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2248#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2249#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 2243#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2244#L519 assume 1 == ~t4_pc~0; 2546#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2547#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2348#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2349#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 2643#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2410#L538 assume !(1 == ~t5_pc~0); 2411#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2308#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2309#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2589#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2590#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3141#L557 assume 1 == ~t6_pc~0; 2936#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2624#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2711#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2644#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 2645#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3318#L576 assume !(1 == ~t7_pc~0); 2613#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2614#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2935#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3328#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 3192#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2730#L595 assume 1 == ~t8_pc~0; 2731#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 3205#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3146#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3053#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 3054#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2539#L614 assume !(1 == ~t9_pc~0); 2540#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 2436#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2437#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2762#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 2696#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2697#L1025 assume !(1 == ~M_E~0); 2955#L1025-2 assume !(1 == ~T1_E~0); 3013#L1030-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3136#L1035-1 assume !(1 == ~T3_E~0); 2689#L1040-1 assume !(1 == ~T4_E~0); 2690#L1045-1 assume !(1 == ~T5_E~0); 2599#L1050-1 assume !(1 == ~T6_E~0); 2600#L1055-1 assume !(1 == ~T7_E~0); 2421#L1060-1 assume !(1 == ~T8_E~0); 2422#L1065-1 assume !(1 == ~T9_E~0); 2486#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 3100#L1075-1 assume !(1 == ~E_2~0); 3101#L1080-1 assume !(1 == ~E_3~0); 3089#L1085-1 assume !(1 == ~E_4~0); 3090#L1090-1 assume !(1 == ~E_5~0); 3289#L1095-1 assume !(1 == ~E_6~0); 3123#L1100-1 assume !(1 == ~E_7~0); 3124#L1105-1 assume !(1 == ~E_8~0); 2392#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 2393#L1115-1 assume { :end_inline_reset_delta_events } true; 2558#L1396-2 [2024-10-31 21:56:07,144 INFO L747 eck$LassoCheckResult]: Loop: 2558#L1396-2 assume !false; 2635#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3293#L897-1 assume !false; 3316#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 3227#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2266#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2267#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2750#L766 assume !(0 != eval_~tmp~0#1); 3151#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2905#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2857#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2858#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2581#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2582#L932-3 assume !(0 == ~T3_E~0); 2755#L937-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2384#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2385#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2756#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2757#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 3278#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3173#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3174#L972-3 assume !(0 == ~E_2~0); 3092#L977-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3093#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3333#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2709#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2710#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2704#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2705#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 2423#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2424#L443-30 assume 1 == ~m_pc~0; 2457#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 2458#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2736#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2741#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3216#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2846#L462-30 assume 1 == ~t1_pc~0; 2678#L463-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2679#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2965#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2966#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3241#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2831#L481-30 assume 1 == ~t2_pc~0; 2549#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2550#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2639#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2518#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 2519#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2791#L500-30 assume 1 == ~t3_pc~0; 2554#L501-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2555#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2884#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2940#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2775#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2776#L519-30 assume !(1 == ~t4_pc~0); 2964#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 2941#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2942#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2952#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2953#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3072#L538-30 assume 1 == ~t5_pc~0; 2432#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2433#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2759#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3059#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2512#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2513#L557-30 assume 1 == ~t6_pc~0; 2231#L558-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2233#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2352#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2353#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2537#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2538#L576-30 assume !(1 == ~t7_pc~0); 2306#L576-32 is_transmit7_triggered_~__retres1~7#1 := 0; 2307#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2914#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3121#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2688#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2652#L595-30 assume !(1 == ~t8_pc~0); 2653#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 2591#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2592#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3287#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3288#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3319#L614-30 assume 1 == ~t9_pc~0; 2595#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 2596#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2270#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2271#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 2425#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3046#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2820#L1025-5 assume !(1 == ~T1_E~0); 2821#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3018#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3297#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3329#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3292#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3204#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2316#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2317#L1065-3 assume !(1 == ~T9_E~0); 3218#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3075#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3076#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3298#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3209#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3210#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3229#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3230#L1105-3 assume !(1 == ~E_8~0); 2471#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 2472#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 3245#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2327#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2480#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 2672#L1415 assume !(0 == start_simulation_~tmp~3#1); 2945#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2946#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2380#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2281#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 2282#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3334#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2937#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 2557#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 2558#L1396-2 [2024-10-31 21:56:07,145 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 21:56:07,145 INFO L85 PathProgramCache]: Analyzing trace with hash -1247434205, now seen corresponding path program 1 times [2024-10-31 21:56:07,145 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 21:56:07,146 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [628761273] [2024-10-31 21:56:07,148 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 21:56:07,149 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 21:56:07,177 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 21:56:07,291 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 21:56:07,292 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 21:56:07,292 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [628761273] [2024-10-31 21:56:07,292 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [628761273] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 21:56:07,293 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 21:56:07,293 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 21:56:07,293 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [831055780] [2024-10-31 21:56:07,293 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 21:56:07,294 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 21:56:07,294 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 21:56:07,294 INFO L85 PathProgramCache]: Analyzing trace with hash -2034235564, now seen corresponding path program 1 times [2024-10-31 21:56:07,295 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 21:56:07,295 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [56389947] [2024-10-31 21:56:07,295 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 21:56:07,296 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 21:56:07,345 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 21:56:07,422 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 21:56:07,423 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 21:56:07,423 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [56389947] [2024-10-31 21:56:07,423 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [56389947] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 21:56:07,424 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 21:56:07,426 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 21:56:07,426 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [692297293] [2024-10-31 21:56:07,426 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 21:56:07,427 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 21:56:07,428 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 21:56:07,429 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 21:56:07,429 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 21:56:07,430 INFO L87 Difference]: Start difference. First operand 1104 states and 1640 transitions. cyclomatic complexity: 537 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 21:56:07,492 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 21:56:07,493 INFO L93 Difference]: Finished difference Result 1104 states and 1639 transitions. [2024-10-31 21:56:07,493 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1104 states and 1639 transitions. [2024-10-31 21:56:07,503 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 979 [2024-10-31 21:56:07,510 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1104 states to 1104 states and 1639 transitions. [2024-10-31 21:56:07,511 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1104 [2024-10-31 21:56:07,513 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1104 [2024-10-31 21:56:07,513 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1104 states and 1639 transitions. [2024-10-31 21:56:07,517 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 21:56:07,517 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1104 states and 1639 transitions. [2024-10-31 21:56:07,519 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1104 states and 1639 transitions. [2024-10-31 21:56:07,547 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1104 to 1104. [2024-10-31 21:56:07,550 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1104 states, 1104 states have (on average 1.4846014492753623) internal successors, (1639), 1103 states have internal predecessors, (1639), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 21:56:07,556 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1104 states to 1104 states and 1639 transitions. [2024-10-31 21:56:07,556 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1104 states and 1639 transitions. [2024-10-31 21:56:07,557 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 21:56:07,558 INFO L425 stractBuchiCegarLoop]: Abstraction has 1104 states and 1639 transitions. [2024-10-31 21:56:07,558 INFO L332 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-10-31 21:56:07,558 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1104 states and 1639 transitions. [2024-10-31 21:56:07,568 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 979 [2024-10-31 21:56:07,568 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 21:56:07,569 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 21:56:07,573 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 21:56:07,573 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 21:56:07,574 INFO L745 eck$LassoCheckResult]: Stem: 4729#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 4730#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 5488#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5489#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5440#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 5441#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5423#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5245#L651-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 5246#L656-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5054#L661-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5055#L666-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5509#L671-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 5415#L676-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 5114#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4885#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4886#L922 assume !(0 == ~M_E~0); 5546#L922-2 assume !(0 == ~T1_E~0); 5547#L927-1 assume !(0 == ~T2_E~0); 5309#L932-1 assume !(0 == ~T3_E~0); 5184#L937-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5185#L942-1 assume !(0 == ~T5_E~0); 5244#L947-1 assume !(0 == ~T6_E~0); 5313#L952-1 assume !(0 == ~T7_E~0); 5314#L957-1 assume !(0 == ~T8_E~0); 5373#L962-1 assume !(0 == ~T9_E~0); 5163#L967-1 assume !(0 == ~E_1~0); 5164#L972-1 assume !(0 == ~E_2~0); 5427#L977-1 assume 0 == ~E_3~0;~E_3~0 := 1; 5428#L982-1 assume !(0 == ~E_4~0); 4662#L987-1 assume !(0 == ~E_5~0); 4663#L992-1 assume !(0 == ~E_6~0); 4669#L997-1 assume !(0 == ~E_7~0); 5090#L1002-1 assume !(0 == ~E_8~0); 5079#L1007-1 assume !(0 == ~E_9~0); 4456#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4457#L443 assume !(1 == ~m_pc~0); 5329#L443-2 is_master_triggered_~__retres1~0#1 := 0; 5321#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5322#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4824#L1140 assume !(0 != activate_threads_~tmp~1#1); 4561#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4562#L462 assume 1 == ~t1_pc~0; 5210#L463 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5176#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4498#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4499#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 5033#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5034#L481 assume !(1 == ~t2_pc~0); 4818#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4817#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4944#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4908#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 4909#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5003#L500 assume 1 == ~t3_pc~0; 5229#L501 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5230#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4463#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4464#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 4458#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4459#L519 assume 1 == ~t4_pc~0; 4761#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4762#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4563#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4564#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 4860#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4625#L538 assume !(1 == ~t5_pc~0); 4626#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4523#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4524#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4804#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4805#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5358#L557 assume 1 == ~t6_pc~0; 5151#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4839#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4926#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4861#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 4862#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5533#L576 assume !(1 == ~t7_pc~0); 4828#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 4829#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5150#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5543#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 5407#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4945#L595 assume 1 == ~t8_pc~0; 4946#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 5420#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5361#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5268#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 5269#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4754#L614 assume !(1 == ~t9_pc~0); 4755#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 4651#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4652#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4977#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 4911#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4912#L1025 assume !(1 == ~M_E~0); 5170#L1025-2 assume !(1 == ~T1_E~0); 5228#L1030-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5351#L1035-1 assume !(1 == ~T3_E~0); 4904#L1040-1 assume !(1 == ~T4_E~0); 4905#L1045-1 assume !(1 == ~T5_E~0); 4814#L1050-1 assume !(1 == ~T6_E~0); 4815#L1055-1 assume !(1 == ~T7_E~0); 4636#L1060-1 assume !(1 == ~T8_E~0); 4637#L1065-1 assume !(1 == ~T9_E~0); 4701#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 5315#L1075-1 assume !(1 == ~E_2~0); 5316#L1080-1 assume !(1 == ~E_3~0); 5304#L1085-1 assume !(1 == ~E_4~0); 5305#L1090-1 assume !(1 == ~E_5~0); 5504#L1095-1 assume !(1 == ~E_6~0); 5338#L1100-1 assume !(1 == ~E_7~0); 5339#L1105-1 assume !(1 == ~E_8~0); 4607#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 4608#L1115-1 assume { :end_inline_reset_delta_events } true; 4773#L1396-2 [2024-10-31 21:56:07,576 INFO L747 eck$LassoCheckResult]: Loop: 4773#L1396-2 assume !false; 4850#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5508#L897-1 assume !false; 5531#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 5442#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 4481#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 4482#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 4965#L766 assume !(0 != eval_~tmp~0#1); 5366#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5120#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5072#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5073#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4796#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4797#L932-3 assume !(0 == ~T3_E~0); 4970#L937-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4599#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4600#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4971#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4972#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 5493#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 5388#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5389#L972-3 assume !(0 == ~E_2~0); 5307#L977-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5308#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5548#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4924#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4925#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 4922#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 4923#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 4638#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4639#L443-30 assume 1 == ~m_pc~0; 4672#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 4673#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4951#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4956#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5431#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5061#L462-30 assume !(1 == ~t1_pc~0); 4897#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 4896#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5180#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5181#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5456#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5046#L481-30 assume 1 == ~t2_pc~0; 4764#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4765#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4854#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4733#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 4734#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5006#L500-30 assume 1 == ~t3_pc~0; 4769#L501-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4770#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5099#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5155#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4991#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4992#L519-30 assume 1 == ~t4_pc~0; 5344#L520-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5156#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5157#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5167#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5168#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5287#L538-30 assume 1 == ~t5_pc~0; 4647#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4648#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4973#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5273#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4727#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4728#L557-30 assume 1 == ~t6_pc~0; 4446#L558-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4448#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4567#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4568#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4752#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4753#L576-30 assume !(1 == ~t7_pc~0); 4516#L576-32 is_transmit7_triggered_~__retres1~7#1 := 0; 4517#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5129#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5335#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4903#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4867#L595-30 assume !(1 == ~t8_pc~0); 4868#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 4806#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4807#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5502#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 5503#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5534#L614-30 assume 1 == ~t9_pc~0; 4810#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4811#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4485#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4486#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 4640#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5261#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5035#L1025-5 assume !(1 == ~T1_E~0); 5036#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5233#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5512#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5544#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5507#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5419#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4531#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4532#L1065-3 assume !(1 == ~T9_E~0); 5433#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5290#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5291#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5513#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5424#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5425#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5444#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5445#L1105-3 assume !(1 == ~E_8~0); 4686#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 4687#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 5461#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 4542#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 4695#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 4887#L1415 assume !(0 == start_simulation_~tmp~3#1); 5160#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 5161#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 4595#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 4496#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 4497#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5549#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5152#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 4772#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 4773#L1396-2 [2024-10-31 21:56:07,578 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 21:56:07,579 INFO L85 PathProgramCache]: Analyzing trace with hash -208849631, now seen corresponding path program 1 times [2024-10-31 21:56:07,579 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 21:56:07,579 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1318528305] [2024-10-31 21:56:07,580 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 21:56:07,584 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 21:56:07,617 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 21:56:07,701 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 21:56:07,701 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 21:56:07,702 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1318528305] [2024-10-31 21:56:07,702 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1318528305] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 21:56:07,704 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 21:56:07,704 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 21:56:07,704 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1359343228] [2024-10-31 21:56:07,705 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 21:56:07,705 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 21:56:07,706 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 21:56:07,706 INFO L85 PathProgramCache]: Analyzing trace with hash 1344839060, now seen corresponding path program 1 times [2024-10-31 21:56:07,706 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 21:56:07,707 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1360541375] [2024-10-31 21:56:07,707 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 21:56:07,707 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 21:56:07,741 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 21:56:07,828 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 21:56:07,828 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 21:56:07,828 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1360541375] [2024-10-31 21:56:07,829 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1360541375] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 21:56:07,829 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 21:56:07,829 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 21:56:07,829 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [683320923] [2024-10-31 21:56:07,830 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 21:56:07,830 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 21:56:07,830 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 21:56:07,831 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 21:56:07,831 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 21:56:07,831 INFO L87 Difference]: Start difference. First operand 1104 states and 1639 transitions. cyclomatic complexity: 536 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 21:56:07,868 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 21:56:07,869 INFO L93 Difference]: Finished difference Result 1104 states and 1638 transitions. [2024-10-31 21:56:07,869 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1104 states and 1638 transitions. [2024-10-31 21:56:07,877 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 979 [2024-10-31 21:56:07,885 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1104 states to 1104 states and 1638 transitions. [2024-10-31 21:56:07,885 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1104 [2024-10-31 21:56:07,886 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1104 [2024-10-31 21:56:07,887 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1104 states and 1638 transitions. [2024-10-31 21:56:07,889 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 21:56:07,889 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1104 states and 1638 transitions. [2024-10-31 21:56:07,891 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1104 states and 1638 transitions. [2024-10-31 21:56:07,904 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1104 to 1104. [2024-10-31 21:56:07,907 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1104 states, 1104 states have (on average 1.483695652173913) internal successors, (1638), 1103 states have internal predecessors, (1638), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 21:56:07,910 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1104 states to 1104 states and 1638 transitions. [2024-10-31 21:56:07,910 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1104 states and 1638 transitions. [2024-10-31 21:56:07,911 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 21:56:07,911 INFO L425 stractBuchiCegarLoop]: Abstraction has 1104 states and 1638 transitions. [2024-10-31 21:56:07,912 INFO L332 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-10-31 21:56:07,912 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1104 states and 1638 transitions. [2024-10-31 21:56:07,918 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 979 [2024-10-31 21:56:07,918 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 21:56:07,918 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 21:56:07,924 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 21:56:07,924 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 21:56:07,925 INFO L745 eck$LassoCheckResult]: Stem: 6946#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 6947#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 7703#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7704#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7655#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 7656#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7638#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7460#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7461#L656-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 7269#L661-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 7270#L666-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 7725#L671-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 7630#L676-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 7329#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 7100#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7101#L922 assume !(0 == ~M_E~0); 7761#L922-2 assume !(0 == ~T1_E~0); 7762#L927-1 assume !(0 == ~T2_E~0); 7524#L932-1 assume !(0 == ~T3_E~0); 7399#L937-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7400#L942-1 assume !(0 == ~T5_E~0); 7459#L947-1 assume !(0 == ~T6_E~0); 7528#L952-1 assume !(0 == ~T7_E~0); 7529#L957-1 assume !(0 == ~T8_E~0); 7588#L962-1 assume !(0 == ~T9_E~0); 7378#L967-1 assume !(0 == ~E_1~0); 7379#L972-1 assume !(0 == ~E_2~0); 7642#L977-1 assume 0 == ~E_3~0;~E_3~0 := 1; 7643#L982-1 assume !(0 == ~E_4~0); 6877#L987-1 assume !(0 == ~E_5~0); 6878#L992-1 assume !(0 == ~E_6~0); 6884#L997-1 assume !(0 == ~E_7~0); 7307#L1002-1 assume !(0 == ~E_8~0); 7294#L1007-1 assume !(0 == ~E_9~0); 6671#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6672#L443 assume !(1 == ~m_pc~0); 7544#L443-2 is_master_triggered_~__retres1~0#1 := 0; 7536#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7537#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7039#L1140 assume !(0 != activate_threads_~tmp~1#1); 6776#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6777#L462 assume 1 == ~t1_pc~0; 7425#L463 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7392#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6713#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6714#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 7248#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7249#L481 assume !(1 == ~t2_pc~0); 7033#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 7032#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7159#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7123#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 7124#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7218#L500 assume 1 == ~t3_pc~0; 7444#L501 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7445#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6678#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6679#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 6676#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6677#L519 assume 1 == ~t4_pc~0; 6976#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6977#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6778#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6779#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 7075#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6840#L538 assume !(1 == ~t5_pc~0); 6841#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 6738#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6739#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7019#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7020#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7573#L557 assume 1 == ~t6_pc~0; 7366#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 7054#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7141#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7076#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 7077#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7748#L576 assume !(1 == ~t7_pc~0); 7043#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 7044#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7365#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7758#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 7622#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7160#L595 assume 1 == ~t8_pc~0; 7161#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 7635#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7576#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7483#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 7484#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 6969#L614 assume !(1 == ~t9_pc~0); 6970#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 6866#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6867#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7192#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 7126#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7127#L1025 assume !(1 == ~M_E~0); 7385#L1025-2 assume !(1 == ~T1_E~0); 7443#L1030-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7566#L1035-1 assume !(1 == ~T3_E~0); 7119#L1040-1 assume !(1 == ~T4_E~0); 7120#L1045-1 assume !(1 == ~T5_E~0); 7029#L1050-1 assume !(1 == ~T6_E~0); 7030#L1055-1 assume !(1 == ~T7_E~0); 6851#L1060-1 assume !(1 == ~T8_E~0); 6852#L1065-1 assume !(1 == ~T9_E~0); 6916#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 7531#L1075-1 assume !(1 == ~E_2~0); 7532#L1080-1 assume !(1 == ~E_3~0); 7519#L1085-1 assume !(1 == ~E_4~0); 7520#L1090-1 assume !(1 == ~E_5~0); 7719#L1095-1 assume !(1 == ~E_6~0); 7553#L1100-1 assume !(1 == ~E_7~0); 7554#L1105-1 assume !(1 == ~E_8~0); 6822#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 6823#L1115-1 assume { :end_inline_reset_delta_events } true; 6988#L1396-2 [2024-10-31 21:56:07,925 INFO L747 eck$LassoCheckResult]: Loop: 6988#L1396-2 assume !false; 7065#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7723#L897-1 assume !false; 7746#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 7657#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 6696#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 6697#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 7180#L766 assume !(0 != eval_~tmp~0#1); 7581#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7335#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7289#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 7290#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7011#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7012#L932-3 assume !(0 == ~T3_E~0); 7185#L937-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6814#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6815#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7186#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 7187#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 7708#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 7603#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7604#L972-3 assume !(0 == ~E_2~0); 7522#L977-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7523#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7763#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7139#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 7140#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 7137#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 7138#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 6853#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6854#L443-30 assume 1 == ~m_pc~0; 6887#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 6888#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7166#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7171#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7647#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7276#L462-30 assume 1 == ~t1_pc~0; 7110#L463-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7111#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7395#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7396#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7671#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7261#L481-30 assume 1 == ~t2_pc~0; 6979#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6980#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7069#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6948#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 6949#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7221#L500-30 assume 1 == ~t3_pc~0; 6984#L501-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6985#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7314#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7370#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7205#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7206#L519-30 assume 1 == ~t4_pc~0; 7558#L520-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7371#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7372#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7382#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7383#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7502#L538-30 assume !(1 == ~t5_pc~0); 6864#L538-32 is_transmit5_triggered_~__retres1~5#1 := 0; 6863#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7188#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7488#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6942#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6943#L557-30 assume 1 == ~t6_pc~0; 6661#L558-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6663#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6782#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6783#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 6967#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6968#L576-30 assume 1 == ~t7_pc~0; 7492#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 6735#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7344#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7550#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 7118#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7082#L595-30 assume !(1 == ~t8_pc~0); 7083#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 7023#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7024#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7717#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 7718#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7749#L614-30 assume 1 == ~t9_pc~0; 7026#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 7027#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6700#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6701#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 6855#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7476#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7250#L1025-5 assume !(1 == ~T1_E~0); 7251#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7448#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7727#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7759#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7722#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 7634#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 6746#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 6747#L1065-3 assume !(1 == ~T9_E~0); 7648#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7505#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7506#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7728#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7639#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7640#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 7659#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 7660#L1105-3 assume !(1 == ~E_8~0); 6901#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 6902#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 7676#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 6757#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 6910#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 7102#L1415 assume !(0 == start_simulation_~tmp~3#1); 7376#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 7377#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 6810#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 6711#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 6712#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7764#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7367#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 6987#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 6988#L1396-2 [2024-10-31 21:56:07,926 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 21:56:07,926 INFO L85 PathProgramCache]: Analyzing trace with hash 1764315747, now seen corresponding path program 1 times [2024-10-31 21:56:07,926 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 21:56:07,926 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [346563827] [2024-10-31 21:56:07,927 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 21:56:07,927 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 21:56:07,945 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 21:56:07,985 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 21:56:07,985 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 21:56:07,986 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [346563827] [2024-10-31 21:56:07,986 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [346563827] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 21:56:07,988 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 21:56:07,988 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 21:56:07,988 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [773420979] [2024-10-31 21:56:07,990 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 21:56:07,991 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 21:56:07,991 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 21:56:07,991 INFO L85 PathProgramCache]: Analyzing trace with hash -321985611, now seen corresponding path program 1 times [2024-10-31 21:56:07,992 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 21:56:07,992 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1563294354] [2024-10-31 21:56:07,992 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 21:56:07,994 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 21:56:08,013 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 21:56:08,077 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 21:56:08,078 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 21:56:08,078 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1563294354] [2024-10-31 21:56:08,078 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1563294354] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 21:56:08,079 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 21:56:08,079 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 21:56:08,079 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [353324706] [2024-10-31 21:56:08,080 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 21:56:08,080 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 21:56:08,080 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 21:56:08,081 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 21:56:08,081 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 21:56:08,081 INFO L87 Difference]: Start difference. First operand 1104 states and 1638 transitions. cyclomatic complexity: 535 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 21:56:08,108 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 21:56:08,108 INFO L93 Difference]: Finished difference Result 1104 states and 1637 transitions. [2024-10-31 21:56:08,108 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1104 states and 1637 transitions. [2024-10-31 21:56:08,114 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 979 [2024-10-31 21:56:08,119 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1104 states to 1104 states and 1637 transitions. [2024-10-31 21:56:08,120 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1104 [2024-10-31 21:56:08,121 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1104 [2024-10-31 21:56:08,121 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1104 states and 1637 transitions. [2024-10-31 21:56:08,122 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 21:56:08,122 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1104 states and 1637 transitions. [2024-10-31 21:56:08,124 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1104 states and 1637 transitions. [2024-10-31 21:56:08,136 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1104 to 1104. [2024-10-31 21:56:08,142 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1104 states, 1104 states have (on average 1.4827898550724639) internal successors, (1637), 1103 states have internal predecessors, (1637), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 21:56:08,146 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1104 states to 1104 states and 1637 transitions. [2024-10-31 21:56:08,146 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1104 states and 1637 transitions. [2024-10-31 21:56:08,146 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 21:56:08,148 INFO L425 stractBuchiCegarLoop]: Abstraction has 1104 states and 1637 transitions. [2024-10-31 21:56:08,148 INFO L332 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-10-31 21:56:08,148 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1104 states and 1637 transitions. [2024-10-31 21:56:08,153 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 979 [2024-10-31 21:56:08,154 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 21:56:08,154 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 21:56:08,157 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 21:56:08,157 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 21:56:08,158 INFO L745 eck$LassoCheckResult]: Stem: 9161#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 9162#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 9918#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9919#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9870#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 9871#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9853#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9675#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9676#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9484#L661-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 9485#L666-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 9940#L671-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 9845#L676-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 9544#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 9315#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9316#L922 assume !(0 == ~M_E~0); 9976#L922-2 assume !(0 == ~T1_E~0); 9977#L927-1 assume !(0 == ~T2_E~0); 9739#L932-1 assume !(0 == ~T3_E~0); 9614#L937-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9615#L942-1 assume !(0 == ~T5_E~0); 9674#L947-1 assume !(0 == ~T6_E~0); 9743#L952-1 assume !(0 == ~T7_E~0); 9744#L957-1 assume !(0 == ~T8_E~0); 9803#L962-1 assume !(0 == ~T9_E~0); 9593#L967-1 assume !(0 == ~E_1~0); 9594#L972-1 assume !(0 == ~E_2~0); 9857#L977-1 assume 0 == ~E_3~0;~E_3~0 := 1; 9858#L982-1 assume !(0 == ~E_4~0); 9092#L987-1 assume !(0 == ~E_5~0); 9093#L992-1 assume !(0 == ~E_6~0); 9099#L997-1 assume !(0 == ~E_7~0); 9522#L1002-1 assume !(0 == ~E_8~0); 9509#L1007-1 assume !(0 == ~E_9~0); 8886#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8887#L443 assume !(1 == ~m_pc~0); 9759#L443-2 is_master_triggered_~__retres1~0#1 := 0; 9751#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9752#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9254#L1140 assume !(0 != activate_threads_~tmp~1#1); 8991#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8992#L462 assume 1 == ~t1_pc~0; 9640#L463 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9609#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8930#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8931#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 9463#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9464#L481 assume !(1 == ~t2_pc~0); 9248#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 9247#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9374#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9338#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 9339#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9433#L500 assume 1 == ~t3_pc~0; 9659#L501 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9660#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8893#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8894#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 8891#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8892#L519 assume 1 == ~t4_pc~0; 9194#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9195#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8993#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8994#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 9290#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9055#L538 assume !(1 == ~t5_pc~0); 9056#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 8953#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8954#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9234#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 9235#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9788#L557 assume 1 == ~t6_pc~0; 9581#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 9269#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9356#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9291#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 9292#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9963#L576 assume !(1 == ~t7_pc~0); 9258#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 9259#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9580#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9973#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 9837#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9377#L595 assume 1 == ~t8_pc~0; 9378#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 9850#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9791#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9698#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 9699#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 9184#L614 assume !(1 == ~t9_pc~0); 9185#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 9081#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9082#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9407#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 9341#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9342#L1025 assume !(1 == ~M_E~0); 9600#L1025-2 assume !(1 == ~T1_E~0); 9658#L1030-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9781#L1035-1 assume !(1 == ~T3_E~0); 9334#L1040-1 assume !(1 == ~T4_E~0); 9335#L1045-1 assume !(1 == ~T5_E~0); 9244#L1050-1 assume !(1 == ~T6_E~0); 9245#L1055-1 assume !(1 == ~T7_E~0); 9066#L1060-1 assume !(1 == ~T8_E~0); 9067#L1065-1 assume !(1 == ~T9_E~0); 9131#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 9746#L1075-1 assume !(1 == ~E_2~0); 9747#L1080-1 assume !(1 == ~E_3~0); 9734#L1085-1 assume !(1 == ~E_4~0); 9735#L1090-1 assume !(1 == ~E_5~0); 9934#L1095-1 assume !(1 == ~E_6~0); 9768#L1100-1 assume !(1 == ~E_7~0); 9769#L1105-1 assume !(1 == ~E_8~0); 9037#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 9038#L1115-1 assume { :end_inline_reset_delta_events } true; 9203#L1396-2 [2024-10-31 21:56:08,158 INFO L747 eck$LassoCheckResult]: Loop: 9203#L1396-2 assume !false; 9283#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9938#L897-1 assume !false; 9961#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 9872#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 8911#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 8912#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 9395#L766 assume !(0 != eval_~tmp~0#1); 9797#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9552#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9504#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9505#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9226#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9227#L932-3 assume !(0 == ~T3_E~0); 9400#L937-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9029#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9030#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9401#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 9402#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 9923#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 9818#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9819#L972-3 assume !(0 == ~E_2~0); 9737#L977-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9738#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 9978#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9354#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9355#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 9352#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 9353#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 9068#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9069#L443-30 assume !(1 == ~m_pc~0); 9104#L443-32 is_master_triggered_~__retres1~0#1 := 0; 9103#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9381#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9386#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 9861#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9491#L462-30 assume 1 == ~t1_pc~0; 9323#L463-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9324#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9610#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9611#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 9886#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9476#L481-30 assume 1 == ~t2_pc~0; 9191#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9192#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9284#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9163#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 9164#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9436#L500-30 assume !(1 == ~t3_pc~0); 9201#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 9200#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9529#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9585#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9420#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9421#L519-30 assume !(1 == ~t4_pc~0); 9607#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 9586#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9587#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9597#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9598#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9717#L538-30 assume 1 == ~t5_pc~0; 9077#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9078#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9403#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9703#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 9157#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9158#L557-30 assume 1 == ~t6_pc~0; 8876#L558-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8878#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8997#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8998#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9182#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9183#L576-30 assume !(1 == ~t7_pc~0); 8949#L576-32 is_transmit7_triggered_~__retres1~7#1 := 0; 8950#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9559#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9766#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 9333#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9297#L595-30 assume !(1 == ~t8_pc~0); 9298#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 9238#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9239#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9932#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 9933#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 9964#L614-30 assume 1 == ~t9_pc~0; 9241#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 9242#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 8915#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8916#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 9070#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9691#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9465#L1025-5 assume !(1 == ~T1_E~0); 9466#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9663#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9942#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9974#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9937#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 9849#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 8961#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 8962#L1065-3 assume !(1 == ~T9_E~0); 9863#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9720#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 9721#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9943#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9854#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9855#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 9874#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 9875#L1105-3 assume !(1 == ~E_8~0); 9116#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 9117#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 9891#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 8972#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 9125#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 9317#L1415 assume !(0 == start_simulation_~tmp~3#1); 9591#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 9592#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 9025#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 8926#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 8927#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9979#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9582#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 9202#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 9203#L1396-2 [2024-10-31 21:56:08,158 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 21:56:08,158 INFO L85 PathProgramCache]: Analyzing trace with hash -388791071, now seen corresponding path program 1 times [2024-10-31 21:56:08,159 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 21:56:08,159 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1465662113] [2024-10-31 21:56:08,159 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 21:56:08,159 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 21:56:08,209 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 21:56:08,250 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 21:56:08,250 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 21:56:08,250 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1465662113] [2024-10-31 21:56:08,250 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1465662113] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 21:56:08,251 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 21:56:08,251 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 21:56:08,251 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1673963702] [2024-10-31 21:56:08,251 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 21:56:08,252 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 21:56:08,252 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 21:56:08,252 INFO L85 PathProgramCache]: Analyzing trace with hash -1993645742, now seen corresponding path program 1 times [2024-10-31 21:56:08,252 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 21:56:08,253 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [361305049] [2024-10-31 21:56:08,253 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 21:56:08,253 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 21:56:08,269 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 21:56:08,319 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 21:56:08,319 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 21:56:08,319 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [361305049] [2024-10-31 21:56:08,319 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [361305049] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 21:56:08,319 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 21:56:08,320 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 21:56:08,320 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1293174331] [2024-10-31 21:56:08,320 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 21:56:08,321 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 21:56:08,321 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 21:56:08,321 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 21:56:08,321 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 21:56:08,322 INFO L87 Difference]: Start difference. First operand 1104 states and 1637 transitions. cyclomatic complexity: 534 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 21:56:08,348 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 21:56:08,349 INFO L93 Difference]: Finished difference Result 1104 states and 1636 transitions. [2024-10-31 21:56:08,349 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1104 states and 1636 transitions. [2024-10-31 21:56:08,355 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 979 [2024-10-31 21:56:08,359 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1104 states to 1104 states and 1636 transitions. [2024-10-31 21:56:08,360 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1104 [2024-10-31 21:56:08,360 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1104 [2024-10-31 21:56:08,361 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1104 states and 1636 transitions. [2024-10-31 21:56:08,362 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 21:56:08,362 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1104 states and 1636 transitions. [2024-10-31 21:56:08,364 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1104 states and 1636 transitions. [2024-10-31 21:56:08,376 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1104 to 1104. [2024-10-31 21:56:08,379 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1104 states, 1104 states have (on average 1.4818840579710144) internal successors, (1636), 1103 states have internal predecessors, (1636), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 21:56:08,382 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1104 states to 1104 states and 1636 transitions. [2024-10-31 21:56:08,382 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1104 states and 1636 transitions. [2024-10-31 21:56:08,383 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 21:56:08,384 INFO L425 stractBuchiCegarLoop]: Abstraction has 1104 states and 1636 transitions. [2024-10-31 21:56:08,384 INFO L332 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-10-31 21:56:08,385 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1104 states and 1636 transitions. [2024-10-31 21:56:08,390 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 979 [2024-10-31 21:56:08,390 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 21:56:08,390 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 21:56:08,392 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 21:56:08,392 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 21:56:08,392 INFO L745 eck$LassoCheckResult]: Stem: 11376#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 11377#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 12133#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12134#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12085#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 12086#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12068#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11890#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 11891#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 11699#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 11700#L666-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 12155#L671-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 12060#L676-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 11759#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 11530#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11531#L922 assume !(0 == ~M_E~0); 12191#L922-2 assume !(0 == ~T1_E~0); 12192#L927-1 assume !(0 == ~T2_E~0); 11954#L932-1 assume !(0 == ~T3_E~0); 11829#L937-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11830#L942-1 assume !(0 == ~T5_E~0); 11889#L947-1 assume !(0 == ~T6_E~0); 11958#L952-1 assume !(0 == ~T7_E~0); 11959#L957-1 assume !(0 == ~T8_E~0); 12019#L962-1 assume !(0 == ~T9_E~0); 11808#L967-1 assume !(0 == ~E_1~0); 11809#L972-1 assume !(0 == ~E_2~0); 12072#L977-1 assume 0 == ~E_3~0;~E_3~0 := 1; 12073#L982-1 assume !(0 == ~E_4~0); 11309#L987-1 assume !(0 == ~E_5~0); 11310#L992-1 assume !(0 == ~E_6~0); 11314#L997-1 assume !(0 == ~E_7~0); 11737#L1002-1 assume !(0 == ~E_8~0); 11724#L1007-1 assume !(0 == ~E_9~0); 11101#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11102#L443 assume !(1 == ~m_pc~0); 11974#L443-2 is_master_triggered_~__retres1~0#1 := 0; 11966#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11967#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11469#L1140 assume !(0 != activate_threads_~tmp~1#1); 11206#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11207#L462 assume 1 == ~t1_pc~0; 11855#L463 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 11824#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11145#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 11146#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 11678#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11679#L481 assume !(1 == ~t2_pc~0); 11463#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 11462#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11589#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 11553#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 11554#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11648#L500 assume 1 == ~t3_pc~0; 11874#L501 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11875#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11108#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11109#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 11106#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11107#L519 assume 1 == ~t4_pc~0; 11409#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 11410#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11208#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11209#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 11505#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11270#L538 assume !(1 == ~t5_pc~0); 11271#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 11170#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11171#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11449#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 11450#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12003#L557 assume 1 == ~t6_pc~0; 11796#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11484#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11571#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11506#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 11507#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12178#L576 assume !(1 == ~t7_pc~0); 11473#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 11474#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11795#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12188#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 12052#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11592#L595 assume 1 == ~t8_pc~0; 11593#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 12065#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12008#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 11913#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 11914#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11399#L614 assume !(1 == ~t9_pc~0); 11400#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 11296#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11297#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 11622#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 11556#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11557#L1025 assume !(1 == ~M_E~0); 11815#L1025-2 assume !(1 == ~T1_E~0); 11873#L1030-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11997#L1035-1 assume !(1 == ~T3_E~0); 11549#L1040-1 assume !(1 == ~T4_E~0); 11550#L1045-1 assume !(1 == ~T5_E~0); 11459#L1050-1 assume !(1 == ~T6_E~0); 11460#L1055-1 assume !(1 == ~T7_E~0); 11281#L1060-1 assume !(1 == ~T8_E~0); 11282#L1065-1 assume !(1 == ~T9_E~0); 11346#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 11961#L1075-1 assume !(1 == ~E_2~0); 11962#L1080-1 assume !(1 == ~E_3~0); 11949#L1085-1 assume !(1 == ~E_4~0); 11950#L1090-1 assume !(1 == ~E_5~0); 12149#L1095-1 assume !(1 == ~E_6~0); 11983#L1100-1 assume !(1 == ~E_7~0); 11984#L1105-1 assume !(1 == ~E_8~0); 11252#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 11253#L1115-1 assume { :end_inline_reset_delta_events } true; 11418#L1396-2 [2024-10-31 21:56:08,392 INFO L747 eck$LassoCheckResult]: Loop: 11418#L1396-2 assume !false; 11498#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12153#L897-1 assume !false; 12176#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 12087#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 11126#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 11127#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 11610#L766 assume !(0 != eval_~tmp~0#1); 12012#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11767#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11719#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 11720#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11441#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11442#L932-3 assume !(0 == ~T3_E~0); 11615#L937-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11244#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11245#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11616#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 11617#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 12138#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 12033#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 12034#L972-3 assume !(0 == ~E_2~0); 11952#L977-3 assume 0 == ~E_3~0;~E_3~0 := 1; 11953#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12193#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 11569#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 11570#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 11564#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 11565#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 11283#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11284#L443-30 assume 1 == ~m_pc~0; 11317#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 11318#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11596#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11601#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12076#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11706#L462-30 assume 1 == ~t1_pc~0; 11538#L463-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 11539#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11825#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 11826#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12101#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11691#L481-30 assume !(1 == ~t2_pc~0); 11408#L481-32 is_transmit2_triggered_~__retres1~2#1 := 0; 11407#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11499#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 11378#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 11379#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11651#L500-30 assume 1 == ~t3_pc~0; 11414#L501-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11415#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11744#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11800#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 11635#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11636#L519-30 assume 1 == ~t4_pc~0; 11988#L520-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 11801#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11802#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11812#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 11813#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11932#L538-30 assume 1 == ~t5_pc~0; 11292#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 11293#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11619#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11919#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 11372#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11373#L557-30 assume 1 == ~t6_pc~0; 11091#L558-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11093#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11212#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11213#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 11397#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11398#L576-30 assume 1 == ~t7_pc~0; 11922#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11167#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11774#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11981#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 11548#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11512#L595-30 assume !(1 == ~t8_pc~0); 11513#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 11453#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 11454#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12147#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 12148#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12179#L614-30 assume 1 == ~t9_pc~0; 11456#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 11457#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11130#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 11131#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 11285#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11906#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 11680#L1025-5 assume !(1 == ~T1_E~0); 11681#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11878#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12157#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12189#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12152#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12064#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 11176#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 11177#L1065-3 assume !(1 == ~T9_E~0); 12078#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 11935#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 11936#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 12158#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12069#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12070#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12089#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12090#L1105-3 assume !(1 == ~E_8~0); 11331#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 11332#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 12106#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 11187#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 11340#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 11532#L1415 assume !(0 == start_simulation_~tmp~3#1); 11806#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 11807#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 11240#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 11141#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 11142#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12194#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11797#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 11417#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 11418#L1396-2 [2024-10-31 21:56:08,393 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 21:56:08,393 INFO L85 PathProgramCache]: Analyzing trace with hash 234490531, now seen corresponding path program 1 times [2024-10-31 21:56:08,393 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 21:56:08,393 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1904657930] [2024-10-31 21:56:08,393 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 21:56:08,394 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 21:56:08,407 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 21:56:08,446 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 21:56:08,447 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 21:56:08,447 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1904657930] [2024-10-31 21:56:08,447 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1904657930] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 21:56:08,451 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 21:56:08,451 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 21:56:08,451 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1878759018] [2024-10-31 21:56:08,451 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 21:56:08,451 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 21:56:08,452 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 21:56:08,452 INFO L85 PathProgramCache]: Analyzing trace with hash -1124783627, now seen corresponding path program 1 times [2024-10-31 21:56:08,452 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 21:56:08,452 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1380065483] [2024-10-31 21:56:08,452 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 21:56:08,453 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 21:56:08,470 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 21:56:08,517 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 21:56:08,517 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 21:56:08,518 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1380065483] [2024-10-31 21:56:08,518 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1380065483] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 21:56:08,518 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 21:56:08,518 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 21:56:08,518 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2028791527] [2024-10-31 21:56:08,518 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 21:56:08,520 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 21:56:08,520 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 21:56:08,521 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 21:56:08,521 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 21:56:08,521 INFO L87 Difference]: Start difference. First operand 1104 states and 1636 transitions. cyclomatic complexity: 533 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 21:56:08,547 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 21:56:08,547 INFO L93 Difference]: Finished difference Result 1104 states and 1635 transitions. [2024-10-31 21:56:08,548 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1104 states and 1635 transitions. [2024-10-31 21:56:08,554 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 979 [2024-10-31 21:56:08,559 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1104 states to 1104 states and 1635 transitions. [2024-10-31 21:56:08,559 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1104 [2024-10-31 21:56:08,560 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1104 [2024-10-31 21:56:08,560 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1104 states and 1635 transitions. [2024-10-31 21:56:08,562 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 21:56:08,562 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1104 states and 1635 transitions. [2024-10-31 21:56:08,564 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1104 states and 1635 transitions. [2024-10-31 21:56:08,575 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1104 to 1104. [2024-10-31 21:56:08,577 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1104 states, 1104 states have (on average 1.4809782608695652) internal successors, (1635), 1103 states have internal predecessors, (1635), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 21:56:08,581 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1104 states to 1104 states and 1635 transitions. [2024-10-31 21:56:08,581 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1104 states and 1635 transitions. [2024-10-31 21:56:08,584 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 21:56:08,584 INFO L425 stractBuchiCegarLoop]: Abstraction has 1104 states and 1635 transitions. [2024-10-31 21:56:08,585 INFO L332 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-10-31 21:56:08,585 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1104 states and 1635 transitions. [2024-10-31 21:56:08,590 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 979 [2024-10-31 21:56:08,591 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 21:56:08,591 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 21:56:08,592 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 21:56:08,592 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 21:56:08,593 INFO L745 eck$LassoCheckResult]: Stem: 13591#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 13592#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 14348#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14349#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14300#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 14301#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14283#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14105#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14106#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 13914#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 13915#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 14370#L671-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 14275#L676-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 13974#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 13745#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13746#L922 assume !(0 == ~M_E~0); 14406#L922-2 assume !(0 == ~T1_E~0); 14407#L927-1 assume !(0 == ~T2_E~0); 14169#L932-1 assume !(0 == ~T3_E~0); 14044#L937-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14045#L942-1 assume !(0 == ~T5_E~0); 14104#L947-1 assume !(0 == ~T6_E~0); 14173#L952-1 assume !(0 == ~T7_E~0); 14174#L957-1 assume !(0 == ~T8_E~0); 14234#L962-1 assume !(0 == ~T9_E~0); 14025#L967-1 assume !(0 == ~E_1~0); 14026#L972-1 assume !(0 == ~E_2~0); 14287#L977-1 assume 0 == ~E_3~0;~E_3~0 := 1; 14288#L982-1 assume !(0 == ~E_4~0); 13524#L987-1 assume !(0 == ~E_5~0); 13525#L992-1 assume !(0 == ~E_6~0); 13529#L997-1 assume !(0 == ~E_7~0); 13952#L1002-1 assume !(0 == ~E_8~0); 13939#L1007-1 assume !(0 == ~E_9~0); 13316#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13317#L443 assume !(1 == ~m_pc~0); 14189#L443-2 is_master_triggered_~__retres1~0#1 := 0; 14181#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14182#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 13684#L1140 assume !(0 != activate_threads_~tmp~1#1); 13421#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13422#L462 assume 1 == ~t1_pc~0; 14070#L463 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14039#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13360#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 13361#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 13893#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13894#L481 assume !(1 == ~t2_pc~0); 13678#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 13677#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13804#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 13768#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 13769#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13863#L500 assume 1 == ~t3_pc~0; 14089#L501 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14090#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13323#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 13324#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 13321#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13322#L519 assume 1 == ~t4_pc~0; 13624#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13625#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13423#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13424#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 13720#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13485#L538 assume !(1 == ~t5_pc~0); 13486#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 13385#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13386#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13664#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 13665#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14219#L557 assume 1 == ~t6_pc~0; 14011#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13699#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13786#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13721#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 13722#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14393#L576 assume !(1 == ~t7_pc~0); 13688#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 13689#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14010#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14403#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 14267#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 13805#L595 assume 1 == ~t8_pc~0; 13806#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 14280#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14221#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14128#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 14129#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13614#L614 assume !(1 == ~t9_pc~0); 13615#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 13510#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 13511#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13837#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 13771#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13772#L1025 assume !(1 == ~M_E~0); 14030#L1025-2 assume !(1 == ~T1_E~0); 14088#L1030-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14211#L1035-1 assume !(1 == ~T3_E~0); 13763#L1040-1 assume !(1 == ~T4_E~0); 13764#L1045-1 assume !(1 == ~T5_E~0); 13674#L1050-1 assume !(1 == ~T6_E~0); 13675#L1055-1 assume !(1 == ~T7_E~0); 13496#L1060-1 assume !(1 == ~T8_E~0); 13497#L1065-1 assume !(1 == ~T9_E~0); 13561#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 14175#L1075-1 assume !(1 == ~E_2~0); 14176#L1080-1 assume !(1 == ~E_3~0); 14164#L1085-1 assume !(1 == ~E_4~0); 14165#L1090-1 assume !(1 == ~E_5~0); 14364#L1095-1 assume !(1 == ~E_6~0); 14198#L1100-1 assume !(1 == ~E_7~0); 14199#L1105-1 assume !(1 == ~E_8~0); 13467#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 13468#L1115-1 assume { :end_inline_reset_delta_events } true; 13635#L1396-2 [2024-10-31 21:56:08,593 INFO L747 eck$LassoCheckResult]: Loop: 13635#L1396-2 assume !false; 13710#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 14368#L897-1 assume !false; 14391#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 14302#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 13339#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 13340#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 13825#L766 assume !(0 != eval_~tmp~0#1); 14226#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 13979#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 13931#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 13932#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13656#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13657#L932-3 assume !(0 == ~T3_E~0); 13830#L937-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13459#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13460#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 13831#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 13832#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 14353#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 14248#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14249#L972-3 assume !(0 == ~E_2~0); 14167#L977-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14168#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 14408#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 13784#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 13785#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 13779#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 13780#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 13498#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13499#L443-30 assume 1 == ~m_pc~0; 13532#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 13533#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13811#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 13816#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14291#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13921#L462-30 assume 1 == ~t1_pc~0; 13753#L463-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 13754#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14040#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 14041#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14316#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13906#L481-30 assume 1 == ~t2_pc~0; 13621#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13622#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13714#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 13593#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 13594#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13866#L500-30 assume 1 == ~t3_pc~0; 13629#L501-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 13630#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13959#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14015#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13850#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13851#L519-30 assume !(1 == ~t4_pc~0); 14037#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 14016#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14017#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14027#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 14028#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14147#L538-30 assume 1 == ~t5_pc~0; 13507#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 13508#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13834#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14134#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 13587#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13588#L557-30 assume 1 == ~t6_pc~0; 13306#L558-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13308#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13427#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13428#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 13612#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13613#L576-30 assume !(1 == ~t7_pc~0); 13381#L576-32 is_transmit7_triggered_~__retres1~7#1 := 0; 13382#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13989#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14196#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 13765#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 13727#L595-30 assume !(1 == ~t8_pc~0); 13728#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 13668#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 13669#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14362#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 14363#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 14394#L614-30 assume 1 == ~t9_pc~0; 13671#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 13672#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 13345#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13346#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 13500#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14121#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 13895#L1025-5 assume !(1 == ~T1_E~0); 13896#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14093#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14372#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14404#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14367#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 14279#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 13391#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 13392#L1065-3 assume !(1 == ~T9_E~0); 14293#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 14150#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 14151#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 14373#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14284#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14285#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 14304#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 14305#L1105-3 assume !(1 == ~E_8~0); 13546#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 13547#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 14321#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 13402#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 13555#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 13747#L1415 assume !(0 == start_simulation_~tmp~3#1); 14021#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 14022#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 13455#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 13356#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 13357#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 14409#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14012#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 13634#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 13635#L1396-2 [2024-10-31 21:56:08,594 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 21:56:08,594 INFO L85 PathProgramCache]: Analyzing trace with hash 116049057, now seen corresponding path program 1 times [2024-10-31 21:56:08,594 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 21:56:08,595 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1009849031] [2024-10-31 21:56:08,595 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 21:56:08,595 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 21:56:08,607 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 21:56:08,647 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 21:56:08,647 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 21:56:08,647 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1009849031] [2024-10-31 21:56:08,648 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1009849031] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 21:56:08,648 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 21:56:08,649 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 21:56:08,649 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [396524861] [2024-10-31 21:56:08,649 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 21:56:08,649 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 21:56:08,650 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 21:56:08,650 INFO L85 PathProgramCache]: Analyzing trace with hash -2034235564, now seen corresponding path program 2 times [2024-10-31 21:56:08,650 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 21:56:08,650 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [271420807] [2024-10-31 21:56:08,651 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 21:56:08,651 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 21:56:08,667 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 21:56:08,723 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 21:56:08,723 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 21:56:08,723 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [271420807] [2024-10-31 21:56:08,723 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [271420807] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 21:56:08,723 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 21:56:08,724 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 21:56:08,724 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1850827293] [2024-10-31 21:56:08,724 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 21:56:08,724 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 21:56:08,724 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 21:56:08,725 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 21:56:08,725 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 21:56:08,725 INFO L87 Difference]: Start difference. First operand 1104 states and 1635 transitions. cyclomatic complexity: 532 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 21:56:08,754 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 21:56:08,754 INFO L93 Difference]: Finished difference Result 1104 states and 1634 transitions. [2024-10-31 21:56:08,754 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1104 states and 1634 transitions. [2024-10-31 21:56:08,761 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 979 [2024-10-31 21:56:08,767 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1104 states to 1104 states and 1634 transitions. [2024-10-31 21:56:08,767 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1104 [2024-10-31 21:56:08,768 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1104 [2024-10-31 21:56:08,769 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1104 states and 1634 transitions. [2024-10-31 21:56:08,770 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 21:56:08,771 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1104 states and 1634 transitions. [2024-10-31 21:56:08,773 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1104 states and 1634 transitions. [2024-10-31 21:56:08,786 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1104 to 1104. [2024-10-31 21:56:08,789 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1104 states, 1104 states have (on average 1.480072463768116) internal successors, (1634), 1103 states have internal predecessors, (1634), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 21:56:08,792 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1104 states to 1104 states and 1634 transitions. [2024-10-31 21:56:08,793 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1104 states and 1634 transitions. [2024-10-31 21:56:08,793 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 21:56:08,795 INFO L425 stractBuchiCegarLoop]: Abstraction has 1104 states and 1634 transitions. [2024-10-31 21:56:08,795 INFO L332 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-10-31 21:56:08,795 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1104 states and 1634 transitions. [2024-10-31 21:56:08,801 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 979 [2024-10-31 21:56:08,801 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 21:56:08,801 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 21:56:08,803 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 21:56:08,803 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 21:56:08,833 INFO L745 eck$LassoCheckResult]: Stem: 15804#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 15805#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 16563#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16564#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16515#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 16516#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16498#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 16320#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 16321#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 16128#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 16129#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 16584#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 16489#L676-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 16189#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 15960#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15961#L922 assume !(0 == ~M_E~0); 16621#L922-2 assume !(0 == ~T1_E~0); 16622#L927-1 assume !(0 == ~T2_E~0); 16384#L932-1 assume !(0 == ~T3_E~0); 16259#L937-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 16260#L942-1 assume !(0 == ~T5_E~0); 16319#L947-1 assume !(0 == ~T6_E~0); 16388#L952-1 assume !(0 == ~T7_E~0); 16389#L957-1 assume !(0 == ~T8_E~0); 16446#L962-1 assume !(0 == ~T9_E~0); 16238#L967-1 assume !(0 == ~E_1~0); 16239#L972-1 assume !(0 == ~E_2~0); 16502#L977-1 assume 0 == ~E_3~0;~E_3~0 := 1; 16503#L982-1 assume !(0 == ~E_4~0); 15737#L987-1 assume !(0 == ~E_5~0); 15738#L992-1 assume !(0 == ~E_6~0); 15744#L997-1 assume !(0 == ~E_7~0); 16165#L1002-1 assume !(0 == ~E_8~0); 16154#L1007-1 assume !(0 == ~E_9~0); 15531#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15532#L443 assume !(1 == ~m_pc~0); 16404#L443-2 is_master_triggered_~__retres1~0#1 := 0; 16396#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16397#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 15899#L1140 assume !(0 != activate_threads_~tmp~1#1); 15636#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15637#L462 assume 1 == ~t1_pc~0; 16285#L463 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 16251#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15573#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 15574#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 16106#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16107#L481 assume !(1 == ~t2_pc~0); 15893#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 15892#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16019#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15983#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 15984#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16076#L500 assume 1 == ~t3_pc~0; 16304#L501 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 16305#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15538#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 15539#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 15533#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15534#L519 assume 1 == ~t4_pc~0; 15836#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 15837#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15638#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15639#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 15933#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15700#L538 assume !(1 == ~t5_pc~0); 15701#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 15598#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15599#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15879#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 15880#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16431#L557 assume 1 == ~t6_pc~0; 16226#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 15914#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16001#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15934#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 15935#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16608#L576 assume !(1 == ~t7_pc~0); 15903#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 15904#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16225#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16618#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 16482#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16020#L595 assume 1 == ~t8_pc~0; 16021#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16495#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16436#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16343#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 16344#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 15829#L614 assume !(1 == ~t9_pc~0); 15830#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 15725#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 15726#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 16052#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 15986#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15987#L1025 assume !(1 == ~M_E~0); 16245#L1025-2 assume !(1 == ~T1_E~0); 16303#L1030-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 16426#L1035-1 assume !(1 == ~T3_E~0); 15978#L1040-1 assume !(1 == ~T4_E~0); 15979#L1045-1 assume !(1 == ~T5_E~0); 15889#L1050-1 assume !(1 == ~T6_E~0); 15890#L1055-1 assume !(1 == ~T7_E~0); 15711#L1060-1 assume !(1 == ~T8_E~0); 15712#L1065-1 assume !(1 == ~T9_E~0); 15776#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 16390#L1075-1 assume !(1 == ~E_2~0); 16391#L1080-1 assume !(1 == ~E_3~0); 16379#L1085-1 assume !(1 == ~E_4~0); 16380#L1090-1 assume !(1 == ~E_5~0); 16579#L1095-1 assume !(1 == ~E_6~0); 16413#L1100-1 assume !(1 == ~E_7~0); 16414#L1105-1 assume !(1 == ~E_8~0); 15682#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 15683#L1115-1 assume { :end_inline_reset_delta_events } true; 15850#L1396-2 [2024-10-31 21:56:08,833 INFO L747 eck$LassoCheckResult]: Loop: 15850#L1396-2 assume !false; 15925#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16583#L897-1 assume !false; 16606#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 16517#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 15554#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 15555#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 16040#L766 assume !(0 != eval_~tmp~0#1); 16441#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 16194#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 16146#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 16147#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 15871#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 15872#L932-3 assume !(0 == ~T3_E~0); 16045#L937-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 15674#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 15675#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 16046#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 16047#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16568#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 16463#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 16464#L972-3 assume !(0 == ~E_2~0); 16382#L977-3 assume 0 == ~E_3~0;~E_3~0 := 1; 16383#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 16623#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 15999#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 16000#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 15994#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 15995#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 15713#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15714#L443-30 assume 1 == ~m_pc~0; 15747#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 15748#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16026#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 16031#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16506#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16136#L462-30 assume 1 == ~t1_pc~0; 15968#L463-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 15969#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16255#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 16256#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 16531#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16121#L481-30 assume !(1 == ~t2_pc~0); 15841#L481-32 is_transmit2_triggered_~__retres1~2#1 := 0; 15840#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15929#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15808#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 15809#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16081#L500-30 assume 1 == ~t3_pc~0; 15844#L501-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15845#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16174#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 16230#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 16065#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16066#L519-30 assume 1 == ~t4_pc~0; 16418#L520-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 16231#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16232#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16242#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 16243#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16362#L538-30 assume 1 == ~t5_pc~0; 15722#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15723#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16049#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16349#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 15802#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15803#L557-30 assume 1 == ~t6_pc~0; 15521#L558-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 15523#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15642#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15643#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 15827#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15828#L576-30 assume 1 == ~t7_pc~0; 16352#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 15597#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16204#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16411#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 15980#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15942#L595-30 assume !(1 == ~t8_pc~0); 15943#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 15883#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15884#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16577#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 16578#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16609#L614-30 assume !(1 == ~t9_pc~0); 15888#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 15887#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 15560#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 15561#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 15715#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16336#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 16110#L1025-5 assume !(1 == ~T1_E~0); 16111#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 16308#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 16587#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16619#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 16582#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 16494#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 15606#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 15607#L1065-3 assume !(1 == ~T9_E~0); 16508#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 16365#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 16366#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 16588#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 16499#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 16500#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 16519#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 16520#L1105-3 assume !(1 == ~E_8~0); 15761#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 15762#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 16536#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 15617#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 15770#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 15962#L1415 assume !(0 == start_simulation_~tmp~3#1); 16236#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 16237#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 15670#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 15571#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 15572#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 16624#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16227#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 15849#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 15850#L1396-2 [2024-10-31 21:56:08,836 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 21:56:08,836 INFO L85 PathProgramCache]: Analyzing trace with hash -1273244957, now seen corresponding path program 1 times [2024-10-31 21:56:08,836 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 21:56:08,837 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1085531903] [2024-10-31 21:56:08,838 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 21:56:08,838 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 21:56:08,856 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 21:56:08,891 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 21:56:08,892 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 21:56:08,892 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1085531903] [2024-10-31 21:56:08,893 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1085531903] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 21:56:08,893 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 21:56:08,893 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 21:56:08,893 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [422142861] [2024-10-31 21:56:08,894 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 21:56:08,894 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 21:56:08,894 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 21:56:08,894 INFO L85 PathProgramCache]: Analyzing trace with hash -601462956, now seen corresponding path program 1 times [2024-10-31 21:56:08,895 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 21:56:08,895 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [351642216] [2024-10-31 21:56:08,895 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 21:56:08,895 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 21:56:08,914 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 21:56:08,965 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 21:56:08,966 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 21:56:08,966 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [351642216] [2024-10-31 21:56:08,968 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [351642216] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 21:56:08,968 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 21:56:08,968 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 21:56:08,969 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [222152803] [2024-10-31 21:56:08,969 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 21:56:08,969 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 21:56:08,969 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 21:56:08,970 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 21:56:08,970 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 21:56:08,970 INFO L87 Difference]: Start difference. First operand 1104 states and 1634 transitions. cyclomatic complexity: 531 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 21:56:08,997 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 21:56:08,998 INFO L93 Difference]: Finished difference Result 1104 states and 1633 transitions. [2024-10-31 21:56:08,998 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1104 states and 1633 transitions. [2024-10-31 21:56:09,005 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 979 [2024-10-31 21:56:09,011 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1104 states to 1104 states and 1633 transitions. [2024-10-31 21:56:09,011 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1104 [2024-10-31 21:56:09,013 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1104 [2024-10-31 21:56:09,013 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1104 states and 1633 transitions. [2024-10-31 21:56:09,014 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 21:56:09,015 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1104 states and 1633 transitions. [2024-10-31 21:56:09,016 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1104 states and 1633 transitions. [2024-10-31 21:56:09,030 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1104 to 1104. [2024-10-31 21:56:09,032 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1104 states, 1104 states have (on average 1.4791666666666667) internal successors, (1633), 1103 states have internal predecessors, (1633), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 21:56:09,036 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1104 states to 1104 states and 1633 transitions. [2024-10-31 21:56:09,036 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1104 states and 1633 transitions. [2024-10-31 21:56:09,036 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 21:56:09,037 INFO L425 stractBuchiCegarLoop]: Abstraction has 1104 states and 1633 transitions. [2024-10-31 21:56:09,038 INFO L332 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-10-31 21:56:09,038 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1104 states and 1633 transitions. [2024-10-31 21:56:09,043 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 979 [2024-10-31 21:56:09,044 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 21:56:09,045 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 21:56:09,046 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 21:56:09,047 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 21:56:09,047 INFO L745 eck$LassoCheckResult]: Stem: 18019#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 18020#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 18778#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 18779#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 18730#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 18731#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 18713#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 18535#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 18536#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 18343#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 18344#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 18799#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 18704#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 18404#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 18175#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 18176#L922 assume !(0 == ~M_E~0); 18836#L922-2 assume !(0 == ~T1_E~0); 18837#L927-1 assume !(0 == ~T2_E~0); 18599#L932-1 assume !(0 == ~T3_E~0); 18474#L937-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 18475#L942-1 assume !(0 == ~T5_E~0); 18534#L947-1 assume !(0 == ~T6_E~0); 18603#L952-1 assume !(0 == ~T7_E~0); 18604#L957-1 assume !(0 == ~T8_E~0); 18661#L962-1 assume !(0 == ~T9_E~0); 18453#L967-1 assume !(0 == ~E_1~0); 18454#L972-1 assume !(0 == ~E_2~0); 18717#L977-1 assume 0 == ~E_3~0;~E_3~0 := 1; 18718#L982-1 assume !(0 == ~E_4~0); 17952#L987-1 assume !(0 == ~E_5~0); 17953#L992-1 assume !(0 == ~E_6~0); 17959#L997-1 assume !(0 == ~E_7~0); 18380#L1002-1 assume !(0 == ~E_8~0); 18369#L1007-1 assume !(0 == ~E_9~0); 17746#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17747#L443 assume !(1 == ~m_pc~0); 18619#L443-2 is_master_triggered_~__retres1~0#1 := 0; 18611#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18612#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 18114#L1140 assume !(0 != activate_threads_~tmp~1#1); 17851#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17852#L462 assume 1 == ~t1_pc~0; 18500#L463 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 18466#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17788#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 17789#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 18321#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18322#L481 assume !(1 == ~t2_pc~0); 18108#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 18107#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18234#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 18198#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 18199#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18291#L500 assume 1 == ~t3_pc~0; 18519#L501 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 18520#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17753#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 17754#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 17748#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17749#L519 assume 1 == ~t4_pc~0; 18051#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 18052#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17853#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 17854#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 18148#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17915#L538 assume !(1 == ~t5_pc~0); 17916#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 17813#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17814#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 18094#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 18095#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18646#L557 assume 1 == ~t6_pc~0; 18441#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 18129#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18216#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18149#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 18150#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18823#L576 assume !(1 == ~t7_pc~0); 18118#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 18119#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 18440#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18833#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 18697#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18235#L595 assume 1 == ~t8_pc~0; 18236#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 18710#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 18651#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 18558#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 18559#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 18044#L614 assume !(1 == ~t9_pc~0); 18045#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 17940#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17941#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 18267#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 18201#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18202#L1025 assume !(1 == ~M_E~0); 18460#L1025-2 assume !(1 == ~T1_E~0); 18518#L1030-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 18641#L1035-1 assume !(1 == ~T3_E~0); 18193#L1040-1 assume !(1 == ~T4_E~0); 18194#L1045-1 assume !(1 == ~T5_E~0); 18104#L1050-1 assume !(1 == ~T6_E~0); 18105#L1055-1 assume !(1 == ~T7_E~0); 17926#L1060-1 assume !(1 == ~T8_E~0); 17927#L1065-1 assume !(1 == ~T9_E~0); 17991#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 18605#L1075-1 assume !(1 == ~E_2~0); 18606#L1080-1 assume !(1 == ~E_3~0); 18594#L1085-1 assume !(1 == ~E_4~0); 18595#L1090-1 assume !(1 == ~E_5~0); 18794#L1095-1 assume !(1 == ~E_6~0); 18628#L1100-1 assume !(1 == ~E_7~0); 18629#L1105-1 assume !(1 == ~E_8~0); 17897#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 17898#L1115-1 assume { :end_inline_reset_delta_events } true; 18065#L1396-2 [2024-10-31 21:56:09,048 INFO L747 eck$LassoCheckResult]: Loop: 18065#L1396-2 assume !false; 18140#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 18798#L897-1 assume !false; 18821#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 18732#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 17769#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 17770#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 18255#L766 assume !(0 != eval_~tmp~0#1); 18656#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 18409#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 18361#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 18362#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 18086#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 18087#L932-3 assume !(0 == ~T3_E~0); 18260#L937-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17889#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 17890#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 18261#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 18262#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 18783#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 18678#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 18679#L972-3 assume !(0 == ~E_2~0); 18597#L977-3 assume 0 == ~E_3~0;~E_3~0 := 1; 18598#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 18838#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 18214#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 18215#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 18209#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 18210#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 17928#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17929#L443-30 assume 1 == ~m_pc~0; 17962#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 17963#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18241#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 18246#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 18721#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18351#L462-30 assume 1 == ~t1_pc~0; 18183#L463-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 18184#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18470#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 18471#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 18746#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18336#L481-30 assume 1 == ~t2_pc~0; 18054#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 18055#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18144#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 18023#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 18024#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18296#L500-30 assume 1 == ~t3_pc~0; 18059#L501-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 18060#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18389#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 18445#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 18280#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 18281#L519-30 assume !(1 == ~t4_pc~0); 18469#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 18446#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18447#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 18457#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 18458#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18577#L538-30 assume 1 == ~t5_pc~0; 17937#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 17938#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18264#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 18564#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 18017#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18018#L557-30 assume 1 == ~t6_pc~0; 17736#L558-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 17738#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17857#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17858#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 18042#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18043#L576-30 assume !(1 == ~t7_pc~0); 17811#L576-32 is_transmit7_triggered_~__retres1~7#1 := 0; 17812#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 18419#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18626#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 18195#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18157#L595-30 assume !(1 == ~t8_pc~0); 18158#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 18098#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 18099#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 18792#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 18793#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 18824#L614-30 assume 1 == ~t9_pc~0; 18101#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 18102#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17775#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17776#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 17930#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18551#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 18325#L1025-5 assume !(1 == ~T1_E~0); 18326#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 18523#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 18802#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 18834#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 18797#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 18709#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 17821#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 17822#L1065-3 assume !(1 == ~T9_E~0); 18723#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 18580#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 18581#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 18803#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 18714#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 18715#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 18734#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 18735#L1105-3 assume !(1 == ~E_8~0); 17976#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 17977#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 18751#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 17832#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 17985#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 18177#L1415 assume !(0 == start_simulation_~tmp~3#1); 18451#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 18452#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 17885#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 17786#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 17787#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 18839#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 18442#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 18064#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 18065#L1396-2 [2024-10-31 21:56:09,048 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 21:56:09,048 INFO L85 PathProgramCache]: Analyzing trace with hash 760149089, now seen corresponding path program 1 times [2024-10-31 21:56:09,049 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 21:56:09,049 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [601512022] [2024-10-31 21:56:09,049 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 21:56:09,049 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 21:56:09,066 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 21:56:09,149 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 21:56:09,149 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 21:56:09,149 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [601512022] [2024-10-31 21:56:09,150 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [601512022] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 21:56:09,150 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 21:56:09,150 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 21:56:09,150 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1125548891] [2024-10-31 21:56:09,150 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 21:56:09,151 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 21:56:09,151 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 21:56:09,152 INFO L85 PathProgramCache]: Analyzing trace with hash -2034235564, now seen corresponding path program 3 times [2024-10-31 21:56:09,152 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 21:56:09,152 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [878554433] [2024-10-31 21:56:09,152 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 21:56:09,153 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 21:56:09,170 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 21:56:09,225 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 21:56:09,225 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 21:56:09,225 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [878554433] [2024-10-31 21:56:09,225 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [878554433] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 21:56:09,226 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 21:56:09,226 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 21:56:09,226 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1815481153] [2024-10-31 21:56:09,226 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 21:56:09,226 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 21:56:09,227 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 21:56:09,227 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-10-31 21:56:09,227 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-10-31 21:56:09,227 INFO L87 Difference]: Start difference. First operand 1104 states and 1633 transitions. cyclomatic complexity: 530 Second operand has 4 states, 4 states have (on average 28.75) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 21:56:09,394 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 21:56:09,394 INFO L93 Difference]: Finished difference Result 2100 states and 3099 transitions. [2024-10-31 21:56:09,394 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2100 states and 3099 transitions. [2024-10-31 21:56:09,406 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1958 [2024-10-31 21:56:09,415 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2100 states to 2100 states and 3099 transitions. [2024-10-31 21:56:09,416 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2100 [2024-10-31 21:56:09,418 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2100 [2024-10-31 21:56:09,418 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2100 states and 3099 transitions. [2024-10-31 21:56:09,421 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 21:56:09,422 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2100 states and 3099 transitions. [2024-10-31 21:56:09,424 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2100 states and 3099 transitions. [2024-10-31 21:56:09,455 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2100 to 2100. [2024-10-31 21:56:09,459 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2100 states, 2100 states have (on average 1.4757142857142858) internal successors, (3099), 2099 states have internal predecessors, (3099), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 21:56:09,465 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2100 states to 2100 states and 3099 transitions. [2024-10-31 21:56:09,465 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2100 states and 3099 transitions. [2024-10-31 21:56:09,466 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-10-31 21:56:09,467 INFO L425 stractBuchiCegarLoop]: Abstraction has 2100 states and 3099 transitions. [2024-10-31 21:56:09,467 INFO L332 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-10-31 21:56:09,468 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2100 states and 3099 transitions. [2024-10-31 21:56:09,476 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1958 [2024-10-31 21:56:09,477 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 21:56:09,477 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 21:56:09,478 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 21:56:09,479 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 21:56:09,479 INFO L745 eck$LassoCheckResult]: Stem: 21234#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 21235#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 22035#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 22036#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21976#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 21977#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21954#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21757#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21758#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 21561#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 21562#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 22065#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 21944#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 21621#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 21390#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 21391#L922 assume !(0 == ~M_E~0); 22129#L922-2 assume !(0 == ~T1_E~0); 22130#L927-1 assume !(0 == ~T2_E~0); 21821#L932-1 assume !(0 == ~T3_E~0); 21695#L937-1 assume !(0 == ~T4_E~0); 21696#L942-1 assume !(0 == ~T5_E~0); 21756#L947-1 assume !(0 == ~T6_E~0); 21825#L952-1 assume !(0 == ~T7_E~0); 21826#L957-1 assume !(0 == ~T8_E~0); 21890#L962-1 assume !(0 == ~T9_E~0); 21673#L967-1 assume !(0 == ~E_1~0); 21674#L972-1 assume !(0 == ~E_2~0); 21959#L977-1 assume 0 == ~E_3~0;~E_3~0 := 1; 21960#L982-1 assume !(0 == ~E_4~0); 21166#L987-1 assume !(0 == ~E_5~0); 21167#L992-1 assume !(0 == ~E_6~0); 21173#L997-1 assume !(0 == ~E_7~0); 21597#L1002-1 assume !(0 == ~E_8~0); 21586#L1007-1 assume !(0 == ~E_9~0); 20960#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20961#L443 assume !(1 == ~m_pc~0); 21841#L443-2 is_master_triggered_~__retres1~0#1 := 0; 21833#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21834#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 21329#L1140 assume !(0 != activate_threads_~tmp~1#1); 21065#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21066#L462 assume 1 == ~t1_pc~0; 21721#L463 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 21687#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21002#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 21003#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 21540#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21541#L481 assume !(1 == ~t2_pc~0); 21323#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 21322#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21451#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 21414#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 21415#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21508#L500 assume 1 == ~t3_pc~0; 21741#L501 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 21742#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20967#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 20968#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 20962#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20963#L519 assume 1 == ~t4_pc~0; 21266#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21267#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21067#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 21068#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 21363#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 21129#L538 assume !(1 == ~t5_pc~0); 21130#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 21027#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21028#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 21309#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 21310#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 21872#L557 assume 1 == ~t6_pc~0; 21659#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 21344#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21432#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21364#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 21365#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 22101#L576 assume !(1 == ~t7_pc~0); 21333#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 21334#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 21658#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22126#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 21934#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21452#L595 assume 1 == ~t8_pc~0; 21453#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 21951#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 21878#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 21780#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 21781#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 21259#L614 assume !(1 == ~t9_pc~0); 21260#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 21155#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 21156#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 21484#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 21417#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21418#L1025 assume !(1 == ~M_E~0); 21681#L1025-2 assume !(1 == ~T1_E~0); 21740#L1030-1 assume !(1 == ~T2_E~0); 21866#L1035-1 assume !(1 == ~T3_E~0); 21409#L1040-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 21410#L1045-1 assume !(1 == ~T5_E~0); 21319#L1050-1 assume !(1 == ~T6_E~0); 21320#L1055-1 assume !(1 == ~T7_E~0); 21140#L1060-1 assume !(1 == ~T8_E~0); 21141#L1065-1 assume !(1 == ~T9_E~0); 21206#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 21827#L1075-1 assume !(1 == ~E_2~0); 21828#L1080-1 assume !(1 == ~E_3~0); 21816#L1085-1 assume !(1 == ~E_4~0); 21817#L1090-1 assume !(1 == ~E_5~0); 22060#L1095-1 assume !(1 == ~E_6~0); 21851#L1100-1 assume !(1 == ~E_7~0); 21852#L1105-1 assume !(1 == ~E_8~0); 21111#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 21112#L1115-1 assume { :end_inline_reset_delta_events } true; 21278#L1396-2 [2024-10-31 21:56:09,480 INFO L747 eck$LassoCheckResult]: Loop: 21278#L1396-2 assume !false; 21355#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 22155#L897-1 assume !false; 22154#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 22153#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 22143#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 22142#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 22048#L766 assume !(0 != eval_~tmp~0#1); 22050#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 22141#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 21579#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 21580#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22139#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 22140#L932-3 assume !(0 == ~T3_E~0); 23023#L937-3 assume !(0 == ~T4_E~0); 23022#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 23021#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 23020#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 23019#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 23018#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 23017#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 23016#L972-3 assume !(0 == ~E_2~0); 23015#L977-3 assume 0 == ~E_3~0;~E_3~0 := 1; 22138#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 22135#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 21430#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 21431#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 21425#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 21426#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 21142#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21143#L443-30 assume 1 == ~m_pc~0; 21176#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 21177#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21458#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 21463#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 21966#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21568#L462-30 assume 1 == ~t1_pc~0; 21400#L463-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 21401#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21691#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 21692#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 22770#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22768#L481-30 assume 1 == ~t2_pc~0; 22764#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 22762#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22760#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 22758#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 22756#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22754#L500-30 assume 1 == ~t3_pc~0; 22750#L501-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 22749#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22748#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 22747#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 22746#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22745#L519-30 assume 1 == ~t4_pc~0; 22743#L520-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 22742#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22741#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 22740#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 22739#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22738#L538-30 assume 1 == ~t5_pc~0; 22736#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 22735#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22734#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22733#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 22732#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22731#L557-30 assume !(1 == ~t6_pc~0); 22729#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 22728#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22727#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 22726#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 22725#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 22724#L576-30 assume 1 == ~t7_pc~0; 22722#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 22721#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 22720#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22719#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 22718#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 22717#L595-30 assume !(1 == ~t8_pc~0); 22714#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 22713#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22711#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22058#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 22059#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22106#L614-30 assume 1 == ~t9_pc~0; 21315#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 21316#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 20989#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20990#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 21144#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21773#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 21542#L1025-5 assume !(1 == ~T1_E~0); 21543#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 21745#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 22068#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 22127#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 22063#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 21950#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 21035#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 21036#L1065-3 assume !(1 == ~T9_E~0); 21969#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 21802#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 21803#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 22069#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 21956#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 21957#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 21980#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 21981#L1105-3 assume !(1 == ~E_8~0); 21191#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 21192#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 22000#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 21046#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 21200#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 21392#L1415 assume !(0 == start_simulation_~tmp~3#1); 22520#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 22115#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 21099#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 21000#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 21001#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 22136#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 21660#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 21277#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 21278#L1396-2 [2024-10-31 21:56:09,480 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 21:56:09,484 INFO L85 PathProgramCache]: Analyzing trace with hash -1269658465, now seen corresponding path program 1 times [2024-10-31 21:56:09,484 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 21:56:09,484 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [984539513] [2024-10-31 21:56:09,484 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 21:56:09,485 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 21:56:09,502 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 21:56:09,614 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 21:56:09,614 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 21:56:09,614 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [984539513] [2024-10-31 21:56:09,614 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [984539513] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 21:56:09,614 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 21:56:09,615 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 21:56:09,615 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [539012435] [2024-10-31 21:56:09,615 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 21:56:09,615 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 21:56:09,616 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 21:56:09,617 INFO L85 PathProgramCache]: Analyzing trace with hash 187840947, now seen corresponding path program 1 times [2024-10-31 21:56:09,617 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 21:56:09,617 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [860889018] [2024-10-31 21:56:09,617 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 21:56:09,617 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 21:56:09,634 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 21:56:09,680 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 21:56:09,680 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 21:56:09,681 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [860889018] [2024-10-31 21:56:09,681 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [860889018] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 21:56:09,681 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 21:56:09,681 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 21:56:09,681 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1907240941] [2024-10-31 21:56:09,682 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 21:56:09,682 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 21:56:09,682 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 21:56:09,682 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-10-31 21:56:09,683 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-10-31 21:56:09,683 INFO L87 Difference]: Start difference. First operand 2100 states and 3099 transitions. cyclomatic complexity: 1001 Second operand has 4 states, 4 states have (on average 28.75) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 21:56:09,899 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 21:56:09,900 INFO L93 Difference]: Finished difference Result 3938 states and 5806 transitions. [2024-10-31 21:56:09,900 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3938 states and 5806 transitions. [2024-10-31 21:56:09,921 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3772 [2024-10-31 21:56:09,939 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3938 states to 3938 states and 5806 transitions. [2024-10-31 21:56:09,939 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3938 [2024-10-31 21:56:09,943 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3938 [2024-10-31 21:56:09,943 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3938 states and 5806 transitions. [2024-10-31 21:56:09,949 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 21:56:09,949 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3938 states and 5806 transitions. [2024-10-31 21:56:09,953 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3938 states and 5806 transitions. [2024-10-31 21:56:10,009 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3938 to 3936. [2024-10-31 21:56:10,016 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3936 states, 3936 states have (on average 1.4745934959349594) internal successors, (5804), 3935 states have internal predecessors, (5804), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 21:56:10,030 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3936 states to 3936 states and 5804 transitions. [2024-10-31 21:56:10,031 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3936 states and 5804 transitions. [2024-10-31 21:56:10,031 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-10-31 21:56:10,032 INFO L425 stractBuchiCegarLoop]: Abstraction has 3936 states and 5804 transitions. [2024-10-31 21:56:10,032 INFO L332 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-10-31 21:56:10,032 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3936 states and 5804 transitions. [2024-10-31 21:56:10,049 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3772 [2024-10-31 21:56:10,050 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 21:56:10,050 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 21:56:10,052 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 21:56:10,052 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 21:56:10,052 INFO L745 eck$LassoCheckResult]: Stem: 27284#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 27285#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 28099#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 28100#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 28044#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 28045#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 28023#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 27817#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 27818#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 27612#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 27613#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 28135#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 28012#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 27675#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 27439#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 27440#L922 assume !(0 == ~M_E~0); 28186#L922-2 assume !(0 == ~T1_E~0); 28187#L927-1 assume !(0 == ~T2_E~0); 27888#L932-1 assume !(0 == ~T3_E~0); 27750#L937-1 assume !(0 == ~T4_E~0); 27751#L942-1 assume !(0 == ~T5_E~0); 27816#L947-1 assume !(0 == ~T6_E~0); 27892#L952-1 assume !(0 == ~T7_E~0); 27893#L957-1 assume !(0 == ~T8_E~0); 27963#L962-1 assume !(0 == ~T9_E~0); 27726#L967-1 assume !(0 == ~E_1~0); 27727#L972-1 assume !(0 == ~E_2~0); 28028#L977-1 assume !(0 == ~E_3~0); 28029#L982-1 assume !(0 == ~E_4~0); 27214#L987-1 assume !(0 == ~E_5~0); 27215#L992-1 assume !(0 == ~E_6~0); 27221#L997-1 assume !(0 == ~E_7~0); 27652#L1002-1 assume !(0 == ~E_8~0); 27637#L1007-1 assume !(0 == ~E_9~0); 27008#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 27009#L443 assume !(1 == ~m_pc~0); 27909#L443-2 is_master_triggered_~__retres1~0#1 := 0; 27900#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27901#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 27377#L1140 assume !(0 != activate_threads_~tmp~1#1); 27113#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 27114#L462 assume 1 == ~t1_pc~0; 27776#L463 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 27745#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27052#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 27053#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 27591#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 27592#L481 assume !(1 == ~t2_pc~0); 27371#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 27370#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27499#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 27462#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 27463#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 27561#L500 assume 1 == ~t3_pc~0; 27797#L501 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 27798#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 27015#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 27016#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 27013#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 27014#L519 assume 1 == ~t4_pc~0; 27317#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 27318#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 27115#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 27116#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 27414#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 27177#L538 assume !(1 == ~t5_pc~0); 27178#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 27075#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 27076#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 27357#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 27358#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 27944#L557 assume 1 == ~t6_pc~0; 27714#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 27393#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 27481#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 27415#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 27416#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 28162#L576 assume !(1 == ~t7_pc~0); 27381#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 27382#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 27713#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 28182#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 28004#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 27500#L595 assume 1 == ~t8_pc~0; 27501#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 28019#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 27947#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 27841#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 27842#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 27307#L614 assume !(1 == ~t9_pc~0); 27308#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 27203#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 27204#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 27534#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 27465#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27466#L1025 assume !(1 == ~M_E~0); 27734#L1025-2 assume !(1 == ~T1_E~0); 27796#L1030-1 assume !(1 == ~T2_E~0); 27935#L1035-1 assume !(1 == ~T3_E~0); 28360#L1040-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 28050#L1045-1 assume !(1 == ~T5_E~0); 27367#L1050-1 assume !(1 == ~T6_E~0); 27368#L1055-1 assume !(1 == ~T7_E~0); 27188#L1060-1 assume !(1 == ~T8_E~0); 27189#L1065-1 assume !(1 == ~T9_E~0); 27254#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 28166#L1075-1 assume !(1 == ~E_2~0); 28350#L1080-1 assume 1 == ~E_3~0;~E_3~0 := 2; 28284#L1085-1 assume !(1 == ~E_4~0); 28262#L1090-1 assume !(1 == ~E_5~0); 28260#L1095-1 assume !(1 == ~E_6~0); 28258#L1100-1 assume !(1 == ~E_7~0); 28256#L1105-1 assume !(1 == ~E_8~0); 28246#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 28237#L1115-1 assume { :end_inline_reset_delta_events } true; 28230#L1396-2 [2024-10-31 21:56:10,053 INFO L747 eck$LassoCheckResult]: Loop: 28230#L1396-2 assume !false; 28224#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 28220#L897-1 assume !false; 28219#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 28218#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 28208#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 28207#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 28205#L766 assume !(0 != eval_~tmp~0#1); 28204#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 28203#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 28202#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 28201#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 28200#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 27526#L932-3 assume !(0 == ~T3_E~0); 27527#L937-3 assume !(0 == ~T4_E~0); 27151#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 27152#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 27528#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 27529#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 28104#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 27981#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 27982#L972-3 assume !(0 == ~E_2~0); 27886#L977-3 assume !(0 == ~E_3~0); 27887#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 28191#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 27479#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 27480#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 27477#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 27478#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 27190#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 27191#L443-30 assume 1 == ~m_pc~0; 30699#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 30697#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30695#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 30693#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 30692#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 27619#L462-30 assume 1 == ~t1_pc~0; 27447#L463-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 27448#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27746#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 27747#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 28062#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 27604#L481-30 assume 1 == ~t2_pc~0; 27314#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 27315#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27408#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 27286#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 27287#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 27564#L500-30 assume 1 == ~t3_pc~0; 27322#L501-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 27323#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 27659#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 27718#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 27547#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 27548#L519-30 assume 1 == ~t4_pc~0; 27927#L520-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 27719#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 27720#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 27731#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 27732#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29313#L538-30 assume 1 == ~t5_pc~0; 29310#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 29307#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29305#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29303#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 29302#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29300#L557-30 assume !(1 == ~t6_pc~0); 29296#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 29294#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29291#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 29289#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 29163#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29161#L576-30 assume 1 == ~t7_pc~0; 29158#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 29155#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29153#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29151#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 29149#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29147#L595-30 assume !(1 == ~t8_pc~0); 29143#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 29053#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 29050#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 29048#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 28966#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 28963#L614-30 assume 1 == ~t9_pc~0; 28960#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 28854#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 28735#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 28732#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 28730#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28624#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 28621#L1025-5 assume !(1 == ~T1_E~0); 28619#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 27801#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 28616#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 28183#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 28541#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 28539#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 28537#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 28535#L1065-3 assume !(1 == ~T9_E~0); 28534#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 28465#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 28418#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 28415#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 28413#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 28412#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 28410#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 28408#L1105-3 assume !(1 == ~E_8~0); 28406#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 28361#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 28310#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 28299#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 28297#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 28289#L1415 assume !(0 == start_simulation_~tmp~3#1); 28287#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 28270#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 28263#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 28261#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 28259#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 28257#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 28247#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 28238#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 28230#L1396-2 [2024-10-31 21:56:10,053 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 21:56:10,054 INFO L85 PathProgramCache]: Analyzing trace with hash -1455005537, now seen corresponding path program 1 times [2024-10-31 21:56:10,054 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 21:56:10,054 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [413495762] [2024-10-31 21:56:10,055 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 21:56:10,055 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 21:56:10,072 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 21:56:10,131 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 21:56:10,131 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 21:56:10,131 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [413495762] [2024-10-31 21:56:10,131 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [413495762] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 21:56:10,132 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 21:56:10,132 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-31 21:56:10,132 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1430528568] [2024-10-31 21:56:10,132 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 21:56:10,132 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 21:56:10,133 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 21:56:10,134 INFO L85 PathProgramCache]: Analyzing trace with hash 2085337713, now seen corresponding path program 1 times [2024-10-31 21:56:10,134 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 21:56:10,135 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1824125788] [2024-10-31 21:56:10,135 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 21:56:10,135 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 21:56:10,154 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 21:56:10,206 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 21:56:10,206 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 21:56:10,207 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1824125788] [2024-10-31 21:56:10,207 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1824125788] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 21:56:10,207 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 21:56:10,207 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 21:56:10,207 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1557594251] [2024-10-31 21:56:10,208 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 21:56:10,208 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 21:56:10,208 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 21:56:10,208 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 21:56:10,209 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 21:56:10,209 INFO L87 Difference]: Start difference. First operand 3936 states and 5804 transitions. cyclomatic complexity: 1872 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 2 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 21:56:10,352 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 21:56:10,352 INFO L93 Difference]: Finished difference Result 7377 states and 10808 transitions. [2024-10-31 21:56:10,352 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7377 states and 10808 transitions. [2024-10-31 21:56:10,444 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 7206 [2024-10-31 21:56:10,482 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7377 states to 7377 states and 10808 transitions. [2024-10-31 21:56:10,482 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7377 [2024-10-31 21:56:10,489 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7377 [2024-10-31 21:56:10,490 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7377 states and 10808 transitions. [2024-10-31 21:56:10,502 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 21:56:10,502 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7377 states and 10808 transitions. [2024-10-31 21:56:10,510 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7377 states and 10808 transitions. [2024-10-31 21:56:10,662 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7377 to 7369. [2024-10-31 21:56:10,677 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7369 states, 7369 states have (on average 1.4655991314968109) internal successors, (10800), 7368 states have internal predecessors, (10800), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 21:56:10,705 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7369 states to 7369 states and 10800 transitions. [2024-10-31 21:56:10,705 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7369 states and 10800 transitions. [2024-10-31 21:56:10,706 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 21:56:10,706 INFO L425 stractBuchiCegarLoop]: Abstraction has 7369 states and 10800 transitions. [2024-10-31 21:56:10,707 INFO L332 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-10-31 21:56:10,707 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7369 states and 10800 transitions. [2024-10-31 21:56:10,744 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 7198 [2024-10-31 21:56:10,745 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 21:56:10,745 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 21:56:10,747 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 21:56:10,748 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 21:56:10,748 INFO L745 eck$LassoCheckResult]: Stem: 38605#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 38606#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 39496#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 39497#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 39427#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 39428#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 39399#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 39168#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 39169#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 38946#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 38947#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 39543#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 39387#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 39017#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 38763#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 38764#L922 assume !(0 == ~M_E~0); 39619#L922-2 assume !(0 == ~T1_E~0); 39620#L927-1 assume !(0 == ~T2_E~0); 39249#L932-1 assume !(0 == ~T3_E~0); 39099#L937-1 assume !(0 == ~T4_E~0); 39100#L942-1 assume !(0 == ~T5_E~0); 39167#L947-1 assume !(0 == ~T6_E~0); 39253#L952-1 assume !(0 == ~T7_E~0); 39254#L957-1 assume !(0 == ~T8_E~0); 39329#L962-1 assume !(0 == ~T9_E~0); 39072#L967-1 assume !(0 == ~E_1~0); 39073#L972-1 assume !(0 == ~E_2~0); 39407#L977-1 assume !(0 == ~E_3~0); 39408#L982-1 assume !(0 == ~E_4~0); 38534#L987-1 assume !(0 == ~E_5~0); 38535#L992-1 assume !(0 == ~E_6~0); 38541#L997-1 assume !(0 == ~E_7~0); 38991#L1002-1 assume !(0 == ~E_8~0); 38978#L1007-1 assume !(0 == ~E_9~0); 38328#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 38329#L443 assume !(1 == ~m_pc~0); 39272#L443-2 is_master_triggered_~__retres1~0#1 := 0; 39263#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 39264#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 38699#L1140 assume !(0 != activate_threads_~tmp~1#1); 38433#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 38434#L462 assume !(1 == ~t1_pc~0); 39092#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 39093#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 38372#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 38373#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 38920#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38921#L481 assume !(1 == ~t2_pc~0); 38693#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 38692#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 38824#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 38787#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 38788#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 38887#L500 assume 1 == ~t3_pc~0; 39148#L501 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 39149#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38335#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 38336#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 38333#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 38334#L519 assume 1 == ~t4_pc~0; 38638#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 38639#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 38435#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 38436#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 38737#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 38497#L538 assume !(1 == ~t5_pc~0); 38498#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 38395#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 38396#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 38679#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 38680#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 39312#L557 assume 1 == ~t6_pc~0; 39059#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 38715#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 38806#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 38738#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 38739#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 39575#L576 assume !(1 == ~t7_pc~0); 38703#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 38704#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 39058#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 39611#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 39373#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 38827#L595 assume 1 == ~t8_pc~0; 38828#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 39395#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 39316#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 39200#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 39201#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 38628#L614 assume !(1 == ~t9_pc~0); 38629#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 38523#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 38524#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 38859#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 38790#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 38791#L1025 assume !(1 == ~M_E~0); 39081#L1025-2 assume !(1 == ~T1_E~0); 39147#L1030-1 assume !(1 == ~T2_E~0); 39301#L1035-1 assume !(1 == ~T3_E~0); 39450#L1040-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 40703#L1045-1 assume !(1 == ~T5_E~0); 40702#L1050-1 assume !(1 == ~T6_E~0); 40700#L1055-1 assume !(1 == ~T7_E~0); 38508#L1060-1 assume !(1 == ~T8_E~0); 38509#L1065-1 assume !(1 == ~T9_E~0); 38575#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 40664#L1075-1 assume !(1 == ~E_2~0); 40661#L1080-1 assume 1 == ~E_3~0;~E_3~0 := 2; 40660#L1085-1 assume !(1 == ~E_4~0); 40659#L1090-1 assume !(1 == ~E_5~0); 40658#L1095-1 assume !(1 == ~E_6~0); 40633#L1100-1 assume !(1 == ~E_7~0); 40614#L1105-1 assume !(1 == ~E_8~0); 40601#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 40592#L1115-1 assume { :end_inline_reset_delta_events } true; 40585#L1396-2 [2024-10-31 21:56:10,749 INFO L747 eck$LassoCheckResult]: Loop: 40585#L1396-2 assume !false; 40579#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 40575#L897-1 assume !false; 40574#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 40573#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 40563#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 40562#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 40560#L766 assume !(0 != eval_~tmp~0#1); 40559#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 40558#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 40557#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 40556#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 40553#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 40554#L932-3 assume !(0 == ~T3_E~0); 42854#L937-3 assume !(0 == ~T4_E~0); 42852#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 42850#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 42848#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 42846#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 42845#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 42844#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 42843#L972-3 assume !(0 == ~E_2~0); 42842#L977-3 assume !(0 == ~E_3~0); 42841#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 42840#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 42839#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 42838#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 42837#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 42836#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 42835#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 42834#L443-30 assume 1 == ~m_pc~0; 42832#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 42831#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 42830#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 42829#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 42828#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 42827#L462-30 assume !(1 == ~t1_pc~0); 39499#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 39405#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 39095#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 39096#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 39448#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38936#L481-30 assume !(1 == ~t2_pc~0); 38937#L481-32 is_transmit2_triggered_~__retres1~2#1 := 0; 42821#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 42820#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 38607#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 38608#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 39268#L500-30 assume 1 == ~t3_pc~0; 38643#L501-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 38644#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 39000#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 39063#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 38872#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 38873#L519-30 assume !(1 == ~t4_pc~0); 39091#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 39064#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 39065#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 39077#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 39078#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 39223#L538-30 assume 1 == ~t5_pc~0; 38519#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 38520#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 38856#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 39206#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 38601#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 38602#L557-30 assume 1 == ~t6_pc~0; 38318#L558-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 38320#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 38439#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 38440#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 38626#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 38627#L576-30 assume !(1 == ~t7_pc~0); 38393#L576-32 is_transmit7_triggered_~__retres1~7#1 := 0; 38394#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 39037#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 39280#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 38782#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 38744#L595-30 assume !(1 == ~t8_pc~0); 38745#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 38683#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 38684#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 39526#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 39527#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 39578#L614-30 assume !(1 == ~t9_pc~0); 38688#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 38687#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 38357#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 38358#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 38512#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 39192#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 38922#L1025-5 assume !(1 == ~T1_E~0); 38923#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 39152#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 39547#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 39612#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 39535#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 39394#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 38403#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 38404#L1065-3 assume !(1 == ~T9_E~0); 39417#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 39226#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 39227#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 39548#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 39579#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 40845#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 40843#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 40811#L1105-3 assume !(1 == ~E_8~0); 40809#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 40807#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 40747#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 40736#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 40711#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 40689#L1415 assume !(0 == start_simulation_~tmp~3#1); 40663#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 40640#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 40619#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 40617#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 40616#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 40615#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 40602#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 40593#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 40585#L1396-2 [2024-10-31 21:56:10,750 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 21:56:10,750 INFO L85 PathProgramCache]: Analyzing trace with hash 212114046, now seen corresponding path program 1 times [2024-10-31 21:56:10,751 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 21:56:10,751 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [516898289] [2024-10-31 21:56:10,751 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 21:56:10,751 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 21:56:10,771 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 21:56:10,829 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 21:56:10,829 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 21:56:10,829 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [516898289] [2024-10-31 21:56:10,829 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [516898289] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 21:56:10,829 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 21:56:10,830 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-31 21:56:10,831 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [861587120] [2024-10-31 21:56:10,831 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 21:56:10,831 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 21:56:10,832 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 21:56:10,832 INFO L85 PathProgramCache]: Analyzing trace with hash 352264749, now seen corresponding path program 1 times [2024-10-31 21:56:10,832 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 21:56:10,832 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1287085582] [2024-10-31 21:56:10,832 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 21:56:10,833 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 21:56:10,848 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 21:56:10,893 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 21:56:10,893 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 21:56:10,893 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1287085582] [2024-10-31 21:56:10,894 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1287085582] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 21:56:10,894 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 21:56:10,894 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 21:56:10,894 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1277759517] [2024-10-31 21:56:10,894 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 21:56:10,894 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 21:56:10,895 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 21:56:10,895 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 21:56:10,895 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 21:56:10,895 INFO L87 Difference]: Start difference. First operand 7369 states and 10800 transitions. cyclomatic complexity: 3439 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 2 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 21:56:11,069 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 21:56:11,069 INFO L93 Difference]: Finished difference Result 13914 states and 20281 transitions. [2024-10-31 21:56:11,069 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 13914 states and 20281 transitions. [2024-10-31 21:56:11,142 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 13728 [2024-10-31 21:56:11,293 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 13914 states to 13914 states and 20281 transitions. [2024-10-31 21:56:11,293 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13914 [2024-10-31 21:56:11,306 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13914 [2024-10-31 21:56:11,306 INFO L73 IsDeterministic]: Start isDeterministic. Operand 13914 states and 20281 transitions. [2024-10-31 21:56:11,324 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 21:56:11,324 INFO L218 hiAutomatonCegarLoop]: Abstraction has 13914 states and 20281 transitions. [2024-10-31 21:56:11,338 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13914 states and 20281 transitions. [2024-10-31 21:56:11,509 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13914 to 13898. [2024-10-31 21:56:11,536 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13898 states, 13898 states have (on average 1.458123471003022) internal successors, (20265), 13897 states have internal predecessors, (20265), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 21:56:11,572 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13898 states to 13898 states and 20265 transitions. [2024-10-31 21:56:11,572 INFO L240 hiAutomatonCegarLoop]: Abstraction has 13898 states and 20265 transitions. [2024-10-31 21:56:11,573 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 21:56:11,574 INFO L425 stractBuchiCegarLoop]: Abstraction has 13898 states and 20265 transitions. [2024-10-31 21:56:11,575 INFO L332 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-10-31 21:56:11,575 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 13898 states and 20265 transitions. [2024-10-31 21:56:11,625 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 13712 [2024-10-31 21:56:11,625 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 21:56:11,626 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 21:56:11,627 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 21:56:11,627 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 21:56:11,628 INFO L745 eck$LassoCheckResult]: Stem: 59892#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 59893#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 60775#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 60776#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 60708#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 60709#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 60686#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 60448#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 60449#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 60229#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 60230#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 60820#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 60675#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 60298#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 60050#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 60051#L922 assume !(0 == ~M_E~0); 60895#L922-2 assume !(0 == ~T1_E~0); 60896#L927-1 assume !(0 == ~T2_E~0); 60528#L932-1 assume !(0 == ~T3_E~0); 60375#L937-1 assume !(0 == ~T4_E~0); 60376#L942-1 assume !(0 == ~T5_E~0); 60447#L947-1 assume !(0 == ~T6_E~0); 60532#L952-1 assume !(0 == ~T7_E~0); 60533#L957-1 assume !(0 == ~T8_E~0); 60610#L962-1 assume !(0 == ~T9_E~0); 60352#L967-1 assume !(0 == ~E_1~0); 60353#L972-1 assume !(0 == ~E_2~0); 60692#L977-1 assume !(0 == ~E_3~0); 60693#L982-1 assume !(0 == ~E_4~0); 59824#L987-1 assume !(0 == ~E_5~0); 59825#L992-1 assume !(0 == ~E_6~0); 59831#L997-1 assume !(0 == ~E_7~0); 60271#L1002-1 assume !(0 == ~E_8~0); 60260#L1007-1 assume !(0 == ~E_9~0); 59618#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 59619#L443 assume !(1 == ~m_pc~0); 60551#L443-2 is_master_triggered_~__retres1~0#1 := 0; 60541#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 60542#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 59988#L1140 assume !(0 != activate_threads_~tmp~1#1); 59723#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 59724#L462 assume !(1 == ~t1_pc~0); 60366#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 60367#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 59660#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 59661#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 60205#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 60206#L481 assume !(1 == ~t2_pc~0); 59982#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 59981#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 60114#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 60076#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 60077#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 60174#L500 assume !(1 == ~t3_pc~0); 60763#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 60726#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 59625#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 59626#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 59620#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 59621#L519 assume 1 == ~t4_pc~0; 59924#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 59925#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 59725#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 59726#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 60023#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 59787#L538 assume !(1 == ~t5_pc~0); 59788#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 59685#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 59686#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 59968#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 59969#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 60591#L557 assume 1 == ~t6_pc~0; 60340#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 60004#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 60094#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 60024#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 60025#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 60860#L576 assume !(1 == ~t7_pc~0); 59992#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 59993#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 60339#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 60889#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 60663#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 60115#L595 assume 1 == ~t8_pc~0; 60116#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 60683#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 60597#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 60480#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 60481#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 59917#L614 assume !(1 == ~t9_pc~0); 59918#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 59812#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 59813#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 60150#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 60079#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 60080#L1025 assume !(1 == ~M_E~0); 60361#L1025-2 assume !(1 == ~T1_E~0); 60425#L1030-1 assume !(1 == ~T2_E~0); 60585#L1035-1 assume !(1 == ~T3_E~0); 60733#L1040-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 69430#L1045-1 assume !(1 == ~T5_E~0); 69424#L1050-1 assume !(1 == ~T6_E~0); 69418#L1055-1 assume !(1 == ~T7_E~0); 69414#L1060-1 assume !(1 == ~T8_E~0); 69411#L1065-1 assume !(1 == ~T9_E~0); 69408#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 69404#L1075-1 assume !(1 == ~E_2~0); 69400#L1080-1 assume 1 == ~E_3~0;~E_3~0 := 2; 69401#L1085-1 assume !(1 == ~E_4~0); 70260#L1090-1 assume !(1 == ~E_5~0); 70258#L1095-1 assume !(1 == ~E_6~0); 70257#L1100-1 assume !(1 == ~E_7~0); 70246#L1105-1 assume !(1 == ~E_8~0); 70244#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 70236#L1115-1 assume { :end_inline_reset_delta_events } true; 70225#L1396-2 [2024-10-31 21:56:11,628 INFO L747 eck$LassoCheckResult]: Loop: 70225#L1396-2 assume !false; 70214#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 70204#L897-1 assume !false; 70199#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 70026#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 70010#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 70004#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 69997#L766 assume !(0 != eval_~tmp~0#1); 69998#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 71917#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 71915#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 71913#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 71910#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 60141#L932-3 assume !(0 == ~T3_E~0); 60142#L937-3 assume !(0 == ~T4_E~0); 59761#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 59762#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 60143#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 60144#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 60785#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 60633#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 60634#L972-3 assume !(0 == ~E_2~0); 60526#L977-3 assume !(0 == ~E_3~0); 60527#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 71956#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 71955#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 71954#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 60087#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 60088#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 71767#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 60134#L443-30 assume 1 == ~m_pc~0; 59834#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 59835#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 60121#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 60126#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 60695#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 60239#L462-30 assume !(1 == ~t1_pc~0); 60240#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 60691#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 60371#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 60372#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 60730#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 60222#L481-30 assume 1 == ~t2_pc~0; 59927#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 59928#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 60019#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 59896#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 59897#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 60179#L500-30 assume !(1 == ~t3_pc~0); 60548#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 60281#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 60282#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 60344#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 60163#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 60164#L519-30 assume !(1 == ~t4_pc~0); 60370#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 60345#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 60346#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 60357#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 60358#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 60504#L538-30 assume 1 == ~t5_pc~0; 59809#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 59810#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 60147#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 60487#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 59890#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 59891#L557-30 assume 1 == ~t6_pc~0; 59608#L558-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 59610#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 59729#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 59730#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 59915#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 59916#L576-30 assume !(1 == ~t7_pc~0); 59683#L576-32 is_transmit7_triggered_~__retres1~7#1 := 0; 59684#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 60314#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 60559#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 60072#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 60032#L595-30 assume !(1 == ~t8_pc~0); 60033#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 59970#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 59971#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 60806#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 60807#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 60863#L614-30 assume 1 == ~t9_pc~0; 59975#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 59976#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 59647#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 59648#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 59802#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 60470#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 60209#L1025-5 assume !(1 == ~T1_E~0); 60210#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 60427#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 60823#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 60890#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 70935#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 70930#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 70924#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 70919#L1065-3 assume !(1 == ~T9_E~0); 70911#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 70904#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 70897#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 69463#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 70885#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 70879#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 70871#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 70866#L1105-3 assume !(1 == ~E_8~0); 70861#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 70856#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 70462#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 70451#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 70449#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 70445#L1415 assume !(0 == start_simulation_~tmp~3#1); 70360#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 70253#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 70245#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 70243#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 70242#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 70241#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 70239#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 70237#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 70225#L1396-2 [2024-10-31 21:56:11,628 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 21:56:11,629 INFO L85 PathProgramCache]: Analyzing trace with hash 2031839965, now seen corresponding path program 1 times [2024-10-31 21:56:11,629 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 21:56:11,629 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1653422490] [2024-10-31 21:56:11,629 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 21:56:11,630 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 21:56:11,645 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 21:56:11,710 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 21:56:11,710 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 21:56:11,710 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1653422490] [2024-10-31 21:56:11,710 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1653422490] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 21:56:11,710 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 21:56:11,711 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-31 21:56:11,711 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [409261095] [2024-10-31 21:56:11,711 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 21:56:11,711 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 21:56:11,711 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 21:56:11,712 INFO L85 PathProgramCache]: Analyzing trace with hash 479135758, now seen corresponding path program 1 times [2024-10-31 21:56:11,712 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 21:56:11,712 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1229924099] [2024-10-31 21:56:11,712 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 21:56:11,712 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 21:56:11,728 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 21:56:11,775 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 21:56:11,776 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 21:56:11,776 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1229924099] [2024-10-31 21:56:11,776 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1229924099] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 21:56:11,776 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 21:56:11,776 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 21:56:11,776 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [537635758] [2024-10-31 21:56:11,776 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 21:56:11,777 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 21:56:11,777 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 21:56:11,778 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 21:56:11,778 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 21:56:11,778 INFO L87 Difference]: Start difference. First operand 13898 states and 20265 transitions. cyclomatic complexity: 6383 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 2 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 21:56:12,118 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 21:56:12,118 INFO L93 Difference]: Finished difference Result 26345 states and 38242 transitions. [2024-10-31 21:56:12,118 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 26345 states and 38242 transitions. [2024-10-31 21:56:12,233 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 26104 [2024-10-31 21:56:12,320 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 26345 states to 26345 states and 38242 transitions. [2024-10-31 21:56:12,321 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 26345 [2024-10-31 21:56:12,344 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 26345 [2024-10-31 21:56:12,344 INFO L73 IsDeterministic]: Start isDeterministic. Operand 26345 states and 38242 transitions. [2024-10-31 21:56:12,375 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 21:56:12,376 INFO L218 hiAutomatonCegarLoop]: Abstraction has 26345 states and 38242 transitions. [2024-10-31 21:56:12,401 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26345 states and 38242 transitions. [2024-10-31 21:56:13,030 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26345 to 26313. [2024-10-31 21:56:13,075 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 26313 states, 26313 states have (on average 1.4521339261961768) internal successors, (38210), 26312 states have internal predecessors, (38210), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 21:56:13,167 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26313 states to 26313 states and 38210 transitions. [2024-10-31 21:56:13,168 INFO L240 hiAutomatonCegarLoop]: Abstraction has 26313 states and 38210 transitions. [2024-10-31 21:56:13,168 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 21:56:13,169 INFO L425 stractBuchiCegarLoop]: Abstraction has 26313 states and 38210 transitions. [2024-10-31 21:56:13,169 INFO L332 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2024-10-31 21:56:13,169 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 26313 states and 38210 transitions. [2024-10-31 21:56:13,279 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 26072 [2024-10-31 21:56:13,279 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 21:56:13,279 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 21:56:13,281 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 21:56:13,282 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 21:56:13,282 INFO L745 eck$LassoCheckResult]: Stem: 100144#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 100145#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 101018#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 101019#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 100956#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 100957#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 100928#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 100700#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 100701#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 100483#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 100484#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 101058#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 100917#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 100552#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 100301#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 100302#L922 assume !(0 == ~M_E~0); 101151#L922-2 assume !(0 == ~T1_E~0); 101152#L927-1 assume !(0 == ~T2_E~0); 100772#L932-1 assume !(0 == ~T3_E~0); 100634#L937-1 assume !(0 == ~T4_E~0); 100635#L942-1 assume !(0 == ~T5_E~0); 100699#L947-1 assume !(0 == ~T6_E~0); 100776#L952-1 assume !(0 == ~T7_E~0); 100777#L957-1 assume !(0 == ~T8_E~0); 100855#L962-1 assume !(0 == ~T9_E~0); 100609#L967-1 assume !(0 == ~E_1~0); 100610#L972-1 assume !(0 == ~E_2~0); 100936#L977-1 assume !(0 == ~E_3~0); 100937#L982-1 assume !(0 == ~E_4~0); 100075#L987-1 assume !(0 == ~E_5~0); 100076#L992-1 assume !(0 == ~E_6~0); 100082#L997-1 assume !(0 == ~E_7~0); 100525#L1002-1 assume !(0 == ~E_8~0); 100512#L1007-1 assume !(0 == ~E_9~0); 99868#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 99869#L443 assume !(1 == ~m_pc~0); 100796#L443-2 is_master_triggered_~__retres1~0#1 := 0; 100785#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 100786#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 100238#L1140 assume !(0 != activate_threads_~tmp~1#1); 99973#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 99974#L462 assume !(1 == ~t1_pc~0); 100625#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 100626#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 99910#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 99911#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 100460#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 100461#L481 assume !(1 == ~t2_pc~0); 100232#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 100231#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 100365#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 100326#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 100327#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 100430#L500 assume !(1 == ~t3_pc~0); 101007#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 100975#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 99875#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 99876#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 99870#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 99871#L519 assume !(1 == ~t4_pc~0); 100688#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 100429#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 99975#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 99976#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 100274#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 100038#L538 assume !(1 == ~t5_pc~0); 100039#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 99935#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 99936#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 100218#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 100219#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 100839#L557 assume 1 == ~t6_pc~0; 100594#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 100254#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 100345#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 100275#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 100276#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 101100#L576 assume !(1 == ~t7_pc~0); 100242#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 100243#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 100593#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 101139#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 100906#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 100366#L595 assume 1 == ~t8_pc~0; 100367#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 100923#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 100844#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 100724#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 100725#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 100169#L614 assume !(1 == ~t9_pc~0); 100170#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 100063#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 100064#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 100401#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 100329#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 100330#L1025 assume !(1 == ~M_E~0); 100618#L1025-2 assume !(1 == ~T1_E~0); 100679#L1030-1 assume !(1 == ~T2_E~0); 100828#L1035-1 assume !(1 == ~T3_E~0); 100320#L1040-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 100321#L1045-1 assume !(1 == ~T5_E~0); 106392#L1050-1 assume !(1 == ~T6_E~0); 100419#L1055-1 assume !(1 == ~T7_E~0); 100420#L1060-1 assume !(1 == ~T8_E~0); 100115#L1065-1 assume !(1 == ~T9_E~0); 100116#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 100778#L1075-1 assume !(1 == ~E_2~0); 100779#L1080-1 assume 1 == ~E_3~0;~E_3~0 := 2; 106334#L1085-1 assume !(1 == ~E_4~0); 106328#L1090-1 assume !(1 == ~E_5~0); 105933#L1095-1 assume !(1 == ~E_6~0); 105931#L1100-1 assume !(1 == ~E_7~0); 105841#L1105-1 assume !(1 == ~E_8~0); 105822#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 105811#L1115-1 assume { :end_inline_reset_delta_events } true; 105801#L1396-2 [2024-10-31 21:56:13,283 INFO L747 eck$LassoCheckResult]: Loop: 105801#L1396-2 assume !false; 105793#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 105787#L897-1 assume !false; 105784#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 105780#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 105766#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 105763#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 105759#L766 assume !(0 != eval_~tmp~0#1); 105760#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 106789#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 106787#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 106785#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 106783#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 106781#L932-3 assume !(0 == ~T3_E~0); 106779#L937-3 assume !(0 == ~T4_E~0); 106777#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 106776#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 106773#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 106771#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 106769#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 106767#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 106765#L972-3 assume !(0 == ~E_2~0); 106763#L977-3 assume !(0 == ~E_3~0); 106761#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 106759#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 106757#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 106755#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 106753#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 106751#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 106748#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 106746#L443-30 assume 1 == ~m_pc~0; 106743#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 106741#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 106739#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 106737#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 106735#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 106733#L462-30 assume !(1 == ~t1_pc~0); 106731#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 106729#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 106727#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 106725#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 106723#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 106721#L481-30 assume 1 == ~t2_pc~0; 106715#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 106713#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 106711#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 106709#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 106707#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 106704#L500-30 assume !(1 == ~t3_pc~0); 106702#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 106685#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 106679#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 106672#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 106664#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 106658#L519-30 assume !(1 == ~t4_pc~0); 106652#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 106645#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 106637#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 106629#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 106622#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 106611#L538-30 assume 1 == ~t5_pc~0; 106603#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 106580#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 106577#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 106575#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 106573#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 106571#L557-30 assume !(1 == ~t6_pc~0); 106567#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 106565#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 106563#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 106561#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 106559#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 106557#L576-30 assume !(1 == ~t7_pc~0); 106555#L576-32 is_transmit7_triggered_~__retres1~7#1 := 0; 106552#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 106550#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 106548#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 106546#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 106543#L595-30 assume 1 == ~t8_pc~0; 106541#L596-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 106538#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 106536#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 106534#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 106533#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 106521#L614-30 assume !(1 == ~t9_pc~0); 106401#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 106398#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 106396#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 106386#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 106375#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 106367#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 106357#L1025-5 assume !(1 == ~T1_E~0); 106348#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 106092#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 106085#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 106081#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 106079#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 106077#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 106074#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 106070#L1065-3 assume !(1 == ~T9_E~0); 106068#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 106066#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 106064#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 106060#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 106058#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 106056#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 106054#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 106050#L1105-3 assume !(1 == ~E_8~0); 106048#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 106046#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 106043#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 106026#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 106020#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 106013#L1415 assume !(0 == start_simulation_~tmp~3#1); 106010#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 105858#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 105849#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 105847#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 105845#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 105843#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 105823#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 105812#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 105801#L1396-2 [2024-10-31 21:56:13,283 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 21:56:13,283 INFO L85 PathProgramCache]: Analyzing trace with hash 2039590524, now seen corresponding path program 1 times [2024-10-31 21:56:13,284 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 21:56:13,284 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1130118216] [2024-10-31 21:56:13,284 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 21:56:13,284 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 21:56:13,304 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 21:56:13,388 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 21:56:13,389 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 21:56:13,389 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1130118216] [2024-10-31 21:56:13,389 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1130118216] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 21:56:13,389 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 21:56:13,389 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-10-31 21:56:13,390 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1343123096] [2024-10-31 21:56:13,390 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 21:56:13,390 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 21:56:13,391 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 21:56:13,391 INFO L85 PathProgramCache]: Analyzing trace with hash -2009657619, now seen corresponding path program 1 times [2024-10-31 21:56:13,391 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 21:56:13,392 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [765992358] [2024-10-31 21:56:13,392 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 21:56:13,392 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 21:56:13,412 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 21:56:13,467 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 21:56:13,467 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 21:56:13,467 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [765992358] [2024-10-31 21:56:13,468 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [765992358] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 21:56:13,468 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 21:56:13,468 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 21:56:13,468 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [300823878] [2024-10-31 21:56:13,469 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 21:56:13,469 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 21:56:13,469 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 21:56:13,470 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-10-31 21:56:13,470 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-10-31 21:56:13,471 INFO L87 Difference]: Start difference. First operand 26313 states and 38210 transitions. cyclomatic complexity: 11929 Second operand has 5 states, 5 states have (on average 23.0) internal successors, (115), 5 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 21:56:13,986 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 21:56:13,987 INFO L93 Difference]: Finished difference Result 27180 states and 39077 transitions. [2024-10-31 21:56:13,987 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 27180 states and 39077 transitions. [2024-10-31 21:56:14,094 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 26936 [2024-10-31 21:56:14,289 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 27180 states to 27180 states and 39077 transitions. [2024-10-31 21:56:14,289 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27180 [2024-10-31 21:56:14,311 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 27180 [2024-10-31 21:56:14,311 INFO L73 IsDeterministic]: Start isDeterministic. Operand 27180 states and 39077 transitions. [2024-10-31 21:56:14,344 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 21:56:14,344 INFO L218 hiAutomatonCegarLoop]: Abstraction has 27180 states and 39077 transitions. [2024-10-31 21:56:14,368 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27180 states and 39077 transitions. [2024-10-31 21:56:14,847 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27180 to 27180. [2024-10-31 21:56:14,893 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 27180 states, 27180 states have (on average 1.4377115526122148) internal successors, (39077), 27179 states have internal predecessors, (39077), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 21:56:14,974 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27180 states to 27180 states and 39077 transitions. [2024-10-31 21:56:14,974 INFO L240 hiAutomatonCegarLoop]: Abstraction has 27180 states and 39077 transitions. [2024-10-31 21:56:14,975 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-10-31 21:56:14,976 INFO L425 stractBuchiCegarLoop]: Abstraction has 27180 states and 39077 transitions. [2024-10-31 21:56:14,976 INFO L332 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2024-10-31 21:56:14,976 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 27180 states and 39077 transitions. [2024-10-31 21:56:15,056 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 26936 [2024-10-31 21:56:15,057 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 21:56:15,057 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 21:56:15,058 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 21:56:15,059 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 21:56:15,059 INFO L745 eck$LassoCheckResult]: Stem: 153647#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 153648#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 154484#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 154485#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 154430#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 154431#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 154410#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 154197#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 154198#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 153990#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 153991#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 154521#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 154398#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 154056#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 153806#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 153807#L922 assume !(0 == ~M_E~0); 154585#L922-2 assume !(0 == ~T1_E~0); 154586#L927-1 assume !(0 == ~T2_E~0); 154270#L932-1 assume !(0 == ~T3_E~0); 154131#L937-1 assume !(0 == ~T4_E~0); 154132#L942-1 assume !(0 == ~T5_E~0); 154196#L947-1 assume !(0 == ~T6_E~0); 154274#L952-1 assume !(0 == ~T7_E~0); 154275#L957-1 assume !(0 == ~T8_E~0); 154349#L962-1 assume !(0 == ~T9_E~0); 154109#L967-1 assume !(0 == ~E_1~0); 154110#L972-1 assume !(0 == ~E_2~0); 154416#L977-1 assume !(0 == ~E_3~0); 154417#L982-1 assume !(0 == ~E_4~0); 153577#L987-1 assume !(0 == ~E_5~0); 153578#L992-1 assume !(0 == ~E_6~0); 153584#L997-1 assume !(0 == ~E_7~0); 154031#L1002-1 assume !(0 == ~E_8~0); 154018#L1007-1 assume !(0 == ~E_9~0); 153370#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 153371#L443 assume !(1 == ~m_pc~0); 154294#L443-2 is_master_triggered_~__retres1~0#1 := 0; 154283#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 154284#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 153740#L1140 assume !(0 != activate_threads_~tmp~1#1); 153476#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 153477#L462 assume !(1 == ~t1_pc~0); 154125#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 154126#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 153414#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 153415#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 153967#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 153968#L481 assume !(1 == ~t2_pc~0); 153734#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 153733#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 153868#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 153829#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 153830#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 153935#L500 assume !(1 == ~t3_pc~0); 154474#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 154448#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 153377#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 153378#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 153375#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 153376#L519 assume !(1 == ~t4_pc~0); 154186#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 153932#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 153478#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 153479#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 153779#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 153540#L538 assume !(1 == ~t5_pc~0); 153541#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 153437#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 153438#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 153720#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 153721#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 154333#L557 assume 1 == ~t6_pc~0; 154094#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 153756#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 153848#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 153780#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 153781#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 154560#L576 assume !(1 == ~t7_pc~0); 153744#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 153745#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 154093#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 154581#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 154388#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 153871#L595 assume 1 == ~t8_pc~0; 153872#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 154405#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 154338#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 154222#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 154223#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 153670#L614 assume !(1 == ~t9_pc~0); 153671#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 153566#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 153567#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 153906#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 153832#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 153833#L1025 assume !(1 == ~M_E~0); 154115#L1025-2 assume !(1 == ~T1_E~0); 154178#L1030-1 assume !(1 == ~T2_E~0); 154323#L1035-1 assume !(1 == ~T3_E~0); 157965#L1040-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 157966#L1045-1 assume !(1 == ~T5_E~0); 158210#L1050-1 assume !(1 == ~T6_E~0); 157962#L1055-1 assume !(1 == ~T7_E~0); 157960#L1060-1 assume !(1 == ~T8_E~0); 157958#L1065-1 assume !(1 == ~T9_E~0); 157957#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 157956#L1075-1 assume !(1 == ~E_2~0); 157873#L1080-1 assume 1 == ~E_3~0;~E_3~0 := 2; 157833#L1085-1 assume !(1 == ~E_4~0); 157831#L1090-1 assume !(1 == ~E_5~0); 157829#L1095-1 assume !(1 == ~E_6~0); 157789#L1100-1 assume !(1 == ~E_7~0); 157787#L1105-1 assume !(1 == ~E_8~0); 157786#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 157758#L1115-1 assume { :end_inline_reset_delta_events } true; 157730#L1396-2 [2024-10-31 21:56:15,060 INFO L747 eck$LassoCheckResult]: Loop: 157730#L1396-2 assume !false; 157718#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 157710#L897-1 assume !false; 157661#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 157624#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 157594#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 157561#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 157557#L766 assume !(0 != eval_~tmp~0#1); 157558#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 159790#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 159788#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 159786#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 159645#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 159643#L932-3 assume !(0 == ~T3_E~0); 159641#L937-3 assume !(0 == ~T4_E~0); 159638#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 159636#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 159634#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 159632#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 159630#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 159628#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 159465#L972-3 assume !(0 == ~E_2~0); 159230#L977-3 assume !(0 == ~E_3~0); 159219#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 159217#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 159215#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 159213#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 159211#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 159209#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 159207#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 159205#L443-30 assume 1 == ~m_pc~0; 159202#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 159200#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 159198#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 159196#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 159194#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 159192#L462-30 assume !(1 == ~t1_pc~0); 159190#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 159188#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 159186#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 159184#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 159182#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 159180#L481-30 assume !(1 == ~t2_pc~0); 159178#L481-32 is_transmit2_triggered_~__retres1~2#1 := 0; 159175#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 159173#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 159171#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 159169#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 159167#L500-30 assume !(1 == ~t3_pc~0); 159165#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 159162#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 159160#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 159158#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 159156#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 159154#L519-30 assume !(1 == ~t4_pc~0); 159152#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 159150#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 159148#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 159146#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 158949#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 158331#L538-30 assume !(1 == ~t5_pc~0); 158327#L538-32 is_transmit5_triggered_~__retres1~5#1 := 0; 158325#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 158323#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 158320#L1180-30 assume !(0 != activate_threads_~tmp___4~0#1); 158317#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 158315#L557-30 assume !(1 == ~t6_pc~0); 158310#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 158308#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 158306#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 158304#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 158301#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 158299#L576-30 assume 1 == ~t7_pc~0; 158296#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 158294#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 158292#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 158290#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 158289#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 158286#L595-30 assume !(1 == ~t8_pc~0); 158283#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 158281#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 158279#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 158277#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 158275#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 158272#L614-30 assume !(1 == ~t9_pc~0); 158270#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 158267#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 158265#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 158263#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 158261#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 158259#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 158257#L1025-5 assume !(1 == ~T1_E~0); 158255#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 158249#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 158247#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 158243#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 158241#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 158239#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 158237#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 158235#L1065-3 assume !(1 == ~T9_E~0); 158233#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 158232#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 158231#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 158227#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 158226#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 158225#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 158224#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 158223#L1105-3 assume !(1 == ~E_8~0); 158222#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 158220#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 157987#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 157976#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 157974#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 157970#L1415 assume !(0 == start_simulation_~tmp~3#1); 157967#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 157881#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 157834#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 157832#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 157830#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 157790#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 157788#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 157759#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 157730#L1396-2 [2024-10-31 21:56:15,060 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 21:56:15,061 INFO L85 PathProgramCache]: Analyzing trace with hash -327104070, now seen corresponding path program 1 times [2024-10-31 21:56:15,061 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 21:56:15,062 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [497116241] [2024-10-31 21:56:15,062 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 21:56:15,062 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 21:56:15,081 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 21:56:15,136 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 21:56:15,136 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 21:56:15,136 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [497116241] [2024-10-31 21:56:15,136 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [497116241] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 21:56:15,137 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 21:56:15,137 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-31 21:56:15,137 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1191932561] [2024-10-31 21:56:15,137 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 21:56:15,137 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 21:56:15,138 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 21:56:15,138 INFO L85 PathProgramCache]: Analyzing trace with hash 1715959657, now seen corresponding path program 1 times [2024-10-31 21:56:15,138 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 21:56:15,138 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1336380288] [2024-10-31 21:56:15,138 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 21:56:15,139 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 21:56:15,156 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 21:56:15,359 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 21:56:15,359 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 21:56:15,359 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1336380288] [2024-10-31 21:56:15,360 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1336380288] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 21:56:15,360 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 21:56:15,360 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 21:56:15,360 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1746697624] [2024-10-31 21:56:15,360 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 21:56:15,361 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 21:56:15,361 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 21:56:15,361 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 21:56:15,362 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 21:56:15,362 INFO L87 Difference]: Start difference. First operand 27180 states and 39077 transitions. cyclomatic complexity: 11929 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 2 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 21:56:15,710 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 21:56:15,710 INFO L93 Difference]: Finished difference Result 51555 states and 73842 transitions. [2024-10-31 21:56:15,710 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 51555 states and 73842 transitions. [2024-10-31 21:56:16,108 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 51168 [2024-10-31 21:56:16,423 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 51555 states to 51555 states and 73842 transitions. [2024-10-31 21:56:16,423 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 51555 [2024-10-31 21:56:16,458 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 51555 [2024-10-31 21:56:16,458 INFO L73 IsDeterministic]: Start isDeterministic. Operand 51555 states and 73842 transitions. [2024-10-31 21:56:16,496 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 21:56:16,496 INFO L218 hiAutomatonCegarLoop]: Abstraction has 51555 states and 73842 transitions. [2024-10-31 21:56:16,541 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 51555 states and 73842 transitions. [2024-10-31 21:56:17,167 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 51555 to 51491. [2024-10-31 21:56:17,245 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 51491 states, 51491 states have (on average 1.4328329222582588) internal successors, (73778), 51490 states have internal predecessors, (73778), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 21:56:17,410 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51491 states to 51491 states and 73778 transitions. [2024-10-31 21:56:17,410 INFO L240 hiAutomatonCegarLoop]: Abstraction has 51491 states and 73778 transitions. [2024-10-31 21:56:17,411 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 21:56:17,412 INFO L425 stractBuchiCegarLoop]: Abstraction has 51491 states and 73778 transitions. [2024-10-31 21:56:17,412 INFO L332 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2024-10-31 21:56:17,412 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 51491 states and 73778 transitions. [2024-10-31 21:56:17,787 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 51104 [2024-10-31 21:56:17,787 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 21:56:17,788 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 21:56:17,790 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 21:56:17,790 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 21:56:17,790 INFO L745 eck$LassoCheckResult]: Stem: 232384#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 232385#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 233246#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 233247#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 233181#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 233182#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 233155#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 232935#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 232936#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 232720#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 232721#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 233276#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 233142#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 232791#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 232545#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 232546#L922 assume !(0 == ~M_E~0); 233343#L922-2 assume !(0 == ~T1_E~0); 233344#L927-1 assume !(0 == ~T2_E~0); 233009#L932-1 assume !(0 == ~T3_E~0); 232867#L937-1 assume !(0 == ~T4_E~0); 232868#L942-1 assume !(0 == ~T5_E~0); 232934#L947-1 assume !(0 == ~T6_E~0); 233013#L952-1 assume !(0 == ~T7_E~0); 233014#L957-1 assume !(0 == ~T8_E~0); 233084#L962-1 assume !(0 == ~T9_E~0); 232841#L967-1 assume !(0 == ~E_1~0); 232842#L972-1 assume !(0 == ~E_2~0); 233161#L977-1 assume !(0 == ~E_3~0); 233162#L982-1 assume !(0 == ~E_4~0); 232318#L987-1 assume !(0 == ~E_5~0); 232319#L992-1 assume !(0 == ~E_6~0); 232325#L997-1 assume !(0 == ~E_7~0); 232762#L1002-1 assume !(0 == ~E_8~0); 232748#L1007-1 assume !(0 == ~E_9~0); 232112#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 232113#L443 assume !(1 == ~m_pc~0); 233031#L443-2 is_master_triggered_~__retres1~0#1 := 0; 233021#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 233022#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 232481#L1140 assume !(0 != activate_threads_~tmp~1#1); 232218#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 232219#L462 assume !(1 == ~t1_pc~0); 232858#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 232859#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 232154#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 232155#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 232698#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 232699#L481 assume !(1 == ~t2_pc~0); 232475#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 232474#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 232609#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 232568#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 232569#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 232668#L500 assume !(1 == ~t3_pc~0); 233234#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 233199#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 232119#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 232120#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 232114#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 232115#L519 assume !(1 == ~t4_pc~0); 232923#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 232667#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 232220#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 232221#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 232517#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 232282#L538 assume !(1 == ~t5_pc~0); 232283#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 232179#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 232180#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 232460#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 232461#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 233065#L557 assume !(1 == ~t6_pc~0); 232496#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 232497#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 232588#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 232518#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 232519#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 233318#L576 assume !(1 == ~t7_pc~0); 232485#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 232486#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 232828#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 233340#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 233132#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 232610#L595 assume 1 == ~t8_pc~0; 232611#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 233151#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 233070#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 232961#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 232962#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 232412#L614 assume !(1 == ~t9_pc~0); 232413#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 232307#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 232308#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 232644#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 232572#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 232573#L1025 assume !(1 == ~M_E~0); 232849#L1025-2 assume !(1 == ~T1_E~0); 232915#L1030-1 assume !(1 == ~T2_E~0); 233057#L1035-1 assume !(1 == ~T3_E~0); 238817#L1040-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 238815#L1045-1 assume !(1 == ~T5_E~0); 238814#L1050-1 assume !(1 == ~T6_E~0); 238813#L1055-1 assume !(1 == ~T7_E~0); 238811#L1060-1 assume !(1 == ~T8_E~0); 238809#L1065-1 assume !(1 == ~T9_E~0); 238807#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 238805#L1075-1 assume !(1 == ~E_2~0); 238802#L1080-1 assume 1 == ~E_3~0;~E_3~0 := 2; 238801#L1085-1 assume !(1 == ~E_4~0); 238797#L1090-1 assume !(1 == ~E_5~0); 238796#L1095-1 assume !(1 == ~E_6~0); 238795#L1100-1 assume !(1 == ~E_7~0); 238794#L1105-1 assume !(1 == ~E_8~0); 238793#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 238768#L1115-1 assume { :end_inline_reset_delta_events } true; 238765#L1396-2 [2024-10-31 21:56:17,790 INFO L747 eck$LassoCheckResult]: Loop: 238765#L1396-2 assume !false; 238763#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 238758#L897-1 assume !false; 238756#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 238753#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 238741#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 238739#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 238736#L766 assume !(0 != eval_~tmp~0#1); 238737#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 249582#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 249580#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 249577#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 249575#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 249573#L932-3 assume !(0 == ~T3_E~0); 249571#L937-3 assume !(0 == ~T4_E~0); 249569#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 249567#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 249565#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 249563#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 249533#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 249526#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 249519#L972-3 assume !(0 == ~E_2~0); 249511#L977-3 assume !(0 == ~E_3~0); 249503#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 249496#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 249487#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 249480#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 249472#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 249466#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 249460#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 249453#L443-30 assume !(1 == ~m_pc~0); 249446#L443-32 is_master_triggered_~__retres1~0#1 := 0; 249442#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 249439#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 249438#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 249437#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 249436#L462-30 assume !(1 == ~t1_pc~0); 249434#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 249432#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 249430#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 249428#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 249426#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 249424#L481-30 assume !(1 == ~t2_pc~0); 249411#L481-32 is_transmit2_triggered_~__retres1~2#1 := 0; 249406#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 249403#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 249362#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 249359#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 249357#L500-30 assume !(1 == ~t3_pc~0); 249355#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 249353#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 249351#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 249349#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 249347#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 249345#L519-30 assume !(1 == ~t4_pc~0); 249343#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 249341#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 249326#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 249320#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 249312#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 249305#L538-30 assume !(1 == ~t5_pc~0); 249299#L538-32 is_transmit5_triggered_~__retres1~5#1 := 0; 249290#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 249282#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 249275#L1180-30 assume !(0 != activate_threads_~tmp___4~0#1); 249268#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 249262#L557-30 assume !(1 == ~t6_pc~0); 249256#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 249250#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 249244#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 249238#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 249231#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 249225#L576-30 assume !(1 == ~t7_pc~0); 249219#L576-32 is_transmit7_triggered_~__retres1~7#1 := 0; 249210#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 249204#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 249199#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 249193#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 249187#L595-30 assume 1 == ~t8_pc~0; 249181#L596-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 249174#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 249168#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 249163#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 249158#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 249153#L614-30 assume !(1 == ~t9_pc~0); 248274#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 248267#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 248262#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 248257#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 248253#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 248248#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 248242#L1025-5 assume !(1 == ~T1_E~0); 248235#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 244230#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 248222#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 248214#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 248210#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 248204#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 248197#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 248191#L1065-3 assume !(1 == ~T9_E~0); 248186#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 248181#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 248176#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 248169#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 248162#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 248158#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 248153#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 248150#L1105-3 assume !(1 == ~E_8~0); 248144#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 248138#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 247708#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 247697#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 247695#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 247616#L1415 assume !(0 == start_simulation_~tmp~3#1); 247614#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 238788#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 238779#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 238777#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 238775#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 238773#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 238771#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 238769#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 238765#L1396-2 [2024-10-31 21:56:17,791 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 21:56:17,791 INFO L85 PathProgramCache]: Analyzing trace with hash -1602206759, now seen corresponding path program 1 times [2024-10-31 21:56:17,792 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 21:56:17,792 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1968953353] [2024-10-31 21:56:17,792 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 21:56:17,792 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 21:56:17,810 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 21:56:17,862 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 21:56:17,863 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 21:56:17,863 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1968953353] [2024-10-31 21:56:17,863 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1968953353] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 21:56:17,863 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 21:56:17,863 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-10-31 21:56:17,863 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1909398340] [2024-10-31 21:56:17,864 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 21:56:17,864 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 21:56:17,864 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 21:56:17,865 INFO L85 PathProgramCache]: Analyzing trace with hash -365804472, now seen corresponding path program 1 times [2024-10-31 21:56:17,865 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 21:56:17,865 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2052506279] [2024-10-31 21:56:17,865 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 21:56:17,865 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 21:56:17,882 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 21:56:17,925 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 21:56:17,926 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 21:56:17,926 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2052506279] [2024-10-31 21:56:17,926 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2052506279] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 21:56:17,926 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 21:56:17,926 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 21:56:17,927 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2029868455] [2024-10-31 21:56:17,927 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 21:56:17,927 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 21:56:17,927 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 21:56:17,928 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-10-31 21:56:17,928 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-10-31 21:56:17,928 INFO L87 Difference]: Start difference. First operand 51491 states and 73778 transitions. cyclomatic complexity: 22351 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 2 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 21:56:18,572 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 21:56:18,572 INFO L93 Difference]: Finished difference Result 97602 states and 139391 transitions. [2024-10-31 21:56:18,573 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 97602 states and 139391 transitions. [2024-10-31 21:56:18,954 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 96864 [2024-10-31 21:56:19,525 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 97602 states to 97602 states and 139391 transitions. [2024-10-31 21:56:19,525 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 97602 [2024-10-31 21:56:19,577 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 97602 [2024-10-31 21:56:19,578 INFO L73 IsDeterministic]: Start isDeterministic. Operand 97602 states and 139391 transitions. [2024-10-31 21:56:19,634 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 21:56:19,634 INFO L218 hiAutomatonCegarLoop]: Abstraction has 97602 states and 139391 transitions. [2024-10-31 21:56:19,688 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 97602 states and 139391 transitions. [2024-10-31 21:56:20,903 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 97602 to 97474. [2024-10-31 21:56:21,002 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 97474 states, 97474 states have (on average 1.4287194533926997) internal successors, (139263), 97473 states have internal predecessors, (139263), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 21:56:21,599 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 97474 states to 97474 states and 139263 transitions. [2024-10-31 21:56:21,599 INFO L240 hiAutomatonCegarLoop]: Abstraction has 97474 states and 139263 transitions. [2024-10-31 21:56:21,599 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 21:56:21,600 INFO L425 stractBuchiCegarLoop]: Abstraction has 97474 states and 139263 transitions. [2024-10-31 21:56:21,600 INFO L332 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2024-10-31 21:56:21,600 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 97474 states and 139263 transitions. [2024-10-31 21:56:21,911 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 96736 [2024-10-31 21:56:21,912 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 21:56:21,912 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 21:56:21,914 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 21:56:21,914 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 21:56:21,915 INFO L745 eck$LassoCheckResult]: Stem: 381484#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 381485#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 382364#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 382365#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 382299#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 382300#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 382274#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 382053#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 382054#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 381827#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 381828#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 382410#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 382261#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 381903#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 381642#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 381643#L922 assume !(0 == ~M_E~0); 382495#L922-2 assume !(0 == ~T1_E~0); 382496#L927-1 assume !(0 == ~T2_E~0); 382127#L932-1 assume !(0 == ~T3_E~0); 381988#L937-1 assume !(0 == ~T4_E~0); 381989#L942-1 assume !(0 == ~T5_E~0); 382052#L947-1 assume !(0 == ~T6_E~0); 382132#L952-1 assume !(0 == ~T7_E~0); 382133#L957-1 assume !(0 == ~T8_E~0); 382208#L962-1 assume !(0 == ~T9_E~0); 381961#L967-1 assume !(0 == ~E_1~0); 381962#L972-1 assume !(0 == ~E_2~0); 382284#L977-1 assume !(0 == ~E_3~0); 382285#L982-1 assume !(0 == ~E_4~0); 381418#L987-1 assume !(0 == ~E_5~0); 381419#L992-1 assume !(0 == ~E_6~0); 381425#L997-1 assume !(0 == ~E_7~0); 381874#L1002-1 assume !(0 == ~E_8~0); 381861#L1007-1 assume !(0 == ~E_9~0); 381212#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 381213#L443 assume !(1 == ~m_pc~0); 382150#L443-2 is_master_triggered_~__retres1~0#1 := 0; 382140#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 382141#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 381578#L1140 assume !(0 != activate_threads_~tmp~1#1); 381318#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 381319#L462 assume !(1 == ~t1_pc~0); 381977#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 381978#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 381254#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 381255#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 381801#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 381802#L481 assume !(1 == ~t2_pc~0); 381572#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 381571#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 381708#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 381668#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 381669#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 381771#L500 assume !(1 == ~t3_pc~0); 382353#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 382319#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 381219#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 381220#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 381214#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 381215#L519 assume !(1 == ~t4_pc~0); 382044#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 381770#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 381320#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 381321#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 381614#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 381382#L538 assume !(1 == ~t5_pc~0); 381383#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 381279#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 381280#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 381557#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 381558#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 382190#L557 assume !(1 == ~t6_pc~0); 381593#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 381594#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 381687#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 381615#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 381616#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 382457#L576 assume !(1 == ~t7_pc~0); 381582#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 381583#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 381946#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 382487#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 382253#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 381709#L595 assume !(1 == ~t8_pc~0); 381710#L595-2 is_transmit8_triggered_~__retres1~8#1 := 0; 382269#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 382196#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 382080#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 382081#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 381509#L614 assume !(1 == ~t9_pc~0); 381510#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 381407#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 381408#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 381746#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 381671#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 381672#L1025 assume !(1 == ~M_E~0); 381971#L1025-2 assume !(1 == ~T1_E~0); 382035#L1030-1 assume !(1 == ~T2_E~0); 382182#L1035-1 assume !(1 == ~T3_E~0); 381662#L1040-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 381663#L1045-1 assume !(1 == ~T5_E~0); 388342#L1050-1 assume !(1 == ~T6_E~0); 388340#L1055-1 assume !(1 == ~T7_E~0); 388338#L1060-1 assume !(1 == ~T8_E~0); 388336#L1065-1 assume !(1 == ~T9_E~0); 388334#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 388332#L1075-1 assume !(1 == ~E_2~0); 388329#L1080-1 assume 1 == ~E_3~0;~E_3~0 := 2; 388330#L1085-1 assume !(1 == ~E_4~0); 388366#L1090-1 assume !(1 == ~E_5~0); 388365#L1095-1 assume !(1 == ~E_6~0); 388362#L1100-1 assume !(1 == ~E_7~0); 388361#L1105-1 assume !(1 == ~E_8~0); 388359#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 388354#L1115-1 assume { :end_inline_reset_delta_events } true; 388350#L1396-2 [2024-10-31 21:56:21,915 INFO L747 eck$LassoCheckResult]: Loop: 388350#L1396-2 assume !false; 388349#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 388345#L897-1 assume !false; 388344#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 387359#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 387348#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 387346#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 387342#L766 assume !(0 != eval_~tmp~0#1); 387343#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 393857#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 393855#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 393853#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 393851#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 393849#L932-3 assume !(0 == ~T3_E~0); 393847#L937-3 assume !(0 == ~T4_E~0); 393845#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 393843#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 393841#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 393839#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 393837#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 393835#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 393833#L972-3 assume !(0 == ~E_2~0); 393831#L977-3 assume !(0 == ~E_3~0); 393829#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 393827#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 393825#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 393823#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 393821#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 393819#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 393817#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 393814#L443-30 assume !(1 == ~m_pc~0); 393812#L443-32 is_master_triggered_~__retres1~0#1 := 0; 393809#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 393807#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 393805#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 393803#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 393801#L462-30 assume !(1 == ~t1_pc~0); 393799#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 393797#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 393795#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 393793#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 393791#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 393790#L481-30 assume 1 == ~t2_pc~0; 393788#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 393785#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 393783#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 393781#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 393779#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 393777#L500-30 assume !(1 == ~t3_pc~0); 393775#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 393773#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 393771#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 393769#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 393757#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 393754#L519-30 assume !(1 == ~t4_pc~0); 393751#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 393747#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 393744#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 393741#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 393737#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 393734#L538-30 assume 1 == ~t5_pc~0; 393730#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 393725#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 393720#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 393715#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 393711#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 393708#L557-30 assume !(1 == ~t6_pc~0); 393704#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 393699#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 393695#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 393691#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 393686#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 393682#L576-30 assume !(1 == ~t7_pc~0); 393678#L576-32 is_transmit7_triggered_~__retres1~7#1 := 0; 393672#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 393668#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 393664#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 393660#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 393656#L595-30 assume !(1 == ~t8_pc~0); 393652#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 393647#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 393643#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 393639#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 393635#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 393631#L614-30 assume 1 == ~t9_pc~0; 393626#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 393621#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 393617#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 393613#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 393608#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 393603#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 393598#L1025-5 assume !(1 == ~T1_E~0); 393593#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 392767#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 393586#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 393581#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 393578#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 393575#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 393571#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 393567#L1065-3 assume !(1 == ~T9_E~0); 393563#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 393558#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 393555#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 392743#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 393550#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 393547#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 393543#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 393538#L1105-3 assume !(1 == ~E_8~0); 393535#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 393533#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 393459#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 393447#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 393444#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 393440#L1415 assume !(0 == start_simulation_~tmp~3#1); 393438#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 393427#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 393418#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 393415#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 390332#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 390329#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 390325#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 388355#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 388350#L1396-2 [2024-10-31 21:56:21,916 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 21:56:21,916 INFO L85 PathProgramCache]: Analyzing trace with hash -683232136, now seen corresponding path program 1 times [2024-10-31 21:56:21,916 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 21:56:21,916 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [200367118] [2024-10-31 21:56:21,916 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 21:56:21,917 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 21:56:21,933 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 21:56:22,005 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 21:56:22,005 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 21:56:22,005 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [200367118] [2024-10-31 21:56:22,006 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [200367118] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 21:56:22,006 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 21:56:22,006 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 21:56:22,006 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1285634062] [2024-10-31 21:56:22,006 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 21:56:22,007 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 21:56:22,007 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 21:56:22,007 INFO L85 PathProgramCache]: Analyzing trace with hash -1139643444, now seen corresponding path program 1 times [2024-10-31 21:56:22,007 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 21:56:22,007 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1067868029] [2024-10-31 21:56:22,007 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 21:56:22,008 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 21:56:22,023 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 21:56:22,063 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 21:56:22,063 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 21:56:22,063 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1067868029] [2024-10-31 21:56:22,063 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1067868029] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 21:56:22,063 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 21:56:22,063 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 21:56:22,064 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [85947046] [2024-10-31 21:56:22,064 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 21:56:22,064 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 21:56:22,064 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 21:56:22,065 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-10-31 21:56:22,065 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-10-31 21:56:22,065 INFO L87 Difference]: Start difference. First operand 97474 states and 139263 transitions. cyclomatic complexity: 41917 Second operand has 4 states, 4 states have (on average 28.75) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 21:56:22,264 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 21:56:22,265 INFO L93 Difference]: Finished difference Result 48786 states and 69423 transitions. [2024-10-31 21:56:22,265 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 48786 states and 69423 transitions. [2024-10-31 21:56:22,471 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 48368 [2024-10-31 21:56:22,621 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 48786 states to 48786 states and 69423 transitions. [2024-10-31 21:56:22,622 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 48786 [2024-10-31 21:56:22,651 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 48786 [2024-10-31 21:56:22,651 INFO L73 IsDeterministic]: Start isDeterministic. Operand 48786 states and 69423 transitions. [2024-10-31 21:56:22,684 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 21:56:22,685 INFO L218 hiAutomatonCegarLoop]: Abstraction has 48786 states and 69423 transitions. [2024-10-31 21:56:22,716 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 48786 states and 69423 transitions. [2024-10-31 21:56:23,546 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 48786 to 25611. [2024-10-31 21:56:23,568 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 25611 states, 25611 states have (on average 1.4194681972589902) internal successors, (36354), 25610 states have internal predecessors, (36354), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 21:56:23,612 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25611 states to 25611 states and 36354 transitions. [2024-10-31 21:56:23,612 INFO L240 hiAutomatonCegarLoop]: Abstraction has 25611 states and 36354 transitions. [2024-10-31 21:56:23,613 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-10-31 21:56:23,614 INFO L425 stractBuchiCegarLoop]: Abstraction has 25611 states and 36354 transitions. [2024-10-31 21:56:23,614 INFO L332 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2024-10-31 21:56:23,614 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 25611 states and 36354 transitions. [2024-10-31 21:56:23,688 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 25344 [2024-10-31 21:56:23,688 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 21:56:23,688 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 21:56:23,690 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 21:56:23,690 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 21:56:23,691 INFO L745 eck$LassoCheckResult]: Stem: 527754#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 527755#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 528603#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 528604#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 528543#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 528544#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 528516#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 528301#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 528302#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 528092#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 528093#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 528638#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 528499#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 528159#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 527910#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 527911#L922 assume !(0 == ~M_E~0); 528706#L922-2 assume !(0 == ~T1_E~0); 528707#L927-1 assume !(0 == ~T2_E~0); 528373#L932-1 assume !(0 == ~T3_E~0); 528234#L937-1 assume !(0 == ~T4_E~0); 528235#L942-1 assume !(0 == ~T5_E~0); 528300#L947-1 assume !(0 == ~T6_E~0); 528378#L952-1 assume !(0 == ~T7_E~0); 528379#L957-1 assume !(0 == ~T8_E~0); 528441#L962-1 assume !(0 == ~T9_E~0); 528208#L967-1 assume !(0 == ~E_1~0); 528209#L972-1 assume !(0 == ~E_2~0); 528525#L977-1 assume !(0 == ~E_3~0); 528526#L982-1 assume !(0 == ~E_4~0); 527689#L987-1 assume !(0 == ~E_5~0); 527690#L992-1 assume !(0 == ~E_6~0); 527696#L997-1 assume !(0 == ~E_7~0); 528133#L1002-1 assume !(0 == ~E_8~0); 528120#L1007-1 assume !(0 == ~E_9~0); 527482#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 527483#L443 assume !(1 == ~m_pc~0); 528393#L443-2 is_master_triggered_~__retres1~0#1 := 0; 528385#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 528386#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 527850#L1140 assume !(0 != activate_threads_~tmp~1#1); 527588#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 527589#L462 assume !(1 == ~t1_pc~0); 528223#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 528224#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 527524#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 527525#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 528070#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 528071#L481 assume !(1 == ~t2_pc~0); 527844#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 527843#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 527972#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 527934#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 527935#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 528037#L500 assume !(1 == ~t3_pc~0); 528594#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 528564#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 527489#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 527490#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 527484#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 527485#L519 assume !(1 == ~t4_pc~0); 528289#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 528036#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 527590#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 527591#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 527884#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 527652#L538 assume !(1 == ~t5_pc~0); 527653#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 527549#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 527550#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 527829#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 527830#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 528426#L557 assume !(1 == ~t6_pc~0); 527864#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 527865#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 527953#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 527885#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 527886#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 528673#L576 assume !(1 == ~t7_pc~0); 527854#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 527855#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 528195#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 528698#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 528491#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 527976#L595 assume !(1 == ~t8_pc~0); 527977#L595-2 is_transmit8_triggered_~__retres1~8#1 := 0; 528510#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 528431#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 528330#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 528331#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 527779#L614 assume !(1 == ~t9_pc~0); 527780#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 527677#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 527678#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 528012#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 527937#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 527938#L1025 assume !(1 == ~M_E~0); 528217#L1025-2 assume !(1 == ~T1_E~0); 528281#L1030-1 assume !(1 == ~T2_E~0); 528418#L1035-1 assume !(1 == ~T3_E~0); 527929#L1040-1 assume !(1 == ~T4_E~0); 527930#L1045-1 assume !(1 == ~T5_E~0); 527840#L1050-1 assume !(1 == ~T6_E~0); 527841#L1055-1 assume !(1 == ~T7_E~0); 527663#L1060-1 assume !(1 == ~T8_E~0); 527664#L1065-1 assume !(1 == ~T9_E~0); 527727#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 528380#L1075-1 assume !(1 == ~E_2~0); 528381#L1080-1 assume !(1 == ~E_3~0); 528368#L1085-1 assume !(1 == ~E_4~0); 528369#L1090-1 assume !(1 == ~E_5~0); 528627#L1095-1 assume !(1 == ~E_6~0); 528402#L1100-1 assume !(1 == ~E_7~0); 528403#L1105-1 assume !(1 == ~E_8~0); 527634#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 527635#L1115-1 assume { :end_inline_reset_delta_events } true; 527985#L1396-2 [2024-10-31 21:56:23,691 INFO L747 eck$LassoCheckResult]: Loop: 527985#L1396-2 assume !false; 536795#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 536791#L897-1 assume !false; 536789#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 536785#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 536774#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 536772#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 536769#L766 assume !(0 != eval_~tmp~0#1); 536770#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 537139#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 537137#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 537135#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 537133#L927-3 assume !(0 == ~T2_E~0); 537131#L932-3 assume !(0 == ~T3_E~0); 537129#L937-3 assume !(0 == ~T4_E~0); 537127#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 537122#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 537120#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 537118#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 537117#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 537106#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 537104#L972-3 assume !(0 == ~E_2~0); 537102#L977-3 assume !(0 == ~E_3~0); 537099#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 537095#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 537091#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 537087#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 537083#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 537080#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 537077#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 537076#L443-30 assume 1 == ~m_pc~0; 537074#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 537073#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 537072#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 537071#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 537070#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 537069#L462-30 assume !(1 == ~t1_pc~0); 537068#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 537067#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 537066#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 537065#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 537064#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 537063#L481-30 assume 1 == ~t2_pc~0; 537060#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 537058#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 537056#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 537055#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 537052#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 537051#L500-30 assume !(1 == ~t3_pc~0); 537050#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 537049#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 537048#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 537047#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 537046#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 537045#L519-30 assume !(1 == ~t4_pc~0); 537044#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 537043#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 537042#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 537041#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 537040#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 537038#L538-30 assume !(1 == ~t5_pc~0); 537035#L538-32 is_transmit5_triggered_~__retres1~5#1 := 0; 537034#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 537032#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 537030#L1180-30 assume !(0 != activate_threads_~tmp___4~0#1); 537027#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 537026#L557-30 assume !(1 == ~t6_pc~0); 537023#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 537022#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 537021#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 537020#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 537019#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 537018#L576-30 assume 1 == ~t7_pc~0; 537016#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 537015#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 537014#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 537013#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 537012#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 537011#L595-30 assume !(1 == ~t8_pc~0); 537010#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 537009#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 537008#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 537007#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 537006#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 537005#L614-30 assume 1 == ~t9_pc~0; 537003#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 537002#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 537001#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 537000#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 536998#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 536995#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 536993#L1025-5 assume !(1 == ~T1_E~0); 536991#L1030-3 assume !(1 == ~T2_E~0); 536989#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 536987#L1040-3 assume !(1 == ~T4_E~0); 536985#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 536983#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 536981#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 536979#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 536977#L1065-3 assume !(1 == ~T9_E~0); 536975#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 536973#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 536970#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 536968#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 536966#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 536964#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 536962#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 536960#L1105-3 assume !(1 == ~E_8~0); 536958#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 536956#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 536953#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 536942#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 536940#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 536831#L1415 assume !(0 == start_simulation_~tmp~3#1); 536828#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 536816#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 536808#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 536806#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 536804#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 536802#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 536800#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 536798#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 527985#L1396-2 [2024-10-31 21:56:23,692 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 21:56:23,692 INFO L85 PathProgramCache]: Analyzing trace with hash 1781320180, now seen corresponding path program 1 times [2024-10-31 21:56:23,692 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 21:56:23,692 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1443773385] [2024-10-31 21:56:23,692 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 21:56:23,693 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 21:56:23,710 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 21:56:23,778 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 21:56:23,779 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 21:56:23,779 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1443773385] [2024-10-31 21:56:23,779 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1443773385] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 21:56:23,779 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 21:56:23,779 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 21:56:23,780 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [93815374] [2024-10-31 21:56:23,780 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 21:56:23,780 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 21:56:23,780 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 21:56:23,781 INFO L85 PathProgramCache]: Analyzing trace with hash 1852486821, now seen corresponding path program 1 times [2024-10-31 21:56:23,781 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 21:56:23,781 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [613682442] [2024-10-31 21:56:23,781 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 21:56:23,782 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 21:56:23,797 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 21:56:23,837 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 21:56:23,837 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 21:56:23,837 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [613682442] [2024-10-31 21:56:23,837 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [613682442] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 21:56:23,838 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 21:56:23,838 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 21:56:23,838 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [532055170] [2024-10-31 21:56:23,838 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 21:56:23,839 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 21:56:23,839 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 21:56:23,839 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-10-31 21:56:23,840 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-10-31 21:56:23,840 INFO L87 Difference]: Start difference. First operand 25611 states and 36354 transitions. cyclomatic complexity: 10775 Second operand has 4 states, 4 states have (on average 28.75) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 21:56:24,142 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 21:56:24,142 INFO L93 Difference]: Finished difference Result 52812 states and 74750 transitions. [2024-10-31 21:56:24,142 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 52812 states and 74750 transitions. [2024-10-31 21:56:24,346 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 52240 [2024-10-31 21:56:24,890 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 52812 states to 52812 states and 74750 transitions. [2024-10-31 21:56:24,890 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 52812 [2024-10-31 21:56:24,912 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 52812 [2024-10-31 21:56:24,912 INFO L73 IsDeterministic]: Start isDeterministic. Operand 52812 states and 74750 transitions. [2024-10-31 21:56:24,949 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 21:56:24,949 INFO L218 hiAutomatonCegarLoop]: Abstraction has 52812 states and 74750 transitions. [2024-10-31 21:56:24,973 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 52812 states and 74750 transitions. [2024-10-31 21:56:25,244 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 52812 to 28595. [2024-10-31 21:56:25,269 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 28595 states, 28595 states have (on average 1.4160867284490295) internal successors, (40493), 28594 states have internal predecessors, (40493), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 21:56:25,314 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28595 states to 28595 states and 40493 transitions. [2024-10-31 21:56:25,315 INFO L240 hiAutomatonCegarLoop]: Abstraction has 28595 states and 40493 transitions. [2024-10-31 21:56:25,315 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-10-31 21:56:25,315 INFO L425 stractBuchiCegarLoop]: Abstraction has 28595 states and 40493 transitions. [2024-10-31 21:56:25,316 INFO L332 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2024-10-31 21:56:25,316 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 28595 states and 40493 transitions. [2024-10-31 21:56:25,392 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 28240 [2024-10-31 21:56:25,392 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 21:56:25,393 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 21:56:25,394 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 21:56:25,395 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 21:56:25,395 INFO L745 eck$LassoCheckResult]: Stem: 606190#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 606191#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 607017#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 607018#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 606959#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 606960#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 606939#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 606737#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 606738#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 606521#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 606522#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 607046#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 606926#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 606595#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 606346#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 606347#L922 assume !(0 == ~M_E~0); 607101#L922-2 assume !(0 == ~T1_E~0); 607102#L927-1 assume !(0 == ~T2_E~0); 606804#L932-1 assume !(0 == ~T3_E~0); 606672#L937-1 assume !(0 == ~T4_E~0); 606673#L942-1 assume !(0 == ~T5_E~0); 606736#L947-1 assume !(0 == ~T6_E~0); 606808#L952-1 assume !(0 == ~T7_E~0); 606809#L957-1 assume !(0 == ~T8_E~0); 606876#L962-1 assume !(0 == ~T9_E~0); 606645#L967-1 assume 0 == ~E_1~0;~E_1~0 := 1; 606646#L972-1 assume !(0 == ~E_2~0); 606944#L977-1 assume !(0 == ~E_3~0); 606945#L982-1 assume !(0 == ~E_4~0); 606122#L987-1 assume !(0 == ~E_5~0); 606123#L992-1 assume !(0 == ~E_6~0); 606567#L997-1 assume !(0 == ~E_7~0); 606568#L1002-1 assume !(0 == ~E_8~0); 606552#L1007-1 assume !(0 == ~E_9~0); 606553#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 607059#L443 assume !(1 == ~m_pc~0); 607060#L443-2 is_master_triggered_~__retres1~0#1 := 0; 606815#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 606816#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 606284#L1140 assume !(0 != activate_threads_~tmp~1#1); 606021#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 606022#L462 assume !(1 == ~t1_pc~0); 606663#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 606664#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 605957#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 605958#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 606500#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 606501#L481 assume !(1 == ~t2_pc~0); 606278#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 606277#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 607171#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 607170#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 606468#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 606469#L500 assume !(1 == ~t3_pc~0); 607169#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 607168#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 605922#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 605923#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 605917#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 605918#L519 assume !(1 == ~t4_pc~0); 606726#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 606727#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 607163#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 607162#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 607161#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 607160#L538 assume !(1 == ~t5_pc~0); 606499#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 607159#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 607156#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 607153#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 606858#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 606859#L557 assume !(1 == ~t6_pc~0); 607151#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 607150#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 607149#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 607148#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 607147#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 607107#L576 assume !(1 == ~t7_pc~0); 606288#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 606289#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 606633#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 607098#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 607142#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 607141#L595 assume !(1 == ~t8_pc~0); 607140#L595-2 is_transmit8_triggered_~__retres1~8#1 := 0; 607139#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 607138#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 607137#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 607136#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 607135#L614 assume !(1 == ~t9_pc~0); 607133#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 607132#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 606443#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 606444#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 606371#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 606372#L1025 assume !(1 == ~M_E~0); 606655#L1025-2 assume !(1 == ~T1_E~0); 606719#L1030-1 assume !(1 == ~T2_E~0); 606851#L1035-1 assume !(1 == ~T3_E~0); 606363#L1040-1 assume !(1 == ~T4_E~0); 606364#L1045-1 assume !(1 == ~T5_E~0); 606274#L1050-1 assume !(1 == ~T6_E~0); 606275#L1055-1 assume !(1 == ~T7_E~0); 607122#L1060-1 assume !(1 == ~T8_E~0); 607121#L1065-1 assume !(1 == ~T9_E~0); 607120#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 606810#L1075-1 assume !(1 == ~E_2~0); 606811#L1080-1 assume !(1 == ~E_3~0); 606799#L1085-1 assume !(1 == ~E_4~0); 606800#L1090-1 assume !(1 == ~E_5~0); 607037#L1095-1 assume !(1 == ~E_6~0); 606837#L1100-1 assume !(1 == ~E_7~0); 606838#L1105-1 assume !(1 == ~E_8~0); 606067#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 606068#L1115-1 assume { :end_inline_reset_delta_events } true; 606418#L1396-2 [2024-10-31 21:56:25,395 INFO L747 eck$LassoCheckResult]: Loop: 606418#L1396-2 assume !false; 613919#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 613914#L897-1 assume !false; 613912#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 613909#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 613898#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 613896#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 613893#L766 assume !(0 != eval_~tmp~0#1); 613894#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 614247#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 614245#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 614244#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 614240#L927-3 assume !(0 == ~T2_E~0); 614238#L932-3 assume !(0 == ~T3_E~0); 614236#L937-3 assume !(0 == ~T4_E~0); 614234#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 614231#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 614229#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 614227#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 614224#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 614222#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 614221#L972-3 assume !(0 == ~E_2~0); 614220#L977-3 assume !(0 == ~E_3~0); 614219#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 614218#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 614217#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 614216#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 614215#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 614214#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 614213#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 614212#L443-30 assume !(1 == ~m_pc~0); 614211#L443-32 is_master_triggered_~__retres1~0#1 := 0; 614209#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 614208#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 614207#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 614206#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 614205#L462-30 assume !(1 == ~t1_pc~0); 614204#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 614203#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 614202#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 614201#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 614200#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 614199#L481-30 assume 1 == ~t2_pc~0; 614197#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 614196#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 614195#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 614194#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 614193#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 614192#L500-30 assume !(1 == ~t3_pc~0); 614191#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 614190#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 614189#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 614188#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 614187#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 614186#L519-30 assume !(1 == ~t4_pc~0); 614185#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 614184#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 614183#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 614182#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 614181#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 614180#L538-30 assume !(1 == ~t5_pc~0); 614179#L538-32 is_transmit5_triggered_~__retres1~5#1 := 0; 614177#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 614175#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 614173#L1180-30 assume !(0 != activate_threads_~tmp___4~0#1); 614171#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 614170#L557-30 assume !(1 == ~t6_pc~0); 614169#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 614168#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 614167#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 614166#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 614165#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 614164#L576-30 assume !(1 == ~t7_pc~0); 614163#L576-32 is_transmit7_triggered_~__retres1~7#1 := 0; 614161#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 614160#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 614159#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 614158#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 614157#L595-30 assume !(1 == ~t8_pc~0); 614156#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 614155#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 614154#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 614153#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 614152#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 614151#L614-30 assume 1 == ~t9_pc~0; 614149#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 614148#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 614147#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 614146#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 614145#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 614144#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 614143#L1025-5 assume !(1 == ~T1_E~0); 614142#L1030-3 assume !(1 == ~T2_E~0); 614141#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 614140#L1040-3 assume !(1 == ~T4_E~0); 614139#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 614138#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 614137#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 614136#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 614135#L1065-3 assume !(1 == ~T9_E~0); 614133#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 614132#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 614131#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 614130#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 614129#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 614128#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 614126#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 614123#L1105-3 assume !(1 == ~E_8~0); 614121#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 614119#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 614116#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 614105#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 614103#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 613958#L1415 assume !(0 == start_simulation_~tmp~3#1); 613956#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 613940#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 613930#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 613929#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 613928#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 613927#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 613925#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 613922#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 606418#L1396-2 [2024-10-31 21:56:25,396 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 21:56:25,396 INFO L85 PathProgramCache]: Analyzing trace with hash -95743050, now seen corresponding path program 1 times [2024-10-31 21:56:25,396 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 21:56:25,397 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1873814803] [2024-10-31 21:56:25,397 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 21:56:25,397 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 21:56:25,411 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 21:56:25,468 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 21:56:25,468 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 21:56:25,468 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1873814803] [2024-10-31 21:56:25,468 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1873814803] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 21:56:25,468 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 21:56:25,469 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 21:56:25,469 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [732725022] [2024-10-31 21:56:25,469 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 21:56:25,470 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 21:56:25,470 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 21:56:25,471 INFO L85 PathProgramCache]: Analyzing trace with hash -1504379997, now seen corresponding path program 1 times [2024-10-31 21:56:25,471 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 21:56:25,471 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [848558882] [2024-10-31 21:56:25,472 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 21:56:25,472 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 21:56:25,486 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 21:56:25,523 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 21:56:25,523 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 21:56:25,523 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [848558882] [2024-10-31 21:56:25,523 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [848558882] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 21:56:25,523 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 21:56:25,523 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 21:56:25,523 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1530979848] [2024-10-31 21:56:25,524 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 21:56:25,524 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 21:56:25,524 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 21:56:25,524 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-10-31 21:56:25,524 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-10-31 21:56:25,525 INFO L87 Difference]: Start difference. First operand 28595 states and 40493 transitions. cyclomatic complexity: 11930 Second operand has 4 states, 4 states have (on average 28.75) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 21:56:25,768 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 21:56:25,768 INFO L93 Difference]: Finished difference Result 48811 states and 68992 transitions. [2024-10-31 21:56:25,768 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 48811 states and 68992 transitions. [2024-10-31 21:56:26,359 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 48336 [2024-10-31 21:56:26,462 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 48811 states to 48811 states and 68992 transitions. [2024-10-31 21:56:26,462 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 48811 [2024-10-31 21:56:26,490 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 48811 [2024-10-31 21:56:26,490 INFO L73 IsDeterministic]: Start isDeterministic. Operand 48811 states and 68992 transitions. [2024-10-31 21:56:26,526 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-10-31 21:56:26,526 INFO L218 hiAutomatonCegarLoop]: Abstraction has 48811 states and 68992 transitions. [2024-10-31 21:56:26,562 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 48811 states and 68992 transitions. [2024-10-31 21:56:26,910 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 48811 to 25611. [2024-10-31 21:56:26,927 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 25611 states, 25611 states have (on average 1.4106438639647028) internal successors, (36128), 25610 states have internal predecessors, (36128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 21:56:26,978 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25611 states to 25611 states and 36128 transitions. [2024-10-31 21:56:26,978 INFO L240 hiAutomatonCegarLoop]: Abstraction has 25611 states and 36128 transitions. [2024-10-31 21:56:26,979 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-10-31 21:56:26,979 INFO L425 stractBuchiCegarLoop]: Abstraction has 25611 states and 36128 transitions. [2024-10-31 21:56:26,979 INFO L332 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2024-10-31 21:56:26,979 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 25611 states and 36128 transitions. [2024-10-31 21:56:27,051 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 25344 [2024-10-31 21:56:27,051 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-10-31 21:56:27,051 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-10-31 21:56:27,053 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 21:56:27,053 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-10-31 21:56:27,054 INFO L745 eck$LassoCheckResult]: Stem: 683607#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 683608#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 684436#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 684437#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 684376#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 684377#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 684353#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 684141#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 684142#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 683935#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 683936#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 684477#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 684343#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 684002#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 683759#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 683760#L922 assume !(0 == ~M_E~0); 684533#L922-2 assume !(0 == ~T1_E~0); 684534#L927-1 assume !(0 == ~T2_E~0); 684213#L932-1 assume !(0 == ~T3_E~0); 684080#L937-1 assume !(0 == ~T4_E~0); 684081#L942-1 assume !(0 == ~T5_E~0); 684140#L947-1 assume !(0 == ~T6_E~0); 684219#L952-1 assume !(0 == ~T7_E~0); 684220#L957-1 assume !(0 == ~T8_E~0); 684287#L962-1 assume !(0 == ~T9_E~0); 684059#L967-1 assume !(0 == ~E_1~0); 684060#L972-1 assume !(0 == ~E_2~0); 684358#L977-1 assume !(0 == ~E_3~0); 684359#L982-1 assume !(0 == ~E_4~0); 683541#L987-1 assume !(0 == ~E_5~0); 683542#L992-1 assume !(0 == ~E_6~0); 683546#L997-1 assume !(0 == ~E_7~0); 683978#L1002-1 assume !(0 == ~E_8~0); 683965#L1007-1 assume !(0 == ~E_9~0); 683331#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 683332#L443 assume !(1 == ~m_pc~0); 684235#L443-2 is_master_triggered_~__retres1~0#1 := 0; 684227#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 684228#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 683698#L1140 assume !(0 != activate_threads_~tmp~1#1); 683438#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 683439#L462 assume !(1 == ~t1_pc~0); 684071#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 684072#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 683373#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 683374#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 683914#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 683915#L481 assume !(1 == ~t2_pc~0); 683692#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 683691#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 683820#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 683782#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 683783#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 683884#L500 assume !(1 == ~t3_pc~0); 684427#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 684393#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 683338#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 683339#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 683336#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 683337#L519 assume !(1 == ~t4_pc~0); 684132#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 683881#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 683440#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 683441#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 683734#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 683502#L538 assume !(1 == ~t5_pc~0); 683503#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 683400#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 683401#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 683677#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 683678#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 684271#L557 assume !(1 == ~t6_pc~0); 683712#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 683713#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 683801#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 683735#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 683736#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 684507#L576 assume !(1 == ~t7_pc~0); 683702#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 683703#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 684042#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 684529#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 684332#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 683825#L595 assume !(1 == ~t8_pc~0); 683826#L595-2 is_transmit8_triggered_~__retres1~8#1 := 0; 684349#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 684275#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 684164#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 684165#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 683629#L614 assume !(1 == ~t9_pc~0); 683630#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 683528#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 683529#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 683858#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 683785#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 683786#L1025 assume !(1 == ~M_E~0); 684064#L1025-2 assume !(1 == ~T1_E~0); 684125#L1030-1 assume !(1 == ~T2_E~0); 684261#L1035-1 assume !(1 == ~T3_E~0); 683778#L1040-1 assume !(1 == ~T4_E~0); 683779#L1045-1 assume !(1 == ~T5_E~0); 683688#L1050-1 assume !(1 == ~T6_E~0); 683689#L1055-1 assume !(1 == ~T7_E~0); 683513#L1060-1 assume !(1 == ~T8_E~0); 683514#L1065-1 assume !(1 == ~T9_E~0); 683578#L1070-1 assume !(1 == ~E_1~0); 684222#L1075-1 assume !(1 == ~E_2~0); 684223#L1080-1 assume !(1 == ~E_3~0); 684208#L1085-1 assume !(1 == ~E_4~0); 684209#L1090-1 assume !(1 == ~E_5~0); 684467#L1095-1 assume !(1 == ~E_6~0); 684244#L1100-1 assume !(1 == ~E_7~0); 684245#L1105-1 assume !(1 == ~E_8~0); 683484#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 683485#L1115-1 assume { :end_inline_reset_delta_events } true; 683832#L1396-2 [2024-10-31 21:56:27,055 INFO L747 eck$LassoCheckResult]: Loop: 683832#L1396-2 assume !false; 694726#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 694671#L897-1 assume !false; 694668#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 694543#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 694533#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 694532#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 694526#L766 assume !(0 != eval_~tmp~0#1); 694527#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 695481#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 695479#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 695477#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 695475#L927-3 assume !(0 == ~T2_E~0); 695473#L932-3 assume !(0 == ~T3_E~0); 695471#L937-3 assume !(0 == ~T4_E~0); 695469#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 695467#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 695465#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 695437#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 695432#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 695427#L967-3 assume !(0 == ~E_1~0); 695418#L972-3 assume !(0 == ~E_2~0); 695415#L977-3 assume !(0 == ~E_3~0); 695413#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 695411#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 695409#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 695407#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 695405#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 695403#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 695401#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 695399#L443-30 assume 1 == ~m_pc~0; 695396#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 695394#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 695392#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 695379#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 695374#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 695368#L462-30 assume !(1 == ~t1_pc~0); 695363#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 695359#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 695355#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 695351#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 695346#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 695338#L481-30 assume 1 == ~t2_pc~0; 695332#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 695327#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 695323#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 695319#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 695315#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 695309#L500-30 assume !(1 == ~t3_pc~0); 695305#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 695300#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 695295#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 695290#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 695284#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 695278#L519-30 assume !(1 == ~t4_pc~0); 695273#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 695268#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 695263#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 695258#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 695253#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 695247#L538-30 assume !(1 == ~t5_pc~0); 695242#L538-32 is_transmit5_triggered_~__retres1~5#1 := 0; 695236#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 695230#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 695224#L1180-30 assume !(0 != activate_threads_~tmp___4~0#1); 695218#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 695212#L557-30 assume !(1 == ~t6_pc~0); 695206#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 695200#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 695194#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 695189#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 695184#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 695177#L576-30 assume 1 == ~t7_pc~0; 695170#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 695164#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 695158#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 695153#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 695149#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 695143#L595-30 assume !(1 == ~t8_pc~0); 695137#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 695131#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 695125#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 695119#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 695111#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 695108#L614-30 assume !(1 == ~t9_pc~0); 695106#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 695103#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 695101#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 695099#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 695097#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 695087#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 695080#L1025-5 assume !(1 == ~T1_E~0); 695074#L1030-3 assume !(1 == ~T2_E~0); 694851#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 694850#L1040-3 assume !(1 == ~T4_E~0); 694849#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 694848#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 694847#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 694845#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 694843#L1065-3 assume !(1 == ~T9_E~0); 694841#L1070-3 assume !(1 == ~E_1~0); 694838#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 694836#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 694834#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 694832#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 694830#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 694829#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 694828#L1105-3 assume !(1 == ~E_8~0); 694827#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 694826#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 694823#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 694811#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 694809#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 694800#L1415 assume !(0 == start_simulation_~tmp~3#1); 694797#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 694748#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 694739#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 694737#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 694735#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 694733#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 694731#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 694729#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 683832#L1396-2 [2024-10-31 21:56:27,056 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 21:56:27,056 INFO L85 PathProgramCache]: Analyzing trace with hash 1388293170, now seen corresponding path program 1 times [2024-10-31 21:56:27,056 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 21:56:27,056 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1063325660] [2024-10-31 21:56:27,056 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 21:56:27,057 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 21:56:27,076 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 21:56:27,160 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 21:56:27,161 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 21:56:27,161 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1063325660] [2024-10-31 21:56:27,161 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1063325660] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 21:56:27,161 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 21:56:27,161 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 21:56:27,162 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1140423099] [2024-10-31 21:56:27,162 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 21:56:27,162 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-10-31 21:56:27,163 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-10-31 21:56:27,163 INFO L85 PathProgramCache]: Analyzing trace with hash 727953536, now seen corresponding path program 1 times [2024-10-31 21:56:27,163 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-10-31 21:56:27,163 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1842677333] [2024-10-31 21:56:27,164 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-10-31 21:56:27,164 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-10-31 21:56:27,181 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-10-31 21:56:27,224 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-10-31 21:56:27,224 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-10-31 21:56:27,224 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1842677333] [2024-10-31 21:56:27,225 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1842677333] provided 1 perfect and 0 imperfect interpolant sequences [2024-10-31 21:56:27,225 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-10-31 21:56:27,225 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-10-31 21:56:27,225 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1104573120] [2024-10-31 21:56:27,225 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-10-31 21:56:27,226 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-10-31 21:56:27,226 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-10-31 21:56:27,227 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-10-31 21:56:27,227 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-10-31 21:56:27,227 INFO L87 Difference]: Start difference. First operand 25611 states and 36128 transitions. cyclomatic complexity: 10549 Second operand has 4 states, 4 states have (on average 28.75) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-10-31 21:56:27,603 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-10-31 21:56:27,604 INFO L93 Difference]: Finished difference Result 53052 states and 74347 transitions. [2024-10-31 21:56:27,604 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 53052 states and 74347 transitions. [2024-10-31 21:56:27,847 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 52512