./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/termination-restricted-15/NarrowKonv.c --full-output --architecture 64bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version a0165632 Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/termination-restricted-15/NarrowKonv.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/config/svcomp-Termination-64bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash 2c8d79b985e49ac5d6f27b4e25f4e3597dadc4ec57e262caec7782b796e874b7 --- Real Ultimate output --- This is Ultimate 0.2.5-dev-a016563 [2024-11-08 18:35:06,789 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-08 18:35:06,884 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/config/svcomp-Termination-64bit-Automizer_Default.epf [2024-11-08 18:35:06,893 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-08 18:35:06,894 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-08 18:35:06,928 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-08 18:35:06,930 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-08 18:35:06,931 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-08 18:35:06,932 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-08 18:35:06,936 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-08 18:35:06,937 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-08 18:35:06,937 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-08 18:35:06,938 INFO L153 SettingsManager]: * Use SBE=true [2024-11-08 18:35:06,938 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-11-08 18:35:06,938 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-11-08 18:35:06,939 INFO L153 SettingsManager]: * Use old map elimination=false [2024-11-08 18:35:06,939 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-11-08 18:35:06,939 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-11-08 18:35:06,940 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-11-08 18:35:06,940 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-08 18:35:06,940 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-11-08 18:35:06,944 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-08 18:35:06,944 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-08 18:35:06,944 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-11-08 18:35:06,945 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-11-08 18:35:06,945 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-11-08 18:35:06,946 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-11-08 18:35:06,946 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-11-08 18:35:06,946 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-08 18:35:06,947 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-11-08 18:35:06,947 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-08 18:35:06,947 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-11-08 18:35:06,948 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-08 18:35:06,948 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-08 18:35:06,948 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-11-08 18:35:06,949 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-11-08 18:35:06,949 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 2c8d79b985e49ac5d6f27b4e25f4e3597dadc4ec57e262caec7782b796e874b7 [2024-11-08 18:35:07,229 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-08 18:35:07,259 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-08 18:35:07,262 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-08 18:35:07,265 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-08 18:35:07,265 INFO L274 PluginConnector]: CDTParser initialized [2024-11-08 18:35:07,267 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/../../sv-benchmarks/c/termination-restricted-15/NarrowKonv.c Unable to find full path for "g++" [2024-11-08 18:35:09,189 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-11-08 18:35:09,357 INFO L384 CDTParser]: Found 1 translation units. [2024-11-08 18:35:09,357 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/sv-benchmarks/c/termination-restricted-15/NarrowKonv.c [2024-11-08 18:35:09,363 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/data/82015623a/a40a2216324f47919d4ab962bec7405f/FLAG8eb86dc08 [2024-11-08 18:35:09,377 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/data/82015623a/a40a2216324f47919d4ab962bec7405f [2024-11-08 18:35:09,380 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-08 18:35:09,381 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-08 18:35:09,383 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-08 18:35:09,383 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-08 18:35:09,388 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-08 18:35:09,389 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 08.11 06:35:09" (1/1) ... [2024-11-08 18:35:09,390 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@436bdbf1 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 06:35:09, skipping insertion in model container [2024-11-08 18:35:09,390 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 08.11 06:35:09" (1/1) ... [2024-11-08 18:35:09,413 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-08 18:35:09,586 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-08 18:35:09,592 INFO L200 MainTranslator]: Completed pre-run [2024-11-08 18:35:09,602 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-08 18:35:09,615 INFO L204 MainTranslator]: Completed translation [2024-11-08 18:35:09,615 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 06:35:09 WrapperNode [2024-11-08 18:35:09,616 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-08 18:35:09,616 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-08 18:35:09,616 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-08 18:35:09,617 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-08 18:35:09,622 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 06:35:09" (1/1) ... [2024-11-08 18:35:09,626 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 06:35:09" (1/1) ... [2024-11-08 18:35:09,642 INFO L138 Inliner]: procedures = 4, calls = 2, calls flagged for inlining = 2, calls inlined = 2, statements flattened = 18 [2024-11-08 18:35:09,643 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-08 18:35:09,643 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-08 18:35:09,643 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-08 18:35:09,644 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-08 18:35:09,655 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 06:35:09" (1/1) ... [2024-11-08 18:35:09,655 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 06:35:09" (1/1) ... [2024-11-08 18:35:09,655 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 06:35:09" (1/1) ... [2024-11-08 18:35:09,661 INFO L175 MemorySlicer]: No memory access in input program. [2024-11-08 18:35:09,662 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 06:35:09" (1/1) ... [2024-11-08 18:35:09,662 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 06:35:09" (1/1) ... [2024-11-08 18:35:09,664 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 06:35:09" (1/1) ... [2024-11-08 18:35:09,667 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 06:35:09" (1/1) ... [2024-11-08 18:35:09,668 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 06:35:09" (1/1) ... [2024-11-08 18:35:09,669 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 06:35:09" (1/1) ... [2024-11-08 18:35:09,670 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-08 18:35:09,670 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-11-08 18:35:09,671 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-11-08 18:35:09,671 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-11-08 18:35:09,672 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 06:35:09" (1/1) ... [2024-11-08 18:35:09,678 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 18:35:09,690 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 [2024-11-08 18:35:09,702 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 18:35:09,708 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-11-08 18:35:09,743 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-08 18:35:09,744 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-08 18:35:09,825 INFO L238 CfgBuilder]: Building ICFG [2024-11-08 18:35:09,828 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-08 18:35:09,923 INFO L? ?]: Removed 6 outVars from TransFormulas that were not future-live. [2024-11-08 18:35:09,923 INFO L287 CfgBuilder]: Performing block encoding [2024-11-08 18:35:09,934 INFO L311 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-08 18:35:09,934 INFO L316 CfgBuilder]: Removed 0 assume(true) statements. [2024-11-08 18:35:09,935 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 08.11 06:35:09 BoogieIcfgContainer [2024-11-08 18:35:09,935 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-11-08 18:35:09,936 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-11-08 18:35:09,936 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-11-08 18:35:09,940 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-11-08 18:35:09,941 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-08 18:35:09,941 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 08.11 06:35:09" (1/3) ... [2024-11-08 18:35:09,942 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7b82f1a8 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 08.11 06:35:09, skipping insertion in model container [2024-11-08 18:35:09,942 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-08 18:35:09,942 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 06:35:09" (2/3) ... [2024-11-08 18:35:09,943 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7b82f1a8 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 08.11 06:35:09, skipping insertion in model container [2024-11-08 18:35:09,943 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-08 18:35:09,943 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 08.11 06:35:09" (3/3) ... [2024-11-08 18:35:09,945 INFO L332 chiAutomizerObserver]: Analyzing ICFG NarrowKonv.c [2024-11-08 18:35:10,002 INFO L300 stractBuchiCegarLoop]: Interprodecural is true [2024-11-08 18:35:10,002 INFO L301 stractBuchiCegarLoop]: Hoare is None [2024-11-08 18:35:10,002 INFO L302 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-11-08 18:35:10,002 INFO L303 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-11-08 18:35:10,002 INFO L304 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-11-08 18:35:10,003 INFO L305 stractBuchiCegarLoop]: Difference is false [2024-11-08 18:35:10,003 INFO L306 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-11-08 18:35:10,003 INFO L310 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-11-08 18:35:10,008 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 10 states, 9 states have (on average 1.4444444444444444) internal successors, (13), 9 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 18:35:10,025 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2024-11-08 18:35:10,025 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 18:35:10,026 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 18:35:10,032 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2024-11-08 18:35:10,032 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-11-08 18:35:10,032 INFO L332 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-11-08 18:35:10,033 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 10 states, 9 states have (on average 1.4444444444444444) internal successors, (13), 9 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 18:35:10,034 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2024-11-08 18:35:10,034 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 18:35:10,034 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 18:35:10,035 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2024-11-08 18:35:10,035 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-11-08 18:35:10,042 INFO L745 eck$LassoCheckResult]: Stem: 7#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true; 8#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;havoc main_#t~nondet0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 3#L12-1true [2024-11-08 18:35:10,042 INFO L747 eck$LassoCheckResult]: Loop: 3#L12-1true assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 4#L11-1true assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 10#L12true assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3#L12-1true [2024-11-08 18:35:10,048 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:35:10,049 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 1 times [2024-11-08 18:35:10,063 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 18:35:10,064 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1225221473] [2024-11-08 18:35:10,064 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:35:10,065 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 18:35:10,151 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:35:10,152 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 18:35:10,166 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:35:10,183 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 18:35:10,185 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:35:10,185 INFO L85 PathProgramCache]: Analyzing trace with hash 35920, now seen corresponding path program 1 times [2024-11-08 18:35:10,185 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 18:35:10,186 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [713439442] [2024-11-08 18:35:10,186 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:35:10,186 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 18:35:10,200 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:35:10,201 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 18:35:10,207 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:35:10,212 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 18:35:10,214 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:35:10,214 INFO L85 PathProgramCache]: Analyzing trace with hash 28694862, now seen corresponding path program 1 times [2024-11-08 18:35:10,215 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 18:35:10,215 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1182051135] [2024-11-08 18:35:10,215 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:35:10,215 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 18:35:10,235 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 18:35:10,363 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 18:35:10,364 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 18:35:10,364 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1182051135] [2024-11-08 18:35:10,365 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1182051135] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 18:35:10,365 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 18:35:10,365 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-08 18:35:10,367 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [832416728] [2024-11-08 18:35:10,369 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 18:35:10,430 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 18:35:10,461 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 18:35:10,461 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 18:35:10,463 INFO L87 Difference]: Start difference. First operand has 10 states, 9 states have (on average 1.4444444444444444) internal successors, (13), 9 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 2 states have (on average 2.5) internal successors, (5), 3 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 18:35:10,498 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 18:35:10,499 INFO L93 Difference]: Finished difference Result 14 states and 20 transitions. [2024-11-08 18:35:10,500 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 14 states and 20 transitions. [2024-11-08 18:35:10,501 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 8 [2024-11-08 18:35:10,504 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 14 states to 10 states and 13 transitions. [2024-11-08 18:35:10,505 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10 [2024-11-08 18:35:10,506 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10 [2024-11-08 18:35:10,506 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10 states and 13 transitions. [2024-11-08 18:35:10,507 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 18:35:10,507 INFO L218 hiAutomatonCegarLoop]: Abstraction has 10 states and 13 transitions. [2024-11-08 18:35:10,524 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10 states and 13 transitions. [2024-11-08 18:35:10,532 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10 to 10. [2024-11-08 18:35:10,533 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10 states, 10 states have (on average 1.3) internal successors, (13), 9 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 18:35:10,533 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10 states to 10 states and 13 transitions. [2024-11-08 18:35:10,535 INFO L240 hiAutomatonCegarLoop]: Abstraction has 10 states and 13 transitions. [2024-11-08 18:35:10,536 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 18:35:10,539 INFO L425 stractBuchiCegarLoop]: Abstraction has 10 states and 13 transitions. [2024-11-08 18:35:10,540 INFO L332 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-11-08 18:35:10,540 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10 states and 13 transitions. [2024-11-08 18:35:10,540 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 8 [2024-11-08 18:35:10,541 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 18:35:10,541 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 18:35:10,541 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2024-11-08 18:35:10,541 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2024-11-08 18:35:10,542 INFO L745 eck$LassoCheckResult]: Stem: 40#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true; 41#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;havoc main_#t~nondet0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 35#L12-1 [2024-11-08 18:35:10,542 INFO L747 eck$LassoCheckResult]: Loop: 35#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 36#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 37#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 38#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 35#L12-1 [2024-11-08 18:35:10,542 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:35:10,543 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 2 times [2024-11-08 18:35:10,543 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 18:35:10,543 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1442128952] [2024-11-08 18:35:10,543 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:35:10,544 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 18:35:10,548 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:35:10,548 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 18:35:10,550 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:35:10,551 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 18:35:10,552 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:35:10,552 INFO L85 PathProgramCache]: Analyzing trace with hash 1113291, now seen corresponding path program 1 times [2024-11-08 18:35:10,552 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 18:35:10,553 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1719568964] [2024-11-08 18:35:10,553 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:35:10,553 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 18:35:10,562 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:35:10,562 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 18:35:10,567 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:35:10,569 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 18:35:10,569 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:35:10,570 INFO L85 PathProgramCache]: Analyzing trace with hash 889540493, now seen corresponding path program 1 times [2024-11-08 18:35:10,570 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 18:35:10,570 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [249082936] [2024-11-08 18:35:10,571 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:35:10,571 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 18:35:10,578 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:35:10,579 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 18:35:10,583 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:35:10,585 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 18:35:10,695 INFO L204 LassoAnalysis]: Preferences: [2024-11-08 18:35:10,696 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-11-08 18:35:10,696 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-11-08 18:35:10,696 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-11-08 18:35:10,697 INFO L128 ssoRankerPreferences]: Use exernal solver: true [2024-11-08 18:35:10,697 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 18:35:10,697 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-11-08 18:35:10,697 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-11-08 18:35:10,697 INFO L132 ssoRankerPreferences]: Filename of dumped script: NarrowKonv.c_Iteration2_Loop [2024-11-08 18:35:10,698 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-11-08 18:35:10,698 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-11-08 18:35:10,715 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:35:10,735 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:35:10,740 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:35:10,835 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-11-08 18:35:10,836 INFO L365 LassoAnalysis]: Checking for nontermination... [2024-11-08 18:35:10,841 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 18:35:10,841 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 [2024-11-08 18:35:10,843 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 18:35:10,845 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2024-11-08 18:35:10,847 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-08 18:35:10,848 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-08 18:35:10,889 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Forceful destruction successful, exit code 0 [2024-11-08 18:35:10,889 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 18:35:10,890 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 [2024-11-08 18:35:10,894 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 18:35:10,896 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2024-11-08 18:35:10,897 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2024-11-08 18:35:10,898 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-08 18:35:10,970 INFO L405 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2024-11-08 18:35:10,974 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Forceful destruction successful, exit code 0 [2024-11-08 18:35:10,975 INFO L204 LassoAnalysis]: Preferences: [2024-11-08 18:35:10,975 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-11-08 18:35:10,975 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-11-08 18:35:10,975 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-11-08 18:35:10,975 INFO L128 ssoRankerPreferences]: Use exernal solver: false [2024-11-08 18:35:10,975 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 18:35:10,975 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-11-08 18:35:10,976 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-11-08 18:35:10,976 INFO L132 ssoRankerPreferences]: Filename of dumped script: NarrowKonv.c_Iteration2_Loop [2024-11-08 18:35:10,976 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-11-08 18:35:10,976 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-11-08 18:35:10,978 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:35:10,993 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:35:10,998 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:35:11,076 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-11-08 18:35:11,080 INFO L451 LassoAnalysis]: Using template 'affine'. [2024-11-08 18:35:11,082 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 18:35:11,082 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 [2024-11-08 18:35:11,084 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 18:35:11,085 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2024-11-08 18:35:11,090 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-08 18:35:11,117 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-08 18:35:11,117 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-08 18:35:11,122 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-08 18:35:11,122 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-08 18:35:11,122 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-08 18:35:11,125 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-08 18:35:11,125 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-08 18:35:11,130 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2024-11-08 18:35:11,138 INFO L443 ModelExtractionUtils]: Simplification made 4 calls to the SMT solver. [2024-11-08 18:35:11,138 INFO L444 ModelExtractionUtils]: 0 out of 4 variables were initially zero. Simplification set additionally 1 variables to zero. [2024-11-08 18:35:11,140 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 18:35:11,140 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 [2024-11-08 18:35:11,142 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 18:35:11,146 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2024-11-08 18:35:11,147 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2024-11-08 18:35:11,147 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2024-11-08 18:35:11,148 INFO L474 LassoAnalysis]: Proved termination. [2024-11-08 18:35:11,148 INFO L476 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~i~0#1, ULTIMATE.start_main_~range~0#1) = -1*ULTIMATE.start_main_~i~0#1 + 1*ULTIMATE.start_main_~range~0#1 Supporting invariants [] [2024-11-08 18:35:11,167 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Forceful destruction successful, exit code 0 [2024-11-08 18:35:11,172 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2024-11-08 18:35:11,211 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:35:11,219 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 18:35:11,220 INFO L255 TraceCheckSpWp]: Trace formula consists of 5 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-11-08 18:35:11,221 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-08 18:35:11,234 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 18:35:11,235 WARN L253 TraceCheckSpWp]: Trace formula consists of 10 conjuncts, 5 conjuncts are in the unsatisfiable core [2024-11-08 18:35:11,236 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-08 18:35:11,283 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 18:35:11,287 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2024-11-08 18:35:11,289 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 10 states and 13 transitions. cyclomatic complexity: 5 Second operand has 3 states, 3 states have (on average 2.0) internal successors, (6), 3 states have internal predecessors, (6), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 18:35:11,338 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 10 states and 13 transitions. cyclomatic complexity: 5. Second operand has 3 states, 3 states have (on average 2.0) internal successors, (6), 3 states have internal predecessors, (6), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 14 states and 18 transitions. Complement of second has 5 states. [2024-11-08 18:35:11,341 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2024-11-08 18:35:11,342 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 2.0) internal successors, (6), 3 states have internal predecessors, (6), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 18:35:11,344 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 6 transitions. [2024-11-08 18:35:11,345 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 6 transitions. Stem has 2 letters. Loop has 4 letters. [2024-11-08 18:35:11,346 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-08 18:35:11,346 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 6 transitions. Stem has 6 letters. Loop has 4 letters. [2024-11-08 18:35:11,347 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-08 18:35:11,347 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 6 transitions. Stem has 2 letters. Loop has 8 letters. [2024-11-08 18:35:11,347 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-08 18:35:11,348 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 14 states and 18 transitions. [2024-11-08 18:35:11,349 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2024-11-08 18:35:11,351 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 14 states to 14 states and 18 transitions. [2024-11-08 18:35:11,351 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9 [2024-11-08 18:35:11,351 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10 [2024-11-08 18:35:11,351 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14 states and 18 transitions. [2024-11-08 18:35:11,352 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-08 18:35:11,352 INFO L218 hiAutomatonCegarLoop]: Abstraction has 14 states and 18 transitions. [2024-11-08 18:35:11,352 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14 states and 18 transitions. [2024-11-08 18:35:11,353 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14 to 14. [2024-11-08 18:35:11,353 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14 states, 14 states have (on average 1.2857142857142858) internal successors, (18), 13 states have internal predecessors, (18), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 18:35:11,354 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14 states to 14 states and 18 transitions. [2024-11-08 18:35:11,354 INFO L240 hiAutomatonCegarLoop]: Abstraction has 14 states and 18 transitions. [2024-11-08 18:35:11,354 INFO L425 stractBuchiCegarLoop]: Abstraction has 14 states and 18 transitions. [2024-11-08 18:35:11,354 INFO L332 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-11-08 18:35:11,357 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14 states and 18 transitions. [2024-11-08 18:35:11,358 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2024-11-08 18:35:11,359 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 18:35:11,359 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 18:35:11,359 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1] [2024-11-08 18:35:11,360 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-11-08 18:35:11,361 INFO L745 eck$LassoCheckResult]: Stem: 106#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true; 107#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;havoc main_#t~nondet0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 108#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 101#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 104#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 102#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 97#L12-1 [2024-11-08 18:35:11,361 INFO L747 eck$LassoCheckResult]: Loop: 97#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 98#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 110#L12 assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 97#L12-1 [2024-11-08 18:35:11,361 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:35:11,362 INFO L85 PathProgramCache]: Analyzing trace with hash 889540491, now seen corresponding path program 1 times [2024-11-08 18:35:11,362 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 18:35:11,362 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1594261280] [2024-11-08 18:35:11,362 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:35:11,363 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 18:35:11,378 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:35:11,380 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 18:35:11,389 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:35:11,390 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 18:35:11,392 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:35:11,392 INFO L85 PathProgramCache]: Analyzing trace with hash 35920, now seen corresponding path program 2 times [2024-11-08 18:35:11,392 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 18:35:11,392 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [637497289] [2024-11-08 18:35:11,393 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:35:11,393 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 18:35:11,401 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:35:11,402 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 18:35:11,406 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:35:11,408 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 18:35:11,410 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:35:11,410 INFO L85 PathProgramCache]: Analyzing trace with hash 352557190, now seen corresponding path program 1 times [2024-11-08 18:35:11,411 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 18:35:11,411 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1816250810] [2024-11-08 18:35:11,411 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:35:11,412 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 18:35:11,426 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 18:35:11,491 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 18:35:11,491 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 18:35:11,492 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1816250810] [2024-11-08 18:35:11,492 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1816250810] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-08 18:35:11,492 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1285251397] [2024-11-08 18:35:11,492 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:35:11,493 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-08 18:35:11,493 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 [2024-11-08 18:35:11,495 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-08 18:35:11,496 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Waiting until timeout for monitored process [2024-11-08 18:35:11,526 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 18:35:11,527 INFO L255 TraceCheckSpWp]: Trace formula consists of 24 conjuncts, 4 conjuncts are in the unsatisfiable core [2024-11-08 18:35:11,528 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-08 18:35:11,588 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 18:35:11,588 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-08 18:35:11,628 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 18:35:11,629 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1285251397] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-08 18:35:11,629 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-08 18:35:11,629 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 6 [2024-11-08 18:35:11,629 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [508195042] [2024-11-08 18:35:11,630 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-08 18:35:11,653 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 18:35:11,653 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2024-11-08 18:35:11,654 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=26, Unknown=0, NotChecked=0, Total=42 [2024-11-08 18:35:11,654 INFO L87 Difference]: Start difference. First operand 14 states and 18 transitions. cyclomatic complexity: 6 Second operand has 7 states, 6 states have (on average 3.5) internal successors, (21), 7 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 18:35:11,725 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 18:35:11,725 INFO L93 Difference]: Finished difference Result 30 states and 35 transitions. [2024-11-08 18:35:11,725 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 30 states and 35 transitions. [2024-11-08 18:35:11,727 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 8 [2024-11-08 18:35:11,727 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 30 states to 30 states and 35 transitions. [2024-11-08 18:35:11,728 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 26 [2024-11-08 18:35:11,728 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 26 [2024-11-08 18:35:11,728 INFO L73 IsDeterministic]: Start isDeterministic. Operand 30 states and 35 transitions. [2024-11-08 18:35:11,728 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-08 18:35:11,728 INFO L218 hiAutomatonCegarLoop]: Abstraction has 30 states and 35 transitions. [2024-11-08 18:35:11,729 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30 states and 35 transitions. [2024-11-08 18:35:11,730 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30 to 30. [2024-11-08 18:35:11,731 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 30 states, 30 states have (on average 1.1666666666666667) internal successors, (35), 29 states have internal predecessors, (35), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 18:35:11,732 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 30 states to 30 states and 35 transitions. [2024-11-08 18:35:11,732 INFO L240 hiAutomatonCegarLoop]: Abstraction has 30 states and 35 transitions. [2024-11-08 18:35:11,732 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2024-11-08 18:35:11,733 INFO L425 stractBuchiCegarLoop]: Abstraction has 30 states and 35 transitions. [2024-11-08 18:35:11,733 INFO L332 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-11-08 18:35:11,733 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 30 states and 35 transitions. [2024-11-08 18:35:11,734 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 8 [2024-11-08 18:35:11,734 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 18:35:11,734 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 18:35:11,735 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [3, 3, 3, 2, 1, 1, 1] [2024-11-08 18:35:11,735 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2024-11-08 18:35:11,735 INFO L745 eck$LassoCheckResult]: Stem: 213#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true; 214#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;havoc main_#t~nondet0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 215#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 207#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 224#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 216#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 203#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 204#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 208#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 210#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 211#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 232#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 231#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 230#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 219#L12-1 [2024-11-08 18:35:11,735 INFO L747 eck$LassoCheckResult]: Loop: 219#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 228#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 226#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 217#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 219#L12-1 [2024-11-08 18:35:11,736 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:35:11,736 INFO L85 PathProgramCache]: Analyzing trace with hash -846419425, now seen corresponding path program 1 times [2024-11-08 18:35:11,736 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 18:35:11,737 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1829906890] [2024-11-08 18:35:11,737 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:35:11,737 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 18:35:11,745 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:35:11,746 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 18:35:11,751 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:35:11,753 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 18:35:11,754 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:35:11,754 INFO L85 PathProgramCache]: Analyzing trace with hash 1113291, now seen corresponding path program 2 times [2024-11-08 18:35:11,754 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 18:35:11,754 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1764151662] [2024-11-08 18:35:11,754 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:35:11,755 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 18:35:11,759 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:35:11,759 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 18:35:11,762 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:35:11,763 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 18:35:11,764 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:35:11,764 INFO L85 PathProgramCache]: Analyzing trace with hash -2065733655, now seen corresponding path program 2 times [2024-11-08 18:35:11,764 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 18:35:11,764 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1993115777] [2024-11-08 18:35:11,765 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:35:11,765 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 18:35:11,804 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:35:11,804 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 18:35:11,814 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:35:11,820 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Ended with exit code 0 [2024-11-08 18:35:11,821 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 18:35:11,875 INFO L204 LassoAnalysis]: Preferences: [2024-11-08 18:35:11,875 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-11-08 18:35:11,875 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-11-08 18:35:11,875 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-11-08 18:35:11,875 INFO L128 ssoRankerPreferences]: Use exernal solver: true [2024-11-08 18:35:11,876 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 18:35:11,876 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-11-08 18:35:11,876 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-11-08 18:35:11,876 INFO L132 ssoRankerPreferences]: Filename of dumped script: NarrowKonv.c_Iteration4_Loop [2024-11-08 18:35:11,876 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-11-08 18:35:11,876 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-11-08 18:35:11,878 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:35:11,885 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:35:11,889 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:35:11,975 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-11-08 18:35:11,975 INFO L365 LassoAnalysis]: Checking for nontermination... [2024-11-08 18:35:11,975 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 18:35:11,975 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 [2024-11-08 18:35:11,977 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 18:35:11,978 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2024-11-08 18:35:11,979 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-08 18:35:11,979 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-08 18:35:12,004 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-08 18:35:12,005 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {v_rep~unnamed0~0~false_3=0} Honda state: {v_rep~unnamed0~0~false_3=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-08 18:35:12,025 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Forceful destruction successful, exit code 0 [2024-11-08 18:35:12,026 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 18:35:12,026 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 [2024-11-08 18:35:12,027 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 18:35:12,029 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2024-11-08 18:35:12,031 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-08 18:35:12,031 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-08 18:35:12,057 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-08 18:35:12,057 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {v_rep~unnamed0~0~true_3=1} Honda state: {v_rep~unnamed0~0~true_3=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-08 18:35:12,076 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Ended with exit code 0 [2024-11-08 18:35:12,077 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 18:35:12,077 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 [2024-11-08 18:35:12,079 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 18:35:12,081 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2024-11-08 18:35:12,082 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-08 18:35:12,082 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-08 18:35:12,119 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Ended with exit code 0 [2024-11-08 18:35:12,120 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 18:35:12,120 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 [2024-11-08 18:35:12,121 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 18:35:12,125 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Waiting until timeout for monitored process [2024-11-08 18:35:12,127 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2024-11-08 18:35:12,128 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-08 18:35:12,208 INFO L405 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2024-11-08 18:35:12,213 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Forceful destruction successful, exit code 0 [2024-11-08 18:35:12,213 INFO L204 LassoAnalysis]: Preferences: [2024-11-08 18:35:12,213 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-11-08 18:35:12,213 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-11-08 18:35:12,214 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-11-08 18:35:12,214 INFO L128 ssoRankerPreferences]: Use exernal solver: false [2024-11-08 18:35:12,214 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 18:35:12,214 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-11-08 18:35:12,214 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-11-08 18:35:12,214 INFO L132 ssoRankerPreferences]: Filename of dumped script: NarrowKonv.c_Iteration4_Loop [2024-11-08 18:35:12,214 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-11-08 18:35:12,214 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-11-08 18:35:12,215 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:35:12,222 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:35:12,236 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:35:12,302 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-11-08 18:35:12,303 INFO L451 LassoAnalysis]: Using template 'affine'. [2024-11-08 18:35:12,303 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 18:35:12,303 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 [2024-11-08 18:35:12,305 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 18:35:12,307 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Waiting until timeout for monitored process [2024-11-08 18:35:12,308 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-08 18:35:12,322 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-08 18:35:12,322 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-08 18:35:12,322 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-08 18:35:12,323 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-08 18:35:12,326 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2024-11-08 18:35:12,327 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2024-11-08 18:35:12,333 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-08 18:35:12,353 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Ended with exit code 0 [2024-11-08 18:35:12,353 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 18:35:12,354 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 [2024-11-08 18:35:12,357 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 18:35:12,364 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Waiting until timeout for monitored process [2024-11-08 18:35:12,364 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-08 18:35:12,378 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-08 18:35:12,378 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-08 18:35:12,378 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-08 18:35:12,379 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-08 18:35:12,379 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-08 18:35:12,380 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-08 18:35:12,380 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-08 18:35:12,385 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2024-11-08 18:35:12,393 INFO L443 ModelExtractionUtils]: Simplification made 4 calls to the SMT solver. [2024-11-08 18:35:12,393 INFO L444 ModelExtractionUtils]: 0 out of 4 variables were initially zero. Simplification set additionally 1 variables to zero. [2024-11-08 18:35:12,393 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 18:35:12,394 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 [2024-11-08 18:35:12,395 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 18:35:12,398 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Waiting until timeout for monitored process [2024-11-08 18:35:12,398 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2024-11-08 18:35:12,398 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2024-11-08 18:35:12,399 INFO L474 LassoAnalysis]: Proved termination. [2024-11-08 18:35:12,399 INFO L476 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~range~0#1, ULTIMATE.start_main_~i~0#1) = 1*ULTIMATE.start_main_~range~0#1 - 1*ULTIMATE.start_main_~i~0#1 Supporting invariants [] [2024-11-08 18:35:12,416 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Ended with exit code 0 [2024-11-08 18:35:12,418 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2024-11-08 18:35:12,437 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:35:12,452 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 18:35:12,453 INFO L255 TraceCheckSpWp]: Trace formula consists of 32 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-11-08 18:35:12,453 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-08 18:35:12,497 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 18:35:12,498 WARN L253 TraceCheckSpWp]: Trace formula consists of 10 conjuncts, 5 conjuncts are in the unsatisfiable core [2024-11-08 18:35:12,499 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-08 18:35:12,547 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 18:35:12,548 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2024-11-08 18:35:12,548 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 30 states and 35 transitions. cyclomatic complexity: 8 Second operand has 3 states, 3 states have (on average 4.0) internal successors, (12), 3 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 18:35:12,594 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 30 states and 35 transitions. cyclomatic complexity: 8. Second operand has 3 states, 3 states have (on average 4.0) internal successors, (12), 3 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 60 states and 66 transitions. Complement of second has 5 states. [2024-11-08 18:35:12,596 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2024-11-08 18:35:12,597 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 4.0) internal successors, (12), 3 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 18:35:12,597 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 11 transitions. [2024-11-08 18:35:12,598 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 11 transitions. Stem has 14 letters. Loop has 4 letters. [2024-11-08 18:35:12,598 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-08 18:35:12,601 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 11 transitions. Stem has 18 letters. Loop has 4 letters. [2024-11-08 18:35:12,602 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-08 18:35:12,602 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 11 transitions. Stem has 14 letters. Loop has 8 letters. [2024-11-08 18:35:12,602 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-08 18:35:12,602 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 60 states and 66 transitions. [2024-11-08 18:35:12,606 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 8 [2024-11-08 18:35:12,607 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 60 states to 51 states and 57 transitions. [2024-11-08 18:35:12,607 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 36 [2024-11-08 18:35:12,608 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 37 [2024-11-08 18:35:12,609 INFO L73 IsDeterministic]: Start isDeterministic. Operand 51 states and 57 transitions. [2024-11-08 18:35:12,610 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-08 18:35:12,610 INFO L218 hiAutomatonCegarLoop]: Abstraction has 51 states and 57 transitions. [2024-11-08 18:35:12,610 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 51 states and 57 transitions. [2024-11-08 18:35:12,612 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 51 to 45. [2024-11-08 18:35:12,615 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 45 states, 45 states have (on average 1.1333333333333333) internal successors, (51), 44 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 18:35:12,616 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45 states to 45 states and 51 transitions. [2024-11-08 18:35:12,616 INFO L240 hiAutomatonCegarLoop]: Abstraction has 45 states and 51 transitions. [2024-11-08 18:35:12,616 INFO L425 stractBuchiCegarLoop]: Abstraction has 45 states and 51 transitions. [2024-11-08 18:35:12,616 INFO L332 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-11-08 18:35:12,616 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 45 states and 51 transitions. [2024-11-08 18:35:12,619 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 8 [2024-11-08 18:35:12,619 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 18:35:12,620 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 18:35:12,620 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [4, 4, 4, 3, 1, 1, 1] [2024-11-08 18:35:12,620 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2024-11-08 18:35:12,621 INFO L745 eck$LassoCheckResult]: Stem: 378#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true; 379#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;havoc main_#t~nondet0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 380#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 371#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 411#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 377#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 369#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 370#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 372#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 381#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 367#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 368#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 410#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 375#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 376#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 407#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 405#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 403#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 393#L12-1 [2024-11-08 18:35:12,623 INFO L747 eck$LassoCheckResult]: Loop: 393#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 401#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 399#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 391#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 393#L12-1 [2024-11-08 18:35:12,623 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:35:12,623 INFO L85 PathProgramCache]: Analyzing trace with hash 962369257, now seen corresponding path program 3 times [2024-11-08 18:35:12,623 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 18:35:12,624 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1493707637] [2024-11-08 18:35:12,624 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:35:12,624 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 18:35:12,642 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:35:12,642 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 18:35:12,650 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:35:12,651 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 18:35:12,652 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:35:12,652 INFO L85 PathProgramCache]: Analyzing trace with hash 1113291, now seen corresponding path program 3 times [2024-11-08 18:35:12,652 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 18:35:12,653 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [206773964] [2024-11-08 18:35:12,653 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:35:12,653 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 18:35:12,657 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:35:12,657 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 18:35:12,660 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:35:12,661 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 18:35:12,661 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:35:12,662 INFO L85 PathProgramCache]: Analyzing trace with hash 2046287795, now seen corresponding path program 4 times [2024-11-08 18:35:12,662 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 18:35:12,662 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [371164833] [2024-11-08 18:35:12,662 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:35:12,663 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 18:35:12,683 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:35:12,687 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 18:35:12,695 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:35:12,697 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 18:35:12,744 INFO L204 LassoAnalysis]: Preferences: [2024-11-08 18:35:12,745 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-11-08 18:35:12,745 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-11-08 18:35:12,745 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-11-08 18:35:12,745 INFO L128 ssoRankerPreferences]: Use exernal solver: true [2024-11-08 18:35:12,745 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 18:35:12,745 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-11-08 18:35:12,745 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-11-08 18:35:12,745 INFO L132 ssoRankerPreferences]: Filename of dumped script: NarrowKonv.c_Iteration5_Loop [2024-11-08 18:35:12,746 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-11-08 18:35:12,746 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-11-08 18:35:12,747 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:35:12,750 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:35:12,761 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:35:12,819 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-11-08 18:35:12,819 INFO L365 LassoAnalysis]: Checking for nontermination... [2024-11-08 18:35:12,819 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 18:35:12,819 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 [2024-11-08 18:35:12,821 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 18:35:12,822 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Waiting until timeout for monitored process [2024-11-08 18:35:12,824 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-08 18:35:12,824 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-08 18:35:12,848 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-08 18:35:12,848 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {v_rep~unnamed0~0~true_5=1} Honda state: {v_rep~unnamed0~0~true_5=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-08 18:35:12,867 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Ended with exit code 0 [2024-11-08 18:35:12,868 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 18:35:12,868 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 [2024-11-08 18:35:12,870 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 18:35:12,871 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Waiting until timeout for monitored process [2024-11-08 18:35:12,872 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-08 18:35:12,873 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-08 18:35:12,907 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Ended with exit code 0 [2024-11-08 18:35:12,908 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 18:35:12,908 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 [2024-11-08 18:35:12,910 INFO L229 MonitoredProcess]: Starting monitored process 16 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 18:35:12,911 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Waiting until timeout for monitored process [2024-11-08 18:35:12,913 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2024-11-08 18:35:12,913 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-08 18:35:12,988 INFO L405 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2024-11-08 18:35:12,992 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Forceful destruction successful, exit code 0 [2024-11-08 18:35:12,993 INFO L204 LassoAnalysis]: Preferences: [2024-11-08 18:35:12,993 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-11-08 18:35:12,993 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-11-08 18:35:12,993 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-11-08 18:35:12,993 INFO L128 ssoRankerPreferences]: Use exernal solver: false [2024-11-08 18:35:12,993 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 18:35:12,993 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-11-08 18:35:12,993 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-11-08 18:35:12,993 INFO L132 ssoRankerPreferences]: Filename of dumped script: NarrowKonv.c_Iteration5_Loop [2024-11-08 18:35:12,993 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-11-08 18:35:12,993 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-11-08 18:35:12,994 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:35:13,002 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:35:13,013 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:35:13,077 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-11-08 18:35:13,077 INFO L451 LassoAnalysis]: Using template 'affine'. [2024-11-08 18:35:13,078 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 18:35:13,078 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 [2024-11-08 18:35:13,079 INFO L229 MonitoredProcess]: Starting monitored process 17 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 18:35:13,082 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Waiting until timeout for monitored process [2024-11-08 18:35:13,083 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-08 18:35:13,097 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-08 18:35:13,097 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-08 18:35:13,097 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-08 18:35:13,097 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-08 18:35:13,100 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2024-11-08 18:35:13,100 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2024-11-08 18:35:13,104 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-08 18:35:13,123 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Ended with exit code 0 [2024-11-08 18:35:13,123 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 18:35:13,124 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 [2024-11-08 18:35:13,125 INFO L229 MonitoredProcess]: Starting monitored process 18 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 18:35:13,127 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Waiting until timeout for monitored process [2024-11-08 18:35:13,128 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-08 18:35:13,142 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-08 18:35:13,142 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-08 18:35:13,142 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-08 18:35:13,142 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-08 18:35:13,143 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-08 18:35:13,144 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-08 18:35:13,144 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-08 18:35:13,148 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2024-11-08 18:35:13,151 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2024-11-08 18:35:13,152 INFO L444 ModelExtractionUtils]: 1 out of 4 variables were initially zero. Simplification set additionally 0 variables to zero. [2024-11-08 18:35:13,152 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 18:35:13,152 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 [2024-11-08 18:35:13,155 INFO L229 MonitoredProcess]: Starting monitored process 19 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 18:35:13,156 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Waiting until timeout for monitored process [2024-11-08 18:35:13,157 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2024-11-08 18:35:13,157 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2024-11-08 18:35:13,157 INFO L474 LassoAnalysis]: Proved termination. [2024-11-08 18:35:13,157 INFO L476 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~range~0#1, ULTIMATE.start_main_~i~0#1) = 1*ULTIMATE.start_main_~range~0#1 - 1*ULTIMATE.start_main_~i~0#1 Supporting invariants [] [2024-11-08 18:35:13,175 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Ended with exit code 0 [2024-11-08 18:35:13,177 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2024-11-08 18:35:13,192 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:35:13,206 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 18:35:13,207 INFO L255 TraceCheckSpWp]: Trace formula consists of 40 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-11-08 18:35:13,208 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-08 18:35:13,258 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 18:35:13,259 WARN L253 TraceCheckSpWp]: Trace formula consists of 10 conjuncts, 5 conjuncts are in the unsatisfiable core [2024-11-08 18:35:13,260 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-08 18:35:13,299 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 18:35:13,300 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2024-11-08 18:35:13,300 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 45 states and 51 transitions. cyclomatic complexity: 10 Second operand has 3 states, 3 states have (on average 4.0) internal successors, (12), 3 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 18:35:13,333 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 45 states and 51 transitions. cyclomatic complexity: 10. Second operand has 3 states, 3 states have (on average 4.0) internal successors, (12), 3 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 60 states and 67 transitions. Complement of second has 5 states. [2024-11-08 18:35:13,337 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2024-11-08 18:35:13,338 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 4.0) internal successors, (12), 3 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 18:35:13,338 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 11 transitions. [2024-11-08 18:35:13,338 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 11 transitions. Stem has 18 letters. Loop has 4 letters. [2024-11-08 18:35:13,338 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-08 18:35:13,339 INFO L682 stractBuchiCegarLoop]: Bad chosen interpolant automaton: word not accepted [2024-11-08 18:35:13,355 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:35:13,365 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 18:35:13,366 INFO L255 TraceCheckSpWp]: Trace formula consists of 40 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-11-08 18:35:13,367 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-08 18:35:13,413 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 18:35:13,414 WARN L253 TraceCheckSpWp]: Trace formula consists of 10 conjuncts, 5 conjuncts are in the unsatisfiable core [2024-11-08 18:35:13,414 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-08 18:35:13,444 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 18:35:13,444 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and with honda bouncer for loop.1 stem predicates 2 loop predicates [2024-11-08 18:35:13,445 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 45 states and 51 transitions. cyclomatic complexity: 10 Second operand has 3 states, 3 states have (on average 4.0) internal successors, (12), 3 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 18:35:13,471 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 45 states and 51 transitions. cyclomatic complexity: 10. Second operand has 3 states, 3 states have (on average 4.0) internal successors, (12), 3 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 60 states and 67 transitions. Complement of second has 5 states. [2024-11-08 18:35:13,472 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2024-11-08 18:35:13,473 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 4.0) internal successors, (12), 3 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 18:35:13,474 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 11 transitions. [2024-11-08 18:35:13,474 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 11 transitions. Stem has 18 letters. Loop has 4 letters. [2024-11-08 18:35:13,474 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-08 18:35:13,475 INFO L682 stractBuchiCegarLoop]: Bad chosen interpolant automaton: word not accepted [2024-11-08 18:35:13,489 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:35:13,503 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 18:35:13,503 INFO L255 TraceCheckSpWp]: Trace formula consists of 40 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-11-08 18:35:13,504 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-08 18:35:13,544 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 18:35:13,544 WARN L253 TraceCheckSpWp]: Trace formula consists of 10 conjuncts, 5 conjuncts are in the unsatisfiable core [2024-11-08 18:35:13,545 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-08 18:35:13,583 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 18:35:13,584 INFO L141 lantAutomatonBouncer]: Defining Buchi interpolant automaton with scrooge nondeterminism in stemwith honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2024-11-08 18:35:13,584 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 45 states and 51 transitions. cyclomatic complexity: 10 Second operand has 3 states, 3 states have (on average 4.0) internal successors, (12), 3 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 18:35:13,624 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 45 states and 51 transitions. cyclomatic complexity: 10. Second operand has 3 states, 3 states have (on average 4.0) internal successors, (12), 3 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 77 states and 88 transitions. Complement of second has 4 states. [2024-11-08 18:35:13,625 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2024-11-08 18:35:13,625 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 4.0) internal successors, (12), 3 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 18:35:13,626 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 15 transitions. [2024-11-08 18:35:13,626 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 15 transitions. Stem has 18 letters. Loop has 4 letters. [2024-11-08 18:35:13,626 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-08 18:35:13,626 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 15 transitions. Stem has 22 letters. Loop has 4 letters. [2024-11-08 18:35:13,626 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-08 18:35:13,626 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 15 transitions. Stem has 18 letters. Loop has 8 letters. [2024-11-08 18:35:13,627 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-08 18:35:13,627 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 77 states and 88 transitions. [2024-11-08 18:35:13,628 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 15 [2024-11-08 18:35:13,629 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 77 states to 62 states and 72 transitions. [2024-11-08 18:35:13,629 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 36 [2024-11-08 18:35:13,630 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 39 [2024-11-08 18:35:13,630 INFO L73 IsDeterministic]: Start isDeterministic. Operand 62 states and 72 transitions. [2024-11-08 18:35:13,630 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-08 18:35:13,630 INFO L218 hiAutomatonCegarLoop]: Abstraction has 62 states and 72 transitions. [2024-11-08 18:35:13,630 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 62 states and 72 transitions. [2024-11-08 18:35:13,633 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 62 to 40. [2024-11-08 18:35:13,633 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 40 states, 40 states have (on average 1.225) internal successors, (49), 39 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 18:35:13,634 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40 states to 40 states and 49 transitions. [2024-11-08 18:35:13,634 INFO L240 hiAutomatonCegarLoop]: Abstraction has 40 states and 49 transitions. [2024-11-08 18:35:13,634 INFO L425 stractBuchiCegarLoop]: Abstraction has 40 states and 49 transitions. [2024-11-08 18:35:13,634 INFO L332 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-11-08 18:35:13,634 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 40 states and 49 transitions. [2024-11-08 18:35:13,635 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 14 [2024-11-08 18:35:13,635 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 18:35:13,635 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 18:35:13,636 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [5, 5, 5, 3, 2, 1, 1] [2024-11-08 18:35:13,636 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 2, 2, 1, 1] [2024-11-08 18:35:13,636 INFO L745 eck$LassoCheckResult]: Stem: 848#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true; 849#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;havoc main_#t~nondet0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 850#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 839#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 875#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 874#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 836#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 837#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 841#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 844#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 845#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 842#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 843#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 846#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 847#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 871#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 868#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 867#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 862#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 863#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 859#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 857#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 855#L12-1 [2024-11-08 18:35:13,636 INFO L747 eck$LassoCheckResult]: Loop: 855#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 856#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 869#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 866#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 865#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 860#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 861#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 864#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 855#L12-1 [2024-11-08 18:35:13,637 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:35:13,637 INFO L85 PathProgramCache]: Analyzing trace with hash -1248984655, now seen corresponding path program 5 times [2024-11-08 18:35:13,637 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 18:35:13,637 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1878250238] [2024-11-08 18:35:13,637 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:35:13,638 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 18:35:13,650 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 18:35:13,743 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 16 proven. 24 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 18:35:13,744 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 18:35:13,744 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1878250238] [2024-11-08 18:35:13,744 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1878250238] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-08 18:35:13,744 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [695159175] [2024-11-08 18:35:13,744 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2024-11-08 18:35:13,745 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-08 18:35:13,745 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 [2024-11-08 18:35:13,746 INFO L229 MonitoredProcess]: Starting monitored process 20 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-08 18:35:13,749 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (20)] Waiting until timeout for monitored process [2024-11-08 18:35:13,797 INFO L227 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 5 check-sat command(s) [2024-11-08 18:35:13,798 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-08 18:35:13,800 INFO L255 TraceCheckSpWp]: Trace formula consists of 51 conjuncts, 6 conjuncts are in the unsatisfiable core [2024-11-08 18:35:13,801 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-08 18:35:13,898 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Ended with exit code 0 [2024-11-08 18:35:13,930 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Ended with exit code 0 [2024-11-08 18:35:13,957 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 16 proven. 24 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 18:35:13,957 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-08 18:35:14,041 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 16 proven. 24 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 18:35:14,042 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [695159175] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-08 18:35:14,042 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-08 18:35:14,042 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6] total 13 [2024-11-08 18:35:14,042 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [156034277] [2024-11-08 18:35:14,042 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-08 18:35:14,042 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 18:35:14,043 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:35:14,045 INFO L85 PathProgramCache]: Analyzing trace with hash 1648776595, now seen corresponding path program 1 times [2024-11-08 18:35:14,045 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 18:35:14,045 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2009792463] [2024-11-08 18:35:14,045 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:35:14,046 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 18:35:14,054 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:35:14,055 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 18:35:14,057 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:35:14,058 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 18:35:14,125 INFO L204 LassoAnalysis]: Preferences: [2024-11-08 18:35:14,125 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-11-08 18:35:14,125 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-11-08 18:35:14,125 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-11-08 18:35:14,125 INFO L128 ssoRankerPreferences]: Use exernal solver: true [2024-11-08 18:35:14,125 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 18:35:14,125 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-11-08 18:35:14,126 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-11-08 18:35:14,126 INFO L132 ssoRankerPreferences]: Filename of dumped script: NarrowKonv.c_Iteration6_Loop [2024-11-08 18:35:14,126 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-11-08 18:35:14,126 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-11-08 18:35:14,127 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:35:14,131 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:35:14,142 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:35:14,206 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-11-08 18:35:14,206 INFO L365 LassoAnalysis]: Checking for nontermination... [2024-11-08 18:35:14,206 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 18:35:14,206 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 [2024-11-08 18:35:14,208 INFO L229 MonitoredProcess]: Starting monitored process 21 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 18:35:14,209 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (21)] Waiting until timeout for monitored process [2024-11-08 18:35:14,210 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-08 18:35:14,210 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-08 18:35:14,237 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-08 18:35:14,237 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {v_rep~unnamed0~0~true_7=1} Honda state: {v_rep~unnamed0~0~true_7=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-08 18:35:14,255 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (21)] Ended with exit code 0 [2024-11-08 18:35:14,256 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 18:35:14,256 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 [2024-11-08 18:35:14,258 INFO L229 MonitoredProcess]: Starting monitored process 22 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 18:35:14,259 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (22)] Waiting until timeout for monitored process [2024-11-08 18:35:14,261 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-08 18:35:14,261 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-08 18:35:14,298 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (22)] Forceful destruction successful, exit code 0 [2024-11-08 18:35:14,298 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 18:35:14,298 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 [2024-11-08 18:35:14,300 INFO L229 MonitoredProcess]: Starting monitored process 23 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 18:35:14,301 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (23)] Waiting until timeout for monitored process [2024-11-08 18:35:14,302 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2024-11-08 18:35:14,303 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-08 18:35:14,425 INFO L405 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2024-11-08 18:35:14,429 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (23)] Ended with exit code 0 [2024-11-08 18:35:14,429 INFO L204 LassoAnalysis]: Preferences: [2024-11-08 18:35:14,430 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-11-08 18:35:14,430 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-11-08 18:35:14,430 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-11-08 18:35:14,430 INFO L128 ssoRankerPreferences]: Use exernal solver: false [2024-11-08 18:35:14,430 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 18:35:14,430 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-11-08 18:35:14,430 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-11-08 18:35:14,430 INFO L132 ssoRankerPreferences]: Filename of dumped script: NarrowKonv.c_Iteration6_Loop [2024-11-08 18:35:14,430 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-11-08 18:35:14,430 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-11-08 18:35:14,431 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:35:14,444 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:35:14,447 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:35:14,511 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-11-08 18:35:14,511 INFO L451 LassoAnalysis]: Using template 'affine'. [2024-11-08 18:35:14,511 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 18:35:14,512 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 [2024-11-08 18:35:14,513 INFO L229 MonitoredProcess]: Starting monitored process 24 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 18:35:14,515 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (24)] Waiting until timeout for monitored process [2024-11-08 18:35:14,516 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-08 18:35:14,529 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-08 18:35:14,529 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-08 18:35:14,529 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-08 18:35:14,529 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-08 18:35:14,530 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-08 18:35:14,532 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-08 18:35:14,532 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-08 18:35:14,535 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2024-11-08 18:35:14,540 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2024-11-08 18:35:14,540 INFO L444 ModelExtractionUtils]: 1 out of 4 variables were initially zero. Simplification set additionally 1 variables to zero. [2024-11-08 18:35:14,541 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 18:35:14,541 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 [2024-11-08 18:35:14,542 INFO L229 MonitoredProcess]: Starting monitored process 25 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 18:35:14,544 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (25)] Waiting until timeout for monitored process [2024-11-08 18:35:14,544 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2024-11-08 18:35:14,544 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2024-11-08 18:35:14,545 INFO L474 LassoAnalysis]: Proved termination. [2024-11-08 18:35:14,545 INFO L476 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~range~0#1) = 1*ULTIMATE.start_main_~range~0#1 Supporting invariants [] [2024-11-08 18:35:14,562 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (24)] Forceful destruction successful, exit code 0 [2024-11-08 18:35:14,563 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2024-11-08 18:35:14,576 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:35:14,588 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 18:35:14,589 INFO L255 TraceCheckSpWp]: Trace formula consists of 51 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-11-08 18:35:14,591 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-08 18:35:14,629 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 18:35:14,629 INFO L255 TraceCheckSpWp]: Trace formula consists of 21 conjuncts, 6 conjuncts are in the unsatisfiable core [2024-11-08 18:35:14,630 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-08 18:35:14,688 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 18:35:14,689 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2024-11-08 18:35:14,689 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 40 states and 49 transitions. cyclomatic complexity: 12 Second operand has 5 states, 5 states have (on average 3.2) internal successors, (16), 5 states have internal predecessors, (16), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 18:35:14,722 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 40 states and 49 transitions. cyclomatic complexity: 12. Second operand has 5 states, 5 states have (on average 3.2) internal successors, (16), 5 states have internal predecessors, (16), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 92 states and 114 transitions. Complement of second has 6 states. [2024-11-08 18:35:14,722 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 4 states 1 stem states 2 non-accepting loop states 1 accepting loop states [2024-11-08 18:35:14,723 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 3.2) internal successors, (16), 5 states have internal predecessors, (16), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 18:35:14,723 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 16 transitions. [2024-11-08 18:35:14,723 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 16 transitions. Stem has 22 letters. Loop has 8 letters. [2024-11-08 18:35:14,723 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-08 18:35:14,724 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 16 transitions. Stem has 30 letters. Loop has 8 letters. [2024-11-08 18:35:14,724 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-08 18:35:14,724 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 16 transitions. Stem has 22 letters. Loop has 16 letters. [2024-11-08 18:35:14,724 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-08 18:35:14,724 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 92 states and 114 transitions. [2024-11-08 18:35:14,726 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6 [2024-11-08 18:35:14,726 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 92 states to 70 states and 87 transitions. [2024-11-08 18:35:14,727 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21 [2024-11-08 18:35:14,727 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 23 [2024-11-08 18:35:14,727 INFO L73 IsDeterministic]: Start isDeterministic. Operand 70 states and 87 transitions. [2024-11-08 18:35:14,727 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-08 18:35:14,727 INFO L218 hiAutomatonCegarLoop]: Abstraction has 70 states and 87 transitions. [2024-11-08 18:35:14,727 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 70 states and 87 transitions. [2024-11-08 18:35:14,730 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 70 to 62. [2024-11-08 18:35:14,730 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 62 states, 62 states have (on average 1.2258064516129032) internal successors, (76), 61 states have internal predecessors, (76), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 18:35:14,731 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 62 states to 62 states and 76 transitions. [2024-11-08 18:35:14,731 INFO L240 hiAutomatonCegarLoop]: Abstraction has 62 states and 76 transitions. [2024-11-08 18:35:14,731 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 18:35:14,732 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2024-11-08 18:35:14,732 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=60, Invalid=96, Unknown=0, NotChecked=0, Total=156 [2024-11-08 18:35:14,732 INFO L87 Difference]: Start difference. First operand 62 states and 76 transitions. Second operand has 13 states, 13 states have (on average 4.0) internal successors, (52), 13 states have internal predecessors, (52), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 18:35:14,854 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 18:35:14,854 INFO L93 Difference]: Finished difference Result 121 states and 135 transitions. [2024-11-08 18:35:14,854 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 121 states and 135 transitions. [2024-11-08 18:35:14,856 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6 [2024-11-08 18:35:14,856 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 121 states to 99 states and 113 transitions. [2024-11-08 18:35:14,857 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 23 [2024-11-08 18:35:14,857 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 23 [2024-11-08 18:35:14,857 INFO L73 IsDeterministic]: Start isDeterministic. Operand 99 states and 113 transitions. [2024-11-08 18:35:14,857 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-08 18:35:14,857 INFO L218 hiAutomatonCegarLoop]: Abstraction has 99 states and 113 transitions. [2024-11-08 18:35:14,857 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 99 states and 113 transitions. [2024-11-08 18:35:14,861 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 99 to 94. [2024-11-08 18:35:14,862 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 94 states, 94 states have (on average 1.148936170212766) internal successors, (108), 93 states have internal predecessors, (108), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 18:35:14,863 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 94 states to 94 states and 108 transitions. [2024-11-08 18:35:14,863 INFO L240 hiAutomatonCegarLoop]: Abstraction has 94 states and 108 transitions. [2024-11-08 18:35:14,863 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2024-11-08 18:35:14,864 INFO L425 stractBuchiCegarLoop]: Abstraction has 94 states and 108 transitions. [2024-11-08 18:35:14,864 INFO L332 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-11-08 18:35:14,864 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 94 states and 108 transitions. [2024-11-08 18:35:14,865 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6 [2024-11-08 18:35:14,865 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 18:35:14,865 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 18:35:14,866 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [12, 11, 11, 9, 2, 1, 1] [2024-11-08 18:35:14,867 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-11-08 18:35:14,867 INFO L745 eck$LassoCheckResult]: Stem: 1415#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true; 1416#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;havoc main_#t~nondet0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 1417#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 1434#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1445#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1444#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 1424#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 1425#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1449#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1412#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1405#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 1406#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1483#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1482#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1481#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 1480#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1479#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1478#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1477#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 1476#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1475#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1474#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1473#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 1472#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1471#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1470#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1469#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 1456#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1465#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1457#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1455#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 1454#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1453#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1452#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 1451#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 1447#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1422#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1423#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1464#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 1463#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1461#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1459#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1460#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 1462#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1446#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1432#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 1429#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 1428#L11-1 [2024-11-08 18:35:14,867 INFO L747 eck$LassoCheckResult]: Loop: 1428#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 1418#L12 assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 1419#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 1428#L11-1 [2024-11-08 18:35:14,867 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:35:14,868 INFO L85 PathProgramCache]: Analyzing trace with hash -605147591, now seen corresponding path program 6 times [2024-11-08 18:35:14,868 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 18:35:14,868 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1637111987] [2024-11-08 18:35:14,868 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:35:14,868 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 18:35:14,882 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 18:35:15,130 INFO L134 CoverageAnalysis]: Checked inductivity of 231 backedges. 104 proven. 112 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2024-11-08 18:35:15,130 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 18:35:15,130 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1637111987] [2024-11-08 18:35:15,131 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1637111987] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-08 18:35:15,131 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [529820924] [2024-11-08 18:35:15,131 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2024-11-08 18:35:15,131 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-08 18:35:15,131 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 [2024-11-08 18:35:15,133 INFO L229 MonitoredProcess]: Starting monitored process 26 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-08 18:35:15,136 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (26)] Waiting until timeout for monitored process [2024-11-08 18:35:15,188 INFO L227 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 12 check-sat command(s) [2024-11-08 18:35:15,188 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-08 18:35:15,189 INFO L255 TraceCheckSpWp]: Trace formula consists of 101 conjuncts, 10 conjuncts are in the unsatisfiable core [2024-11-08 18:35:15,190 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-08 18:35:15,411 INFO L134 CoverageAnalysis]: Checked inductivity of 231 backedges. 104 proven. 112 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2024-11-08 18:35:15,411 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-08 18:35:15,640 INFO L134 CoverageAnalysis]: Checked inductivity of 231 backedges. 104 proven. 112 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2024-11-08 18:35:15,641 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [529820924] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-08 18:35:15,641 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-08 18:35:15,641 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 10] total 25 [2024-11-08 18:35:15,641 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1527680618] [2024-11-08 18:35:15,641 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-08 18:35:15,641 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 18:35:15,642 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:35:15,642 INFO L85 PathProgramCache]: Analyzing trace with hash 41050, now seen corresponding path program 3 times [2024-11-08 18:35:15,642 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 18:35:15,642 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [164294686] [2024-11-08 18:35:15,642 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:35:15,642 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 18:35:15,645 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:35:15,645 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 18:35:15,646 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:35:15,647 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 18:35:15,664 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (25)] Forceful destruction successful, exit code 0 [2024-11-08 18:35:15,673 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 18:35:15,674 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2024-11-08 18:35:15,674 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=244, Invalid=356, Unknown=0, NotChecked=0, Total=600 [2024-11-08 18:35:15,674 INFO L87 Difference]: Start difference. First operand 94 states and 108 transitions. cyclomatic complexity: 20 Second operand has 25 states, 25 states have (on average 4.0) internal successors, (100), 25 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 18:35:15,962 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 18:35:15,962 INFO L93 Difference]: Finished difference Result 207 states and 221 transitions. [2024-11-08 18:35:15,962 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 207 states and 221 transitions. [2024-11-08 18:35:15,964 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6 [2024-11-08 18:35:15,965 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 207 states to 163 states and 177 transitions. [2024-11-08 18:35:15,965 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 23 [2024-11-08 18:35:15,966 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 23 [2024-11-08 18:35:15,966 INFO L73 IsDeterministic]: Start isDeterministic. Operand 163 states and 177 transitions. [2024-11-08 18:35:15,966 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-08 18:35:15,966 INFO L218 hiAutomatonCegarLoop]: Abstraction has 163 states and 177 transitions. [2024-11-08 18:35:15,966 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 163 states and 177 transitions. [2024-11-08 18:35:15,972 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 163 to 158. [2024-11-08 18:35:15,972 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 158 states, 158 states have (on average 1.0886075949367089) internal successors, (172), 157 states have internal predecessors, (172), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 18:35:15,974 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 158 states to 158 states and 172 transitions. [2024-11-08 18:35:15,974 INFO L240 hiAutomatonCegarLoop]: Abstraction has 158 states and 172 transitions. [2024-11-08 18:35:15,974 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2024-11-08 18:35:15,975 INFO L425 stractBuchiCegarLoop]: Abstraction has 158 states and 172 transitions. [2024-11-08 18:35:15,975 INFO L332 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-11-08 18:35:15,975 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 158 states and 172 transitions. [2024-11-08 18:35:15,980 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6 [2024-11-08 18:35:15,980 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 18:35:15,980 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 18:35:15,982 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [24, 23, 23, 21, 2, 1, 1] [2024-11-08 18:35:15,982 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-11-08 18:35:15,983 INFO L745 eck$LassoCheckResult]: Stem: 2034#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true; 2035#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;havoc main_#t~nondet0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 2036#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 2052#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2063#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2061#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 2042#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 2043#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2040#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2041#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2024#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 2025#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2147#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2146#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2145#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 2144#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2143#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2142#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2141#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 2140#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2139#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2138#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2137#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 2136#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2135#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2134#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2133#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 2132#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2131#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2130#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2129#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 2128#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2127#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2126#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2125#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 2124#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2123#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2122#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2121#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 2120#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2119#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2118#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2117#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 2116#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2115#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2114#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2113#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 2112#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2111#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2110#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2109#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 2108#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2107#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2106#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2105#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 2104#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2103#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2102#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2101#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 2074#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2077#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2075#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2073#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 2072#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2071#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2070#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 2069#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 2066#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2067#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2031#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2032#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 2100#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2099#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2098#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2097#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 2096#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2095#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2094#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2093#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 2092#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2091#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2090#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2089#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 2088#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2087#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2086#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2085#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 2084#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2083#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2081#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2079#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 2080#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2076#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2050#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 2047#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 2046#L11-1 [2024-11-08 18:35:15,983 INFO L747 eck$LassoCheckResult]: Loop: 2046#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 2037#L12 assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 2038#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 2046#L11-1 [2024-11-08 18:35:15,983 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:35:15,983 INFO L85 PathProgramCache]: Analyzing trace with hash 2086534593, now seen corresponding path program 7 times [2024-11-08 18:35:15,983 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 18:35:15,984 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1669720309] [2024-11-08 18:35:15,984 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:35:15,984 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 18:35:16,004 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 18:35:16,488 INFO L134 CoverageAnalysis]: Checked inductivity of 1035 backedges. 464 proven. 480 refuted. 0 times theorem prover too weak. 91 trivial. 0 not checked. [2024-11-08 18:35:16,489 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 18:35:16,489 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1669720309] [2024-11-08 18:35:16,489 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1669720309] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-08 18:35:16,489 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [457630504] [2024-11-08 18:35:16,489 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2024-11-08 18:35:16,490 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-08 18:35:16,490 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 [2024-11-08 18:35:16,491 INFO L229 MonitoredProcess]: Starting monitored process 27 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-08 18:35:16,493 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (27)] Waiting until timeout for monitored process [2024-11-08 18:35:16,555 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 18:35:16,556 INFO L255 TraceCheckSpWp]: Trace formula consists of 197 conjuncts, 18 conjuncts are in the unsatisfiable core [2024-11-08 18:35:16,558 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-08 18:35:17,074 INFO L134 CoverageAnalysis]: Checked inductivity of 1035 backedges. 464 proven. 480 refuted. 0 times theorem prover too weak. 91 trivial. 0 not checked. [2024-11-08 18:35:17,075 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-08 18:35:17,483 INFO L134 CoverageAnalysis]: Checked inductivity of 1035 backedges. 464 proven. 480 refuted. 0 times theorem prover too weak. 91 trivial. 0 not checked. [2024-11-08 18:35:17,483 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [457630504] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-08 18:35:17,484 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-08 18:35:17,484 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18, 18] total 38 [2024-11-08 18:35:17,484 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [249515353] [2024-11-08 18:35:17,484 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-08 18:35:17,485 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 18:35:17,485 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:35:17,485 INFO L85 PathProgramCache]: Analyzing trace with hash 41050, now seen corresponding path program 4 times [2024-11-08 18:35:17,485 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 18:35:17,485 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1345872502] [2024-11-08 18:35:17,486 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:35:17,486 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 18:35:17,488 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:35:17,489 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 18:35:17,490 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:35:17,490 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 18:35:17,517 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 18:35:17,518 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2024-11-08 18:35:17,519 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=545, Invalid=861, Unknown=0, NotChecked=0, Total=1406 [2024-11-08 18:35:17,519 INFO L87 Difference]: Start difference. First operand 158 states and 172 transitions. cyclomatic complexity: 20 Second operand has 38 states, 38 states have (on average 4.026315789473684) internal successors, (153), 38 states have internal predecessors, (153), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 18:35:17,851 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 18:35:17,851 INFO L93 Difference]: Finished difference Result 302 states and 316 transitions. [2024-11-08 18:35:17,852 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 302 states and 316 transitions. [2024-11-08 18:35:17,855 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6 [2024-11-08 18:35:17,856 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 302 states to 247 states and 261 transitions. [2024-11-08 18:35:17,856 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 23 [2024-11-08 18:35:17,856 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 23 [2024-11-08 18:35:17,856 INFO L73 IsDeterministic]: Start isDeterministic. Operand 247 states and 261 transitions. [2024-11-08 18:35:17,856 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-08 18:35:17,857 INFO L218 hiAutomatonCegarLoop]: Abstraction has 247 states and 261 transitions. [2024-11-08 18:35:17,857 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 247 states and 261 transitions. [2024-11-08 18:35:17,874 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 247 to 242. [2024-11-08 18:35:17,879 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 242 states, 242 states have (on average 1.0578512396694215) internal successors, (256), 241 states have internal predecessors, (256), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 18:35:17,880 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 242 states to 242 states and 256 transitions. [2024-11-08 18:35:17,881 INFO L240 hiAutomatonCegarLoop]: Abstraction has 242 states and 256 transitions. [2024-11-08 18:35:17,883 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2024-11-08 18:35:17,884 INFO L425 stractBuchiCegarLoop]: Abstraction has 242 states and 256 transitions. [2024-11-08 18:35:17,884 INFO L332 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-11-08 18:35:17,884 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 242 states and 256 transitions. [2024-11-08 18:35:17,885 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6 [2024-11-08 18:35:17,886 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 18:35:17,886 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 18:35:17,890 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [37, 36, 36, 34, 2, 1, 1] [2024-11-08 18:35:17,890 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-11-08 18:35:17,890 INFO L745 eck$LassoCheckResult]: Stem: 3107#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true; 3108#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;havoc main_#t~nondet0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 3109#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 3125#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3136#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3134#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 3115#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 3116#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3113#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3114#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3097#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 3098#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3272#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3271#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3270#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 3269#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3268#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3267#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3266#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 3265#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3264#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3263#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3262#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 3261#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3260#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3259#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3258#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 3257#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3256#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3255#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3254#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 3253#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3252#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3251#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3250#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 3249#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3248#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3247#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3246#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 3245#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3244#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3243#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3242#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 3241#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3240#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3239#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3238#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 3237#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3236#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3235#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3234#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 3233#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3232#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3231#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3230#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 3229#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3228#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3227#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3226#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 3225#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3224#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3223#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3222#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 3221#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3220#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3219#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3218#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 3217#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3216#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3215#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3214#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 3213#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3212#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3211#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3210#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 3209#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3208#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3207#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3206#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 3147#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3150#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3148#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3146#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 3145#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3144#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3143#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 3142#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 3139#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3140#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3104#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3105#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 3205#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3204#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3203#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3202#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 3201#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3200#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3199#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3198#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 3197#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3196#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3195#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3194#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 3193#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3192#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3191#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3190#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 3189#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3188#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3187#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3186#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 3185#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3184#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3183#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3182#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 3181#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3180#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3179#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3178#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 3177#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3176#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3175#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3174#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 3173#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3172#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3171#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3170#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 3169#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3168#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3167#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3166#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 3165#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3164#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3163#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3162#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 3161#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3160#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3159#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3158#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 3157#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3156#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3154#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3152#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 3153#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3149#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3123#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3120#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 3119#L11-1 [2024-11-08 18:35:17,891 INFO L747 eck$LassoCheckResult]: Loop: 3119#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3110#L12 assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3111#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 3119#L11-1 [2024-11-08 18:35:17,891 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:35:17,891 INFO L85 PathProgramCache]: Analyzing trace with hash -332958529, now seen corresponding path program 8 times [2024-11-08 18:35:17,892 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 18:35:17,892 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1280206046] [2024-11-08 18:35:17,892 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:35:17,892 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 18:35:17,922 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:35:17,922 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 18:35:17,941 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:35:17,948 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 18:35:17,948 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:35:17,949 INFO L85 PathProgramCache]: Analyzing trace with hash 41050, now seen corresponding path program 5 times [2024-11-08 18:35:17,949 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 18:35:17,949 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [792890743] [2024-11-08 18:35:17,949 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:35:17,949 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 18:35:17,951 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:35:17,951 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 18:35:17,952 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:35:17,952 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 18:35:17,953 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:35:17,953 INFO L85 PathProgramCache]: Analyzing trace with hash -2088039716, now seen corresponding path program 1 times [2024-11-08 18:35:17,953 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 18:35:17,953 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1760488614] [2024-11-08 18:35:17,954 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:35:17,954 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 18:35:17,971 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 18:35:18,109 INFO L134 CoverageAnalysis]: Checked inductivity of 2665 backedges. 250 proven. 0 refuted. 0 times theorem prover too weak. 2415 trivial. 0 not checked. [2024-11-08 18:35:18,109 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 18:35:18,110 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1760488614] [2024-11-08 18:35:18,110 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1760488614] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 18:35:18,110 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 18:35:18,110 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-08 18:35:18,110 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [980400490] [2024-11-08 18:35:18,111 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 18:35:18,129 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 18:35:18,130 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-08 18:35:18,130 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2024-11-08 18:35:18,130 INFO L87 Difference]: Start difference. First operand 242 states and 256 transitions. cyclomatic complexity: 20 Second operand has 4 states, 4 states have (on average 3.75) internal successors, (15), 4 states have internal predecessors, (15), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 18:35:18,152 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 18:35:18,152 INFO L93 Difference]: Finished difference Result 241 states and 251 transitions. [2024-11-08 18:35:18,152 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 241 states and 251 transitions. [2024-11-08 18:35:18,154 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2024-11-08 18:35:18,155 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 241 states to 176 states and 183 transitions. [2024-11-08 18:35:18,156 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 15 [2024-11-08 18:35:18,156 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 15 [2024-11-08 18:35:18,156 INFO L73 IsDeterministic]: Start isDeterministic. Operand 176 states and 183 transitions. [2024-11-08 18:35:18,156 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-08 18:35:18,156 INFO L218 hiAutomatonCegarLoop]: Abstraction has 176 states and 183 transitions. [2024-11-08 18:35:18,157 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 176 states and 183 transitions. [2024-11-08 18:35:18,161 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 176 to 171. [2024-11-08 18:35:18,161 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 171 states, 171 states have (on average 1.04093567251462) internal successors, (178), 170 states have internal predecessors, (178), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 18:35:18,162 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 171 states to 171 states and 178 transitions. [2024-11-08 18:35:18,163 INFO L240 hiAutomatonCegarLoop]: Abstraction has 171 states and 178 transitions. [2024-11-08 18:35:18,163 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-08 18:35:18,164 INFO L425 stractBuchiCegarLoop]: Abstraction has 171 states and 178 transitions. [2024-11-08 18:35:18,164 INFO L332 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-11-08 18:35:18,164 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 171 states and 178 transitions. [2024-11-08 18:35:18,165 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2024-11-08 18:35:18,165 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 18:35:18,165 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 18:35:18,168 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [38, 38, 37, 34, 3, 1, 1] [2024-11-08 18:35:18,168 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-11-08 18:35:18,168 INFO L745 eck$LassoCheckResult]: Stem: 3599#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true; 3600#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;havoc main_#t~nondet0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 3601#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 3611#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3612#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3593#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 3594#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 3617#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3604#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3605#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3589#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 3590#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3757#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3756#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3755#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 3754#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3753#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3752#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3751#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 3750#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3749#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3748#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3747#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 3746#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3745#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3744#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3743#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 3742#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3741#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3740#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3739#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 3738#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3737#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3736#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3735#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 3734#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3733#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3732#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3731#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 3730#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3729#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3728#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3727#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 3726#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3725#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3724#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3723#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 3722#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3721#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3720#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3719#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 3718#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3717#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3716#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3715#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 3714#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3713#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3712#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3711#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 3710#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3709#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3708#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3707#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 3706#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3705#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3704#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3703#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 3702#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3701#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3700#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3699#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 3698#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3697#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3696#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3695#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 3694#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3693#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3692#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3691#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 3688#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3690#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3689#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3687#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 3686#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3685#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3684#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 3683#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 3682#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3681#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3680#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3679#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 3678#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3677#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3676#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3675#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 3674#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3673#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3672#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3671#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 3670#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3669#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3668#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3667#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 3666#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3665#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3664#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3663#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 3662#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3661#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3660#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3659#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 3658#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3657#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3656#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3655#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 3654#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3653#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3652#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3651#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 3650#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3649#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3648#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3647#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 3646#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3645#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3644#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3643#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 3642#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3641#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3640#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3639#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 3638#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3637#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3636#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3635#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 3634#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3633#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3632#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3631#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 3630#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3629#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3628#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3627#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 3621#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3626#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3624#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 3619#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 3620#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3613#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3610#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 3609#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 3607#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3602#L12 [2024-11-08 18:35:18,169 INFO L747 eck$LassoCheckResult]: Loop: 3602#L12 assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 3603#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 3606#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 3602#L12 [2024-11-08 18:35:18,169 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:35:18,169 INFO L85 PathProgramCache]: Analyzing trace with hash -856667404, now seen corresponding path program 9 times [2024-11-08 18:35:18,170 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 18:35:18,170 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1987234510] [2024-11-08 18:35:18,170 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:35:18,170 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 18:35:18,208 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 18:35:18,930 INFO L134 CoverageAnalysis]: Checked inductivity of 2738 backedges. 74 proven. 1904 refuted. 0 times theorem prover too weak. 760 trivial. 0 not checked. [2024-11-08 18:35:18,930 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 18:35:18,931 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1987234510] [2024-11-08 18:35:18,931 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1987234510] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-08 18:35:18,931 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1996041819] [2024-11-08 18:35:18,931 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-11-08 18:35:18,931 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-08 18:35:18,931 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 [2024-11-08 18:35:18,933 INFO L229 MonitoredProcess]: Starting monitored process 28 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-08 18:35:18,934 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (28)] Waiting until timeout for monitored process [2024-11-08 18:35:19,016 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 23 check-sat command(s) [2024-11-08 18:35:19,017 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-08 18:35:19,019 INFO L255 TraceCheckSpWp]: Trace formula consists of 194 conjuncts, 20 conjuncts are in the unsatisfiable core [2024-11-08 18:35:19,022 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-08 18:35:19,673 INFO L134 CoverageAnalysis]: Checked inductivity of 2738 backedges. 74 proven. 1904 refuted. 0 times theorem prover too weak. 760 trivial. 0 not checked. [2024-11-08 18:35:19,673 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-08 18:35:20,200 INFO L134 CoverageAnalysis]: Checked inductivity of 2738 backedges. 74 proven. 1904 refuted. 0 times theorem prover too weak. 760 trivial. 0 not checked. [2024-11-08 18:35:20,200 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1996041819] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-08 18:35:20,200 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-08 18:35:20,200 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 20, 20] total 40 [2024-11-08 18:35:20,201 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1442957324] [2024-11-08 18:35:20,201 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-08 18:35:20,201 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 18:35:20,202 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:35:20,202 INFO L85 PathProgramCache]: Analyzing trace with hash 51130, now seen corresponding path program 6 times [2024-11-08 18:35:20,202 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 18:35:20,202 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [127238198] [2024-11-08 18:35:20,202 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:35:20,203 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 18:35:20,205 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:35:20,205 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 18:35:20,217 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:35:20,218 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 18:35:20,239 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 18:35:20,239 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2024-11-08 18:35:20,240 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=556, Invalid=1004, Unknown=0, NotChecked=0, Total=1560 [2024-11-08 18:35:20,240 INFO L87 Difference]: Start difference. First operand 171 states and 178 transitions. cyclomatic complexity: 11 Second operand has 40 states, 40 states have (on average 4.025) internal successors, (161), 40 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 18:35:21,404 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 18:35:21,404 INFO L93 Difference]: Finished difference Result 439 states and 448 transitions. [2024-11-08 18:35:21,404 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 439 states and 448 transitions. [2024-11-08 18:35:21,407 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2024-11-08 18:35:21,409 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 439 states to 335 states and 344 transitions. [2024-11-08 18:35:21,409 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 15 [2024-11-08 18:35:21,409 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 15 [2024-11-08 18:35:21,409 INFO L73 IsDeterministic]: Start isDeterministic. Operand 335 states and 344 transitions. [2024-11-08 18:35:21,410 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-08 18:35:21,410 INFO L218 hiAutomatonCegarLoop]: Abstraction has 335 states and 344 transitions. [2024-11-08 18:35:21,410 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 335 states and 344 transitions. [2024-11-08 18:35:21,415 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 335 to 323. [2024-11-08 18:35:21,416 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 323 states, 323 states have (on average 1.0278637770897834) internal successors, (332), 322 states have internal predecessors, (332), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 18:35:21,418 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 323 states to 323 states and 332 transitions. [2024-11-08 18:35:21,418 INFO L240 hiAutomatonCegarLoop]: Abstraction has 323 states and 332 transitions. [2024-11-08 18:35:21,418 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 76 states. [2024-11-08 18:35:21,419 INFO L425 stractBuchiCegarLoop]: Abstraction has 323 states and 332 transitions. [2024-11-08 18:35:21,419 INFO L332 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-11-08 18:35:21,419 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 323 states and 332 transitions. [2024-11-08 18:35:21,421 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2024-11-08 18:35:21,421 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 18:35:21,421 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 18:35:21,426 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [76, 76, 75, 70, 5, 1, 1] [2024-11-08 18:35:21,426 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-11-08 18:35:21,427 INFO L745 eck$LassoCheckResult]: Stem: 5234#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true; 5235#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;havoc main_#t~nondet0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 5236#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 5251#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5255#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5254#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 5252#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 5245#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5239#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5228#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5224#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 5225#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5545#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5544#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5543#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 5542#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5541#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5540#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5539#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 5538#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5537#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5536#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5535#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 5534#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5533#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5532#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5531#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 5530#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5529#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5528#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5527#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 5526#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5525#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5524#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5523#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 5522#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5521#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5520#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5519#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 5518#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5517#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5516#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5515#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 5514#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5513#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5512#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5511#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 5510#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5509#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5508#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5507#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 5506#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5505#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5504#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5503#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 5502#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5501#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5500#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5499#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 5498#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5497#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5496#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5495#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 5494#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5493#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5492#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5491#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 5490#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5489#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5488#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5487#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 5486#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5485#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5484#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5483#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 5482#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5481#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5480#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5479#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 5476#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5478#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5477#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5475#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 5474#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5473#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5472#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 5471#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 5470#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5469#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5468#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5467#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 5466#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5465#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5464#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5463#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 5462#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5461#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5460#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5459#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 5458#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5457#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5456#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5455#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 5454#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5453#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5452#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5451#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 5450#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5449#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5448#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5447#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 5446#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5445#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5444#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5443#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 5442#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5441#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5440#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5439#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 5438#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5437#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5436#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5435#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 5434#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5433#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5432#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5431#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 5430#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5429#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5428#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5427#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 5426#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5425#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5424#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5423#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 5422#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5421#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5420#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5419#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 5418#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5417#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5416#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5415#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 5414#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5413#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5412#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5411#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 5410#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5409#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5408#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5407#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 5406#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5405#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5404#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5403#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 5400#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5402#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5401#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5399#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 5398#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5397#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5396#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 5395#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 5394#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5393#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5392#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5391#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 5390#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5389#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5388#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5387#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 5386#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5385#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5384#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5383#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 5382#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5381#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5380#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5379#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 5378#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5377#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5376#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5375#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 5374#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5373#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5372#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5371#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 5370#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5369#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5368#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5367#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 5366#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5365#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5364#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5363#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 5362#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5361#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5360#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5359#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 5358#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5357#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5356#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5355#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 5354#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5353#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5352#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5351#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 5350#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5349#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5348#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5347#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 5346#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5345#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5344#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5343#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 5342#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5341#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5340#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5339#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 5338#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5337#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5336#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5335#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 5334#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5333#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5332#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5331#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 5328#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5330#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5329#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5327#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 5326#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5325#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5324#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 5323#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 5322#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5321#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5320#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5319#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 5318#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5317#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5316#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5315#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 5314#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5313#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5312#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5311#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 5310#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5309#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5308#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5307#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 5306#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5305#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5304#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5303#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 5302#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5301#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5300#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5299#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 5298#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5297#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5296#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5295#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 5294#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5293#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5292#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5291#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 5290#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5289#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5288#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5287#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 5286#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5285#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5284#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5283#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 5282#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5281#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5280#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5279#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 5278#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5277#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5276#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5275#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 5274#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5273#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5272#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5271#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 5270#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5269#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5268#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5267#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 5266#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5265#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5264#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5263#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 5258#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5262#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5260#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 5256#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 5257#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5246#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5244#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 5243#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 5240#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5237#L12 [2024-11-08 18:35:21,427 INFO L747 eck$LassoCheckResult]: Loop: 5237#L12 assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 5238#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 5242#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 5237#L12 [2024-11-08 18:35:21,427 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:35:21,428 INFO L85 PathProgramCache]: Analyzing trace with hash -439301140, now seen corresponding path program 10 times [2024-11-08 18:35:21,428 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 18:35:21,428 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2078944385] [2024-11-08 18:35:21,428 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:35:21,428 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 18:35:21,480 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:35:21,480 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 18:35:21,525 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:35:21,533 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 18:35:21,534 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:35:21,534 INFO L85 PathProgramCache]: Analyzing trace with hash 51130, now seen corresponding path program 7 times [2024-11-08 18:35:21,534 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 18:35:21,534 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [914951588] [2024-11-08 18:35:21,535 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:35:21,535 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 18:35:21,537 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:35:21,537 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 18:35:21,538 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:35:21,538 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 18:35:21,539 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:35:21,539 INFO L85 PathProgramCache]: Analyzing trace with hash -454889489, now seen corresponding path program 2 times [2024-11-08 18:35:21,539 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 18:35:21,539 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1353546161] [2024-11-08 18:35:21,539 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:35:21,540 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 18:35:21,607 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 18:35:22,048 INFO L134 CoverageAnalysis]: Checked inductivity of 11477 backedges. 152 proven. 8725 refuted. 0 times theorem prover too weak. 2600 trivial. 0 not checked. [2024-11-08 18:35:22,049 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 18:35:22,049 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1353546161] [2024-11-08 18:35:22,049 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1353546161] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-08 18:35:22,049 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [983132709] [2024-11-08 18:35:22,049 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-08 18:35:22,049 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-08 18:35:22,050 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 [2024-11-08 18:35:22,051 INFO L229 MonitoredProcess]: Starting monitored process 29 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-08 18:35:22,054 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (29)] Waiting until timeout for monitored process [2024-11-08 18:35:22,183 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2024-11-08 18:35:22,183 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-08 18:35:22,186 INFO L255 TraceCheckSpWp]: Trace formula consists of 632 conjuncts, 8 conjuncts are in the unsatisfiable core [2024-11-08 18:35:22,190 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-08 18:35:22,651 INFO L134 CoverageAnalysis]: Checked inductivity of 11477 backedges. 152 proven. 8725 refuted. 0 times theorem prover too weak. 2600 trivial. 0 not checked. [2024-11-08 18:35:22,652 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-08 18:35:23,210 INFO L134 CoverageAnalysis]: Checked inductivity of 11477 backedges. 152 proven. 8725 refuted. 0 times theorem prover too weak. 2600 trivial. 0 not checked. [2024-11-08 18:35:23,211 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [983132709] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-08 18:35:23,211 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-08 18:35:23,211 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8] total 15 [2024-11-08 18:35:23,211 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1146140429] [2024-11-08 18:35:23,211 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-08 18:35:23,228 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 18:35:23,229 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2024-11-08 18:35:23,229 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=80, Invalid=130, Unknown=0, NotChecked=0, Total=210 [2024-11-08 18:35:23,229 INFO L87 Difference]: Start difference. First operand 323 states and 332 transitions. cyclomatic complexity: 15 Second operand has 15 states, 15 states have (on average 4.2) internal successors, (63), 15 states have internal predecessors, (63), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 18:35:23,512 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 18:35:23,512 INFO L93 Difference]: Finished difference Result 402 states and 417 transitions. [2024-11-08 18:35:23,512 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 402 states and 417 transitions. [2024-11-08 18:35:23,515 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2024-11-08 18:35:23,516 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 402 states to 393 states and 408 transitions. [2024-11-08 18:35:23,516 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 15 [2024-11-08 18:35:23,517 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 15 [2024-11-08 18:35:23,517 INFO L73 IsDeterministic]: Start isDeterministic. Operand 393 states and 408 transitions. [2024-11-08 18:35:23,517 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-08 18:35:23,517 INFO L218 hiAutomatonCegarLoop]: Abstraction has 393 states and 408 transitions. [2024-11-08 18:35:23,517 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 393 states and 408 transitions. [2024-11-08 18:35:23,522 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 393 to 375. [2024-11-08 18:35:23,522 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 375 states, 375 states have (on average 1.04) internal successors, (390), 374 states have internal predecessors, (390), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 18:35:23,524 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 375 states to 375 states and 390 transitions. [2024-11-08 18:35:23,524 INFO L240 hiAutomatonCegarLoop]: Abstraction has 375 states and 390 transitions. [2024-11-08 18:35:23,527 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2024-11-08 18:35:23,527 INFO L425 stractBuchiCegarLoop]: Abstraction has 375 states and 390 transitions. [2024-11-08 18:35:23,528 INFO L332 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-11-08 18:35:23,528 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 375 states and 390 transitions. [2024-11-08 18:35:23,530 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2024-11-08 18:35:23,530 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 18:35:23,530 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 18:35:23,537 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [89, 89, 88, 77, 11, 1, 1] [2024-11-08 18:35:23,537 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-11-08 18:35:23,537 INFO L745 eck$LassoCheckResult]: Stem: 7849#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true; 7850#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;havoc main_#t~nondet0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 7851#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 7868#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 7854#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 7855#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 7869#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 7861#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 7862#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 7846#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 7839#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 7840#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 8212#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 8211#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 8210#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 8209#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 8208#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 8207#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 8206#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 8205#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 8204#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 8203#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 8202#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 8201#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 8200#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 8199#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 8198#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 8197#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 8196#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 8195#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 8194#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 8193#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 8192#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 8191#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 8190#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 8189#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 8188#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 8187#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 8186#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 8185#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 8184#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 8183#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 8182#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 8181#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 8180#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 8179#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 8178#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 8177#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 8176#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 8175#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 8174#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 8173#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 8172#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 8171#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 8170#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 8169#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 8168#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 8167#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 8166#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 8165#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 8164#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 8163#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 8162#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 8161#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 8160#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 8159#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 8158#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 8157#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 8156#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 8155#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 8154#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 8153#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 8152#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 8151#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 8150#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 8149#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 8148#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 8147#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 8146#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 8143#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 8145#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 8144#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 8142#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 8141#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 8140#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 8139#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 8138#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 8137#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 8136#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 8135#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 8134#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 8133#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 8132#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 8131#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 8130#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 8129#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 8128#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 8127#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 8126#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 8125#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 8124#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 8123#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 8122#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 8121#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 8120#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 8119#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 8118#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 8117#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 8116#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 8115#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 8114#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 8113#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 8112#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 8111#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 8110#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 8109#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 8108#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 8107#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 8106#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 8105#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 8104#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 8103#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 8102#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 8101#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 8100#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 8099#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 8098#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 8097#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 8096#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 8095#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 8094#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 8093#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 8092#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 8091#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 8090#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 8089#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 8088#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 8087#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 8086#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 8085#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 8084#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 8083#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 8082#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 8081#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 8080#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 8079#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 8078#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 8077#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 8076#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 8075#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 8074#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 8073#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 8072#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 8071#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 8070#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 8067#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 8069#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 8068#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 8066#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 8065#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 8064#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 8063#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 8062#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 8061#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 8060#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 8059#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 8058#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 8057#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 8056#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 8055#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 8054#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 8053#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 8052#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 8051#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 8050#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 8049#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 8048#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 8047#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 8046#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 8045#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 8044#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 8043#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 8042#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 8041#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 8040#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 8039#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 8038#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 8037#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 8036#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 8035#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 8034#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 8033#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 8032#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 8031#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 8030#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 8029#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 8028#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 8027#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 8026#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 8025#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 8024#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 8023#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 8022#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 8021#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 8020#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 8019#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 8018#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 8017#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 8016#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 8015#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 8014#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 8013#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 8012#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 8011#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 8010#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 8009#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 8008#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 8007#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 8006#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 8005#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 8004#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 8003#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 8002#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 8001#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 8000#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 7999#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 7998#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 7995#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 7997#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 7996#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 7994#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 7993#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 7992#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 7991#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 7990#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 7989#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 7988#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 7987#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 7986#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 7985#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 7984#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 7983#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 7982#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 7981#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 7980#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 7979#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 7978#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 7977#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 7976#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 7975#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 7974#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 7973#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 7972#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 7971#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 7970#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 7969#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 7968#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 7967#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 7966#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 7965#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 7964#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 7963#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 7962#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 7961#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 7960#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 7959#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 7958#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 7957#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 7956#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 7955#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 7954#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 7953#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 7952#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 7951#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 7950#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 7949#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 7948#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 7947#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 7946#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 7945#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 7944#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 7943#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 7942#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 7941#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 7940#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 7939#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 7938#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 7937#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 7936#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 7935#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 7934#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 7933#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 7932#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 7931#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 7930#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 7927#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 7929#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 7928#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 7926#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 7925#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 7924#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 7923#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 7922#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 7921#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 7920#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 7919#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 7918#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 7915#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 7917#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 7916#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 7914#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 7913#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 7912#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 7911#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 7910#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 7907#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 7909#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 7908#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 7906#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 7905#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 7904#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 7903#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 7902#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 7899#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 7901#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 7900#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 7898#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 7897#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 7896#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 7895#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 7894#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 7891#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 7893#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 7892#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 7890#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 7889#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 7888#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 7887#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 7886#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 7883#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 7885#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 7884#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 7882#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 7881#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 7880#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 7879#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 7878#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 7873#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 7877#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 7874#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 7871#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 7872#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 7863#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 7860#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 7859#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 7856#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 7852#L12 [2024-11-08 18:35:23,538 INFO L747 eck$LassoCheckResult]: Loop: 7852#L12 assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 7853#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 7858#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 7852#L12 [2024-11-08 18:35:23,538 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:35:23,539 INFO L85 PathProgramCache]: Analyzing trace with hash -880771678, now seen corresponding path program 11 times [2024-11-08 18:35:23,539 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 18:35:23,539 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1854669371] [2024-11-08 18:35:23,539 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:35:23,539 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 18:35:23,593 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 18:35:24,464 INFO L134 CoverageAnalysis]: Checked inductivity of 15488 backedges. 6197 proven. 7058 refuted. 0 times theorem prover too weak. 2233 trivial. 0 not checked. [2024-11-08 18:35:24,465 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 18:35:24,465 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1854669371] [2024-11-08 18:35:24,465 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1854669371] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-08 18:35:24,465 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1234209752] [2024-11-08 18:35:24,465 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2024-11-08 18:35:24,465 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-08 18:35:24,466 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 [2024-11-08 18:35:24,467 INFO L229 MonitoredProcess]: Starting monitored process 30 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-08 18:35:24,469 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (30)] Waiting until timeout for monitored process [2024-11-08 18:35:24,749 INFO L227 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 75 check-sat command(s) [2024-11-08 18:35:24,749 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-08 18:35:24,752 INFO L255 TraceCheckSpWp]: Trace formula consists of 617 conjuncts, 27 conjuncts are in the unsatisfiable core [2024-11-08 18:35:24,757 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-08 18:35:25,407 INFO L134 CoverageAnalysis]: Checked inductivity of 15488 backedges. 8729 proven. 4521 refuted. 0 times theorem prover too weak. 2238 trivial. 0 not checked. [2024-11-08 18:35:25,407 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-08 18:35:26,088 INFO L134 CoverageAnalysis]: Checked inductivity of 15488 backedges. 8729 proven. 4521 refuted. 0 times theorem prover too weak. 2238 trivial. 0 not checked. [2024-11-08 18:35:26,088 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1234209752] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-08 18:35:26,088 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-08 18:35:26,089 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 27, 27] total 50 [2024-11-08 18:35:26,089 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [205624076] [2024-11-08 18:35:26,089 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-08 18:35:26,090 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 18:35:26,090 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:35:26,090 INFO L85 PathProgramCache]: Analyzing trace with hash 51130, now seen corresponding path program 8 times [2024-11-08 18:35:26,090 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 18:35:26,091 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [643186779] [2024-11-08 18:35:26,091 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:35:26,091 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 18:35:26,093 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:35:26,094 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 18:35:26,096 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:35:26,098 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 18:35:26,117 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 18:35:26,118 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 50 interpolants. [2024-11-08 18:35:26,119 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=644, Invalid=1806, Unknown=0, NotChecked=0, Total=2450 [2024-11-08 18:35:26,119 INFO L87 Difference]: Start difference. First operand 375 states and 390 transitions. cyclomatic complexity: 27 Second operand has 50 states, 50 states have (on average 4.26) internal successors, (213), 50 states have internal predecessors, (213), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 18:35:29,046 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 18:35:29,047 INFO L93 Difference]: Finished difference Result 3832 states and 4127 transitions. [2024-11-08 18:35:29,047 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3832 states and 4127 transitions. [2024-11-08 18:35:29,069 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2024-11-08 18:35:29,083 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3832 states to 3205 states and 3500 transitions. [2024-11-08 18:35:29,084 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 32 [2024-11-08 18:35:29,084 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 32 [2024-11-08 18:35:29,084 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3205 states and 3500 transitions. [2024-11-08 18:35:29,084 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-08 18:35:29,084 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3205 states and 3500 transitions. [2024-11-08 18:35:29,087 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3205 states and 3500 transitions. [2024-11-08 18:35:29,108 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3205 to 803. [2024-11-08 18:35:29,109 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 803 states, 803 states have (on average 1.0672478206724783) internal successors, (857), 802 states have internal predecessors, (857), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 18:35:29,111 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 803 states to 803 states and 857 transitions. [2024-11-08 18:35:29,111 INFO L240 hiAutomatonCegarLoop]: Abstraction has 803 states and 857 transitions. [2024-11-08 18:35:29,112 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 135 states. [2024-11-08 18:35:29,112 INFO L425 stractBuchiCegarLoop]: Abstraction has 803 states and 857 transitions. [2024-11-08 18:35:29,112 INFO L332 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-11-08 18:35:29,113 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 803 states and 857 transitions. [2024-11-08 18:35:29,116 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2024-11-08 18:35:29,116 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 18:35:29,116 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 18:35:29,126 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [123, 123, 122, 108, 14, 1, 1] [2024-11-08 18:35:29,126 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-11-08 18:35:29,127 INFO L745 eck$LassoCheckResult]: Stem: 14494#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true; 14495#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;havoc main_#t~nondet0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 14496#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14506#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14507#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14491#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 14492#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14509#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14499#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14500#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14483#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14484#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 15083#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 15082#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 15081#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 15080#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 15079#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 15078#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 15077#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 15076#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 15075#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 15074#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 15073#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 15072#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 15071#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 15070#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 15069#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 15068#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 15067#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 15066#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 15065#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 15064#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 15063#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 15062#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 15061#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 15060#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 15059#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 15058#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 15057#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 15056#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 15055#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 15054#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 15053#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 15052#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 15051#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 15050#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 15049#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 15048#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 15047#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 15046#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 15045#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 15044#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 15043#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 15042#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 15041#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 15040#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 15039#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 15038#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 15037#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 15036#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 15035#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 15034#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 15033#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 15032#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 15031#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 15030#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 15029#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 15028#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 15027#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 15026#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 15025#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 15024#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 15023#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 15022#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 15021#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 15020#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 15019#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 15018#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 15017#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 15014#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 15016#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 15015#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 15013#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 15012#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 15011#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 15010#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 15009#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 15008#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 15007#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 15006#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 15005#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 15004#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 15003#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 15002#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 15001#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 15000#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14999#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14998#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14997#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14996#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14995#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14994#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14993#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14992#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14991#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14990#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14989#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14988#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14987#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14986#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14985#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14984#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14983#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14982#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14981#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14980#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14979#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14978#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14977#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14976#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14975#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14974#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14973#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14972#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14971#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14970#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14969#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14968#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14967#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14966#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14965#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14964#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14963#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14962#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14961#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14960#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14959#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14958#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14957#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14956#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14955#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14954#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14953#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14952#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14951#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14950#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14949#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14948#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14947#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14946#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14945#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14944#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14943#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14942#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14941#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14938#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14940#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14939#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14937#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14936#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14935#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14934#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 14933#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14932#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14931#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14930#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14929#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14928#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14927#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14926#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14925#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14924#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14923#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14922#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14921#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14920#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14919#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14918#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14917#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14916#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14915#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14914#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14913#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14912#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14911#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14910#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14909#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14908#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14907#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14906#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14905#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14904#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14903#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14902#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14901#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14900#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14899#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14898#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14897#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14896#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14895#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14894#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14893#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14892#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14891#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14890#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14889#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14888#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14887#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14886#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14885#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14884#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14883#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14882#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14881#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14880#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14879#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14878#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14877#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14876#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14875#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14874#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14873#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14872#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14871#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14870#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14869#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14868#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14867#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14866#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14864#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14863#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14862#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14861#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 14860#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14859#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14858#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14857#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14856#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14855#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14854#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14853#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14852#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14851#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14850#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14849#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14848#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14847#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14846#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14845#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14844#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14843#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14842#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14841#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14840#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14839#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14838#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14837#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14836#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14835#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14834#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14833#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14832#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14831#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14830#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14828#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14829#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 15120#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 15119#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 15118#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 15117#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 15116#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 15115#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 15114#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 15113#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 15112#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 15111#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 15110#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 15109#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 15108#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 15107#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 15106#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 15105#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 15104#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 15103#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 15102#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 15101#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 15100#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 15099#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 15098#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 15097#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 15096#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 15095#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 15094#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 15093#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14766#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 15091#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 15090#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14791#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14790#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14789#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14762#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 14761#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14760#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14759#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14758#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14757#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14756#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14755#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14754#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14753#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14752#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14751#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14750#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14749#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14748#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14747#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14746#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14745#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14744#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14743#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14742#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14740#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14738#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14715#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14713#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14711#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14708#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14707#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14704#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14705#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14714#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14712#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14710#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14709#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14694#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14693#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14683#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 14682#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14681#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14680#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14679#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14678#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14677#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14676#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14675#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14674#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14673#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14672#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14671#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14670#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14669#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14668#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14667#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14666#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14664#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14663#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14661#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14662#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14658#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14657#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14651#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 14650#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14649#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14648#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14647#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14646#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14645#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14644#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14643#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14642#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14641#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14640#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14639#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14638#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14637#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14636#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14635#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14633#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14634#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14628#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14629#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14632#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14623#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14622#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14621#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 14620#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14619#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14618#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14617#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14616#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14615#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14614#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14613#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14612#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14611#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14610#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14609#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14608#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14607#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14605#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14603#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14600#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14601#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14606#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14604#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14602#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14595#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14594#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14593#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 14592#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14591#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14590#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14589#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14588#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14587#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14586#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14585#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14584#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14583#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14582#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14581#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14580#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14579#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14578#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14577#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14576#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14553#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14575#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14574#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14572#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14571#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14570#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14569#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 14568#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14567#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14566#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14565#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14564#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14563#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14562#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14561#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14560#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14559#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14558#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14557#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14556#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14537#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14555#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14554#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14552#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14551#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14550#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14549#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 14548#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14547#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14546#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14545#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14544#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14543#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14542#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14541#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14540#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14525#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14539#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14538#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14536#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14535#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14534#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14533#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 14532#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14531#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14530#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14529#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14528#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14514#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14527#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14526#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14524#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14523#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14522#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14521#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 14520#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14519#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14518#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14516#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 14512#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14513#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14508#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14505#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 14504#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14502#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14497#L12 [2024-11-08 18:35:29,127 INFO L747 eck$LassoCheckResult]: Loop: 14497#L12 assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 14498#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 14501#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 14497#L12 [2024-11-08 18:35:29,128 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:35:29,128 INFO L85 PathProgramCache]: Analyzing trace with hash -341017616, now seen corresponding path program 12 times [2024-11-08 18:35:29,128 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 18:35:29,128 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [899207442] [2024-11-08 18:35:29,128 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:35:29,129 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 18:35:29,198 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 18:35:30,709 INFO L134 CoverageAnalysis]: Checked inductivity of 29768 backedges. 14617 proven. 10996 refuted. 0 times theorem prover too weak. 4155 trivial. 0 not checked. [2024-11-08 18:35:30,709 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 18:35:30,709 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [899207442] [2024-11-08 18:35:30,710 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [899207442] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-08 18:35:30,710 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2069947352] [2024-11-08 18:35:30,710 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2024-11-08 18:35:30,710 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-08 18:35:30,710 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 [2024-11-08 18:35:30,712 INFO L229 MonitoredProcess]: Starting monitored process 31 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-08 18:35:30,714 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (31)] Waiting until timeout for monitored process [2024-11-08 18:35:30,950 INFO L227 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 71 check-sat command(s) [2024-11-08 18:35:30,950 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-08 18:35:30,953 INFO L255 TraceCheckSpWp]: Trace formula consists of 596 conjuncts, 15 conjuncts are in the unsatisfiable core [2024-11-08 18:35:30,958 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-08 18:35:31,368 INFO L134 CoverageAnalysis]: Checked inductivity of 29768 backedges. 10864 proven. 528 refuted. 0 times theorem prover too weak. 18376 trivial. 0 not checked. [2024-11-08 18:35:31,368 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-08 18:35:31,751 INFO L134 CoverageAnalysis]: Checked inductivity of 29768 backedges. 10756 proven. 636 refuted. 0 times theorem prover too weak. 18376 trivial. 0 not checked. [2024-11-08 18:35:31,751 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2069947352] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-08 18:35:31,751 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-08 18:35:31,752 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 14, 14] total 39 [2024-11-08 18:35:31,752 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [832478260] [2024-11-08 18:35:31,752 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-08 18:35:31,753 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 18:35:31,753 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:35:31,753 INFO L85 PathProgramCache]: Analyzing trace with hash 51130, now seen corresponding path program 9 times [2024-11-08 18:35:31,754 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 18:35:31,754 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1578506080] [2024-11-08 18:35:31,754 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:35:31,754 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 18:35:31,756 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:35:31,756 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 18:35:31,757 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:35:31,758 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 18:35:31,775 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 18:35:31,776 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 39 interpolants. [2024-11-08 18:35:31,777 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=203, Invalid=1279, Unknown=0, NotChecked=0, Total=1482 [2024-11-08 18:35:31,777 INFO L87 Difference]: Start difference. First operand 803 states and 857 transitions. cyclomatic complexity: 60 Second operand has 39 states, 39 states have (on average 4.205128205128205) internal successors, (164), 39 states have internal predecessors, (164), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 18:35:34,750 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 18:35:34,750 INFO L93 Difference]: Finished difference Result 1237 states and 1291 transitions. [2024-11-08 18:35:34,751 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1237 states and 1291 transitions. [2024-11-08 18:35:34,757 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2024-11-08 18:35:34,762 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1237 states to 1127 states and 1179 transitions. [2024-11-08 18:35:34,762 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 25 [2024-11-08 18:35:34,762 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 86 [2024-11-08 18:35:34,762 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1127 states and 1179 transitions. [2024-11-08 18:35:34,762 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-08 18:35:34,762 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1127 states and 1179 transitions. [2024-11-08 18:35:34,763 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1127 states and 1179 transitions. [2024-11-08 18:35:34,773 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1127 to 785. [2024-11-08 18:35:34,774 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 785 states, 785 states have (on average 1.0305732484076433) internal successors, (809), 784 states have internal predecessors, (809), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 18:35:34,775 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 785 states to 785 states and 809 transitions. [2024-11-08 18:35:34,776 INFO L240 hiAutomatonCegarLoop]: Abstraction has 785 states and 809 transitions. [2024-11-08 18:35:34,776 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 92 states. [2024-11-08 18:35:34,777 INFO L425 stractBuchiCegarLoop]: Abstraction has 785 states and 809 transitions. [2024-11-08 18:35:34,777 INFO L332 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2024-11-08 18:35:34,777 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 785 states and 809 transitions. [2024-11-08 18:35:34,780 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2024-11-08 18:35:34,780 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 18:35:34,780 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 18:35:34,791 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [140, 140, 140, 125, 15, 1, 1] [2024-11-08 18:35:34,791 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-11-08 18:35:34,791 INFO L745 eck$LassoCheckResult]: Stem: 19696#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true; 19697#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;havoc main_#t~nondet0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 19698#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 19791#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 19792#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 19693#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 19694#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 19794#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 19701#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 19702#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 19686#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 19687#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20448#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20447#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20446#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20445#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20444#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20443#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20442#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20441#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20440#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20439#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20438#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20437#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20436#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20435#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20434#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20433#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20432#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20431#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20430#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20429#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20428#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20427#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20426#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20425#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20424#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20423#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20422#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20421#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20420#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20419#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20418#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20417#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20416#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20415#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20414#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20413#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20412#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20411#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20410#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20409#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20408#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20407#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20406#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20405#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20404#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20403#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20402#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20401#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20400#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20399#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20398#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20397#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20396#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20395#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20394#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20393#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20392#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20391#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20390#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20389#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20388#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20387#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20386#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20385#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20384#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20383#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20382#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20379#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20381#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20380#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20378#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20377#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20376#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20375#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 20374#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20373#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20372#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20371#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20370#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20369#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20368#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20367#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20366#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20365#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20364#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20363#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20362#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20361#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20360#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20359#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20358#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20357#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20356#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20355#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20354#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20353#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20352#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20351#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20350#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20349#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20348#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20347#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20346#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20345#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20344#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20343#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20342#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20341#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20340#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20339#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20338#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20337#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20336#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20335#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20334#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20333#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20332#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20331#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20330#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20329#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20328#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20327#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20326#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20325#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20324#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20323#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20322#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20321#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20320#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20319#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20318#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20317#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20316#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20315#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20314#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20313#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20312#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20311#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20310#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20309#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20308#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20307#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20306#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20303#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20305#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20304#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20302#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20301#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20300#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20299#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 20298#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20297#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20296#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20295#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20294#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20293#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20292#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20291#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20290#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20289#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20288#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20287#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20286#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20285#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20284#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20283#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20282#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20281#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20280#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20279#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20278#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20277#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20276#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20275#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20274#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20273#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20272#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20271#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20270#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20269#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20268#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20267#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20266#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20265#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20264#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20263#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20262#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20261#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20260#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20259#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20258#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20257#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20256#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20255#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20254#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20253#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20252#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20251#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20250#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20249#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20248#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20247#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20246#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20245#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20244#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20243#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20242#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20241#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20240#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20239#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20238#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20237#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20236#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20235#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20234#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20231#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20233#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20232#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20230#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20229#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20228#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20227#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 20226#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20225#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20224#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20223#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20222#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20221#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20220#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20219#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20218#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20217#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20216#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20215#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20214#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20213#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20212#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20211#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20210#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20209#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20208#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20207#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20206#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20205#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20204#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20203#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20202#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20201#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20200#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20199#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20198#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20197#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20196#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20195#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20194#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20193#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20192#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20191#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20190#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20189#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20188#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20187#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20186#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20185#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20184#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20183#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20182#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20181#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20180#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20179#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20178#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20177#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20176#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20175#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20174#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20173#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20172#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20171#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20170#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20169#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20168#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20167#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20084#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20049#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20048#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20046#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20044#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20040#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20163#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20162#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 20161#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20160#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20159#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20158#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20157#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20156#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20155#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20154#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20153#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20152#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20151#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20150#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20149#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20148#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20147#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20146#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20145#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20144#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20143#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20142#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20141#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20140#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20139#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20138#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20137#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20136#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20135#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20134#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20133#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20132#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20131#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20130#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20129#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20128#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20127#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20126#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20125#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 19950#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20124#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20123#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20122#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20121#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20120#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20119#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 20118#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20117#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20116#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20115#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20114#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20113#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20112#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20111#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20110#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20109#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20108#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20107#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20106#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20105#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20104#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20103#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20102#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20101#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20100#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20099#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20098#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20097#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20096#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20095#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20094#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20093#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20092#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20091#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20090#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20089#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20088#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20087#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20086#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 19884#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20085#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20083#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20082#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20081#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20080#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20079#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 20078#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20077#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20076#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20075#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20074#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20073#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20072#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20071#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20070#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20069#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20068#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20067#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20066#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20065#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20064#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20063#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20062#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20061#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20060#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20059#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20058#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20057#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20056#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20055#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20054#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 20053#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20052#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20051#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 20050#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 19820#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 20047#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 20045#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 19883#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 19881#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 19879#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 19877#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 19875#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 19873#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 19871#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 19869#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 19867#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 19865#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 19863#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 19861#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 19859#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 19857#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 19855#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 19853#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 19851#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 19849#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 19847#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 19845#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 19843#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 19841#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 19839#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 19837#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 19835#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 19833#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 19831#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 19829#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 19823#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 19789#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 19822#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 19821#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 19819#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 19818#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 19817#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 19816#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 19815#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 19814#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 19813#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 19812#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 19811#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 19810#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 19809#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 19808#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 19807#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 19806#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 19805#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 19804#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 19803#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 19802#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 19801#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 19800#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 19799#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 19798#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 19797#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 19796#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 19795#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 19764#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 19793#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 19790#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 19788#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 19787#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 19786#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 19785#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 19784#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 19783#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 19782#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 19781#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 19780#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 19779#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 19778#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 19777#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 19776#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 19775#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 19774#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 19773#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 19772#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 19771#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 19770#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 19769#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 19768#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 19767#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 19766#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 19765#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 19763#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 19762#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 19761#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 19760#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 19759#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 19758#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 19757#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 19756#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 19755#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 19754#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 19753#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 19752#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 19751#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 19750#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 19749#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 19748#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 19747#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 19746#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 19745#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 19744#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 19743#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 19742#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 19741#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 19740#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 19739#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 19738#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 19737#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 19736#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 19735#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 19734#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 19733#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 19732#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 19731#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 19730#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 19729#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 19728#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 19727#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 19726#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 19725#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 19724#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 19723#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 19722#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 19721#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 19720#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 19719#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 19718#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 19717#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 19716#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 19715#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 19714#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 19713#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 19712#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 19711#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 19710#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 19709#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 19708#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 19707#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 19706#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 19705#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 19704#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 19700#L12-1 [2024-11-08 18:35:34,792 INFO L747 eck$LassoCheckResult]: Loop: 19700#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 19703#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 19699#L12 assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 19700#L12-1 [2024-11-08 18:35:34,792 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:35:34,793 INFO L85 PathProgramCache]: Analyzing trace with hash 1850558237, now seen corresponding path program 13 times [2024-11-08 18:35:34,793 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 18:35:34,793 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [338909907] [2024-11-08 18:35:34,793 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:35:34,793 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 18:35:34,914 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 18:35:36,043 INFO L134 CoverageAnalysis]: Checked inductivity of 38920 backedges. 18576 proven. 12020 refuted. 0 times theorem prover too weak. 8324 trivial. 0 not checked. [2024-11-08 18:35:36,044 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 18:35:36,044 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [338909907] [2024-11-08 18:35:36,044 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [338909907] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-08 18:35:36,045 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [428363695] [2024-11-08 18:35:36,045 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2024-11-08 18:35:36,045 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-08 18:35:36,045 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 [2024-11-08 18:35:36,047 INFO L229 MonitoredProcess]: Starting monitored process 32 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-08 18:35:36,049 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (32)] Waiting until timeout for monitored process [2024-11-08 18:35:36,268 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 18:35:36,272 INFO L255 TraceCheckSpWp]: Trace formula consists of 1170 conjuncts, 18 conjuncts are in the unsatisfiable core [2024-11-08 18:35:36,280 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-08 18:35:36,995 INFO L134 CoverageAnalysis]: Checked inductivity of 38920 backedges. 18576 proven. 12020 refuted. 0 times theorem prover too weak. 8324 trivial. 0 not checked. [2024-11-08 18:35:36,996 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-08 18:35:37,736 INFO L134 CoverageAnalysis]: Checked inductivity of 38920 backedges. 18576 proven. 12020 refuted. 0 times theorem prover too weak. 8324 trivial. 0 not checked. [2024-11-08 18:35:37,737 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [428363695] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-08 18:35:37,737 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-08 18:35:37,737 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18, 18] total 37 [2024-11-08 18:35:37,737 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [699910214] [2024-11-08 18:35:37,737 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-08 18:35:37,738 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 18:35:37,739 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:35:37,739 INFO L85 PathProgramCache]: Analyzing trace with hash 35920, now seen corresponding path program 10 times [2024-11-08 18:35:37,739 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 18:35:37,739 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [928762096] [2024-11-08 18:35:37,739 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:35:37,739 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 18:35:37,741 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:35:37,741 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 18:35:37,742 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:35:37,742 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 18:35:37,759 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 18:35:37,759 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2024-11-08 18:35:37,760 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=421, Invalid=911, Unknown=0, NotChecked=0, Total=1332 [2024-11-08 18:35:37,760 INFO L87 Difference]: Start difference. First operand 785 states and 809 transitions. cyclomatic complexity: 30 Second operand has 37 states, 37 states have (on average 4.297297297297297) internal successors, (159), 37 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 18:35:40,896 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 18:35:40,896 INFO L93 Difference]: Finished difference Result 1437 states and 1486 transitions. [2024-11-08 18:35:40,896 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1437 states and 1486 transitions. [2024-11-08 18:35:40,904 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2024-11-08 18:35:40,909 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1437 states to 1377 states and 1426 transitions. [2024-11-08 18:35:40,909 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 74 [2024-11-08 18:35:40,909 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 74 [2024-11-08 18:35:40,909 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1377 states and 1426 transitions. [2024-11-08 18:35:40,910 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-08 18:35:40,910 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1377 states and 1426 transitions. [2024-11-08 18:35:40,911 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1377 states and 1426 transitions. [2024-11-08 18:35:40,922 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1377 to 1065. [2024-11-08 18:35:40,924 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1065 states, 1065 states have (on average 1.0272300469483568) internal successors, (1094), 1064 states have internal predecessors, (1094), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 18:35:40,926 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1065 states to 1065 states and 1094 transitions. [2024-11-08 18:35:40,926 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1065 states and 1094 transitions. [2024-11-08 18:35:40,927 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 146 states. [2024-11-08 18:35:40,927 INFO L425 stractBuchiCegarLoop]: Abstraction has 1065 states and 1094 transitions. [2024-11-08 18:35:40,927 INFO L332 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2024-11-08 18:35:40,927 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1065 states and 1094 transitions. [2024-11-08 18:35:40,932 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2024-11-08 18:35:40,932 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 18:35:40,932 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 18:35:40,955 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [210, 210, 210, 190, 20, 1, 1] [2024-11-08 18:35:40,955 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-11-08 18:35:40,956 INFO L745 eck$LassoCheckResult]: Stem: 25550#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true; 25551#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet0#1, main_~i~0#1, main_~range~0#1;havoc main_~i~0#1;havoc main_~range~0#1;havoc main_#t~nondet0#1;main_~i~0#1 := main_#t~nondet0#1;havoc main_#t~nondet0#1;main_~range~0#1 := 20; 25552#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 25620#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 25618#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 25557#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 25558#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 25616#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 25614#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 25547#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 25540#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 25541#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26603#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26602#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26601#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26600#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26599#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26598#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26597#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26596#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26595#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26594#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26593#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26592#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26591#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26590#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26589#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26588#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26587#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26586#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26585#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26584#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26583#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26582#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26581#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26580#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26579#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26578#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26577#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26576#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26575#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26574#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26573#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26572#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26571#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26570#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26569#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26568#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26567#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26566#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26565#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26564#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26563#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26562#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26561#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26560#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26559#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26558#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26557#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26556#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26555#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26554#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26553#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26552#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26551#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26550#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26549#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26548#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26547#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26546#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26545#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26544#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26543#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26542#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26541#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26540#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26539#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26538#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26537#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26534#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26536#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26535#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26533#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26532#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26531#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26530#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 26529#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26528#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26527#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26526#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26525#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26524#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26523#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26522#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26521#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26520#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26519#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26518#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26517#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26516#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26515#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26514#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26513#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26512#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26511#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26510#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26509#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26508#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26507#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26506#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26505#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26504#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26503#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26502#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26501#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26500#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26499#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26498#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26497#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26496#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26495#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26494#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26493#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26492#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26491#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26490#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26489#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26488#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26487#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26486#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26485#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26484#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26483#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26482#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26481#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26480#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26479#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26478#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26477#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26476#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26475#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26474#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26473#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26472#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26471#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26470#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26469#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26468#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26467#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26466#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26465#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26464#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26463#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26462#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26461#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26458#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26460#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26459#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26457#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26456#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26455#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26454#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 26453#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26452#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26451#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26450#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26449#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26448#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26447#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26446#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26445#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26444#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26443#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26442#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26441#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26440#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26439#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26438#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26437#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26436#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26435#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26434#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26433#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26432#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26431#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26430#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26429#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26428#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26427#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26426#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26425#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26424#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26423#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26422#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26421#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26420#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26419#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26418#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26417#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26416#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26415#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26414#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26413#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26412#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26411#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26410#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26409#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26408#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26407#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26406#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26405#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26404#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26403#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26402#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26401#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26400#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26399#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26398#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26397#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26396#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26395#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26394#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26393#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26392#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26391#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26390#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26389#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26386#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26388#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26387#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26385#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26384#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26383#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26382#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 26381#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26380#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26379#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26378#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26377#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26376#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26375#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26374#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26373#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26372#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26371#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26370#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26369#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26368#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26367#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26366#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26365#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26364#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26363#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26362#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26361#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26360#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26359#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26358#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26357#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26356#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26355#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26354#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26353#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26352#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26351#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26350#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26349#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26348#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26347#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26346#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26345#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26344#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26343#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26342#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26341#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26340#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26339#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26338#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26337#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26336#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26335#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26334#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26333#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26332#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26331#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26330#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26329#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26328#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26327#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26326#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26325#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26324#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26323#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26322#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26321#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26318#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26320#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26319#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26317#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26316#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26315#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26314#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 26313#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26312#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26311#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26310#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26309#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26308#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26307#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26306#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26305#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26304#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26303#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26302#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26301#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26300#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26299#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26298#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26297#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26296#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26295#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26294#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26293#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26292#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26291#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26290#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26289#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26288#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26287#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26286#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26285#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26284#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26283#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26282#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26281#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26280#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26279#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26278#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26277#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26276#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26275#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26274#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26273#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26272#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26271#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26270#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26269#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26268#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26267#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26266#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26265#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26264#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26263#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26262#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26261#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26260#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26259#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26258#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26257#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26254#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26256#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26255#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26253#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26252#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26251#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26250#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 26249#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26248#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26247#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26246#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26245#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26244#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26243#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26242#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26241#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26240#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26239#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26238#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26237#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26236#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26235#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26234#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26233#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26232#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26231#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26230#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26229#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26228#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26227#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26226#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26225#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26224#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26223#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26222#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26221#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26220#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26219#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26218#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26217#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26216#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26215#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26214#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26213#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26212#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26211#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26210#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26209#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26208#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26207#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26206#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26205#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26204#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26203#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26202#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26201#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26200#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26199#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26198#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26197#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26194#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26196#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26195#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26193#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26192#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26191#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26190#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 26189#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26188#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26187#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26186#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26185#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26184#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26183#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26182#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26181#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26180#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26179#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26178#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26177#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26176#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26175#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26174#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26173#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26172#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26171#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26170#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26169#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26168#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26167#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26166#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26165#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26164#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26163#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26162#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26161#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26160#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26159#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26158#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26157#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26156#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26155#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26154#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26153#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26152#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26151#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26150#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26149#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26148#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26147#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26146#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26145#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26144#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26143#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26142#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26141#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26138#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26140#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26139#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26137#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26136#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26135#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26134#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 26133#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26132#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26131#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26130#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26129#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26128#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26127#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26126#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26125#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26124#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26123#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26122#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26121#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26120#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26119#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26118#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26117#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26116#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26115#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26114#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26113#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26112#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26111#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26110#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26109#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26108#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26107#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26106#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26105#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26104#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26103#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26102#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26101#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26100#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26099#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26098#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26097#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26096#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26095#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26094#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26093#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26092#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26091#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26090#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26089#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26086#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26088#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26087#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26085#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26084#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26083#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26082#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 26081#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26080#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26079#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26078#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26077#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26076#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26075#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26074#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26073#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26072#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26071#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26070#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26069#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26068#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26067#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26066#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26065#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26064#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26063#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26062#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26061#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26060#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26059#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26058#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26057#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26056#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26055#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26054#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26053#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26052#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26051#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26050#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26049#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26048#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26047#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26046#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26045#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 26044#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26043#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26042#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 26041#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 25895#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 26040#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 26037#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 25982#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 25980#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 25978#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 25976#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 25974#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 25972#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 25970#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 25968#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 25966#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 25964#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 25962#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 25960#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 25958#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 25956#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 25954#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 25952#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 25950#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 25948#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 25946#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 25944#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 25942#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 25940#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 25938#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 25936#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 25934#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 25932#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 25930#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 25928#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 25926#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 25924#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 25922#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 25920#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 25918#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 25916#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 25914#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 25912#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 25910#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 25908#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 25906#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 25904#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 25902#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 25815#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 25899#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 25897#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 25894#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 25892#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 25890#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 25888#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 25886#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 25884#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 25882#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 25880#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 25878#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 25876#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 25874#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 25872#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 25870#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 25868#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 25866#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 25864#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 25862#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 25860#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 25858#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 25856#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 25854#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 25852#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 25850#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 25848#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 25846#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 25844#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 25842#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 25840#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 25838#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 25836#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 25834#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 25832#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 25830#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 25828#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 25826#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 25824#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 25822#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 25743#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 25819#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 25817#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 25814#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 25812#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 25810#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 25808#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 25806#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 25804#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 25802#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 25800#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 25798#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 25796#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 25794#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 25792#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 25790#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 25788#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 25786#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 25784#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 25782#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 25780#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 25778#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 25776#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 25774#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 25772#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 25770#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 25768#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 25766#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 25764#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 25762#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 25760#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 25758#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 25756#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 25754#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 25752#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 25750#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 25679#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 25747#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 25745#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 25742#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 25740#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 25738#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 25736#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 25734#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 25732#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 25730#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 25728#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 25726#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 25724#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 25722#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 25720#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 25718#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 25716#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 25714#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 25712#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 25710#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 25708#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 25706#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 25704#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 25702#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 25700#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 25698#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 25696#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 25694#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 25692#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 25690#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 25688#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 25687#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 25651#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 25686#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 25685#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 25678#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 25677#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 25676#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 25675#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 25674#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 25673#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 25672#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 25671#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 25670#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 25669#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 25668#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 25667#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 25666#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 25665#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 25664#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 25663#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 25662#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 25661#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 25660#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 25659#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 25658#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 25657#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 25656#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 25655#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 25654#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 25622#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 25653#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 25652#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 25650#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 25649#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 25648#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 25647#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 25646#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 25645#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 25644#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 25643#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 25642#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 25641#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 25640#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 25639#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 25638#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 25637#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 25636#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 25635#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 25634#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 25633#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 25632#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 25631#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 25629#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 25627#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 25625#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 25624#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 25621#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 25619#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 25612#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 25613#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 25617#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 25615#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 25555#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 25556#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 25611#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 25610#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 25609#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 25608#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 25607#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 25606#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 25605#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 25604#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 25603#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 25602#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 25601#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 25600#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 25599#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 25598#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 25597#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 25596#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 25595#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 25594#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 25593#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 25592#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 25591#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 25590#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 25589#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 25588#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 25587#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 25586#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 25585#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 25584#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 25583#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 25582#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 25581#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 25580#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 25579#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 25578#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 25577#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 25576#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 25575#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 25574#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 25573#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 25572#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 25571#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 25570#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 25569#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 25568#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 25567#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 25566#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 25565#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 25564#L13 assume !(main_~i~0#1 == main_~range~0#1);main_~i~0#1 := 1 + main_~i~0#1; 25563#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 25562#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 25561#L12 assume !(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 25560#L13 assume main_~i~0#1 == main_~range~0#1;main_~i~0#1 := 0;main_~range~0#1 := main_~range~0#1 - 1; 25554#L12-1 [2024-11-08 18:35:40,957 INFO L747 eck$LassoCheckResult]: Loop: 25554#L12-1 assume 0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1; 25559#L11-1 assume !!(0 <= main_~i~0#1 && main_~i~0#1 <= main_~range~0#1); 25553#L12 assume !!(0 == main_~i~0#1 && main_~i~0#1 == main_~range~0#1); 25554#L12-1 [2024-11-08 18:35:40,957 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:35:40,957 INFO L85 PathProgramCache]: Analyzing trace with hash 803181135, now seen corresponding path program 14 times [2024-11-08 18:35:40,958 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 18:35:40,958 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [11906857] [2024-11-08 18:35:40,958 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:35:40,958 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 18:35:41,184 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:35:41,185 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 18:35:41,366 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:35:41,394 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 18:35:41,396 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:35:41,396 INFO L85 PathProgramCache]: Analyzing trace with hash 35920, now seen corresponding path program 11 times [2024-11-08 18:35:41,396 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 18:35:41,396 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [68311888] [2024-11-08 18:35:41,397 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:35:41,397 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 18:35:41,399 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:35:41,399 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 18:35:41,400 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:35:41,401 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 18:35:41,401 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:35:41,402 INFO L85 PathProgramCache]: Analyzing trace with hash 306392898, now seen corresponding path program 3 times [2024-11-08 18:35:41,402 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 18:35:41,402 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [378128236] [2024-11-08 18:35:41,403 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:35:41,403 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 18:35:41,555 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:35:41,555 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 18:35:41,697 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:35:41,723 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 18:36:32,668 WARN L286 SmtUtils]: Spent 50.47s on a formula simplification. DAG size of input: 2128 DAG size of output: 659 (called from [L 276] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.cfg.transitions.TransFormulaUtils.sequentialComposition) [2024-11-08 18:36:34,807 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:36:34,808 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 18:36:34,949 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:36:35,312 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 08.11 06:36:35 BoogieIcfgContainer [2024-11-08 18:36:35,312 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2024-11-08 18:36:35,313 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2024-11-08 18:36:35,313 INFO L270 PluginConnector]: Initializing Witness Printer... [2024-11-08 18:36:35,313 INFO L274 PluginConnector]: Witness Printer initialized [2024-11-08 18:36:35,313 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 08.11 06:35:09" (3/4) ... [2024-11-08 18:36:35,315 INFO L139 WitnessPrinter]: Generating witness for non-termination counterexample [2024-11-08 18:36:35,534 INFO L149 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/witness.graphml [2024-11-08 18:36:35,535 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2024-11-08 18:36:35,536 INFO L158 Benchmark]: Toolchain (without parser) took 86154.35ms. Allocated memory was 140.5MB in the beginning and 497.0MB in the end (delta: 356.5MB). Free memory was 102.6MB in the beginning and 393.0MB in the end (delta: -290.4MB). Peak memory consumption was 67.5MB. Max. memory is 16.1GB. [2024-11-08 18:36:35,536 INFO L158 Benchmark]: CDTParser took 0.80ms. Allocated memory is still 140.5MB. Free memory was 86.1MB in the beginning and 86.0MB in the end (delta: 144.2kB). There was no memory consumed. Max. memory is 16.1GB. [2024-11-08 18:36:35,536 INFO L158 Benchmark]: CACSL2BoogieTranslator took 233.33ms. Allocated memory is still 140.5MB. Free memory was 102.6MB in the beginning and 91.1MB in the end (delta: 11.5MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. [2024-11-08 18:36:35,536 INFO L158 Benchmark]: Boogie Procedure Inliner took 26.29ms. Allocated memory is still 140.5MB. Free memory was 91.1MB in the beginning and 90.0MB in the end (delta: 1.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2024-11-08 18:36:35,537 INFO L158 Benchmark]: Boogie Preprocessor took 26.48ms. Allocated memory is still 140.5MB. Free memory was 90.0MB in the beginning and 88.5MB in the end (delta: 1.5MB). There was no memory consumed. Max. memory is 16.1GB. [2024-11-08 18:36:35,537 INFO L158 Benchmark]: RCFGBuilder took 264.75ms. Allocated memory is still 140.5MB. Free memory was 88.5MB in the beginning and 79.5MB in the end (delta: 9.0MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. [2024-11-08 18:36:35,537 INFO L158 Benchmark]: BuchiAutomizer took 85376.14ms. Allocated memory was 140.5MB in the beginning and 497.0MB in the end (delta: 356.5MB). Free memory was 79.5MB in the beginning and 418.1MB in the end (delta: -338.6MB). Peak memory consumption was 285.6MB. Max. memory is 16.1GB. [2024-11-08 18:36:35,538 INFO L158 Benchmark]: Witness Printer took 222.35ms. Allocated memory is still 497.0MB. Free memory was 418.1MB in the beginning and 393.0MB in the end (delta: 25.2MB). Peak memory consumption was 25.2MB. Max. memory is 16.1GB. [2024-11-08 18:36:35,539 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.80ms. Allocated memory is still 140.5MB. Free memory was 86.1MB in the beginning and 86.0MB in the end (delta: 144.2kB). There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 233.33ms. Allocated memory is still 140.5MB. Free memory was 102.6MB in the beginning and 91.1MB in the end (delta: 11.5MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 26.29ms. Allocated memory is still 140.5MB. Free memory was 91.1MB in the beginning and 90.0MB in the end (delta: 1.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * Boogie Preprocessor took 26.48ms. Allocated memory is still 140.5MB. Free memory was 90.0MB in the beginning and 88.5MB in the end (delta: 1.5MB). There was no memory consumed. Max. memory is 16.1GB. * RCFGBuilder took 264.75ms. Allocated memory is still 140.5MB. Free memory was 88.5MB in the beginning and 79.5MB in the end (delta: 9.0MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. * BuchiAutomizer took 85376.14ms. Allocated memory was 140.5MB in the beginning and 497.0MB in the end (delta: 356.5MB). Free memory was 79.5MB in the beginning and 418.1MB in the end (delta: -338.6MB). Peak memory consumption was 285.6MB. Max. memory is 16.1GB. * Witness Printer took 222.35ms. Allocated memory is still 497.0MB. Free memory was 418.1MB in the beginning and 393.0MB in the end (delta: 25.2MB). Peak memory consumption was 25.2MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 15 terminating modules (11 trivial, 3 deterministic, 1 nondeterministic) and one nonterminating remainder module.One deterministic module has affine ranking function (((long) -1 * i) + range) and consists of 3 locations. One deterministic module has affine ranking function (((long) -1 * i) + range) and consists of 3 locations. One deterministic module has affine ranking function range and consists of 4 locations. One nondeterministic module has affine ranking function (((long) -1 * i) + range) and consists of 3 locations. 11 modules have a trivial ranking function, the largest among these consists of 50 locations. The remainder module has 1065 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 85.0s and 15 iterations. TraceHistogramMax:210. Analysis of lassos took 72.1s. Construction of modules took 3.3s. Büchi inclusion checks took 9.2s. Highest rank in rank-based complementation 3. Minimization of det autom 1. Minimization of nondet autom 14. Automata minimization 0.1s AutomataMinimizationTime, 15 MinimizatonAttempts, 3142 StatesRemovedByMinimization, 12 NontrivialMinimizations. Non-live state removal took 0.1s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [3, 0, 1, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 4/4 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 281 SdHoareTripleChecker+Valid, 4.0s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 275 mSDsluCounter, 149 SdHoareTripleChecker+Invalid, 3.4s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 77 mSDsCounter, 434 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 5030 IncrementalHoareTripleChecker+Invalid, 5464 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 434 mSolverCounterUnsat, 72 mSDtfsCounter, 5030 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI0 SFLT3 conc4 concLT0 SILN6 SILU0 SILI0 SILT1 lasso0 LassoPreprocessingBenchmarks: Lassos: inital17 mio100 ax167 hnf100 lsp59 ukn100 mio100 lsp100 div100 bol100 ite100 ukn100 eq166 hnf95 smp71 dnf100 smp100 tf110 neg100 sie109 LassoTerminationAnalysisBenchmarks: ConstraintsSatisfiability: unsat Degree: 0 Time: 30ms VariablesStem: 1 VariablesLoop: 0 DisjunctsStem: 1 DisjunctsLoop: 1 SupportingInvariants: 2 MotzkinApplications: 6 LassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 4 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 4 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.6s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 11]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L6] int i; [L7] int range; [L8] i = __VERIFIER_nondet_int() [L9] range = 20 VAL [range=20] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=20, range=20] [L11] COND TRUE 0 <= i && i <= range VAL [i=20, range=20] [L12] COND TRUE !(0 == i && i == range) VAL [i=20, range=20] [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 VAL [i=0, range=19] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=0, range=19] [L11] COND TRUE 0 <= i && i <= range VAL [i=0, range=19] [L12] COND TRUE !(0 == i && i == range) VAL [i=0, range=19] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=1, range=19] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=1, range=19] [L11] COND TRUE 0 <= i && i <= range VAL [i=1, range=19] [L12] COND TRUE !(0 == i && i == range) VAL [i=1, range=19] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=2, range=19] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=2, range=19] [L11] COND TRUE 0 <= i && i <= range VAL [i=2, range=19] [L12] COND TRUE !(0 == i && i == range) VAL [i=2, range=19] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=3, range=19] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=3, range=19] [L11] COND TRUE 0 <= i && i <= range VAL [i=3, range=19] [L12] COND TRUE !(0 == i && i == range) VAL [i=3, range=19] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=4, range=19] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=4, range=19] [L11] COND TRUE 0 <= i && i <= range VAL [i=4, range=19] [L12] COND TRUE !(0 == i && i == range) VAL [i=4, range=19] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=5, range=19] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=5, range=19] [L11] COND TRUE 0 <= i && i <= range VAL [i=5, range=19] [L12] COND TRUE !(0 == i && i == range) VAL [i=5, range=19] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=6, range=19] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=6, range=19] [L11] COND TRUE 0 <= i && i <= range VAL [i=6, range=19] [L12] COND TRUE !(0 == i && i == range) VAL [i=6, range=19] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=7, range=19] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=7, range=19] [L11] COND TRUE 0 <= i && i <= range VAL [i=7, range=19] [L12] COND TRUE !(0 == i && i == range) VAL [i=7, range=19] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=8, range=19] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=8, range=19] [L11] COND TRUE 0 <= i && i <= range VAL [i=8, range=19] [L12] COND TRUE !(0 == i && i == range) VAL [i=8, range=19] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=9, range=19] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=9, range=19] [L11] COND TRUE 0 <= i && i <= range VAL [i=9, range=19] [L12] COND TRUE !(0 == i && i == range) VAL [i=9, range=19] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=10, range=19] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=10, range=19] [L11] COND TRUE 0 <= i && i <= range VAL [i=10, range=19] [L12] COND TRUE !(0 == i && i == range) VAL [i=10, range=19] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=11, range=19] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=11, range=19] [L11] COND TRUE 0 <= i && i <= range VAL [i=11, range=19] [L12] COND TRUE !(0 == i && i == range) VAL [i=11, range=19] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=12, range=19] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=12, range=19] [L11] COND TRUE 0 <= i && i <= range VAL [i=12, range=19] [L12] COND TRUE !(0 == i && i == range) VAL [i=12, range=19] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=13, range=19] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=13, range=19] [L11] COND TRUE 0 <= i && i <= range VAL [i=13, range=19] [L12] COND TRUE !(0 == i && i == range) VAL [i=13, range=19] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=14, range=19] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=14, range=19] [L11] COND TRUE 0 <= i && i <= range VAL [i=14, range=19] [L12] COND TRUE !(0 == i && i == range) VAL [i=14, range=19] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=15, range=19] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=15, range=19] [L11] COND TRUE 0 <= i && i <= range VAL [i=15, range=19] [L12] COND TRUE !(0 == i && i == range) VAL [i=15, range=19] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=16, range=19] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=16, range=19] [L11] COND TRUE 0 <= i && i <= range VAL [i=16, range=19] [L12] COND TRUE !(0 == i && i == range) VAL [i=16, range=19] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=17, range=19] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=17, range=19] [L11] COND TRUE 0 <= i && i <= range VAL [i=17, range=19] [L12] COND TRUE !(0 == i && i == range) VAL [i=17, range=19] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=18, range=19] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=18, range=19] [L11] COND TRUE 0 <= i && i <= range VAL [i=18, range=19] [L12] COND TRUE !(0 == i && i == range) VAL [i=18, range=19] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=19, range=19] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=19, range=19] [L11] COND TRUE 0 <= i && i <= range VAL [i=19, range=19] [L12] COND TRUE !(0 == i && i == range) VAL [i=19, range=19] [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 VAL [i=0, range=18] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=0, range=18] [L11] COND TRUE 0 <= i && i <= range VAL [i=0, range=18] [L12] COND TRUE !(0 == i && i == range) VAL [i=0, range=18] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=1, range=18] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=1, range=18] [L11] COND TRUE 0 <= i && i <= range VAL [i=1, range=18] [L12] COND TRUE !(0 == i && i == range) VAL [i=1, range=18] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=2, range=18] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=2, range=18] [L11] COND TRUE 0 <= i && i <= range VAL [i=2, range=18] [L12] COND TRUE !(0 == i && i == range) VAL [i=2, range=18] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=3, range=18] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=3, range=18] [L11] COND TRUE 0 <= i && i <= range VAL [i=3, range=18] [L12] COND TRUE !(0 == i && i == range) VAL [i=3, range=18] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=4, range=18] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=4, range=18] [L11] COND TRUE 0 <= i && i <= range VAL [i=4, range=18] [L12] COND TRUE !(0 == i && i == range) VAL [i=4, range=18] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=5, range=18] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=5, range=18] [L11] COND TRUE 0 <= i && i <= range VAL [i=5, range=18] [L12] COND TRUE !(0 == i && i == range) VAL [i=5, range=18] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=6, range=18] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=6, range=18] [L11] COND TRUE 0 <= i && i <= range VAL [i=6, range=18] [L12] COND TRUE !(0 == i && i == range) VAL [i=6, range=18] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=7, range=18] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=7, range=18] [L11] COND TRUE 0 <= i && i <= range VAL [i=7, range=18] [L12] COND TRUE !(0 == i && i == range) VAL [i=7, range=18] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=8, range=18] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=8, range=18] [L11] COND TRUE 0 <= i && i <= range VAL [i=8, range=18] [L12] COND TRUE !(0 == i && i == range) VAL [i=8, range=18] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=9, range=18] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=9, range=18] [L11] COND TRUE 0 <= i && i <= range VAL [i=9, range=18] [L12] COND TRUE !(0 == i && i == range) VAL [i=9, range=18] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=10, range=18] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=10, range=18] [L11] COND TRUE 0 <= i && i <= range VAL [i=10, range=18] [L12] COND TRUE !(0 == i && i == range) VAL [i=10, range=18] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=11, range=18] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=11, range=18] [L11] COND TRUE 0 <= i && i <= range VAL [i=11, range=18] [L12] COND TRUE !(0 == i && i == range) VAL [i=11, range=18] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=12, range=18] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=12, range=18] [L11] COND TRUE 0 <= i && i <= range VAL [i=12, range=18] [L12] COND TRUE !(0 == i && i == range) VAL [i=12, range=18] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=13, range=18] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=13, range=18] [L11] COND TRUE 0 <= i && i <= range VAL [i=13, range=18] [L12] COND TRUE !(0 == i && i == range) VAL [i=13, range=18] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=14, range=18] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=14, range=18] [L11] COND TRUE 0 <= i && i <= range VAL [i=14, range=18] [L12] COND TRUE !(0 == i && i == range) VAL [i=14, range=18] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=15, range=18] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=15, range=18] [L11] COND TRUE 0 <= i && i <= range VAL [i=15, range=18] [L12] COND TRUE !(0 == i && i == range) VAL [i=15, range=18] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=16, range=18] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=16, range=18] [L11] COND TRUE 0 <= i && i <= range VAL [i=16, range=18] [L12] COND TRUE !(0 == i && i == range) VAL [i=16, range=18] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=17, range=18] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=17, range=18] [L11] COND TRUE 0 <= i && i <= range VAL [i=17, range=18] [L12] COND TRUE !(0 == i && i == range) VAL [i=17, range=18] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=18, range=18] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=18, range=18] [L11] COND TRUE 0 <= i && i <= range VAL [i=18, range=18] [L12] COND TRUE !(0 == i && i == range) VAL [i=18, range=18] [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 VAL [i=0, range=17] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=0, range=17] [L11] COND TRUE 0 <= i && i <= range VAL [i=0, range=17] [L12] COND TRUE !(0 == i && i == range) VAL [i=0, range=17] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=1, range=17] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=1, range=17] [L11] COND TRUE 0 <= i && i <= range VAL [i=1, range=17] [L12] COND TRUE !(0 == i && i == range) VAL [i=1, range=17] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=2, range=17] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=2, range=17] [L11] COND TRUE 0 <= i && i <= range VAL [i=2, range=17] [L12] COND TRUE !(0 == i && i == range) VAL [i=2, range=17] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=3, range=17] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=3, range=17] [L11] COND TRUE 0 <= i && i <= range VAL [i=3, range=17] [L12] COND TRUE !(0 == i && i == range) VAL [i=3, range=17] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=4, range=17] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=4, range=17] [L11] COND TRUE 0 <= i && i <= range VAL [i=4, range=17] [L12] COND TRUE !(0 == i && i == range) VAL [i=4, range=17] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=5, range=17] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=5, range=17] [L11] COND TRUE 0 <= i && i <= range VAL [i=5, range=17] [L12] COND TRUE !(0 == i && i == range) VAL [i=5, range=17] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=6, range=17] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=6, range=17] [L11] COND TRUE 0 <= i && i <= range VAL [i=6, range=17] [L12] COND TRUE !(0 == i && i == range) VAL [i=6, range=17] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=7, range=17] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=7, range=17] [L11] COND TRUE 0 <= i && i <= range VAL [i=7, range=17] [L12] COND TRUE !(0 == i && i == range) VAL [i=7, range=17] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=8, range=17] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=8, range=17] [L11] COND TRUE 0 <= i && i <= range VAL [i=8, range=17] [L12] COND TRUE !(0 == i && i == range) VAL [i=8, range=17] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=9, range=17] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=9, range=17] [L11] COND TRUE 0 <= i && i <= range VAL [i=9, range=17] [L12] COND TRUE !(0 == i && i == range) VAL [i=9, range=17] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=10, range=17] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=10, range=17] [L11] COND TRUE 0 <= i && i <= range VAL [i=10, range=17] [L12] COND TRUE !(0 == i && i == range) VAL [i=10, range=17] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=11, range=17] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=11, range=17] [L11] COND TRUE 0 <= i && i <= range VAL [i=11, range=17] [L12] COND TRUE !(0 == i && i == range) VAL [i=11, range=17] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=12, range=17] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=12, range=17] [L11] COND TRUE 0 <= i && i <= range VAL [i=12, range=17] [L12] COND TRUE !(0 == i && i == range) VAL [i=12, range=17] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=13, range=17] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=13, range=17] [L11] COND TRUE 0 <= i && i <= range VAL [i=13, range=17] [L12] COND TRUE !(0 == i && i == range) VAL [i=13, range=17] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=14, range=17] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=14, range=17] [L11] COND TRUE 0 <= i && i <= range VAL [i=14, range=17] [L12] COND TRUE !(0 == i && i == range) VAL [i=14, range=17] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=15, range=17] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=15, range=17] [L11] COND TRUE 0 <= i && i <= range VAL [i=15, range=17] [L12] COND TRUE !(0 == i && i == range) VAL [i=15, range=17] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=16, range=17] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=16, range=17] [L11] COND TRUE 0 <= i && i <= range VAL [i=16, range=17] [L12] COND TRUE !(0 == i && i == range) VAL [i=16, range=17] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=17, range=17] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=17, range=17] [L11] COND TRUE 0 <= i && i <= range VAL [i=17, range=17] [L12] COND TRUE !(0 == i && i == range) VAL [i=17, range=17] [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 VAL [i=0, range=16] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=0, range=16] [L11] COND TRUE 0 <= i && i <= range VAL [i=0, range=16] [L12] COND TRUE !(0 == i && i == range) VAL [i=0, range=16] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=1, range=16] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=1, range=16] [L11] COND TRUE 0 <= i && i <= range VAL [i=1, range=16] [L12] COND TRUE !(0 == i && i == range) VAL [i=1, range=16] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=2, range=16] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=2, range=16] [L11] COND TRUE 0 <= i && i <= range VAL [i=2, range=16] [L12] COND TRUE !(0 == i && i == range) VAL [i=2, range=16] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=3, range=16] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=3, range=16] [L11] COND TRUE 0 <= i && i <= range VAL [i=3, range=16] [L12] COND TRUE !(0 == i && i == range) VAL [i=3, range=16] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=4, range=16] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=4, range=16] [L11] COND TRUE 0 <= i && i <= range VAL [i=4, range=16] [L12] COND TRUE !(0 == i && i == range) VAL [i=4, range=16] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=5, range=16] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=5, range=16] [L11] COND TRUE 0 <= i && i <= range VAL [i=5, range=16] [L12] COND TRUE !(0 == i && i == range) VAL [i=5, range=16] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=6, range=16] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=6, range=16] [L11] COND TRUE 0 <= i && i <= range VAL [i=6, range=16] [L12] COND TRUE !(0 == i && i == range) VAL [i=6, range=16] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=7, range=16] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=7, range=16] [L11] COND TRUE 0 <= i && i <= range VAL [i=7, range=16] [L12] COND TRUE !(0 == i && i == range) VAL [i=7, range=16] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=8, range=16] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=8, range=16] [L11] COND TRUE 0 <= i && i <= range VAL [i=8, range=16] [L12] COND TRUE !(0 == i && i == range) VAL [i=8, range=16] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=9, range=16] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=9, range=16] [L11] COND TRUE 0 <= i && i <= range VAL [i=9, range=16] [L12] COND TRUE !(0 == i && i == range) VAL [i=9, range=16] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=10, range=16] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=10, range=16] [L11] COND TRUE 0 <= i && i <= range VAL [i=10, range=16] [L12] COND TRUE !(0 == i && i == range) VAL [i=10, range=16] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=11, range=16] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=11, range=16] [L11] COND TRUE 0 <= i && i <= range VAL [i=11, range=16] [L12] COND TRUE !(0 == i && i == range) VAL [i=11, range=16] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=12, range=16] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=12, range=16] [L11] COND TRUE 0 <= i && i <= range VAL [i=12, range=16] [L12] COND TRUE !(0 == i && i == range) VAL [i=12, range=16] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=13, range=16] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=13, range=16] [L11] COND TRUE 0 <= i && i <= range VAL [i=13, range=16] [L12] COND TRUE !(0 == i && i == range) VAL [i=13, range=16] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=14, range=16] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=14, range=16] [L11] COND TRUE 0 <= i && i <= range VAL [i=14, range=16] [L12] COND TRUE !(0 == i && i == range) VAL [i=14, range=16] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=15, range=16] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=15, range=16] [L11] COND TRUE 0 <= i && i <= range VAL [i=15, range=16] [L12] COND TRUE !(0 == i && i == range) VAL [i=15, range=16] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=16, range=16] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=16, range=16] [L11] COND TRUE 0 <= i && i <= range VAL [i=16, range=16] [L12] COND TRUE !(0 == i && i == range) VAL [i=16, range=16] [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 VAL [i=0, range=15] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=0, range=15] [L11] COND TRUE 0 <= i && i <= range VAL [i=0, range=15] [L12] COND TRUE !(0 == i && i == range) VAL [i=0, range=15] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=1, range=15] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=1, range=15] [L11] COND TRUE 0 <= i && i <= range VAL [i=1, range=15] [L12] COND TRUE !(0 == i && i == range) VAL [i=1, range=15] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=2, range=15] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=2, range=15] [L11] COND TRUE 0 <= i && i <= range VAL [i=2, range=15] [L12] COND TRUE !(0 == i && i == range) VAL [i=2, range=15] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=3, range=15] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=3, range=15] [L11] COND TRUE 0 <= i && i <= range VAL [i=3, range=15] [L12] COND TRUE !(0 == i && i == range) VAL [i=3, range=15] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=4, range=15] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=4, range=15] [L11] COND TRUE 0 <= i && i <= range VAL [i=4, range=15] [L12] COND TRUE !(0 == i && i == range) VAL [i=4, range=15] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=5, range=15] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=5, range=15] [L11] COND TRUE 0 <= i && i <= range VAL [i=5, range=15] [L12] COND TRUE !(0 == i && i == range) VAL [i=5, range=15] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=6, range=15] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=6, range=15] [L11] COND TRUE 0 <= i && i <= range VAL [i=6, range=15] [L12] COND TRUE !(0 == i && i == range) VAL [i=6, range=15] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=7, range=15] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=7, range=15] [L11] COND TRUE 0 <= i && i <= range VAL [i=7, range=15] [L12] COND TRUE !(0 == i && i == range) VAL [i=7, range=15] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=8, range=15] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=8, range=15] [L11] COND TRUE 0 <= i && i <= range VAL [i=8, range=15] [L12] COND TRUE !(0 == i && i == range) VAL [i=8, range=15] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=9, range=15] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=9, range=15] [L11] COND TRUE 0 <= i && i <= range VAL [i=9, range=15] [L12] COND TRUE !(0 == i && i == range) VAL [i=9, range=15] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=10, range=15] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=10, range=15] [L11] COND TRUE 0 <= i && i <= range VAL [i=10, range=15] [L12] COND TRUE !(0 == i && i == range) VAL [i=10, range=15] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=11, range=15] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=11, range=15] [L11] COND TRUE 0 <= i && i <= range VAL [i=11, range=15] [L12] COND TRUE !(0 == i && i == range) VAL [i=11, range=15] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=12, range=15] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=12, range=15] [L11] COND TRUE 0 <= i && i <= range VAL [i=12, range=15] [L12] COND TRUE !(0 == i && i == range) VAL [i=12, range=15] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=13, range=15] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=13, range=15] [L11] COND TRUE 0 <= i && i <= range VAL [i=13, range=15] [L12] COND TRUE !(0 == i && i == range) VAL [i=13, range=15] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=14, range=15] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=14, range=15] [L11] COND TRUE 0 <= i && i <= range VAL [i=14, range=15] [L12] COND TRUE !(0 == i && i == range) VAL [i=14, range=15] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=15, range=15] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=15, range=15] [L11] COND TRUE 0 <= i && i <= range VAL [i=15, range=15] [L12] COND TRUE !(0 == i && i == range) VAL [i=15, range=15] [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 VAL [i=0, range=14] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=0, range=14] [L11] COND TRUE 0 <= i && i <= range VAL [i=0, range=14] [L12] COND TRUE !(0 == i && i == range) VAL [i=0, range=14] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=1, range=14] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=1, range=14] [L11] COND TRUE 0 <= i && i <= range VAL [i=1, range=14] [L12] COND TRUE !(0 == i && i == range) VAL [i=1, range=14] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=2, range=14] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=2, range=14] [L11] COND TRUE 0 <= i && i <= range VAL [i=2, range=14] [L12] COND TRUE !(0 == i && i == range) VAL [i=2, range=14] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=3, range=14] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=3, range=14] [L11] COND TRUE 0 <= i && i <= range VAL [i=3, range=14] [L12] COND TRUE !(0 == i && i == range) VAL [i=3, range=14] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=4, range=14] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=4, range=14] [L11] COND TRUE 0 <= i && i <= range VAL [i=4, range=14] [L12] COND TRUE !(0 == i && i == range) VAL [i=4, range=14] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=5, range=14] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=5, range=14] [L11] COND TRUE 0 <= i && i <= range VAL [i=5, range=14] [L12] COND TRUE !(0 == i && i == range) VAL [i=5, range=14] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=6, range=14] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=6, range=14] [L11] COND TRUE 0 <= i && i <= range VAL [i=6, range=14] [L12] COND TRUE !(0 == i && i == range) VAL [i=6, range=14] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=7, range=14] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=7, range=14] [L11] COND TRUE 0 <= i && i <= range VAL [i=7, range=14] [L12] COND TRUE !(0 == i && i == range) VAL [i=7, range=14] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=8, range=14] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=8, range=14] [L11] COND TRUE 0 <= i && i <= range VAL [i=8, range=14] [L12] COND TRUE !(0 == i && i == range) VAL [i=8, range=14] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=9, range=14] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=9, range=14] [L11] COND TRUE 0 <= i && i <= range VAL [i=9, range=14] [L12] COND TRUE !(0 == i && i == range) VAL [i=9, range=14] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=10, range=14] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=10, range=14] [L11] COND TRUE 0 <= i && i <= range VAL [i=10, range=14] [L12] COND TRUE !(0 == i && i == range) VAL [i=10, range=14] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=11, range=14] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=11, range=14] [L11] COND TRUE 0 <= i && i <= range VAL [i=11, range=14] [L12] COND TRUE !(0 == i && i == range) VAL [i=11, range=14] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=12, range=14] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=12, range=14] [L11] COND TRUE 0 <= i && i <= range VAL [i=12, range=14] [L12] COND TRUE !(0 == i && i == range) VAL [i=12, range=14] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=13, range=14] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=13, range=14] [L11] COND TRUE 0 <= i && i <= range VAL [i=13, range=14] [L12] COND TRUE !(0 == i && i == range) VAL [i=13, range=14] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=14, range=14] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=14, range=14] [L11] COND TRUE 0 <= i && i <= range VAL [i=14, range=14] [L12] COND TRUE !(0 == i && i == range) VAL [i=14, range=14] [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 VAL [i=0, range=13] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=0, range=13] [L11] COND TRUE 0 <= i && i <= range VAL [i=0, range=13] [L12] COND TRUE !(0 == i && i == range) VAL [i=0, range=13] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=1, range=13] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=1, range=13] [L11] COND TRUE 0 <= i && i <= range VAL [i=1, range=13] [L12] COND TRUE !(0 == i && i == range) VAL [i=1, range=13] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=2, range=13] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=2, range=13] [L11] COND TRUE 0 <= i && i <= range VAL [i=2, range=13] [L12] COND TRUE !(0 == i && i == range) VAL [i=2, range=13] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=3, range=13] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=3, range=13] [L11] COND TRUE 0 <= i && i <= range VAL [i=3, range=13] [L12] COND TRUE !(0 == i && i == range) VAL [i=3, range=13] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=4, range=13] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=4, range=13] [L11] COND TRUE 0 <= i && i <= range VAL [i=4, range=13] [L12] COND TRUE !(0 == i && i == range) VAL [i=4, range=13] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=5, range=13] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=5, range=13] [L11] COND TRUE 0 <= i && i <= range VAL [i=5, range=13] [L12] COND TRUE !(0 == i && i == range) VAL [i=5, range=13] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=6, range=13] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=6, range=13] [L11] COND TRUE 0 <= i && i <= range VAL [i=6, range=13] [L12] COND TRUE !(0 == i && i == range) VAL [i=6, range=13] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=7, range=13] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=7, range=13] [L11] COND TRUE 0 <= i && i <= range VAL [i=7, range=13] [L12] COND TRUE !(0 == i && i == range) VAL [i=7, range=13] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=8, range=13] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=8, range=13] [L11] COND TRUE 0 <= i && i <= range VAL [i=8, range=13] [L12] COND TRUE !(0 == i && i == range) VAL [i=8, range=13] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=9, range=13] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=9, range=13] [L11] COND TRUE 0 <= i && i <= range VAL [i=9, range=13] [L12] COND TRUE !(0 == i && i == range) VAL [i=9, range=13] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=10, range=13] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=10, range=13] [L11] COND TRUE 0 <= i && i <= range VAL [i=10, range=13] [L12] COND TRUE !(0 == i && i == range) VAL [i=10, range=13] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=11, range=13] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=11, range=13] [L11] COND TRUE 0 <= i && i <= range VAL [i=11, range=13] [L12] COND TRUE !(0 == i && i == range) VAL [i=11, range=13] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=12, range=13] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=12, range=13] [L11] COND TRUE 0 <= i && i <= range VAL [i=12, range=13] [L12] COND TRUE !(0 == i && i == range) VAL [i=12, range=13] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=13, range=13] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=13, range=13] [L11] COND TRUE 0 <= i && i <= range VAL [i=13, range=13] [L12] COND TRUE !(0 == i && i == range) VAL [i=13, range=13] [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 VAL [i=0, range=12] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=0, range=12] [L11] COND TRUE 0 <= i && i <= range VAL [i=0, range=12] [L12] COND TRUE !(0 == i && i == range) VAL [i=0, range=12] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=1, range=12] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=1, range=12] [L11] COND TRUE 0 <= i && i <= range VAL [i=1, range=12] [L12] COND TRUE !(0 == i && i == range) VAL [i=1, range=12] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=2, range=12] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=2, range=12] [L11] COND TRUE 0 <= i && i <= range VAL [i=2, range=12] [L12] COND TRUE !(0 == i && i == range) VAL [i=2, range=12] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=3, range=12] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=3, range=12] [L11] COND TRUE 0 <= i && i <= range VAL [i=3, range=12] [L12] COND TRUE !(0 == i && i == range) VAL [i=3, range=12] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=4, range=12] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=4, range=12] [L11] COND TRUE 0 <= i && i <= range VAL [i=4, range=12] [L12] COND TRUE !(0 == i && i == range) VAL [i=4, range=12] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=5, range=12] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=5, range=12] [L11] COND TRUE 0 <= i && i <= range VAL [i=5, range=12] [L12] COND TRUE !(0 == i && i == range) VAL [i=5, range=12] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=6, range=12] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=6, range=12] [L11] COND TRUE 0 <= i && i <= range VAL [i=6, range=12] [L12] COND TRUE !(0 == i && i == range) VAL [i=6, range=12] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=7, range=12] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=7, range=12] [L11] COND TRUE 0 <= i && i <= range VAL [i=7, range=12] [L12] COND TRUE !(0 == i && i == range) VAL [i=7, range=12] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=8, range=12] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=8, range=12] [L11] COND TRUE 0 <= i && i <= range VAL [i=8, range=12] [L12] COND TRUE !(0 == i && i == range) VAL [i=8, range=12] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=9, range=12] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=9, range=12] [L11] COND TRUE 0 <= i && i <= range VAL [i=9, range=12] [L12] COND TRUE !(0 == i && i == range) VAL [i=9, range=12] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=10, range=12] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=10, range=12] [L11] COND TRUE 0 <= i && i <= range VAL [i=10, range=12] [L12] COND TRUE !(0 == i && i == range) VAL [i=10, range=12] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=11, range=12] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=11, range=12] [L11] COND TRUE 0 <= i && i <= range VAL [i=11, range=12] [L12] COND TRUE !(0 == i && i == range) VAL [i=11, range=12] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=12, range=12] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=12, range=12] [L11] COND TRUE 0 <= i && i <= range VAL [i=12, range=12] [L12] COND TRUE !(0 == i && i == range) VAL [i=12, range=12] [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 VAL [i=0, range=11] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=0, range=11] [L11] COND TRUE 0 <= i && i <= range VAL [i=0, range=11] [L12] COND TRUE !(0 == i && i == range) VAL [i=0, range=11] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=1, range=11] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=1, range=11] [L11] COND TRUE 0 <= i && i <= range VAL [i=1, range=11] [L12] COND TRUE !(0 == i && i == range) VAL [i=1, range=11] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=2, range=11] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=2, range=11] [L11] COND TRUE 0 <= i && i <= range VAL [i=2, range=11] [L12] COND TRUE !(0 == i && i == range) VAL [i=2, range=11] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=3, range=11] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=3, range=11] [L11] COND TRUE 0 <= i && i <= range VAL [i=3, range=11] [L12] COND TRUE !(0 == i && i == range) VAL [i=3, range=11] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=4, range=11] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=4, range=11] [L11] COND TRUE 0 <= i && i <= range VAL [i=4, range=11] [L12] COND TRUE !(0 == i && i == range) VAL [i=4, range=11] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=5, range=11] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=5, range=11] [L11] COND TRUE 0 <= i && i <= range VAL [i=5, range=11] [L12] COND TRUE !(0 == i && i == range) VAL [i=5, range=11] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=6, range=11] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=6, range=11] [L11] COND TRUE 0 <= i && i <= range VAL [i=6, range=11] [L12] COND TRUE !(0 == i && i == range) VAL [i=6, range=11] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=7, range=11] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=7, range=11] [L11] COND TRUE 0 <= i && i <= range VAL [i=7, range=11] [L12] COND TRUE !(0 == i && i == range) VAL [i=7, range=11] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=8, range=11] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=8, range=11] [L11] COND TRUE 0 <= i && i <= range VAL [i=8, range=11] [L12] COND TRUE !(0 == i && i == range) VAL [i=8, range=11] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=9, range=11] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=9, range=11] [L11] COND TRUE 0 <= i && i <= range VAL [i=9, range=11] [L12] COND TRUE !(0 == i && i == range) VAL [i=9, range=11] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=10, range=11] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=10, range=11] [L11] COND TRUE 0 <= i && i <= range VAL [i=10, range=11] [L12] COND TRUE !(0 == i && i == range) VAL [i=10, range=11] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=11, range=11] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=11, range=11] [L11] COND TRUE 0 <= i && i <= range VAL [i=11, range=11] [L12] COND TRUE !(0 == i && i == range) VAL [i=11, range=11] [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 VAL [i=0, range=10] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=0, range=10] [L11] COND TRUE 0 <= i && i <= range VAL [i=0, range=10] [L12] COND TRUE !(0 == i && i == range) VAL [i=0, range=10] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=1, range=10] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=1, range=10] [L11] COND TRUE 0 <= i && i <= range VAL [i=1, range=10] [L12] COND TRUE !(0 == i && i == range) VAL [i=1, range=10] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=2, range=10] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=2, range=10] [L11] COND TRUE 0 <= i && i <= range VAL [i=2, range=10] [L12] COND TRUE !(0 == i && i == range) VAL [i=2, range=10] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=3, range=10] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=3, range=10] [L11] COND TRUE 0 <= i && i <= range VAL [i=3, range=10] [L12] COND TRUE !(0 == i && i == range) VAL [i=3, range=10] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=4, range=10] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=4, range=10] [L11] COND TRUE 0 <= i && i <= range VAL [i=4, range=10] [L12] COND TRUE !(0 == i && i == range) VAL [i=4, range=10] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=5, range=10] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=5, range=10] [L11] COND TRUE 0 <= i && i <= range VAL [i=5, range=10] [L12] COND TRUE !(0 == i && i == range) VAL [i=5, range=10] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=6, range=10] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=6, range=10] [L11] COND TRUE 0 <= i && i <= range VAL [i=6, range=10] [L12] COND TRUE !(0 == i && i == range) VAL [i=6, range=10] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=7, range=10] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=7, range=10] [L11] COND TRUE 0 <= i && i <= range VAL [i=7, range=10] [L12] COND TRUE !(0 == i && i == range) VAL [i=7, range=10] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=8, range=10] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=8, range=10] [L11] COND TRUE 0 <= i && i <= range VAL [i=8, range=10] [L12] COND TRUE !(0 == i && i == range) VAL [i=8, range=10] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=9, range=10] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=9, range=10] [L11] COND TRUE 0 <= i && i <= range VAL [i=9, range=10] [L12] COND TRUE !(0 == i && i == range) VAL [i=9, range=10] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=10, range=10] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=10, range=10] [L11] COND TRUE 0 <= i && i <= range VAL [i=10, range=10] [L12] COND TRUE !(0 == i && i == range) VAL [i=10, range=10] [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 VAL [i=0, range=9] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=0, range=9] [L11] COND TRUE 0 <= i && i <= range VAL [i=0, range=9] [L12] COND TRUE !(0 == i && i == range) VAL [i=0, range=9] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=1, range=9] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=1, range=9] [L11] COND TRUE 0 <= i && i <= range VAL [i=1, range=9] [L12] COND TRUE !(0 == i && i == range) VAL [i=1, range=9] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=2, range=9] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=2, range=9] [L11] COND TRUE 0 <= i && i <= range VAL [i=2, range=9] [L12] COND TRUE !(0 == i && i == range) VAL [i=2, range=9] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=3, range=9] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=3, range=9] [L11] COND TRUE 0 <= i && i <= range VAL [i=3, range=9] [L12] COND TRUE !(0 == i && i == range) VAL [i=3, range=9] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=4, range=9] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=4, range=9] [L11] COND TRUE 0 <= i && i <= range VAL [i=4, range=9] [L12] COND TRUE !(0 == i && i == range) VAL [i=4, range=9] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=5, range=9] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=5, range=9] [L11] COND TRUE 0 <= i && i <= range VAL [i=5, range=9] [L12] COND TRUE !(0 == i && i == range) VAL [i=5, range=9] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=6, range=9] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=6, range=9] [L11] COND TRUE 0 <= i && i <= range VAL [i=6, range=9] [L12] COND TRUE !(0 == i && i == range) VAL [i=6, range=9] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=7, range=9] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=7, range=9] [L11] COND TRUE 0 <= i && i <= range VAL [i=7, range=9] [L12] COND TRUE !(0 == i && i == range) VAL [i=7, range=9] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=8, range=9] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=8, range=9] [L11] COND TRUE 0 <= i && i <= range VAL [i=8, range=9] [L12] COND TRUE !(0 == i && i == range) VAL [i=8, range=9] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=9, range=9] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=9, range=9] [L11] COND TRUE 0 <= i && i <= range VAL [i=9, range=9] [L12] COND TRUE !(0 == i && i == range) VAL [i=9, range=9] [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 VAL [i=0, range=8] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=0, range=8] [L11] COND TRUE 0 <= i && i <= range VAL [i=0, range=8] [L12] COND TRUE !(0 == i && i == range) VAL [i=0, range=8] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=1, range=8] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=1, range=8] [L11] COND TRUE 0 <= i && i <= range VAL [i=1, range=8] [L12] COND TRUE !(0 == i && i == range) VAL [i=1, range=8] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=2, range=8] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=2, range=8] [L11] COND TRUE 0 <= i && i <= range VAL [i=2, range=8] [L12] COND TRUE !(0 == i && i == range) VAL [i=2, range=8] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=3, range=8] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=3, range=8] [L11] COND TRUE 0 <= i && i <= range VAL [i=3, range=8] [L12] COND TRUE !(0 == i && i == range) VAL [i=3, range=8] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=4, range=8] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=4, range=8] [L11] COND TRUE 0 <= i && i <= range VAL [i=4, range=8] [L12] COND TRUE !(0 == i && i == range) VAL [i=4, range=8] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=5, range=8] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=5, range=8] [L11] COND TRUE 0 <= i && i <= range VAL [i=5, range=8] [L12] COND TRUE !(0 == i && i == range) VAL [i=5, range=8] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=6, range=8] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=6, range=8] [L11] COND TRUE 0 <= i && i <= range VAL [i=6, range=8] [L12] COND TRUE !(0 == i && i == range) VAL [i=6, range=8] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=7, range=8] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=7, range=8] [L11] COND TRUE 0 <= i && i <= range VAL [i=7, range=8] [L12] COND TRUE !(0 == i && i == range) VAL [i=7, range=8] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=8, range=8] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=8, range=8] [L11] COND TRUE 0 <= i && i <= range VAL [i=8, range=8] [L12] COND TRUE !(0 == i && i == range) VAL [i=8, range=8] [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 VAL [i=0, range=7] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=0, range=7] [L11] COND TRUE 0 <= i && i <= range VAL [i=0, range=7] [L12] COND TRUE !(0 == i && i == range) VAL [i=0, range=7] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=1, range=7] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=1, range=7] [L11] COND TRUE 0 <= i && i <= range VAL [i=1, range=7] [L12] COND TRUE !(0 == i && i == range) VAL [i=1, range=7] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=2, range=7] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=2, range=7] [L11] COND TRUE 0 <= i && i <= range VAL [i=2, range=7] [L12] COND TRUE !(0 == i && i == range) VAL [i=2, range=7] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=3, range=7] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=3, range=7] [L11] COND TRUE 0 <= i && i <= range VAL [i=3, range=7] [L12] COND TRUE !(0 == i && i == range) VAL [i=3, range=7] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=4, range=7] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=4, range=7] [L11] COND TRUE 0 <= i && i <= range VAL [i=4, range=7] [L12] COND TRUE !(0 == i && i == range) VAL [i=4, range=7] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=5, range=7] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=5, range=7] [L11] COND TRUE 0 <= i && i <= range VAL [i=5, range=7] [L12] COND TRUE !(0 == i && i == range) VAL [i=5, range=7] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=6, range=7] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=6, range=7] [L11] COND TRUE 0 <= i && i <= range VAL [i=6, range=7] [L12] COND TRUE !(0 == i && i == range) VAL [i=6, range=7] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=7, range=7] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=7, range=7] [L11] COND TRUE 0 <= i && i <= range VAL [i=7, range=7] [L12] COND TRUE !(0 == i && i == range) VAL [i=7, range=7] [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 VAL [i=0, range=6] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=0, range=6] [L11] COND TRUE 0 <= i && i <= range VAL [i=0, range=6] [L12] COND TRUE !(0 == i && i == range) VAL [i=0, range=6] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=1, range=6] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=1, range=6] [L11] COND TRUE 0 <= i && i <= range VAL [i=1, range=6] [L12] COND TRUE !(0 == i && i == range) VAL [i=1, range=6] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=2, range=6] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=2, range=6] [L11] COND TRUE 0 <= i && i <= range VAL [i=2, range=6] [L12] COND TRUE !(0 == i && i == range) VAL [i=2, range=6] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=3, range=6] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=3, range=6] [L11] COND TRUE 0 <= i && i <= range VAL [i=3, range=6] [L12] COND TRUE !(0 == i && i == range) VAL [i=3, range=6] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=4, range=6] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=4, range=6] [L11] COND TRUE 0 <= i && i <= range VAL [i=4, range=6] [L12] COND TRUE !(0 == i && i == range) VAL [i=4, range=6] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=5, range=6] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=5, range=6] [L11] COND TRUE 0 <= i && i <= range VAL [i=5, range=6] [L12] COND TRUE !(0 == i && i == range) VAL [i=5, range=6] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=6, range=6] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=6, range=6] [L11] COND TRUE 0 <= i && i <= range VAL [i=6, range=6] [L12] COND TRUE !(0 == i && i == range) VAL [i=6, range=6] [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 VAL [i=0, range=5] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=0, range=5] [L11] COND TRUE 0 <= i && i <= range VAL [i=0, range=5] [L12] COND TRUE !(0 == i && i == range) VAL [i=0, range=5] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=1, range=5] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=1, range=5] [L11] COND TRUE 0 <= i && i <= range VAL [i=1, range=5] [L12] COND TRUE !(0 == i && i == range) VAL [i=1, range=5] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=2, range=5] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=2, range=5] [L11] COND TRUE 0 <= i && i <= range VAL [i=2, range=5] [L12] COND TRUE !(0 == i && i == range) VAL [i=2, range=5] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=3, range=5] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=3, range=5] [L11] COND TRUE 0 <= i && i <= range VAL [i=3, range=5] [L12] COND TRUE !(0 == i && i == range) VAL [i=3, range=5] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=4, range=5] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=4, range=5] [L11] COND TRUE 0 <= i && i <= range VAL [i=4, range=5] [L12] COND TRUE !(0 == i && i == range) VAL [i=4, range=5] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=5, range=5] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=5, range=5] [L11] COND TRUE 0 <= i && i <= range VAL [i=5, range=5] [L12] COND TRUE !(0 == i && i == range) VAL [i=5, range=5] [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 VAL [i=0, range=4] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=0, range=4] [L11] COND TRUE 0 <= i && i <= range VAL [i=0, range=4] [L12] COND TRUE !(0 == i && i == range) VAL [i=0, range=4] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=1, range=4] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=1, range=4] [L11] COND TRUE 0 <= i && i <= range VAL [i=1, range=4] [L12] COND TRUE !(0 == i && i == range) VAL [i=1, range=4] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=2, range=4] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=2, range=4] [L11] COND TRUE 0 <= i && i <= range VAL [i=2, range=4] [L12] COND TRUE !(0 == i && i == range) VAL [i=2, range=4] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=3, range=4] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=3, range=4] [L11] COND TRUE 0 <= i && i <= range VAL [i=3, range=4] [L12] COND TRUE !(0 == i && i == range) VAL [i=3, range=4] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=4, range=4] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=4, range=4] [L11] COND TRUE 0 <= i && i <= range VAL [i=4, range=4] [L12] COND TRUE !(0 == i && i == range) VAL [i=4, range=4] [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 VAL [i=0, range=3] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=0, range=3] [L11] COND TRUE 0 <= i && i <= range VAL [i=0, range=3] [L12] COND TRUE !(0 == i && i == range) VAL [i=0, range=3] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=1, range=3] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=1, range=3] [L11] COND TRUE 0 <= i && i <= range VAL [i=1, range=3] [L12] COND TRUE !(0 == i && i == range) VAL [i=1, range=3] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=2, range=3] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=2, range=3] [L11] COND TRUE 0 <= i && i <= range VAL [i=2, range=3] [L12] COND TRUE !(0 == i && i == range) VAL [i=2, range=3] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=3, range=3] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=3, range=3] [L11] COND TRUE 0 <= i && i <= range VAL [i=3, range=3] [L12] COND TRUE !(0 == i && i == range) VAL [i=3, range=3] [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 VAL [i=0, range=2] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=0, range=2] [L11] COND TRUE 0 <= i && i <= range VAL [i=0, range=2] [L12] COND TRUE !(0 == i && i == range) VAL [i=0, range=2] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=1, range=2] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=1, range=2] [L11] COND TRUE 0 <= i && i <= range VAL [i=1, range=2] [L12] COND TRUE !(0 == i && i == range) VAL [i=1, range=2] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=2, range=2] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=2, range=2] [L11] COND TRUE 0 <= i && i <= range VAL [i=2, range=2] [L12] COND TRUE !(0 == i && i == range) VAL [i=2, range=2] [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 VAL [i=0, range=1] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=0, range=1] [L11] COND TRUE 0 <= i && i <= range VAL [i=0, range=1] [L12] COND TRUE !(0 == i && i == range) VAL [i=0, range=1] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=1, range=1] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=1, range=1] [L11] COND TRUE 0 <= i && i <= range VAL [i=1, range=1] [L12] COND TRUE !(0 == i && i == range) VAL [i=1, range=1] [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 VAL [i=0, range=0] Loop: [L11] COND FALSE !(0 <= i && i <= range) [L11] COND TRUE 0 <= i && i <= range [L12] COND FALSE !(!(0 == i && i == range)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 11]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L6] int i; [L7] int range; [L8] i = __VERIFIER_nondet_int() [L9] range = 20 VAL [range=20] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=20, range=20] [L11] COND TRUE 0 <= i && i <= range VAL [i=20, range=20] [L12] COND TRUE !(0 == i && i == range) VAL [i=20, range=20] [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 VAL [i=0, range=19] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=0, range=19] [L11] COND TRUE 0 <= i && i <= range VAL [i=0, range=19] [L12] COND TRUE !(0 == i && i == range) VAL [i=0, range=19] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=1, range=19] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=1, range=19] [L11] COND TRUE 0 <= i && i <= range VAL [i=1, range=19] [L12] COND TRUE !(0 == i && i == range) VAL [i=1, range=19] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=2, range=19] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=2, range=19] [L11] COND TRUE 0 <= i && i <= range VAL [i=2, range=19] [L12] COND TRUE !(0 == i && i == range) VAL [i=2, range=19] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=3, range=19] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=3, range=19] [L11] COND TRUE 0 <= i && i <= range VAL [i=3, range=19] [L12] COND TRUE !(0 == i && i == range) VAL [i=3, range=19] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=4, range=19] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=4, range=19] [L11] COND TRUE 0 <= i && i <= range VAL [i=4, range=19] [L12] COND TRUE !(0 == i && i == range) VAL [i=4, range=19] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=5, range=19] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=5, range=19] [L11] COND TRUE 0 <= i && i <= range VAL [i=5, range=19] [L12] COND TRUE !(0 == i && i == range) VAL [i=5, range=19] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=6, range=19] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=6, range=19] [L11] COND TRUE 0 <= i && i <= range VAL [i=6, range=19] [L12] COND TRUE !(0 == i && i == range) VAL [i=6, range=19] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=7, range=19] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=7, range=19] [L11] COND TRUE 0 <= i && i <= range VAL [i=7, range=19] [L12] COND TRUE !(0 == i && i == range) VAL [i=7, range=19] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=8, range=19] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=8, range=19] [L11] COND TRUE 0 <= i && i <= range VAL [i=8, range=19] [L12] COND TRUE !(0 == i && i == range) VAL [i=8, range=19] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=9, range=19] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=9, range=19] [L11] COND TRUE 0 <= i && i <= range VAL [i=9, range=19] [L12] COND TRUE !(0 == i && i == range) VAL [i=9, range=19] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=10, range=19] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=10, range=19] [L11] COND TRUE 0 <= i && i <= range VAL [i=10, range=19] [L12] COND TRUE !(0 == i && i == range) VAL [i=10, range=19] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=11, range=19] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=11, range=19] [L11] COND TRUE 0 <= i && i <= range VAL [i=11, range=19] [L12] COND TRUE !(0 == i && i == range) VAL [i=11, range=19] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=12, range=19] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=12, range=19] [L11] COND TRUE 0 <= i && i <= range VAL [i=12, range=19] [L12] COND TRUE !(0 == i && i == range) VAL [i=12, range=19] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=13, range=19] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=13, range=19] [L11] COND TRUE 0 <= i && i <= range VAL [i=13, range=19] [L12] COND TRUE !(0 == i && i == range) VAL [i=13, range=19] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=14, range=19] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=14, range=19] [L11] COND TRUE 0 <= i && i <= range VAL [i=14, range=19] [L12] COND TRUE !(0 == i && i == range) VAL [i=14, range=19] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=15, range=19] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=15, range=19] [L11] COND TRUE 0 <= i && i <= range VAL [i=15, range=19] [L12] COND TRUE !(0 == i && i == range) VAL [i=15, range=19] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=16, range=19] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=16, range=19] [L11] COND TRUE 0 <= i && i <= range VAL [i=16, range=19] [L12] COND TRUE !(0 == i && i == range) VAL [i=16, range=19] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=17, range=19] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=17, range=19] [L11] COND TRUE 0 <= i && i <= range VAL [i=17, range=19] [L12] COND TRUE !(0 == i && i == range) VAL [i=17, range=19] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=18, range=19] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=18, range=19] [L11] COND TRUE 0 <= i && i <= range VAL [i=18, range=19] [L12] COND TRUE !(0 == i && i == range) VAL [i=18, range=19] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=19, range=19] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=19, range=19] [L11] COND TRUE 0 <= i && i <= range VAL [i=19, range=19] [L12] COND TRUE !(0 == i && i == range) VAL [i=19, range=19] [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 VAL [i=0, range=18] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=0, range=18] [L11] COND TRUE 0 <= i && i <= range VAL [i=0, range=18] [L12] COND TRUE !(0 == i && i == range) VAL [i=0, range=18] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=1, range=18] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=1, range=18] [L11] COND TRUE 0 <= i && i <= range VAL [i=1, range=18] [L12] COND TRUE !(0 == i && i == range) VAL [i=1, range=18] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=2, range=18] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=2, range=18] [L11] COND TRUE 0 <= i && i <= range VAL [i=2, range=18] [L12] COND TRUE !(0 == i && i == range) VAL [i=2, range=18] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=3, range=18] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=3, range=18] [L11] COND TRUE 0 <= i && i <= range VAL [i=3, range=18] [L12] COND TRUE !(0 == i && i == range) VAL [i=3, range=18] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=4, range=18] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=4, range=18] [L11] COND TRUE 0 <= i && i <= range VAL [i=4, range=18] [L12] COND TRUE !(0 == i && i == range) VAL [i=4, range=18] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=5, range=18] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=5, range=18] [L11] COND TRUE 0 <= i && i <= range VAL [i=5, range=18] [L12] COND TRUE !(0 == i && i == range) VAL [i=5, range=18] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=6, range=18] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=6, range=18] [L11] COND TRUE 0 <= i && i <= range VAL [i=6, range=18] [L12] COND TRUE !(0 == i && i == range) VAL [i=6, range=18] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=7, range=18] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=7, range=18] [L11] COND TRUE 0 <= i && i <= range VAL [i=7, range=18] [L12] COND TRUE !(0 == i && i == range) VAL [i=7, range=18] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=8, range=18] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=8, range=18] [L11] COND TRUE 0 <= i && i <= range VAL [i=8, range=18] [L12] COND TRUE !(0 == i && i == range) VAL [i=8, range=18] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=9, range=18] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=9, range=18] [L11] COND TRUE 0 <= i && i <= range VAL [i=9, range=18] [L12] COND TRUE !(0 == i && i == range) VAL [i=9, range=18] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=10, range=18] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=10, range=18] [L11] COND TRUE 0 <= i && i <= range VAL [i=10, range=18] [L12] COND TRUE !(0 == i && i == range) VAL [i=10, range=18] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=11, range=18] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=11, range=18] [L11] COND TRUE 0 <= i && i <= range VAL [i=11, range=18] [L12] COND TRUE !(0 == i && i == range) VAL [i=11, range=18] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=12, range=18] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=12, range=18] [L11] COND TRUE 0 <= i && i <= range VAL [i=12, range=18] [L12] COND TRUE !(0 == i && i == range) VAL [i=12, range=18] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=13, range=18] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=13, range=18] [L11] COND TRUE 0 <= i && i <= range VAL [i=13, range=18] [L12] COND TRUE !(0 == i && i == range) VAL [i=13, range=18] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=14, range=18] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=14, range=18] [L11] COND TRUE 0 <= i && i <= range VAL [i=14, range=18] [L12] COND TRUE !(0 == i && i == range) VAL [i=14, range=18] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=15, range=18] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=15, range=18] [L11] COND TRUE 0 <= i && i <= range VAL [i=15, range=18] [L12] COND TRUE !(0 == i && i == range) VAL [i=15, range=18] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=16, range=18] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=16, range=18] [L11] COND TRUE 0 <= i && i <= range VAL [i=16, range=18] [L12] COND TRUE !(0 == i && i == range) VAL [i=16, range=18] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=17, range=18] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=17, range=18] [L11] COND TRUE 0 <= i && i <= range VAL [i=17, range=18] [L12] COND TRUE !(0 == i && i == range) VAL [i=17, range=18] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=18, range=18] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=18, range=18] [L11] COND TRUE 0 <= i && i <= range VAL [i=18, range=18] [L12] COND TRUE !(0 == i && i == range) VAL [i=18, range=18] [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 VAL [i=0, range=17] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=0, range=17] [L11] COND TRUE 0 <= i && i <= range VAL [i=0, range=17] [L12] COND TRUE !(0 == i && i == range) VAL [i=0, range=17] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=1, range=17] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=1, range=17] [L11] COND TRUE 0 <= i && i <= range VAL [i=1, range=17] [L12] COND TRUE !(0 == i && i == range) VAL [i=1, range=17] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=2, range=17] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=2, range=17] [L11] COND TRUE 0 <= i && i <= range VAL [i=2, range=17] [L12] COND TRUE !(0 == i && i == range) VAL [i=2, range=17] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=3, range=17] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=3, range=17] [L11] COND TRUE 0 <= i && i <= range VAL [i=3, range=17] [L12] COND TRUE !(0 == i && i == range) VAL [i=3, range=17] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=4, range=17] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=4, range=17] [L11] COND TRUE 0 <= i && i <= range VAL [i=4, range=17] [L12] COND TRUE !(0 == i && i == range) VAL [i=4, range=17] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=5, range=17] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=5, range=17] [L11] COND TRUE 0 <= i && i <= range VAL [i=5, range=17] [L12] COND TRUE !(0 == i && i == range) VAL [i=5, range=17] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=6, range=17] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=6, range=17] [L11] COND TRUE 0 <= i && i <= range VAL [i=6, range=17] [L12] COND TRUE !(0 == i && i == range) VAL [i=6, range=17] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=7, range=17] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=7, range=17] [L11] COND TRUE 0 <= i && i <= range VAL [i=7, range=17] [L12] COND TRUE !(0 == i && i == range) VAL [i=7, range=17] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=8, range=17] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=8, range=17] [L11] COND TRUE 0 <= i && i <= range VAL [i=8, range=17] [L12] COND TRUE !(0 == i && i == range) VAL [i=8, range=17] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=9, range=17] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=9, range=17] [L11] COND TRUE 0 <= i && i <= range VAL [i=9, range=17] [L12] COND TRUE !(0 == i && i == range) VAL [i=9, range=17] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=10, range=17] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=10, range=17] [L11] COND TRUE 0 <= i && i <= range VAL [i=10, range=17] [L12] COND TRUE !(0 == i && i == range) VAL [i=10, range=17] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=11, range=17] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=11, range=17] [L11] COND TRUE 0 <= i && i <= range VAL [i=11, range=17] [L12] COND TRUE !(0 == i && i == range) VAL [i=11, range=17] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=12, range=17] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=12, range=17] [L11] COND TRUE 0 <= i && i <= range VAL [i=12, range=17] [L12] COND TRUE !(0 == i && i == range) VAL [i=12, range=17] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=13, range=17] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=13, range=17] [L11] COND TRUE 0 <= i && i <= range VAL [i=13, range=17] [L12] COND TRUE !(0 == i && i == range) VAL [i=13, range=17] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=14, range=17] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=14, range=17] [L11] COND TRUE 0 <= i && i <= range VAL [i=14, range=17] [L12] COND TRUE !(0 == i && i == range) VAL [i=14, range=17] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=15, range=17] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=15, range=17] [L11] COND TRUE 0 <= i && i <= range VAL [i=15, range=17] [L12] COND TRUE !(0 == i && i == range) VAL [i=15, range=17] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=16, range=17] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=16, range=17] [L11] COND TRUE 0 <= i && i <= range VAL [i=16, range=17] [L12] COND TRUE !(0 == i && i == range) VAL [i=16, range=17] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=17, range=17] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=17, range=17] [L11] COND TRUE 0 <= i && i <= range VAL [i=17, range=17] [L12] COND TRUE !(0 == i && i == range) VAL [i=17, range=17] [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 VAL [i=0, range=16] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=0, range=16] [L11] COND TRUE 0 <= i && i <= range VAL [i=0, range=16] [L12] COND TRUE !(0 == i && i == range) VAL [i=0, range=16] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=1, range=16] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=1, range=16] [L11] COND TRUE 0 <= i && i <= range VAL [i=1, range=16] [L12] COND TRUE !(0 == i && i == range) VAL [i=1, range=16] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=2, range=16] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=2, range=16] [L11] COND TRUE 0 <= i && i <= range VAL [i=2, range=16] [L12] COND TRUE !(0 == i && i == range) VAL [i=2, range=16] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=3, range=16] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=3, range=16] [L11] COND TRUE 0 <= i && i <= range VAL [i=3, range=16] [L12] COND TRUE !(0 == i && i == range) VAL [i=3, range=16] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=4, range=16] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=4, range=16] [L11] COND TRUE 0 <= i && i <= range VAL [i=4, range=16] [L12] COND TRUE !(0 == i && i == range) VAL [i=4, range=16] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=5, range=16] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=5, range=16] [L11] COND TRUE 0 <= i && i <= range VAL [i=5, range=16] [L12] COND TRUE !(0 == i && i == range) VAL [i=5, range=16] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=6, range=16] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=6, range=16] [L11] COND TRUE 0 <= i && i <= range VAL [i=6, range=16] [L12] COND TRUE !(0 == i && i == range) VAL [i=6, range=16] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=7, range=16] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=7, range=16] [L11] COND TRUE 0 <= i && i <= range VAL [i=7, range=16] [L12] COND TRUE !(0 == i && i == range) VAL [i=7, range=16] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=8, range=16] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=8, range=16] [L11] COND TRUE 0 <= i && i <= range VAL [i=8, range=16] [L12] COND TRUE !(0 == i && i == range) VAL [i=8, range=16] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=9, range=16] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=9, range=16] [L11] COND TRUE 0 <= i && i <= range VAL [i=9, range=16] [L12] COND TRUE !(0 == i && i == range) VAL [i=9, range=16] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=10, range=16] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=10, range=16] [L11] COND TRUE 0 <= i && i <= range VAL [i=10, range=16] [L12] COND TRUE !(0 == i && i == range) VAL [i=10, range=16] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=11, range=16] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=11, range=16] [L11] COND TRUE 0 <= i && i <= range VAL [i=11, range=16] [L12] COND TRUE !(0 == i && i == range) VAL [i=11, range=16] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=12, range=16] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=12, range=16] [L11] COND TRUE 0 <= i && i <= range VAL [i=12, range=16] [L12] COND TRUE !(0 == i && i == range) VAL [i=12, range=16] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=13, range=16] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=13, range=16] [L11] COND TRUE 0 <= i && i <= range VAL [i=13, range=16] [L12] COND TRUE !(0 == i && i == range) VAL [i=13, range=16] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=14, range=16] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=14, range=16] [L11] COND TRUE 0 <= i && i <= range VAL [i=14, range=16] [L12] COND TRUE !(0 == i && i == range) VAL [i=14, range=16] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=15, range=16] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=15, range=16] [L11] COND TRUE 0 <= i && i <= range VAL [i=15, range=16] [L12] COND TRUE !(0 == i && i == range) VAL [i=15, range=16] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=16, range=16] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=16, range=16] [L11] COND TRUE 0 <= i && i <= range VAL [i=16, range=16] [L12] COND TRUE !(0 == i && i == range) VAL [i=16, range=16] [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 VAL [i=0, range=15] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=0, range=15] [L11] COND TRUE 0 <= i && i <= range VAL [i=0, range=15] [L12] COND TRUE !(0 == i && i == range) VAL [i=0, range=15] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=1, range=15] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=1, range=15] [L11] COND TRUE 0 <= i && i <= range VAL [i=1, range=15] [L12] COND TRUE !(0 == i && i == range) VAL [i=1, range=15] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=2, range=15] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=2, range=15] [L11] COND TRUE 0 <= i && i <= range VAL [i=2, range=15] [L12] COND TRUE !(0 == i && i == range) VAL [i=2, range=15] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=3, range=15] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=3, range=15] [L11] COND TRUE 0 <= i && i <= range VAL [i=3, range=15] [L12] COND TRUE !(0 == i && i == range) VAL [i=3, range=15] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=4, range=15] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=4, range=15] [L11] COND TRUE 0 <= i && i <= range VAL [i=4, range=15] [L12] COND TRUE !(0 == i && i == range) VAL [i=4, range=15] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=5, range=15] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=5, range=15] [L11] COND TRUE 0 <= i && i <= range VAL [i=5, range=15] [L12] COND TRUE !(0 == i && i == range) VAL [i=5, range=15] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=6, range=15] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=6, range=15] [L11] COND TRUE 0 <= i && i <= range VAL [i=6, range=15] [L12] COND TRUE !(0 == i && i == range) VAL [i=6, range=15] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=7, range=15] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=7, range=15] [L11] COND TRUE 0 <= i && i <= range VAL [i=7, range=15] [L12] COND TRUE !(0 == i && i == range) VAL [i=7, range=15] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=8, range=15] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=8, range=15] [L11] COND TRUE 0 <= i && i <= range VAL [i=8, range=15] [L12] COND TRUE !(0 == i && i == range) VAL [i=8, range=15] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=9, range=15] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=9, range=15] [L11] COND TRUE 0 <= i && i <= range VAL [i=9, range=15] [L12] COND TRUE !(0 == i && i == range) VAL [i=9, range=15] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=10, range=15] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=10, range=15] [L11] COND TRUE 0 <= i && i <= range VAL [i=10, range=15] [L12] COND TRUE !(0 == i && i == range) VAL [i=10, range=15] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=11, range=15] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=11, range=15] [L11] COND TRUE 0 <= i && i <= range VAL [i=11, range=15] [L12] COND TRUE !(0 == i && i == range) VAL [i=11, range=15] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=12, range=15] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=12, range=15] [L11] COND TRUE 0 <= i && i <= range VAL [i=12, range=15] [L12] COND TRUE !(0 == i && i == range) VAL [i=12, range=15] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=13, range=15] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=13, range=15] [L11] COND TRUE 0 <= i && i <= range VAL [i=13, range=15] [L12] COND TRUE !(0 == i && i == range) VAL [i=13, range=15] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=14, range=15] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=14, range=15] [L11] COND TRUE 0 <= i && i <= range VAL [i=14, range=15] [L12] COND TRUE !(0 == i && i == range) VAL [i=14, range=15] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=15, range=15] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=15, range=15] [L11] COND TRUE 0 <= i && i <= range VAL [i=15, range=15] [L12] COND TRUE !(0 == i && i == range) VAL [i=15, range=15] [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 VAL [i=0, range=14] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=0, range=14] [L11] COND TRUE 0 <= i && i <= range VAL [i=0, range=14] [L12] COND TRUE !(0 == i && i == range) VAL [i=0, range=14] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=1, range=14] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=1, range=14] [L11] COND TRUE 0 <= i && i <= range VAL [i=1, range=14] [L12] COND TRUE !(0 == i && i == range) VAL [i=1, range=14] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=2, range=14] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=2, range=14] [L11] COND TRUE 0 <= i && i <= range VAL [i=2, range=14] [L12] COND TRUE !(0 == i && i == range) VAL [i=2, range=14] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=3, range=14] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=3, range=14] [L11] COND TRUE 0 <= i && i <= range VAL [i=3, range=14] [L12] COND TRUE !(0 == i && i == range) VAL [i=3, range=14] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=4, range=14] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=4, range=14] [L11] COND TRUE 0 <= i && i <= range VAL [i=4, range=14] [L12] COND TRUE !(0 == i && i == range) VAL [i=4, range=14] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=5, range=14] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=5, range=14] [L11] COND TRUE 0 <= i && i <= range VAL [i=5, range=14] [L12] COND TRUE !(0 == i && i == range) VAL [i=5, range=14] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=6, range=14] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=6, range=14] [L11] COND TRUE 0 <= i && i <= range VAL [i=6, range=14] [L12] COND TRUE !(0 == i && i == range) VAL [i=6, range=14] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=7, range=14] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=7, range=14] [L11] COND TRUE 0 <= i && i <= range VAL [i=7, range=14] [L12] COND TRUE !(0 == i && i == range) VAL [i=7, range=14] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=8, range=14] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=8, range=14] [L11] COND TRUE 0 <= i && i <= range VAL [i=8, range=14] [L12] COND TRUE !(0 == i && i == range) VAL [i=8, range=14] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=9, range=14] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=9, range=14] [L11] COND TRUE 0 <= i && i <= range VAL [i=9, range=14] [L12] COND TRUE !(0 == i && i == range) VAL [i=9, range=14] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=10, range=14] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=10, range=14] [L11] COND TRUE 0 <= i && i <= range VAL [i=10, range=14] [L12] COND TRUE !(0 == i && i == range) VAL [i=10, range=14] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=11, range=14] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=11, range=14] [L11] COND TRUE 0 <= i && i <= range VAL [i=11, range=14] [L12] COND TRUE !(0 == i && i == range) VAL [i=11, range=14] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=12, range=14] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=12, range=14] [L11] COND TRUE 0 <= i && i <= range VAL [i=12, range=14] [L12] COND TRUE !(0 == i && i == range) VAL [i=12, range=14] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=13, range=14] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=13, range=14] [L11] COND TRUE 0 <= i && i <= range VAL [i=13, range=14] [L12] COND TRUE !(0 == i && i == range) VAL [i=13, range=14] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=14, range=14] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=14, range=14] [L11] COND TRUE 0 <= i && i <= range VAL [i=14, range=14] [L12] COND TRUE !(0 == i && i == range) VAL [i=14, range=14] [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 VAL [i=0, range=13] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=0, range=13] [L11] COND TRUE 0 <= i && i <= range VAL [i=0, range=13] [L12] COND TRUE !(0 == i && i == range) VAL [i=0, range=13] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=1, range=13] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=1, range=13] [L11] COND TRUE 0 <= i && i <= range VAL [i=1, range=13] [L12] COND TRUE !(0 == i && i == range) VAL [i=1, range=13] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=2, range=13] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=2, range=13] [L11] COND TRUE 0 <= i && i <= range VAL [i=2, range=13] [L12] COND TRUE !(0 == i && i == range) VAL [i=2, range=13] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=3, range=13] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=3, range=13] [L11] COND TRUE 0 <= i && i <= range VAL [i=3, range=13] [L12] COND TRUE !(0 == i && i == range) VAL [i=3, range=13] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=4, range=13] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=4, range=13] [L11] COND TRUE 0 <= i && i <= range VAL [i=4, range=13] [L12] COND TRUE !(0 == i && i == range) VAL [i=4, range=13] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=5, range=13] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=5, range=13] [L11] COND TRUE 0 <= i && i <= range VAL [i=5, range=13] [L12] COND TRUE !(0 == i && i == range) VAL [i=5, range=13] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=6, range=13] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=6, range=13] [L11] COND TRUE 0 <= i && i <= range VAL [i=6, range=13] [L12] COND TRUE !(0 == i && i == range) VAL [i=6, range=13] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=7, range=13] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=7, range=13] [L11] COND TRUE 0 <= i && i <= range VAL [i=7, range=13] [L12] COND TRUE !(0 == i && i == range) VAL [i=7, range=13] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=8, range=13] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=8, range=13] [L11] COND TRUE 0 <= i && i <= range VAL [i=8, range=13] [L12] COND TRUE !(0 == i && i == range) VAL [i=8, range=13] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=9, range=13] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=9, range=13] [L11] COND TRUE 0 <= i && i <= range VAL [i=9, range=13] [L12] COND TRUE !(0 == i && i == range) VAL [i=9, range=13] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=10, range=13] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=10, range=13] [L11] COND TRUE 0 <= i && i <= range VAL [i=10, range=13] [L12] COND TRUE !(0 == i && i == range) VAL [i=10, range=13] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=11, range=13] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=11, range=13] [L11] COND TRUE 0 <= i && i <= range VAL [i=11, range=13] [L12] COND TRUE !(0 == i && i == range) VAL [i=11, range=13] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=12, range=13] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=12, range=13] [L11] COND TRUE 0 <= i && i <= range VAL [i=12, range=13] [L12] COND TRUE !(0 == i && i == range) VAL [i=12, range=13] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=13, range=13] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=13, range=13] [L11] COND TRUE 0 <= i && i <= range VAL [i=13, range=13] [L12] COND TRUE !(0 == i && i == range) VAL [i=13, range=13] [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 VAL [i=0, range=12] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=0, range=12] [L11] COND TRUE 0 <= i && i <= range VAL [i=0, range=12] [L12] COND TRUE !(0 == i && i == range) VAL [i=0, range=12] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=1, range=12] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=1, range=12] [L11] COND TRUE 0 <= i && i <= range VAL [i=1, range=12] [L12] COND TRUE !(0 == i && i == range) VAL [i=1, range=12] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=2, range=12] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=2, range=12] [L11] COND TRUE 0 <= i && i <= range VAL [i=2, range=12] [L12] COND TRUE !(0 == i && i == range) VAL [i=2, range=12] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=3, range=12] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=3, range=12] [L11] COND TRUE 0 <= i && i <= range VAL [i=3, range=12] [L12] COND TRUE !(0 == i && i == range) VAL [i=3, range=12] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=4, range=12] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=4, range=12] [L11] COND TRUE 0 <= i && i <= range VAL [i=4, range=12] [L12] COND TRUE !(0 == i && i == range) VAL [i=4, range=12] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=5, range=12] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=5, range=12] [L11] COND TRUE 0 <= i && i <= range VAL [i=5, range=12] [L12] COND TRUE !(0 == i && i == range) VAL [i=5, range=12] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=6, range=12] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=6, range=12] [L11] COND TRUE 0 <= i && i <= range VAL [i=6, range=12] [L12] COND TRUE !(0 == i && i == range) VAL [i=6, range=12] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=7, range=12] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=7, range=12] [L11] COND TRUE 0 <= i && i <= range VAL [i=7, range=12] [L12] COND TRUE !(0 == i && i == range) VAL [i=7, range=12] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=8, range=12] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=8, range=12] [L11] COND TRUE 0 <= i && i <= range VAL [i=8, range=12] [L12] COND TRUE !(0 == i && i == range) VAL [i=8, range=12] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=9, range=12] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=9, range=12] [L11] COND TRUE 0 <= i && i <= range VAL [i=9, range=12] [L12] COND TRUE !(0 == i && i == range) VAL [i=9, range=12] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=10, range=12] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=10, range=12] [L11] COND TRUE 0 <= i && i <= range VAL [i=10, range=12] [L12] COND TRUE !(0 == i && i == range) VAL [i=10, range=12] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=11, range=12] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=11, range=12] [L11] COND TRUE 0 <= i && i <= range VAL [i=11, range=12] [L12] COND TRUE !(0 == i && i == range) VAL [i=11, range=12] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=12, range=12] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=12, range=12] [L11] COND TRUE 0 <= i && i <= range VAL [i=12, range=12] [L12] COND TRUE !(0 == i && i == range) VAL [i=12, range=12] [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 VAL [i=0, range=11] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=0, range=11] [L11] COND TRUE 0 <= i && i <= range VAL [i=0, range=11] [L12] COND TRUE !(0 == i && i == range) VAL [i=0, range=11] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=1, range=11] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=1, range=11] [L11] COND TRUE 0 <= i && i <= range VAL [i=1, range=11] [L12] COND TRUE !(0 == i && i == range) VAL [i=1, range=11] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=2, range=11] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=2, range=11] [L11] COND TRUE 0 <= i && i <= range VAL [i=2, range=11] [L12] COND TRUE !(0 == i && i == range) VAL [i=2, range=11] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=3, range=11] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=3, range=11] [L11] COND TRUE 0 <= i && i <= range VAL [i=3, range=11] [L12] COND TRUE !(0 == i && i == range) VAL [i=3, range=11] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=4, range=11] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=4, range=11] [L11] COND TRUE 0 <= i && i <= range VAL [i=4, range=11] [L12] COND TRUE !(0 == i && i == range) VAL [i=4, range=11] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=5, range=11] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=5, range=11] [L11] COND TRUE 0 <= i && i <= range VAL [i=5, range=11] [L12] COND TRUE !(0 == i && i == range) VAL [i=5, range=11] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=6, range=11] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=6, range=11] [L11] COND TRUE 0 <= i && i <= range VAL [i=6, range=11] [L12] COND TRUE !(0 == i && i == range) VAL [i=6, range=11] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=7, range=11] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=7, range=11] [L11] COND TRUE 0 <= i && i <= range VAL [i=7, range=11] [L12] COND TRUE !(0 == i && i == range) VAL [i=7, range=11] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=8, range=11] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=8, range=11] [L11] COND TRUE 0 <= i && i <= range VAL [i=8, range=11] [L12] COND TRUE !(0 == i && i == range) VAL [i=8, range=11] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=9, range=11] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=9, range=11] [L11] COND TRUE 0 <= i && i <= range VAL [i=9, range=11] [L12] COND TRUE !(0 == i && i == range) VAL [i=9, range=11] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=10, range=11] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=10, range=11] [L11] COND TRUE 0 <= i && i <= range VAL [i=10, range=11] [L12] COND TRUE !(0 == i && i == range) VAL [i=10, range=11] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=11, range=11] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=11, range=11] [L11] COND TRUE 0 <= i && i <= range VAL [i=11, range=11] [L12] COND TRUE !(0 == i && i == range) VAL [i=11, range=11] [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 VAL [i=0, range=10] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=0, range=10] [L11] COND TRUE 0 <= i && i <= range VAL [i=0, range=10] [L12] COND TRUE !(0 == i && i == range) VAL [i=0, range=10] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=1, range=10] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=1, range=10] [L11] COND TRUE 0 <= i && i <= range VAL [i=1, range=10] [L12] COND TRUE !(0 == i && i == range) VAL [i=1, range=10] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=2, range=10] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=2, range=10] [L11] COND TRUE 0 <= i && i <= range VAL [i=2, range=10] [L12] COND TRUE !(0 == i && i == range) VAL [i=2, range=10] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=3, range=10] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=3, range=10] [L11] COND TRUE 0 <= i && i <= range VAL [i=3, range=10] [L12] COND TRUE !(0 == i && i == range) VAL [i=3, range=10] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=4, range=10] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=4, range=10] [L11] COND TRUE 0 <= i && i <= range VAL [i=4, range=10] [L12] COND TRUE !(0 == i && i == range) VAL [i=4, range=10] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=5, range=10] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=5, range=10] [L11] COND TRUE 0 <= i && i <= range VAL [i=5, range=10] [L12] COND TRUE !(0 == i && i == range) VAL [i=5, range=10] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=6, range=10] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=6, range=10] [L11] COND TRUE 0 <= i && i <= range VAL [i=6, range=10] [L12] COND TRUE !(0 == i && i == range) VAL [i=6, range=10] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=7, range=10] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=7, range=10] [L11] COND TRUE 0 <= i && i <= range VAL [i=7, range=10] [L12] COND TRUE !(0 == i && i == range) VAL [i=7, range=10] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=8, range=10] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=8, range=10] [L11] COND TRUE 0 <= i && i <= range VAL [i=8, range=10] [L12] COND TRUE !(0 == i && i == range) VAL [i=8, range=10] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=9, range=10] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=9, range=10] [L11] COND TRUE 0 <= i && i <= range VAL [i=9, range=10] [L12] COND TRUE !(0 == i && i == range) VAL [i=9, range=10] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=10, range=10] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=10, range=10] [L11] COND TRUE 0 <= i && i <= range VAL [i=10, range=10] [L12] COND TRUE !(0 == i && i == range) VAL [i=10, range=10] [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 VAL [i=0, range=9] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=0, range=9] [L11] COND TRUE 0 <= i && i <= range VAL [i=0, range=9] [L12] COND TRUE !(0 == i && i == range) VAL [i=0, range=9] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=1, range=9] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=1, range=9] [L11] COND TRUE 0 <= i && i <= range VAL [i=1, range=9] [L12] COND TRUE !(0 == i && i == range) VAL [i=1, range=9] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=2, range=9] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=2, range=9] [L11] COND TRUE 0 <= i && i <= range VAL [i=2, range=9] [L12] COND TRUE !(0 == i && i == range) VAL [i=2, range=9] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=3, range=9] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=3, range=9] [L11] COND TRUE 0 <= i && i <= range VAL [i=3, range=9] [L12] COND TRUE !(0 == i && i == range) VAL [i=3, range=9] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=4, range=9] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=4, range=9] [L11] COND TRUE 0 <= i && i <= range VAL [i=4, range=9] [L12] COND TRUE !(0 == i && i == range) VAL [i=4, range=9] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=5, range=9] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=5, range=9] [L11] COND TRUE 0 <= i && i <= range VAL [i=5, range=9] [L12] COND TRUE !(0 == i && i == range) VAL [i=5, range=9] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=6, range=9] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=6, range=9] [L11] COND TRUE 0 <= i && i <= range VAL [i=6, range=9] [L12] COND TRUE !(0 == i && i == range) VAL [i=6, range=9] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=7, range=9] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=7, range=9] [L11] COND TRUE 0 <= i && i <= range VAL [i=7, range=9] [L12] COND TRUE !(0 == i && i == range) VAL [i=7, range=9] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=8, range=9] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=8, range=9] [L11] COND TRUE 0 <= i && i <= range VAL [i=8, range=9] [L12] COND TRUE !(0 == i && i == range) VAL [i=8, range=9] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=9, range=9] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=9, range=9] [L11] COND TRUE 0 <= i && i <= range VAL [i=9, range=9] [L12] COND TRUE !(0 == i && i == range) VAL [i=9, range=9] [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 VAL [i=0, range=8] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=0, range=8] [L11] COND TRUE 0 <= i && i <= range VAL [i=0, range=8] [L12] COND TRUE !(0 == i && i == range) VAL [i=0, range=8] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=1, range=8] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=1, range=8] [L11] COND TRUE 0 <= i && i <= range VAL [i=1, range=8] [L12] COND TRUE !(0 == i && i == range) VAL [i=1, range=8] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=2, range=8] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=2, range=8] [L11] COND TRUE 0 <= i && i <= range VAL [i=2, range=8] [L12] COND TRUE !(0 == i && i == range) VAL [i=2, range=8] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=3, range=8] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=3, range=8] [L11] COND TRUE 0 <= i && i <= range VAL [i=3, range=8] [L12] COND TRUE !(0 == i && i == range) VAL [i=3, range=8] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=4, range=8] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=4, range=8] [L11] COND TRUE 0 <= i && i <= range VAL [i=4, range=8] [L12] COND TRUE !(0 == i && i == range) VAL [i=4, range=8] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=5, range=8] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=5, range=8] [L11] COND TRUE 0 <= i && i <= range VAL [i=5, range=8] [L12] COND TRUE !(0 == i && i == range) VAL [i=5, range=8] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=6, range=8] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=6, range=8] [L11] COND TRUE 0 <= i && i <= range VAL [i=6, range=8] [L12] COND TRUE !(0 == i && i == range) VAL [i=6, range=8] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=7, range=8] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=7, range=8] [L11] COND TRUE 0 <= i && i <= range VAL [i=7, range=8] [L12] COND TRUE !(0 == i && i == range) VAL [i=7, range=8] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=8, range=8] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=8, range=8] [L11] COND TRUE 0 <= i && i <= range VAL [i=8, range=8] [L12] COND TRUE !(0 == i && i == range) VAL [i=8, range=8] [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 VAL [i=0, range=7] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=0, range=7] [L11] COND TRUE 0 <= i && i <= range VAL [i=0, range=7] [L12] COND TRUE !(0 == i && i == range) VAL [i=0, range=7] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=1, range=7] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=1, range=7] [L11] COND TRUE 0 <= i && i <= range VAL [i=1, range=7] [L12] COND TRUE !(0 == i && i == range) VAL [i=1, range=7] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=2, range=7] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=2, range=7] [L11] COND TRUE 0 <= i && i <= range VAL [i=2, range=7] [L12] COND TRUE !(0 == i && i == range) VAL [i=2, range=7] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=3, range=7] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=3, range=7] [L11] COND TRUE 0 <= i && i <= range VAL [i=3, range=7] [L12] COND TRUE !(0 == i && i == range) VAL [i=3, range=7] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=4, range=7] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=4, range=7] [L11] COND TRUE 0 <= i && i <= range VAL [i=4, range=7] [L12] COND TRUE !(0 == i && i == range) VAL [i=4, range=7] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=5, range=7] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=5, range=7] [L11] COND TRUE 0 <= i && i <= range VAL [i=5, range=7] [L12] COND TRUE !(0 == i && i == range) VAL [i=5, range=7] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=6, range=7] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=6, range=7] [L11] COND TRUE 0 <= i && i <= range VAL [i=6, range=7] [L12] COND TRUE !(0 == i && i == range) VAL [i=6, range=7] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=7, range=7] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=7, range=7] [L11] COND TRUE 0 <= i && i <= range VAL [i=7, range=7] [L12] COND TRUE !(0 == i && i == range) VAL [i=7, range=7] [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 VAL [i=0, range=6] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=0, range=6] [L11] COND TRUE 0 <= i && i <= range VAL [i=0, range=6] [L12] COND TRUE !(0 == i && i == range) VAL [i=0, range=6] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=1, range=6] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=1, range=6] [L11] COND TRUE 0 <= i && i <= range VAL [i=1, range=6] [L12] COND TRUE !(0 == i && i == range) VAL [i=1, range=6] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=2, range=6] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=2, range=6] [L11] COND TRUE 0 <= i && i <= range VAL [i=2, range=6] [L12] COND TRUE !(0 == i && i == range) VAL [i=2, range=6] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=3, range=6] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=3, range=6] [L11] COND TRUE 0 <= i && i <= range VAL [i=3, range=6] [L12] COND TRUE !(0 == i && i == range) VAL [i=3, range=6] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=4, range=6] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=4, range=6] [L11] COND TRUE 0 <= i && i <= range VAL [i=4, range=6] [L12] COND TRUE !(0 == i && i == range) VAL [i=4, range=6] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=5, range=6] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=5, range=6] [L11] COND TRUE 0 <= i && i <= range VAL [i=5, range=6] [L12] COND TRUE !(0 == i && i == range) VAL [i=5, range=6] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=6, range=6] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=6, range=6] [L11] COND TRUE 0 <= i && i <= range VAL [i=6, range=6] [L12] COND TRUE !(0 == i && i == range) VAL [i=6, range=6] [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 VAL [i=0, range=5] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=0, range=5] [L11] COND TRUE 0 <= i && i <= range VAL [i=0, range=5] [L12] COND TRUE !(0 == i && i == range) VAL [i=0, range=5] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=1, range=5] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=1, range=5] [L11] COND TRUE 0 <= i && i <= range VAL [i=1, range=5] [L12] COND TRUE !(0 == i && i == range) VAL [i=1, range=5] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=2, range=5] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=2, range=5] [L11] COND TRUE 0 <= i && i <= range VAL [i=2, range=5] [L12] COND TRUE !(0 == i && i == range) VAL [i=2, range=5] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=3, range=5] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=3, range=5] [L11] COND TRUE 0 <= i && i <= range VAL [i=3, range=5] [L12] COND TRUE !(0 == i && i == range) VAL [i=3, range=5] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=4, range=5] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=4, range=5] [L11] COND TRUE 0 <= i && i <= range VAL [i=4, range=5] [L12] COND TRUE !(0 == i && i == range) VAL [i=4, range=5] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=5, range=5] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=5, range=5] [L11] COND TRUE 0 <= i && i <= range VAL [i=5, range=5] [L12] COND TRUE !(0 == i && i == range) VAL [i=5, range=5] [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 VAL [i=0, range=4] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=0, range=4] [L11] COND TRUE 0 <= i && i <= range VAL [i=0, range=4] [L12] COND TRUE !(0 == i && i == range) VAL [i=0, range=4] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=1, range=4] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=1, range=4] [L11] COND TRUE 0 <= i && i <= range VAL [i=1, range=4] [L12] COND TRUE !(0 == i && i == range) VAL [i=1, range=4] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=2, range=4] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=2, range=4] [L11] COND TRUE 0 <= i && i <= range VAL [i=2, range=4] [L12] COND TRUE !(0 == i && i == range) VAL [i=2, range=4] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=3, range=4] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=3, range=4] [L11] COND TRUE 0 <= i && i <= range VAL [i=3, range=4] [L12] COND TRUE !(0 == i && i == range) VAL [i=3, range=4] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=4, range=4] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=4, range=4] [L11] COND TRUE 0 <= i && i <= range VAL [i=4, range=4] [L12] COND TRUE !(0 == i && i == range) VAL [i=4, range=4] [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 VAL [i=0, range=3] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=0, range=3] [L11] COND TRUE 0 <= i && i <= range VAL [i=0, range=3] [L12] COND TRUE !(0 == i && i == range) VAL [i=0, range=3] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=1, range=3] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=1, range=3] [L11] COND TRUE 0 <= i && i <= range VAL [i=1, range=3] [L12] COND TRUE !(0 == i && i == range) VAL [i=1, range=3] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=2, range=3] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=2, range=3] [L11] COND TRUE 0 <= i && i <= range VAL [i=2, range=3] [L12] COND TRUE !(0 == i && i == range) VAL [i=2, range=3] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=3, range=3] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=3, range=3] [L11] COND TRUE 0 <= i && i <= range VAL [i=3, range=3] [L12] COND TRUE !(0 == i && i == range) VAL [i=3, range=3] [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 VAL [i=0, range=2] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=0, range=2] [L11] COND TRUE 0 <= i && i <= range VAL [i=0, range=2] [L12] COND TRUE !(0 == i && i == range) VAL [i=0, range=2] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=1, range=2] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=1, range=2] [L11] COND TRUE 0 <= i && i <= range VAL [i=1, range=2] [L12] COND TRUE !(0 == i && i == range) VAL [i=1, range=2] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=2, range=2] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=2, range=2] [L11] COND TRUE 0 <= i && i <= range VAL [i=2, range=2] [L12] COND TRUE !(0 == i && i == range) VAL [i=2, range=2] [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 VAL [i=0, range=1] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=0, range=1] [L11] COND TRUE 0 <= i && i <= range VAL [i=0, range=1] [L12] COND TRUE !(0 == i && i == range) VAL [i=0, range=1] [L13] COND FALSE !(i == range) [L17] i = i+1 VAL [i=1, range=1] [L11] COND FALSE !(0 <= i && i <= range) VAL [i=1, range=1] [L11] COND TRUE 0 <= i && i <= range VAL [i=1, range=1] [L12] COND TRUE !(0 == i && i == range) VAL [i=1, range=1] [L13] COND TRUE i == range [L14] i = 0 [L15] range = range-1 VAL [i=0, range=0] Loop: [L11] COND FALSE !(0 <= i && i <= range) [L11] COND TRUE 0 <= i && i <= range [L12] COND FALSE !(!(0 == i && i == range)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2024-11-08 18:36:35,617 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (32)] Forceful destruction successful, exit code 0 [2024-11-08 18:36:35,805 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (31)] Ended with exit code 0 [2024-11-08 18:36:36,005 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (30)] Ended with exit code 0 [2024-11-08 18:36:36,205 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (29)] Ended with exit code 0 [2024-11-08 18:36:36,405 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (28)] Forceful destruction successful, exit code 0 [2024-11-08 18:36:36,605 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (27)] Forceful destruction successful, exit code 0 [2024-11-08 18:36:36,805 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (26)] Ended with exit code 0 [2024-11-08 18:36:37,005 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (20)] Forceful destruction successful, exit code 0 [2024-11-08 18:36:37,205 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Ended with exit code 0 [2024-11-08 18:36:37,409 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_162405d6-6023-4d82-ac58-e18a94f32321/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)