./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/kundu.cil.c --full-output --architecture 32bit
--------------------------------------------------------------------------------
Checking for termination
Using default analysis
Version a0165632
Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2995450b-1a7f-4efe-a580-fe680ef040d7/bin/uautomizer-verify-jihMAELWvX/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2995450b-1a7f-4efe-a580-fe680ef040d7/bin/uautomizer-verify-jihMAELWvX/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2995450b-1a7f-4efe-a580-fe680ef040d7/bin/uautomizer-verify-jihMAELWvX/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2995450b-1a7f-4efe-a580-fe680ef040d7/bin/uautomizer-verify-jihMAELWvX/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/kundu.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2995450b-1a7f-4efe-a580-fe680ef040d7/bin/uautomizer-verify-jihMAELWvX/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2995450b-1a7f-4efe-a580-fe680ef040d7/bin/uautomizer-verify-jihMAELWvX --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) )
--witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 941010afb19994aa6e2e07f5c4b80f87a4c5e60b4e0ef3217e91339d9dc3aacb
--- Real Ultimate output ---
This is Ultimate 0.2.5-dev-a016563
[2024-11-08 16:34:18,067 INFO L188 SettingsManager]: Resetting all preferences to default values...
[2024-11-08 16:34:18,182 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2995450b-1a7f-4efe-a580-fe680ef040d7/bin/uautomizer-verify-jihMAELWvX/config/svcomp-Termination-32bit-Automizer_Default.epf
[2024-11-08 16:34:18,187 WARN L101 SettingsManager]: Preference file contains the following unknown settings:
[2024-11-08 16:34:18,188 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class
[2024-11-08 16:34:18,235 INFO L130 SettingsManager]: Preferences different from defaults after loading the file:
[2024-11-08 16:34:18,235 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults:
[2024-11-08 16:34:18,236 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR;
[2024-11-08 16:34:18,237 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults:
[2024-11-08 16:34:18,239 INFO L153 SettingsManager]: * Use memory slicer=true
[2024-11-08 16:34:18,240 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults:
[2024-11-08 16:34:18,240 INFO L153 SettingsManager]: * Create parallel compositions if possible=false
[2024-11-08 16:34:18,241 INFO L153 SettingsManager]: * Use SBE=true
[2024-11-08 16:34:18,243 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults:
[2024-11-08 16:34:18,243 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3
[2024-11-08 16:34:18,244 INFO L153 SettingsManager]: * Use old map elimination=false
[2024-11-08 16:34:18,244 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false
[2024-11-08 16:34:18,245 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true
[2024-11-08 16:34:18,245 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES
[2024-11-08 16:34:18,246 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults:
[2024-11-08 16:34:18,246 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME
[2024-11-08 16:34:18,249 INFO L153 SettingsManager]: * sizeof long=4
[2024-11-08 16:34:18,251 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true
[2024-11-08 16:34:18,252 INFO L153 SettingsManager]: * sizeof POINTER=4
[2024-11-08 16:34:18,256 INFO L153 SettingsManager]: * Check division by zero=IGNORE
[2024-11-08 16:34:18,257 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME
[2024-11-08 16:34:18,257 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME
[2024-11-08 16:34:18,258 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME
[2024-11-08 16:34:18,258 INFO L153 SettingsManager]: * Allow undefined functions=false
[2024-11-08 16:34:18,258 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false
[2024-11-08 16:34:18,259 INFO L153 SettingsManager]: * sizeof long double=12
[2024-11-08 16:34:18,259 INFO L153 SettingsManager]: * Check if freed pointer was valid=false
[2024-11-08 16:34:18,259 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false
[2024-11-08 16:34:18,262 INFO L153 SettingsManager]: * Use constant arrays=true
[2024-11-08 16:34:18,266 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults:
[2024-11-08 16:34:18,267 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements
[2024-11-08 16:34:18,267 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults:
[2024-11-08 16:34:18,267 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL
[2024-11-08 16:34:18,268 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults:
[2024-11-08 16:34:18,268 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR
WARNING: An illegal reflective access operation has occurred
WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2995450b-1a7f-4efe-a580-fe680ef040d7/bin/uautomizer-verify-jihMAELWvX/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int)
WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1
WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations
WARNING: All illegal access operations will be denied in a future release
Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main
Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2995450b-1a7f-4efe-a580-fe680ef040d7/bin/uautomizer-verify-jihMAELWvX
Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness
Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false
Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) )
Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer
Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit
Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 941010afb19994aa6e2e07f5c4b80f87a4c5e60b4e0ef3217e91339d9dc3aacb
[2024-11-08 16:34:18,585 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp
[2024-11-08 16:34:18,625 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized
[2024-11-08 16:34:18,628 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected.
[2024-11-08 16:34:18,631 INFO L270 PluginConnector]: Initializing CDTParser...
[2024-11-08 16:34:18,631 INFO L274 PluginConnector]: CDTParser initialized
[2024-11-08 16:34:18,633 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2995450b-1a7f-4efe-a580-fe680ef040d7/bin/uautomizer-verify-jihMAELWvX/../../sv-benchmarks/c/systemc/kundu.cil.c
Unable to find full path for "g++"
[2024-11-08 16:34:20,926 INFO L533 CDTParser]: Created temporary CDT project at NULL
[2024-11-08 16:34:21,240 INFO L384 CDTParser]: Found 1 translation units.
[2024-11-08 16:34:21,245 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2995450b-1a7f-4efe-a580-fe680ef040d7/sv-benchmarks/c/systemc/kundu.cil.c
[2024-11-08 16:34:21,266 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2995450b-1a7f-4efe-a580-fe680ef040d7/bin/uautomizer-verify-jihMAELWvX/data/14e4b8aa1/93427be3c2a74410899c8dfa4145fa6d/FLAG82df1a456
[2024-11-08 16:34:21,286 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2995450b-1a7f-4efe-a580-fe680ef040d7/bin/uautomizer-verify-jihMAELWvX/data/14e4b8aa1/93427be3c2a74410899c8dfa4145fa6d
[2024-11-08 16:34:21,289 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] #######################
[2024-11-08 16:34:21,291 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements.
[2024-11-08 16:34:21,292 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator----------------------------
[2024-11-08 16:34:21,292 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator...
[2024-11-08 16:34:21,298 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized
[2024-11-08 16:34:21,299 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 08.11 04:34:21" (1/1) ...
[2024-11-08 16:34:21,300 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@1092077e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 04:34:21, skipping insertion in model container
[2024-11-08 16:34:21,301 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 08.11 04:34:21" (1/1) ...
[2024-11-08 16:34:21,342 INFO L175 MainTranslator]: Built tables and reachable declarations
[2024-11-08 16:34:21,673 INFO L210 PostProcessor]: Analyzing one entry point: main
[2024-11-08 16:34:21,700 INFO L200 MainTranslator]: Completed pre-run
[2024-11-08 16:34:21,756 INFO L210 PostProcessor]: Analyzing one entry point: main
[2024-11-08 16:34:21,781 INFO L204 MainTranslator]: Completed translation
[2024-11-08 16:34:21,782 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 04:34:21 WrapperNode
[2024-11-08 16:34:21,782 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator----------------------------
[2024-11-08 16:34:21,783 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner----------------------------
[2024-11-08 16:34:21,783 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner...
[2024-11-08 16:34:21,784 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized
[2024-11-08 16:34:21,794 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 04:34:21" (1/1) ...
[2024-11-08 16:34:21,813 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 04:34:21" (1/1) ...
[2024-11-08 16:34:21,867 INFO L138 Inliner]: procedures = 34, calls = 41, calls flagged for inlining = 36, calls inlined = 49, statements flattened = 535
[2024-11-08 16:34:21,868 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner----------------------------
[2024-11-08 16:34:21,869 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor----------------------------
[2024-11-08 16:34:21,869 INFO L270 PluginConnector]: Initializing Boogie Preprocessor...
[2024-11-08 16:34:21,869 INFO L274 PluginConnector]: Boogie Preprocessor initialized
[2024-11-08 16:34:21,884 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 04:34:21" (1/1) ...
[2024-11-08 16:34:21,885 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 04:34:21" (1/1) ...
[2024-11-08 16:34:21,889 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 04:34:21" (1/1) ...
[2024-11-08 16:34:21,930 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0].
[2024-11-08 16:34:21,930 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 04:34:21" (1/1) ...
[2024-11-08 16:34:21,931 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 04:34:21" (1/1) ...
[2024-11-08 16:34:21,952 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 04:34:21" (1/1) ...
[2024-11-08 16:34:21,969 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 04:34:21" (1/1) ...
[2024-11-08 16:34:21,975 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 04:34:21" (1/1) ...
[2024-11-08 16:34:21,981 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 04:34:21" (1/1) ...
[2024-11-08 16:34:21,990 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor----------------------------
[2024-11-08 16:34:21,991 INFO L112 PluginConnector]: ------------------------RCFGBuilder----------------------------
[2024-11-08 16:34:21,994 INFO L270 PluginConnector]: Initializing RCFGBuilder...
[2024-11-08 16:34:21,995 INFO L274 PluginConnector]: RCFGBuilder initialized
[2024-11-08 16:34:21,996 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 04:34:21" (1/1) ...
[2024-11-08 16:34:22,012 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000
[2024-11-08 16:34:22,030 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2995450b-1a7f-4efe-a580-fe680ef040d7/bin/uautomizer-verify-jihMAELWvX/z3
[2024-11-08 16:34:22,048 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2995450b-1a7f-4efe-a580-fe680ef040d7/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null)
[2024-11-08 16:34:22,053 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2995450b-1a7f-4efe-a580-fe680ef040d7/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process
[2024-11-08 16:34:22,103 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit
[2024-11-08 16:34:22,104 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0
[2024-11-08 16:34:22,104 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start
[2024-11-08 16:34:22,104 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start
[2024-11-08 16:34:22,237 INFO L238 CfgBuilder]: Building ICFG
[2024-11-08 16:34:22,241 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation
[2024-11-08 16:34:23,015 INFO L? ?]: Removed 101 outVars from TransFormulas that were not future-live.
[2024-11-08 16:34:23,015 INFO L287 CfgBuilder]: Performing block encoding
[2024-11-08 16:34:23,054 INFO L311 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start)
[2024-11-08 16:34:23,055 INFO L316 CfgBuilder]: Removed 2 assume(true) statements.
[2024-11-08 16:34:23,055 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 08.11 04:34:23 BoogieIcfgContainer
[2024-11-08 16:34:23,060 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder----------------------------
[2024-11-08 16:34:23,061 INFO L112 PluginConnector]: ------------------------BuchiAutomizer----------------------------
[2024-11-08 16:34:23,062 INFO L270 PluginConnector]: Initializing BuchiAutomizer...
[2024-11-08 16:34:23,067 INFO L274 PluginConnector]: BuchiAutomizer initialized
[2024-11-08 16:34:23,068 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis
[2024-11-08 16:34:23,070 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 08.11 04:34:21" (1/3) ...
[2024-11-08 16:34:23,072 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@41a69baa and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 08.11 04:34:23, skipping insertion in model container
[2024-11-08 16:34:23,073 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis
[2024-11-08 16:34:23,073 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 04:34:21" (2/3) ...
[2024-11-08 16:34:23,075 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@41a69baa and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 08.11 04:34:23, skipping insertion in model container
[2024-11-08 16:34:23,075 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis
[2024-11-08 16:34:23,075 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 08.11 04:34:23" (3/3) ...
[2024-11-08 16:34:23,077 INFO L332 chiAutomizerObserver]: Analyzing ICFG kundu.cil.c
[2024-11-08 16:34:23,171 INFO L300 stractBuchiCegarLoop]: Interprodecural is true
[2024-11-08 16:34:23,172 INFO L301 stractBuchiCegarLoop]: Hoare is None
[2024-11-08 16:34:23,173 INFO L302 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates
[2024-11-08 16:34:23,173 INFO L303 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE
[2024-11-08 16:34:23,173 INFO L304 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION
[2024-11-08 16:34:23,173 INFO L305 stractBuchiCegarLoop]: Difference is false
[2024-11-08 16:34:23,175 INFO L306 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA
[2024-11-08 16:34:23,175 INFO L310 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ========
[2024-11-08 16:34:23,183 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 198 states, 197 states have (on average 1.4873096446700507) internal successors, (293), 197 states have internal predecessors, (293), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 16:34:23,234 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 161
[2024-11-08 16:34:23,236 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2024-11-08 16:34:23,238 INFO L119 BuchiIsEmpty]: Starting construction of run
[2024-11-08 16:34:23,251 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 16:34:23,252 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 16:34:23,252 INFO L332 stractBuchiCegarLoop]: ======== Iteration 1 ============
[2024-11-08 16:34:23,255 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 198 states, 197 states have (on average 1.4873096446700507) internal successors, (293), 197 states have internal predecessors, (293), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 16:34:23,271 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 161
[2024-11-08 16:34:23,275 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2024-11-08 16:34:23,276 INFO L119 BuchiIsEmpty]: Starting construction of run
[2024-11-08 16:34:23,278 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 16:34:23,278 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 16:34:23,289 INFO L745 eck$LassoCheckResult]: Stem: 130#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 138#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 193#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 135#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 148#L305true assume !(1 == ~P_1_i~0);~P_1_st~0 := 2; 187#L305-2true assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 154#L310-1true assume !(1 == ~C_1_i~0);~C_1_st~0 := 2; 189#L315-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 77#fire_delta_events_returnLabel#1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 167#L118true assume !(1 == ~P_1_pc~0); 54#L118-2true is_P_1_triggered_~__retres1~0#1 := 0; 184#L129true is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 47#is_P_1_triggered_returnLabel#1true activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 4#L491true assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 188#L491-2true assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 59#L186true assume 1 == ~P_2_pc~0; 98#L187true assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1; 61#L197true is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 91#is_P_2_triggered_returnLabel#1true activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 45#L499true assume !(0 != activate_threads_~tmp___0~1#1); 145#L499-2true assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 122#L268true assume 1 == ~C_1_pc~0; 57#L269true assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 134#L289true is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 192#is_C_1_triggered_returnLabel#1true activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 123#L507true assume !(0 != activate_threads_~tmp___1~1#1); 30#L507-2true havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 182#reset_delta_events_returnLabel#1true assume { :end_inline_reset_delta_events } true; 40#L561-2true
[2024-11-08 16:34:23,292 INFO L747 eck$LassoCheckResult]: Loop: 40#L561-2true assume !false; 159#L562true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 100#L397true assume !true; 68#eval_returnLabel#1true havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 92#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 41#fire_delta_events_returnLabel#2true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 185#L118-6true assume !(1 == ~P_1_pc~0); 5#L118-8true is_P_1_triggered_~__retres1~0#1 := 0; 16#L129-2true is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 43#is_P_1_triggered_returnLabel#3true activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 84#L491-6true assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 28#L491-8true assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 58#L186-6true assume !(1 == ~P_2_pc~0); 29#L186-8true is_P_2_triggered_~__retres1~1#1 := 0; 181#L197-2true is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 196#is_P_2_triggered_returnLabel#3true activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 131#L499-6true assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 129#L499-8true assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 11#L268-6true assume 1 == ~C_1_pc~0; 105#L269-2true assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 119#L289-2true is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 102#is_C_1_triggered_returnLabel#3true activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 22#L507-6true assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 163#L507-8true havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 79#reset_delta_events_returnLabel#2true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 63#L328-1true assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 67#L345-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 170#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 2#L580true assume !(0 == start_simulation_~tmp~3#1); 13#L580-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 60#L328-2true assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 186#L345-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 36#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 162#L535true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 114#L542true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 107#stop_simulation_returnLabel#1true start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 64#L593true assume !(0 != start_simulation_~tmp___0~2#1); 40#L561-2true
[2024-11-08 16:34:23,300 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 16:34:23,301 INFO L85 PathProgramCache]: Analyzing trace with hash 1332213672, now seen corresponding path program 1 times
[2024-11-08 16:34:23,357 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 16:34:23,358 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [89659742]
[2024-11-08 16:34:23,358 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 16:34:23,363 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 16:34:23,574 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-11-08 16:34:23,745 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2024-11-08 16:34:23,746 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2024-11-08 16:34:23,746 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [89659742]
[2024-11-08 16:34:23,747 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [89659742] provided 1 perfect and 0 imperfect interpolant sequences
[2024-11-08 16:34:23,748 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2024-11-08 16:34:23,748 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2024-11-08 16:34:23,750 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [608378426]
[2024-11-08 16:34:23,751 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2024-11-08 16:34:23,757 INFO L750 eck$LassoCheckResult]: stem already infeasible
[2024-11-08 16:34:23,758 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 16:34:23,758 INFO L85 PathProgramCache]: Analyzing trace with hash 1801641132, now seen corresponding path program 1 times
[2024-11-08 16:34:23,758 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 16:34:23,759 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [672254280]
[2024-11-08 16:34:23,759 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 16:34:23,759 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 16:34:23,772 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-11-08 16:34:23,806 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2024-11-08 16:34:23,806 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2024-11-08 16:34:23,807 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [672254280]
[2024-11-08 16:34:23,810 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [672254280] provided 1 perfect and 0 imperfect interpolant sequences
[2024-11-08 16:34:23,810 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2024-11-08 16:34:23,810 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2
[2024-11-08 16:34:23,811 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [324061524]
[2024-11-08 16:34:23,811 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2024-11-08 16:34:23,812 INFO L762 eck$LassoCheckResult]: loop already infeasible
[2024-11-08 16:34:23,813 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2024-11-08 16:34:23,846 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2024-11-08 16:34:23,847 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2024-11-08 16:34:23,849 INFO L87 Difference]: Start difference. First operand has 198 states, 197 states have (on average 1.4873096446700507) internal successors, (293), 197 states have internal predecessors, (293), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 9.333333333333334) internal successors, (28), 3 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 16:34:23,886 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2024-11-08 16:34:23,886 INFO L93 Difference]: Finished difference Result 190 states and 276 transitions.
[2024-11-08 16:34:23,888 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 190 states and 276 transitions.
[2024-11-08 16:34:23,892 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 149
[2024-11-08 16:34:23,898 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 190 states to 182 states and 268 transitions.
[2024-11-08 16:34:23,900 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 182
[2024-11-08 16:34:23,901 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 182
[2024-11-08 16:34:23,902 INFO L73 IsDeterministic]: Start isDeterministic. Operand 182 states and 268 transitions.
[2024-11-08 16:34:23,903 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2024-11-08 16:34:23,903 INFO L218 hiAutomatonCegarLoop]: Abstraction has 182 states and 268 transitions.
[2024-11-08 16:34:23,923 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 182 states and 268 transitions.
[2024-11-08 16:34:23,953 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 182 to 182.
[2024-11-08 16:34:23,955 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 182 states, 182 states have (on average 1.4725274725274726) internal successors, (268), 181 states have internal predecessors, (268), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 16:34:23,957 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 182 states to 182 states and 268 transitions.
[2024-11-08 16:34:23,963 INFO L240 hiAutomatonCegarLoop]: Abstraction has 182 states and 268 transitions.
[2024-11-08 16:34:23,967 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states.
[2024-11-08 16:34:23,974 INFO L425 stractBuchiCegarLoop]: Abstraction has 182 states and 268 transitions.
[2024-11-08 16:34:23,975 INFO L332 stractBuchiCegarLoop]: ======== Iteration 2 ============
[2024-11-08 16:34:23,975 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 182 states and 268 transitions.
[2024-11-08 16:34:23,984 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 149
[2024-11-08 16:34:23,984 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2024-11-08 16:34:23,984 INFO L119 BuchiIsEmpty]: Starting construction of run
[2024-11-08 16:34:23,989 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 16:34:23,990 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 16:34:23,990 INFO L745 eck$LassoCheckResult]: Stem: 495#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 496#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 523#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 513#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 514#L305 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 542#L305-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 555#L310-1 assume !(1 == ~C_1_i~0);~C_1_st~0 := 2; 556#L315-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 568#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 566#L118 assume !(1 == ~P_1_pc~0); 536#L118-2 is_P_1_triggered_~__retres1~0#1 := 0; 537#L129 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 532#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 406#L491 assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 407#L491-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 544#L186 assume 1 == ~P_2_pc~0; 545#L187 assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1; 429#L197 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 549#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 528#L499 assume !(0 != activate_threads_~tmp___0~1#1); 529#L499-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 470#L268 assume 1 == ~C_1_pc~0; 472#L269 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 507#L289 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 508#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 473#L507 assume !(0 != activate_threads_~tmp___1~1#1); 474#L507-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 487#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 518#L561-2
[2024-11-08 16:34:23,991 INFO L747 eck$LassoCheckResult]: Loop: 518#L561-2 assume !false; 519#L562 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 424#L397 assume !false; 446#L358 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 447#L328 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 489#L345 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 442#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 443#L362 assume !(0 != eval_~tmp___2~0#1); 560#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 561#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 520#fire_delta_events_returnLabel#2 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 521#L118-6 assume !(1 == ~P_1_pc~0); 408#L118-8 is_P_1_triggered_~__retres1~0#1 := 0; 409#L129-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 441#is_P_1_triggered_returnLabel#3 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 525#L491-6 assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 481#L491-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 482#L186-6 assume !(1 == ~P_2_pc~0); 483#L186-8 is_P_2_triggered_~__retres1~1#1 := 0; 484#L197-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 576#is_P_2_triggered_returnLabel#3 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 499#L499-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 494#L499-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 432#L268-6 assume 1 == ~C_1_pc~0; 434#L269-2 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 448#L289-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 449#is_C_1_triggered_returnLabel#3 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 463#L507-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 464#L507-8 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 562#reset_delta_events_returnLabel#2 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 553#L328-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 411#L345-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 558#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 397#L580 assume !(0 == start_simulation_~tmp~3#1); 398#L580-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 438#L328-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 547#L345-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 509#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 510#L535 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 417#L542 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 418#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 554#L593 assume !(0 != start_simulation_~tmp___0~2#1); 518#L561-2
[2024-11-08 16:34:23,995 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 16:34:23,996 INFO L85 PathProgramCache]: Analyzing trace with hash 1466227178, now seen corresponding path program 1 times
[2024-11-08 16:34:23,996 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 16:34:23,997 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [704262293]
[2024-11-08 16:34:23,997 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 16:34:23,997 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 16:34:24,034 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-11-08 16:34:24,085 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2024-11-08 16:34:24,086 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2024-11-08 16:34:24,086 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [704262293]
[2024-11-08 16:34:24,086 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [704262293] provided 1 perfect and 0 imperfect interpolant sequences
[2024-11-08 16:34:24,086 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2024-11-08 16:34:24,087 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2024-11-08 16:34:24,087 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [639456851]
[2024-11-08 16:34:24,087 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2024-11-08 16:34:24,087 INFO L750 eck$LassoCheckResult]: stem already infeasible
[2024-11-08 16:34:24,088 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 16:34:24,088 INFO L85 PathProgramCache]: Analyzing trace with hash -806815871, now seen corresponding path program 1 times
[2024-11-08 16:34:24,089 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 16:34:24,089 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [286240768]
[2024-11-08 16:34:24,089 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 16:34:24,089 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 16:34:24,127 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-11-08 16:34:24,265 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2024-11-08 16:34:24,266 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2024-11-08 16:34:24,267 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [286240768]
[2024-11-08 16:34:24,267 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [286240768] provided 1 perfect and 0 imperfect interpolant sequences
[2024-11-08 16:34:24,267 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2024-11-08 16:34:24,267 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5
[2024-11-08 16:34:24,268 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1877352759]
[2024-11-08 16:34:24,268 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2024-11-08 16:34:24,268 INFO L762 eck$LassoCheckResult]: loop already infeasible
[2024-11-08 16:34:24,268 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2024-11-08 16:34:24,269 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2024-11-08 16:34:24,269 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2024-11-08 16:34:24,272 INFO L87 Difference]: Start difference. First operand 182 states and 268 transitions. cyclomatic complexity: 87 Second operand has 3 states, 3 states have (on average 9.333333333333334) internal successors, (28), 3 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 16:34:24,300 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2024-11-08 16:34:24,301 INFO L93 Difference]: Finished difference Result 182 states and 267 transitions.
[2024-11-08 16:34:24,301 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 182 states and 267 transitions.
[2024-11-08 16:34:24,303 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 149
[2024-11-08 16:34:24,305 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 182 states to 182 states and 267 transitions.
[2024-11-08 16:34:24,306 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 182
[2024-11-08 16:34:24,306 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 182
[2024-11-08 16:34:24,307 INFO L73 IsDeterministic]: Start isDeterministic. Operand 182 states and 267 transitions.
[2024-11-08 16:34:24,308 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2024-11-08 16:34:24,308 INFO L218 hiAutomatonCegarLoop]: Abstraction has 182 states and 267 transitions.
[2024-11-08 16:34:24,309 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 182 states and 267 transitions.
[2024-11-08 16:34:24,316 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 182 to 182.
[2024-11-08 16:34:24,317 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 182 states, 182 states have (on average 1.467032967032967) internal successors, (267), 181 states have internal predecessors, (267), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 16:34:24,318 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 182 states to 182 states and 267 transitions.
[2024-11-08 16:34:24,319 INFO L240 hiAutomatonCegarLoop]: Abstraction has 182 states and 267 transitions.
[2024-11-08 16:34:24,319 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states.
[2024-11-08 16:34:24,320 INFO L425 stractBuchiCegarLoop]: Abstraction has 182 states and 267 transitions.
[2024-11-08 16:34:24,320 INFO L332 stractBuchiCegarLoop]: ======== Iteration 3 ============
[2024-11-08 16:34:24,320 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 182 states and 267 transitions.
[2024-11-08 16:34:24,322 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 149
[2024-11-08 16:34:24,322 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2024-11-08 16:34:24,322 INFO L119 BuchiIsEmpty]: Starting construction of run
[2024-11-08 16:34:24,324 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 16:34:24,324 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 16:34:24,324 INFO L745 eck$LassoCheckResult]: Stem: 868#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 869#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 895#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 885#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 886#L305 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 915#L305-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 928#L310-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 929#L315-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 941#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 939#L118 assume !(1 == ~P_1_pc~0); 909#L118-2 is_P_1_triggered_~__retres1~0#1 := 0; 910#L129 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 905#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 777#L491 assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 778#L491-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 917#L186 assume 1 == ~P_2_pc~0; 918#L187 assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1; 797#L197 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 922#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 900#L499 assume !(0 != activate_threads_~tmp___0~1#1); 901#L499-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 842#L268 assume 1 == ~C_1_pc~0; 844#L269 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 880#L289 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 881#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 845#L507 assume !(0 != activate_threads_~tmp___1~1#1); 846#L507-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 858#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 890#L561-2
[2024-11-08 16:34:24,325 INFO L747 eck$LassoCheckResult]: Loop: 890#L561-2 assume !false; 891#L562 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 799#L397 assume !false; 817#L358 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 818#L328 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 860#L345 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 814#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 815#L362 assume !(0 != eval_~tmp___2~0#1); 933#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 934#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 893#fire_delta_events_returnLabel#2 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 894#L118-6 assume 1 == ~P_1_pc~0; 902#L119-2 assume 1 == ~P_1_ev~0;is_P_1_triggered_~__retres1~0#1 := 1; 782#L129-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 816#is_P_1_triggered_returnLabel#3 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 898#L491-6 assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 854#L491-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 855#L186-6 assume 1 == ~P_2_pc~0; 916#L187-2 assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1; 857#L197-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 949#is_P_2_triggered_returnLabel#3 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 872#L499-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 867#L499-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 805#L268-6 assume 1 == ~C_1_pc~0; 807#L269-2 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 821#L289-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 822#is_C_1_triggered_returnLabel#3 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 836#L507-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 837#L507-8 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 935#reset_delta_events_returnLabel#2 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 926#L328-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 784#L345-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 931#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 770#L580 assume !(0 == start_simulation_~tmp~3#1); 771#L580-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 811#L328-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 920#L345-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 882#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 883#L535 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 790#L542 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 791#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 927#L593 assume !(0 != start_simulation_~tmp___0~2#1); 890#L561-2
[2024-11-08 16:34:24,326 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 16:34:24,326 INFO L85 PathProgramCache]: Analyzing trace with hash 1247372460, now seen corresponding path program 1 times
[2024-11-08 16:34:24,326 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 16:34:24,330 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [137610942]
[2024-11-08 16:34:24,331 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 16:34:24,331 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 16:34:24,362 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-11-08 16:34:24,475 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2024-11-08 16:34:24,476 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2024-11-08 16:34:24,476 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [137610942]
[2024-11-08 16:34:24,476 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [137610942] provided 1 perfect and 0 imperfect interpolant sequences
[2024-11-08 16:34:24,476 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2024-11-08 16:34:24,476 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5
[2024-11-08 16:34:24,477 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [56162538]
[2024-11-08 16:34:24,477 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2024-11-08 16:34:24,477 INFO L750 eck$LassoCheckResult]: stem already infeasible
[2024-11-08 16:34:24,478 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 16:34:24,478 INFO L85 PathProgramCache]: Analyzing trace with hash -1272708161, now seen corresponding path program 1 times
[2024-11-08 16:34:24,481 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 16:34:24,482 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [147244556]
[2024-11-08 16:34:24,482 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 16:34:24,482 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 16:34:24,509 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-11-08 16:34:24,621 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2024-11-08 16:34:24,621 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2024-11-08 16:34:24,621 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [147244556]
[2024-11-08 16:34:24,621 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [147244556] provided 1 perfect and 0 imperfect interpolant sequences
[2024-11-08 16:34:24,622 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2024-11-08 16:34:24,622 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5
[2024-11-08 16:34:24,622 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [897187519]
[2024-11-08 16:34:24,622 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2024-11-08 16:34:24,623 INFO L762 eck$LassoCheckResult]: loop already infeasible
[2024-11-08 16:34:24,623 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2024-11-08 16:34:24,623 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants.
[2024-11-08 16:34:24,624 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20
[2024-11-08 16:34:24,624 INFO L87 Difference]: Start difference. First operand 182 states and 267 transitions. cyclomatic complexity: 86 Second operand has 5 states, 5 states have (on average 5.6) internal successors, (28), 5 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 16:34:24,780 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2024-11-08 16:34:24,780 INFO L93 Difference]: Finished difference Result 194 states and 279 transitions.
[2024-11-08 16:34:24,780 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 194 states and 279 transitions.
[2024-11-08 16:34:24,783 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 158
[2024-11-08 16:34:24,785 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 194 states to 194 states and 279 transitions.
[2024-11-08 16:34:24,785 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 194
[2024-11-08 16:34:24,786 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 194
[2024-11-08 16:34:24,786 INFO L73 IsDeterministic]: Start isDeterministic. Operand 194 states and 279 transitions.
[2024-11-08 16:34:24,787 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2024-11-08 16:34:24,787 INFO L218 hiAutomatonCegarLoop]: Abstraction has 194 states and 279 transitions.
[2024-11-08 16:34:24,788 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 194 states and 279 transitions.
[2024-11-08 16:34:24,796 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 194 to 194.
[2024-11-08 16:34:24,797 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 194 states, 194 states have (on average 1.4381443298969072) internal successors, (279), 193 states have internal predecessors, (279), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 16:34:24,798 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 194 states to 194 states and 279 transitions.
[2024-11-08 16:34:24,799 INFO L240 hiAutomatonCegarLoop]: Abstraction has 194 states and 279 transitions.
[2024-11-08 16:34:24,799 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states.
[2024-11-08 16:34:24,800 INFO L425 stractBuchiCegarLoop]: Abstraction has 194 states and 279 transitions.
[2024-11-08 16:34:24,800 INFO L332 stractBuchiCegarLoop]: ======== Iteration 4 ============
[2024-11-08 16:34:24,800 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 194 states and 279 transitions.
[2024-11-08 16:34:24,802 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 158
[2024-11-08 16:34:24,802 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2024-11-08 16:34:24,803 INFO L119 BuchiIsEmpty]: Starting construction of run
[2024-11-08 16:34:24,804 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 16:34:24,804 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 16:34:24,804 INFO L745 eck$LassoCheckResult]: Stem: 1255#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 1256#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 1284#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1274#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1275#L305 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 1304#L305-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 1317#L310-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 1318#L315-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1330#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 1328#L118 assume !(1 == ~P_1_pc~0); 1298#L118-2 is_P_1_triggered_~__retres1~0#1 := 0; 1299#L129 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 1294#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1166#L491 assume !(0 != activate_threads_~tmp~1#1); 1167#L491-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 1306#L186 assume 1 == ~P_2_pc~0; 1307#L187 assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1; 1186#L197 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 1311#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1290#L499 assume !(0 != activate_threads_~tmp___0~1#1); 1291#L499-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 1230#L268 assume 1 == ~C_1_pc~0; 1232#L269 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 1268#L289 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 1269#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1233#L507 assume !(0 != activate_threads_~tmp___1~1#1); 1234#L507-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1247#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 1279#L561-2
[2024-11-08 16:34:24,805 INFO L747 eck$LassoCheckResult]: Loop: 1279#L561-2 assume !false; 1280#L562 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 1188#L397 assume !false; 1206#L358 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1207#L328 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1249#L345 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1202#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1203#L362 assume !(0 != eval_~tmp___2~0#1); 1322#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1323#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1281#fire_delta_events_returnLabel#2 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 1282#L118-6 assume !(1 == ~P_1_pc~0); 1168#L118-8 is_P_1_triggered_~__retres1~0#1 := 0; 1169#L129-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 1201#is_P_1_triggered_returnLabel#3 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1286#L491-6 assume !(0 != activate_threads_~tmp~1#1); 1241#L491-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 1242#L186-6 assume 1 == ~P_2_pc~0; 1305#L187-2 assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1; 1244#L197-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 1339#is_P_2_triggered_returnLabel#3 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1259#L499-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 1254#L499-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 1192#L268-6 assume 1 == ~C_1_pc~0; 1194#L269-2 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 1208#L289-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 1209#is_C_1_triggered_returnLabel#3 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1223#L507-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 1224#L507-8 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1324#reset_delta_events_returnLabel#2 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1315#L328-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1171#L345-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1320#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 1157#L580 assume !(0 == start_simulation_~tmp~3#1); 1158#L580-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1198#L328-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1309#L345-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1270#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 1271#L535 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1177#L542 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1178#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 1316#L593 assume !(0 != start_simulation_~tmp___0~2#1); 1279#L561-2
[2024-11-08 16:34:24,805 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 16:34:24,806 INFO L85 PathProgramCache]: Analyzing trace with hash -32491218, now seen corresponding path program 1 times
[2024-11-08 16:34:24,806 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 16:34:24,806 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [751474132]
[2024-11-08 16:34:24,806 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 16:34:24,807 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 16:34:24,819 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-11-08 16:34:24,975 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2024-11-08 16:34:24,975 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2024-11-08 16:34:24,975 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [751474132]
[2024-11-08 16:34:24,975 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [751474132] provided 1 perfect and 0 imperfect interpolant sequences
[2024-11-08 16:34:24,976 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2024-11-08 16:34:24,976 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4
[2024-11-08 16:34:24,976 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [631496284]
[2024-11-08 16:34:24,976 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2024-11-08 16:34:24,977 INFO L750 eck$LassoCheckResult]: stem already infeasible
[2024-11-08 16:34:24,977 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 16:34:24,980 INFO L85 PathProgramCache]: Analyzing trace with hash -1120951102, now seen corresponding path program 1 times
[2024-11-08 16:34:24,980 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 16:34:24,981 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1472746726]
[2024-11-08 16:34:24,981 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 16:34:24,981 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 16:34:25,005 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-11-08 16:34:25,089 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2024-11-08 16:34:25,090 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2024-11-08 16:34:25,092 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1472746726]
[2024-11-08 16:34:25,092 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1472746726] provided 1 perfect and 0 imperfect interpolant sequences
[2024-11-08 16:34:25,092 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2024-11-08 16:34:25,093 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5
[2024-11-08 16:34:25,093 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2051052065]
[2024-11-08 16:34:25,093 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2024-11-08 16:34:25,094 INFO L762 eck$LassoCheckResult]: loop already infeasible
[2024-11-08 16:34:25,094 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2024-11-08 16:34:25,096 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants.
[2024-11-08 16:34:25,097 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12
[2024-11-08 16:34:25,097 INFO L87 Difference]: Start difference. First operand 194 states and 279 transitions. cyclomatic complexity: 86 Second operand has 4 states, 4 states have (on average 7.0) internal successors, (28), 4 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 16:34:25,283 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2024-11-08 16:34:25,284 INFO L93 Difference]: Finished difference Result 487 states and 689 transitions.
[2024-11-08 16:34:25,284 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 487 states and 689 transitions.
[2024-11-08 16:34:25,294 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 424
[2024-11-08 16:34:25,298 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 487 states to 487 states and 689 transitions.
[2024-11-08 16:34:25,299 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 487
[2024-11-08 16:34:25,300 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 487
[2024-11-08 16:34:25,301 INFO L73 IsDeterministic]: Start isDeterministic. Operand 487 states and 689 transitions.
[2024-11-08 16:34:25,308 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2024-11-08 16:34:25,308 INFO L218 hiAutomatonCegarLoop]: Abstraction has 487 states and 689 transitions.
[2024-11-08 16:34:25,309 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 487 states and 689 transitions.
[2024-11-08 16:34:25,342 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 487 to 445.
[2024-11-08 16:34:25,346 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 445 states, 445 states have (on average 1.4247191011235956) internal successors, (634), 444 states have internal predecessors, (634), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 16:34:25,349 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 445 states to 445 states and 634 transitions.
[2024-11-08 16:34:25,353 INFO L240 hiAutomatonCegarLoop]: Abstraction has 445 states and 634 transitions.
[2024-11-08 16:34:25,354 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states.
[2024-11-08 16:34:25,357 INFO L425 stractBuchiCegarLoop]: Abstraction has 445 states and 634 transitions.
[2024-11-08 16:34:25,357 INFO L332 stractBuchiCegarLoop]: ======== Iteration 5 ============
[2024-11-08 16:34:25,360 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 445 states and 634 transitions.
[2024-11-08 16:34:25,364 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 408
[2024-11-08 16:34:25,365 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2024-11-08 16:34:25,365 INFO L119 BuchiIsEmpty]: Starting construction of run
[2024-11-08 16:34:25,366 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 16:34:25,366 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 16:34:25,367 INFO L745 eck$LassoCheckResult]: Stem: 1949#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 1950#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 1979#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1967#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1968#L305 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 2000#L305-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 2012#L310-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 2013#L315-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2028#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 2026#L118 assume !(1 == ~P_1_pc~0); 1994#L118-2 is_P_1_triggered_~__retres1~0#1 := 0; 1995#L129 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 1990#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1858#L491 assume !(0 != activate_threads_~tmp~1#1); 1859#L491-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 2002#L186 assume !(1 == ~P_2_pc~0); 1877#L186-2 is_P_2_triggered_~__retres1~1#1 := 0; 1878#L197 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 2006#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1984#L499 assume !(0 != activate_threads_~tmp___0~1#1); 1985#L499-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 1923#L268 assume 1 == ~C_1_pc~0; 1925#L269 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 1962#L289 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 1963#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1926#L507 assume !(0 != activate_threads_~tmp___1~1#1); 1927#L507-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1939#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 2041#L561-2
[2024-11-08 16:34:25,367 INFO L747 eck$LassoCheckResult]: Loop: 2041#L561-2 assume !false; 2220#L562 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 2217#L397 assume !false; 2216#L358 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 2213#L328 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 2210#L345 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 2190#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2188#L362 assume !(0 != eval_~tmp___2~0#1); 2189#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2241#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2222#fire_delta_events_returnLabel#2 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 2215#L118-6 assume !(1 == ~P_1_pc~0); 2211#L118-8 is_P_1_triggered_~__retres1~0#1 := 0; 2209#L129-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 2207#is_P_1_triggered_returnLabel#3 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 2032#L491-6 assume !(0 != activate_threads_~tmp~1#1); 1935#L491-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 1936#L186-6 assume !(1 == ~P_2_pc~0); 1937#L186-8 is_P_2_triggered_~__retres1~1#1 := 0; 1938#L197-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 2038#is_P_2_triggered_returnLabel#3 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1953#L499-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 1948#L499-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 1886#L268-6 assume 1 == ~C_1_pc~0; 1888#L269-2 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 1903#L289-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 1904#is_C_1_triggered_returnLabel#3 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1917#L507-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 1918#L507-8 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2022#reset_delta_events_returnLabel#2 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 2010#L328-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1865#L345-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 2015#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 1851#L580 assume !(0 == start_simulation_~tmp~3#1); 1852#L580-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 2237#L328-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 2231#L345-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 2230#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 2229#L535 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2227#L542 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2226#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 2225#L593 assume !(0 != start_simulation_~tmp___0~2#1); 2041#L561-2
[2024-11-08 16:34:25,370 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 16:34:25,371 INFO L85 PathProgramCache]: Analyzing trace with hash -1311815953, now seen corresponding path program 1 times
[2024-11-08 16:34:25,371 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 16:34:25,373 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [568123696]
[2024-11-08 16:34:25,374 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 16:34:25,374 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 16:34:25,391 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-11-08 16:34:25,462 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2024-11-08 16:34:25,462 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2024-11-08 16:34:25,462 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [568123696]
[2024-11-08 16:34:25,463 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [568123696] provided 1 perfect and 0 imperfect interpolant sequences
[2024-11-08 16:34:25,463 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2024-11-08 16:34:25,463 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4
[2024-11-08 16:34:25,463 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1640833055]
[2024-11-08 16:34:25,463 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2024-11-08 16:34:25,464 INFO L750 eck$LassoCheckResult]: stem already infeasible
[2024-11-08 16:34:25,465 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 16:34:25,468 INFO L85 PathProgramCache]: Analyzing trace with hash 1116412163, now seen corresponding path program 1 times
[2024-11-08 16:34:25,469 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 16:34:25,469 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1920081858]
[2024-11-08 16:34:25,469 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 16:34:25,470 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 16:34:25,487 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-11-08 16:34:25,587 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2024-11-08 16:34:25,588 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2024-11-08 16:34:25,589 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1920081858]
[2024-11-08 16:34:25,589 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1920081858] provided 1 perfect and 0 imperfect interpolant sequences
[2024-11-08 16:34:25,590 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2024-11-08 16:34:25,590 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5
[2024-11-08 16:34:25,590 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1382156239]
[2024-11-08 16:34:25,590 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2024-11-08 16:34:25,591 INFO L762 eck$LassoCheckResult]: loop already infeasible
[2024-11-08 16:34:25,592 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2024-11-08 16:34:25,593 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants.
[2024-11-08 16:34:25,593 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12
[2024-11-08 16:34:25,594 INFO L87 Difference]: Start difference. First operand 445 states and 634 transitions. cyclomatic complexity: 191 Second operand has 4 states, 4 states have (on average 7.0) internal successors, (28), 4 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 16:34:25,815 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2024-11-08 16:34:25,815 INFO L93 Difference]: Finished difference Result 1212 states and 1690 transitions.
[2024-11-08 16:34:25,815 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1212 states and 1690 transitions.
[2024-11-08 16:34:25,827 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1132
[2024-11-08 16:34:25,835 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1212 states to 1212 states and 1690 transitions.
[2024-11-08 16:34:25,835 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1212
[2024-11-08 16:34:25,837 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1212
[2024-11-08 16:34:25,837 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1212 states and 1690 transitions.
[2024-11-08 16:34:25,839 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2024-11-08 16:34:25,840 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1212 states and 1690 transitions.
[2024-11-08 16:34:25,842 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1212 states and 1690 transitions.
[2024-11-08 16:34:25,869 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1212 to 1153.
[2024-11-08 16:34:25,872 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1153 states, 1153 states have (on average 1.4032957502168257) internal successors, (1618), 1152 states have internal predecessors, (1618), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 16:34:25,878 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1153 states to 1153 states and 1618 transitions.
[2024-11-08 16:34:25,879 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1153 states and 1618 transitions.
[2024-11-08 16:34:25,879 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states.
[2024-11-08 16:34:25,880 INFO L425 stractBuchiCegarLoop]: Abstraction has 1153 states and 1618 transitions.
[2024-11-08 16:34:25,880 INFO L332 stractBuchiCegarLoop]: ======== Iteration 6 ============
[2024-11-08 16:34:25,880 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1153 states and 1618 transitions.
[2024-11-08 16:34:25,889 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1111
[2024-11-08 16:34:25,890 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2024-11-08 16:34:25,890 INFO L119 BuchiIsEmpty]: Starting construction of run
[2024-11-08 16:34:25,892 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 16:34:25,894 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 16:34:25,894 INFO L745 eck$LassoCheckResult]: Stem: 3618#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 3619#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 3647#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3635#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3636#L305 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 3676#L305-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 3688#L310-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 3689#L315-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3706#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 3705#L118 assume !(1 == ~P_1_pc~0); 3670#L118-2 is_P_1_triggered_~__retres1~0#1 := 0; 3671#L129 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 3661#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 3528#L491 assume !(0 != activate_threads_~tmp~1#1); 3529#L491-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 3677#L186 assume !(1 == ~P_2_pc~0); 3547#L186-2 is_P_2_triggered_~__retres1~1#1 := 0; 3548#L197 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 3681#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 3653#L499 assume !(0 != activate_threads_~tmp___0~1#1); 3654#L499-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 3593#L268 assume !(1 == ~C_1_pc~0); 3594#L268-2 assume 2 == ~C_1_pc~0; 3665#L279 assume 1 == ~C_1_ev~0;is_C_1_triggered_~__retres1~2#1 := 1; 3630#L289 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 3631#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3595#L507 assume !(0 != activate_threads_~tmp___1~1#1); 3596#L507-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3608#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 3728#L561-2
[2024-11-08 16:34:25,895 INFO L747 eck$LassoCheckResult]: Loop: 3728#L561-2 assume !false; 3692#L562 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 3550#L397 assume !false; 3568#L358 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 3569#L328 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 4598#L345 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 4597#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 3739#L362 assume !(0 != eval_~tmp___2~0#1); 3741#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4648#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4647#fire_delta_events_returnLabel#2 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 4646#L118-6 assume !(1 == ~P_1_pc~0); 4645#L118-8 is_P_1_triggered_~__retres1~0#1 := 0; 4644#L129-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 4643#is_P_1_triggered_returnLabel#3 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 4642#L491-6 assume !(0 != activate_threads_~tmp~1#1); 4641#L491-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 4640#L186-6 assume !(1 == ~P_2_pc~0); 4639#L186-8 is_P_2_triggered_~__retres1~1#1 := 0; 4638#L197-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 4637#is_P_2_triggered_returnLabel#3 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 4636#L499-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 4635#L499-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 4634#L268-6 assume !(1 == ~C_1_pc~0); 4633#L268-8 assume !(2 == ~C_1_pc~0); 4631#L278-5 is_C_1_triggered_~__retres1~2#1 := 0; 4630#L289-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 4629#is_C_1_triggered_returnLabel#3 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4628#L507-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 4627#L507-8 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4626#reset_delta_events_returnLabel#2 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 4618#L328-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 4617#L345-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 4616#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 4614#L580 assume !(0 == start_simulation_~tmp~3#1); 4613#L580-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 4611#L328-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 4609#L345-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 4608#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 4607#L535 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4606#L542 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4605#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 4604#L593 assume !(0 != start_simulation_~tmp___0~2#1); 3728#L561-2
[2024-11-08 16:34:25,895 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 16:34:25,899 INFO L85 PathProgramCache]: Analyzing trace with hash -122788309, now seen corresponding path program 1 times
[2024-11-08 16:34:25,900 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 16:34:25,900 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2070318320]
[2024-11-08 16:34:25,900 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 16:34:25,900 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 16:34:25,918 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-11-08 16:34:25,970 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2024-11-08 16:34:25,971 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2024-11-08 16:34:25,971 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2070318320]
[2024-11-08 16:34:25,975 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2070318320] provided 1 perfect and 0 imperfect interpolant sequences
[2024-11-08 16:34:25,975 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2024-11-08 16:34:25,975 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2024-11-08 16:34:25,975 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2070139066]
[2024-11-08 16:34:25,975 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2024-11-08 16:34:25,976 INFO L750 eck$LassoCheckResult]: stem already infeasible
[2024-11-08 16:34:25,976 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 16:34:25,976 INFO L85 PathProgramCache]: Analyzing trace with hash -1426618079, now seen corresponding path program 1 times
[2024-11-08 16:34:25,977 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 16:34:25,977 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [113302671]
[2024-11-08 16:34:25,977 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 16:34:25,978 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 16:34:25,999 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-11-08 16:34:26,066 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2024-11-08 16:34:26,067 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2024-11-08 16:34:26,067 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [113302671]
[2024-11-08 16:34:26,067 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [113302671] provided 1 perfect and 0 imperfect interpolant sequences
[2024-11-08 16:34:26,068 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2024-11-08 16:34:26,068 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5
[2024-11-08 16:34:26,068 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2067771231]
[2024-11-08 16:34:26,068 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2024-11-08 16:34:26,069 INFO L762 eck$LassoCheckResult]: loop already infeasible
[2024-11-08 16:34:26,069 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2024-11-08 16:34:26,070 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2024-11-08 16:34:26,070 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2024-11-08 16:34:26,070 INFO L87 Difference]: Start difference. First operand 1153 states and 1618 transitions. cyclomatic complexity: 469 Second operand has 3 states, 3 states have (on average 9.666666666666666) internal successors, (29), 3 states have internal predecessors, (29), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 16:34:26,151 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2024-11-08 16:34:26,151 INFO L93 Difference]: Finished difference Result 1533 states and 2121 transitions.
[2024-11-08 16:34:26,152 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1533 states and 2121 transitions.
[2024-11-08 16:34:26,165 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1486
[2024-11-08 16:34:26,175 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1533 states to 1533 states and 2121 transitions.
[2024-11-08 16:34:26,176 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1533
[2024-11-08 16:34:26,178 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1533
[2024-11-08 16:34:26,179 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1533 states and 2121 transitions.
[2024-11-08 16:34:26,216 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2024-11-08 16:34:26,216 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1533 states and 2121 transitions.
[2024-11-08 16:34:26,218 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1533 states and 2121 transitions.
[2024-11-08 16:34:26,239 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1533 to 1509.
[2024-11-08 16:34:26,243 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1509 states, 1509 states have (on average 1.385685884691849) internal successors, (2091), 1508 states have internal predecessors, (2091), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 16:34:26,249 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1509 states to 1509 states and 2091 transitions.
[2024-11-08 16:34:26,249 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1509 states and 2091 transitions.
[2024-11-08 16:34:26,251 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states.
[2024-11-08 16:34:26,254 INFO L425 stractBuchiCegarLoop]: Abstraction has 1509 states and 2091 transitions.
[2024-11-08 16:34:26,256 INFO L332 stractBuchiCegarLoop]: ======== Iteration 7 ============
[2024-11-08 16:34:26,256 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1509 states and 2091 transitions.
[2024-11-08 16:34:26,266 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1462
[2024-11-08 16:34:26,266 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2024-11-08 16:34:26,266 INFO L119 BuchiIsEmpty]: Starting construction of run
[2024-11-08 16:34:26,267 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 16:34:26,270 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 16:34:26,271 INFO L745 eck$LassoCheckResult]: Stem: 6311#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 6312#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 6344#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6332#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6333#L305 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 6368#L305-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 6382#L310-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 6383#L315-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6397#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 6396#L118 assume !(1 == ~P_1_pc~0); 6363#L118-2 is_P_1_triggered_~__retres1~0#1 := 0; 6364#L129 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 6356#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 6223#L491 assume !(0 != activate_threads_~tmp~1#1); 6224#L491-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 6369#L186 assume !(1 == ~P_2_pc~0); 6241#L186-2 is_P_2_triggered_~__retres1~1#1 := 0; 6242#L197 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 6374#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 6348#L499 assume !(0 != activate_threads_~tmp___0~1#1); 6349#L499-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 6285#L268 assume !(1 == ~C_1_pc~0); 6286#L268-2 assume !(2 == ~C_1_pc~0); 6405#L278-1 is_C_1_triggered_~__retres1~2#1 := 0; 6326#L289 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 6327#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 6287#L507 assume !(0 != activate_threads_~tmp___1~1#1); 6288#L507-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6301#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 6380#L561-2
[2024-11-08 16:34:26,271 INFO L747 eck$LassoCheckResult]: Loop: 6380#L561-2 assume !false; 7534#L562 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 7526#L397 assume !false; 7522#L358 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 7517#L328 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 7512#L345 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 7507#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 7500#L362 assume !(0 != eval_~tmp___2~0#1); 7501#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7655#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7654#fire_delta_events_returnLabel#2 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 7653#L118-6 assume !(1 == ~P_1_pc~0); 7651#L118-8 is_P_1_triggered_~__retres1~0#1 := 0; 7649#L129-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 7647#is_P_1_triggered_returnLabel#3 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 7645#L491-6 assume !(0 != activate_threads_~tmp~1#1); 7643#L491-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 7641#L186-6 assume !(1 == ~P_2_pc~0); 7639#L186-8 is_P_2_triggered_~__retres1~1#1 := 0; 7637#L197-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 7635#is_P_2_triggered_returnLabel#3 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 7633#L499-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 7631#L499-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 7629#L268-6 assume !(1 == ~C_1_pc~0); 7627#L268-8 assume !(2 == ~C_1_pc~0); 7625#L278-5 is_C_1_triggered_~__retres1~2#1 := 0; 7623#L289-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 7621#is_C_1_triggered_returnLabel#3 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 7619#L507-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 7617#L507-8 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7615#reset_delta_events_returnLabel#2 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 7609#L328-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 7607#L345-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 6401#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 6216#L580 assume !(0 == start_simulation_~tmp~3#1); 6217#L580-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 6254#L328-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 6372#L345-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 6328#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 6329#L535 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6235#L542 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6236#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 6379#L593 assume !(0 != start_simulation_~tmp___0~2#1); 6380#L561-2
[2024-11-08 16:34:26,271 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 16:34:26,272 INFO L85 PathProgramCache]: Analyzing trace with hash 1966545068, now seen corresponding path program 1 times
[2024-11-08 16:34:26,272 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 16:34:26,272 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [239596357]
[2024-11-08 16:34:26,272 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 16:34:26,272 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 16:34:26,292 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-11-08 16:34:26,293 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2024-11-08 16:34:26,304 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-11-08 16:34:26,352 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2024-11-08 16:34:26,352 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 16:34:26,353 INFO L85 PathProgramCache]: Analyzing trace with hash -1426618079, now seen corresponding path program 2 times
[2024-11-08 16:34:26,353 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 16:34:26,353 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1252566415]
[2024-11-08 16:34:26,354 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 16:34:26,354 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 16:34:26,371 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-11-08 16:34:26,429 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2024-11-08 16:34:26,430 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2024-11-08 16:34:26,430 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1252566415]
[2024-11-08 16:34:26,430 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1252566415] provided 1 perfect and 0 imperfect interpolant sequences
[2024-11-08 16:34:26,430 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2024-11-08 16:34:26,431 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5
[2024-11-08 16:34:26,431 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [409951158]
[2024-11-08 16:34:26,431 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2024-11-08 16:34:26,432 INFO L762 eck$LassoCheckResult]: loop already infeasible
[2024-11-08 16:34:26,432 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2024-11-08 16:34:26,432 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants.
[2024-11-08 16:34:26,433 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20
[2024-11-08 16:34:26,433 INFO L87 Difference]: Start difference. First operand 1509 states and 2091 transitions. cyclomatic complexity: 586 Second operand has 5 states, 5 states have (on average 8.6) internal successors, (43), 5 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 16:34:26,519 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2024-11-08 16:34:26,519 INFO L93 Difference]: Finished difference Result 1593 states and 2175 transitions.
[2024-11-08 16:34:26,519 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1593 states and 2175 transitions.
[2024-11-08 16:34:26,533 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1546
[2024-11-08 16:34:26,544 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1593 states to 1593 states and 2175 transitions.
[2024-11-08 16:34:26,545 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1593
[2024-11-08 16:34:26,547 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1593
[2024-11-08 16:34:26,547 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1593 states and 2175 transitions.
[2024-11-08 16:34:26,550 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2024-11-08 16:34:26,550 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1593 states and 2175 transitions.
[2024-11-08 16:34:26,552 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1593 states and 2175 transitions.
[2024-11-08 16:34:26,575 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1593 to 1545.
[2024-11-08 16:34:26,579 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1545 states, 1545 states have (on average 1.3766990291262136) internal successors, (2127), 1544 states have internal predecessors, (2127), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 16:34:26,585 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1545 states to 1545 states and 2127 transitions.
[2024-11-08 16:34:26,586 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1545 states and 2127 transitions.
[2024-11-08 16:34:26,586 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states.
[2024-11-08 16:34:26,588 INFO L425 stractBuchiCegarLoop]: Abstraction has 1545 states and 2127 transitions.
[2024-11-08 16:34:26,588 INFO L332 stractBuchiCegarLoop]: ======== Iteration 8 ============
[2024-11-08 16:34:26,589 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1545 states and 2127 transitions.
[2024-11-08 16:34:26,599 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1498
[2024-11-08 16:34:26,599 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2024-11-08 16:34:26,599 INFO L119 BuchiIsEmpty]: Starting construction of run
[2024-11-08 16:34:26,600 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 16:34:26,600 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 16:34:26,601 INFO L745 eck$LassoCheckResult]: Stem: 9422#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 9423#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 9454#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9444#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9445#L305 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 9481#L305-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 9492#L310-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 9493#L315-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9511#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 9510#L118 assume !(1 == ~P_1_pc~0); 9476#L118-2 is_P_1_triggered_~__retres1~0#1 := 0; 9477#L129 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 9467#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 9335#L491 assume !(0 != activate_threads_~tmp~1#1); 9336#L491-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 9482#L186 assume !(1 == ~P_2_pc~0); 9356#L186-2 is_P_2_triggered_~__retres1~1#1 := 0; 9357#L197 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 9486#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 9462#L499 assume !(0 != activate_threads_~tmp___0~1#1); 9463#L499-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 9396#L268 assume !(1 == ~C_1_pc~0); 9397#L268-2 assume !(2 == ~C_1_pc~0); 9519#L278-1 is_C_1_triggered_~__retres1~2#1 := 0; 9438#L289 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 9439#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 9398#L507 assume !(0 != activate_threads_~tmp___1~1#1); 9399#L507-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9415#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 9532#L561-2
[2024-11-08 16:34:26,601 INFO L747 eck$LassoCheckResult]: Loop: 9532#L561-2 assume !false; 10507#L562 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 10504#L397 assume !false; 10502#L358 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 10500#L328 assume !(0 == ~P_1_st~0); 10501#L332 assume !(0 == ~P_2_st~0); 10498#L336 assume !(0 == ~C_1_st~0);exists_runnable_thread_~__retres1~3#1 := 0; 10499#L345 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 10476#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 10477#L362 assume !(0 != eval_~tmp___2~0#1); 10720#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10717#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10715#fire_delta_events_returnLabel#2 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 10713#L118-6 assume !(1 == ~P_1_pc~0); 10712#L118-8 is_P_1_triggered_~__retres1~0#1 := 0; 10710#L129-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 10708#is_P_1_triggered_returnLabel#3 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 10706#L491-6 assume !(0 != activate_threads_~tmp~1#1); 10704#L491-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 10702#L186-6 assume !(1 == ~P_2_pc~0); 10700#L186-8 is_P_2_triggered_~__retres1~1#1 := 0; 10698#L197-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 10696#is_P_2_triggered_returnLabel#3 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 10694#L499-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 10692#L499-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 10690#L268-6 assume !(1 == ~C_1_pc~0); 10688#L268-8 assume !(2 == ~C_1_pc~0); 10686#L278-5 is_C_1_triggered_~__retres1~2#1 := 0; 10684#L289-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 10682#is_C_1_triggered_returnLabel#3 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 10681#L507-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 10680#L507-8 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10676#reset_delta_events_returnLabel#2 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 10673#L328-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 10662#L345-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 10567#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 10564#L580 assume !(0 == start_simulation_~tmp~3#1); 10562#L580-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 10560#L328-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 10528#L345-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 10522#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 10519#L535 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10517#L542 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10515#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 10512#L593 assume !(0 != start_simulation_~tmp___0~2#1); 9532#L561-2
[2024-11-08 16:34:26,603 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 16:34:26,603 INFO L85 PathProgramCache]: Analyzing trace with hash 1966545068, now seen corresponding path program 2 times
[2024-11-08 16:34:26,604 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 16:34:26,604 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2032160904]
[2024-11-08 16:34:26,604 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 16:34:26,604 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 16:34:26,618 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-11-08 16:34:26,621 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2024-11-08 16:34:26,628 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-11-08 16:34:26,641 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2024-11-08 16:34:26,643 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 16:34:26,643 INFO L85 PathProgramCache]: Analyzing trace with hash -1911195448, now seen corresponding path program 1 times
[2024-11-08 16:34:26,644 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 16:34:26,644 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2026969957]
[2024-11-08 16:34:26,644 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 16:34:26,644 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 16:34:26,659 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-11-08 16:34:26,697 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2024-11-08 16:34:26,701 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2024-11-08 16:34:26,702 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2026969957]
[2024-11-08 16:34:26,702 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2026969957] provided 1 perfect and 0 imperfect interpolant sequences
[2024-11-08 16:34:26,702 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2024-11-08 16:34:26,702 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2024-11-08 16:34:26,703 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1881085472]
[2024-11-08 16:34:26,703 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2024-11-08 16:34:26,703 INFO L762 eck$LassoCheckResult]: loop already infeasible
[2024-11-08 16:34:26,703 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2024-11-08 16:34:26,704 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2024-11-08 16:34:26,704 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2024-11-08 16:34:26,704 INFO L87 Difference]: Start difference. First operand 1545 states and 2127 transitions. cyclomatic complexity: 586 Second operand has 3 states, 3 states have (on average 15.0) internal successors, (45), 3 states have internal predecessors, (45), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 16:34:26,779 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2024-11-08 16:34:26,780 INFO L93 Difference]: Finished difference Result 2397 states and 3262 transitions.
[2024-11-08 16:34:26,780 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2397 states and 3262 transitions.
[2024-11-08 16:34:26,798 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 2294
[2024-11-08 16:34:26,813 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2397 states to 2397 states and 3262 transitions.
[2024-11-08 16:34:26,814 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2397
[2024-11-08 16:34:26,819 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2397
[2024-11-08 16:34:26,819 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2397 states and 3262 transitions.
[2024-11-08 16:34:26,824 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2024-11-08 16:34:26,824 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2397 states and 3262 transitions.
[2024-11-08 16:34:26,827 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2397 states and 3262 transitions.
[2024-11-08 16:34:26,861 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2397 to 2397.
[2024-11-08 16:34:26,866 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2397 states, 2397 states have (on average 1.3608677513558616) internal successors, (3262), 2396 states have internal predecessors, (3262), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 16:34:26,876 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2397 states to 2397 states and 3262 transitions.
[2024-11-08 16:34:26,877 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2397 states and 3262 transitions.
[2024-11-08 16:34:26,877 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states.
[2024-11-08 16:34:26,878 INFO L425 stractBuchiCegarLoop]: Abstraction has 2397 states and 3262 transitions.
[2024-11-08 16:34:26,878 INFO L332 stractBuchiCegarLoop]: ======== Iteration 9 ============
[2024-11-08 16:34:26,878 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2397 states and 3262 transitions.
[2024-11-08 16:34:26,895 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 2294
[2024-11-08 16:34:26,896 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2024-11-08 16:34:26,896 INFO L119 BuchiIsEmpty]: Starting construction of run
[2024-11-08 16:34:26,897 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 16:34:26,900 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 16:34:26,901 INFO L745 eck$LassoCheckResult]: Stem: 13367#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 13368#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 13398#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13388#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 13389#L305 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 13421#L305-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 13435#L310-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 13436#L315-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13452#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 13451#L118 assume !(1 == ~P_1_pc~0); 13416#L118-2 is_P_1_triggered_~__retres1~0#1 := 0; 13417#L129 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 13409#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 13281#L491 assume !(0 != activate_threads_~tmp~1#1); 13282#L491-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 13425#L186 assume !(1 == ~P_2_pc~0); 13304#L186-2 is_P_2_triggered_~__retres1~1#1 := 0; 13305#L197 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 13428#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 13402#L499 assume !(0 != activate_threads_~tmp___0~1#1); 13403#L499-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 13344#L268 assume !(1 == ~C_1_pc~0); 13345#L268-2 assume !(2 == ~C_1_pc~0); 13459#L278-1 is_C_1_triggered_~__retres1~2#1 := 0; 13382#L289 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 13383#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 13346#L507 assume !(0 != activate_threads_~tmp___1~1#1); 13347#L507-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13357#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 13473#L561-2 assume !false; 15197#L562 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 15193#L397
[2024-11-08 16:34:26,901 INFO L747 eck$LassoCheckResult]: Loop: 15193#L397 assume !false; 15191#L358 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 15190#L328 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 15189#L345 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 15188#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 15153#L362 assume 0 != eval_~tmp___2~0#1; 15146#L362-1 assume 0 == ~P_1_st~0;havoc eval_#t~nondet6#1;eval_~tmp~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 15140#L371 assume !(0 != eval_~tmp~0#1); 14821#L367 assume !(0 == ~P_2_st~0); 14818#L382 assume !(0 == ~C_1_st~0); 15193#L397
[2024-11-08 16:34:26,902 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 16:34:26,902 INFO L85 PathProgramCache]: Analyzing trace with hash 64203918, now seen corresponding path program 1 times
[2024-11-08 16:34:26,902 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 16:34:26,902 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1645524614]
[2024-11-08 16:34:26,902 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 16:34:26,903 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 16:34:26,916 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-11-08 16:34:26,916 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2024-11-08 16:34:26,923 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-11-08 16:34:26,936 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2024-11-08 16:34:26,937 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 16:34:26,937 INFO L85 PathProgramCache]: Analyzing trace with hash -1970157249, now seen corresponding path program 1 times
[2024-11-08 16:34:26,937 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 16:34:26,938 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1350509222]
[2024-11-08 16:34:26,938 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 16:34:26,938 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 16:34:26,945 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-11-08 16:34:26,946 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2024-11-08 16:34:26,948 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-11-08 16:34:26,953 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2024-11-08 16:34:26,955 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 16:34:26,955 INFO L85 PathProgramCache]: Analyzing trace with hash -860558964, now seen corresponding path program 1 times
[2024-11-08 16:34:26,955 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 16:34:26,956 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1388939402]
[2024-11-08 16:34:26,956 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 16:34:26,956 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 16:34:26,969 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-11-08 16:34:27,007 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2024-11-08 16:34:27,008 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2024-11-08 16:34:27,008 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1388939402]
[2024-11-08 16:34:27,008 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1388939402] provided 1 perfect and 0 imperfect interpolant sequences
[2024-11-08 16:34:27,008 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2024-11-08 16:34:27,009 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2024-11-08 16:34:27,009 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1776469392]
[2024-11-08 16:34:27,009 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2024-11-08 16:34:27,133 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2024-11-08 16:34:27,134 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2024-11-08 16:34:27,134 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2024-11-08 16:34:27,134 INFO L87 Difference]: Start difference. First operand 2397 states and 3262 transitions. cyclomatic complexity: 872 Second operand has 3 states, 3 states have (on average 13.666666666666666) internal successors, (41), 3 states have internal predecessors, (41), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 16:34:27,265 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2024-11-08 16:34:27,265 INFO L93 Difference]: Finished difference Result 3997 states and 5360 transitions.
[2024-11-08 16:34:27,265 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3997 states and 5360 transitions.
[2024-11-08 16:34:27,301 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 3833
[2024-11-08 16:34:27,323 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3997 states to 3997 states and 5360 transitions.
[2024-11-08 16:34:27,324 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3997
[2024-11-08 16:34:27,328 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3997
[2024-11-08 16:34:27,329 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3997 states and 5360 transitions.
[2024-11-08 16:34:27,335 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2024-11-08 16:34:27,335 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3997 states and 5360 transitions.
[2024-11-08 16:34:27,340 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3997 states and 5360 transitions.
[2024-11-08 16:34:27,404 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3997 to 3913.
[2024-11-08 16:34:27,415 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3913 states, 3913 states have (on average 1.34372604140046) internal successors, (5258), 3912 states have internal predecessors, (5258), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 16:34:27,428 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3913 states to 3913 states and 5258 transitions.
[2024-11-08 16:34:27,428 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3913 states and 5258 transitions.
[2024-11-08 16:34:27,429 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states.
[2024-11-08 16:34:27,430 INFO L425 stractBuchiCegarLoop]: Abstraction has 3913 states and 5258 transitions.
[2024-11-08 16:34:27,431 INFO L332 stractBuchiCegarLoop]: ======== Iteration 10 ============
[2024-11-08 16:34:27,431 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3913 states and 5258 transitions.
[2024-11-08 16:34:27,453 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 3749
[2024-11-08 16:34:27,453 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2024-11-08 16:34:27,453 INFO L119 BuchiIsEmpty]: Starting construction of run
[2024-11-08 16:34:27,454 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 16:34:27,454 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 16:34:27,455 INFO L745 eck$LassoCheckResult]: Stem: 19770#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 19771#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 19803#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 19793#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19794#L305 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 19832#L305-2 assume !(1 == ~P_2_i~0);~P_2_st~0 := 2; 19847#L310-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 19848#L315-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 19871#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 19870#L118 assume !(1 == ~P_1_pc~0); 19825#L118-2 is_P_1_triggered_~__retres1~0#1 := 0; 19826#L129 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 19815#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 19685#L491 assume !(0 != activate_threads_~tmp~1#1); 19686#L491-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 19835#L186 assume !(1 == ~P_2_pc~0); 19706#L186-2 is_P_2_triggered_~__retres1~1#1 := 0; 19707#L197 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 19839#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 19810#L499 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 19811#L499-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 23047#L268 assume !(1 == ~C_1_pc~0); 23046#L268-2 assume !(2 == ~C_1_pc~0); 23045#L278-1 is_C_1_triggered_~__retres1~2#1 := 0; 23044#L289 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 23043#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 19750#L507 assume !(0 != activate_threads_~tmp___1~1#1); 19751#L507-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19765#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 19895#L561-2 assume !false; 23023#L562 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 23013#L397
[2024-11-08 16:34:27,455 INFO L747 eck$LassoCheckResult]: Loop: 23013#L397 assume !false; 23009#L358 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 23003#L328 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 22998#L345 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 22995#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 22990#L362 assume 0 != eval_~tmp___2~0#1; 22985#L362-1 assume 0 == ~P_1_st~0;havoc eval_#t~nondet6#1;eval_~tmp~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 22979#L371 assume !(0 != eval_~tmp~0#1); 22980#L367 assume 0 == ~P_2_st~0;havoc eval_#t~nondet7#1;eval_~tmp___0~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 23033#L386 assume !(0 != eval_~tmp___0~0#1); 23022#L382 assume !(0 == ~C_1_st~0); 23013#L397
[2024-11-08 16:34:27,456 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 16:34:27,456 INFO L85 PathProgramCache]: Analyzing trace with hash -131921906, now seen corresponding path program 1 times
[2024-11-08 16:34:27,456 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 16:34:27,456 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [950891581]
[2024-11-08 16:34:27,456 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 16:34:27,457 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 16:34:27,466 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-11-08 16:34:27,487 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2024-11-08 16:34:27,487 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2024-11-08 16:34:27,488 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [950891581]
[2024-11-08 16:34:27,488 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [950891581] provided 1 perfect and 0 imperfect interpolant sequences
[2024-11-08 16:34:27,488 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2024-11-08 16:34:27,488 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2024-11-08 16:34:27,489 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1005488160]
[2024-11-08 16:34:27,489 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2024-11-08 16:34:27,489 INFO L750 eck$LassoCheckResult]: stem already infeasible
[2024-11-08 16:34:27,490 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 16:34:27,490 INFO L85 PathProgramCache]: Analyzing trace with hash -945475189, now seen corresponding path program 1 times
[2024-11-08 16:34:27,490 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 16:34:27,490 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [550582985]
[2024-11-08 16:34:27,491 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 16:34:27,491 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 16:34:27,495 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-11-08 16:34:27,495 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2024-11-08 16:34:27,498 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-11-08 16:34:27,500 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2024-11-08 16:34:27,583 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2024-11-08 16:34:27,583 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2024-11-08 16:34:27,583 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2024-11-08 16:34:27,584 INFO L87 Difference]: Start difference. First operand 3913 states and 5258 transitions. cyclomatic complexity: 1352 Second operand has 3 states, 3 states have (on average 10.333333333333334) internal successors, (31), 3 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 16:34:27,612 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2024-11-08 16:34:27,612 INFO L93 Difference]: Finished difference Result 3888 states and 5230 transitions.
[2024-11-08 16:34:27,612 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3888 states and 5230 transitions.
[2024-11-08 16:34:27,637 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 3749
[2024-11-08 16:34:27,659 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3888 states to 3888 states and 5230 transitions.
[2024-11-08 16:34:27,659 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3888
[2024-11-08 16:34:27,663 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3888
[2024-11-08 16:34:27,664 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3888 states and 5230 transitions.
[2024-11-08 16:34:27,670 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2024-11-08 16:34:27,670 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3888 states and 5230 transitions.
[2024-11-08 16:34:27,675 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3888 states and 5230 transitions.
[2024-11-08 16:34:27,736 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3888 to 3888.
[2024-11-08 16:34:27,744 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3888 states, 3888 states have (on average 1.3451646090534979) internal successors, (5230), 3887 states have internal predecessors, (5230), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 16:34:27,764 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3888 states to 3888 states and 5230 transitions.
[2024-11-08 16:34:27,765 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3888 states and 5230 transitions.
[2024-11-08 16:34:27,766 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states.
[2024-11-08 16:34:27,767 INFO L425 stractBuchiCegarLoop]: Abstraction has 3888 states and 5230 transitions.
[2024-11-08 16:34:27,767 INFO L332 stractBuchiCegarLoop]: ======== Iteration 11 ============
[2024-11-08 16:34:27,767 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3888 states and 5230 transitions.
[2024-11-08 16:34:27,790 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 3749
[2024-11-08 16:34:27,790 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2024-11-08 16:34:27,790 INFO L119 BuchiIsEmpty]: Starting construction of run
[2024-11-08 16:34:27,791 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 16:34:27,791 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 16:34:27,792 INFO L745 eck$LassoCheckResult]: Stem: 27577#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 27578#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 27612#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 27601#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 27602#L305 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 27636#L305-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 27651#L310-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 27652#L315-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 27676#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 27675#L118 assume !(1 == ~P_1_pc~0); 27631#L118-2 is_P_1_triggered_~__retres1~0#1 := 0; 27632#L129 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 27623#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 27492#L491 assume !(0 != activate_threads_~tmp~1#1); 27493#L491-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 27640#L186 assume !(1 == ~P_2_pc~0); 27513#L186-2 is_P_2_triggered_~__retres1~1#1 := 0; 27514#L197 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 27644#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 27619#L499 assume !(0 != activate_threads_~tmp___0~1#1); 27620#L499-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 27554#L268 assume !(1 == ~C_1_pc~0); 27555#L268-2 assume !(2 == ~C_1_pc~0); 27683#L278-1 is_C_1_triggered_~__retres1~2#1 := 0; 27594#L289 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 27595#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 27556#L507 assume !(0 != activate_threads_~tmp___1~1#1); 27557#L507-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27572#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 27697#L561-2 assume !false; 29098#L562 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 28922#L397
[2024-11-08 16:34:27,792 INFO L747 eck$LassoCheckResult]: Loop: 28922#L397 assume !false; 29094#L358 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 29091#L328 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 29089#L345 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 29087#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 29084#L362 assume 0 != eval_~tmp___2~0#1; 29080#L362-1 assume 0 == ~P_1_st~0;havoc eval_#t~nondet6#1;eval_~tmp~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 29074#L371 assume !(0 != eval_~tmp~0#1); 29072#L367 assume 0 == ~P_2_st~0;havoc eval_#t~nondet7#1;eval_~tmp___0~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 28939#L386 assume !(0 != eval_~tmp___0~0#1); 28936#L382 assume !(0 == ~C_1_st~0); 28922#L397
[2024-11-08 16:34:27,792 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 16:34:27,793 INFO L85 PathProgramCache]: Analyzing trace with hash 64203918, now seen corresponding path program 2 times
[2024-11-08 16:34:27,793 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 16:34:27,796 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1928286200]
[2024-11-08 16:34:27,799 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 16:34:27,800 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 16:34:27,809 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-11-08 16:34:27,810 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2024-11-08 16:34:27,819 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-11-08 16:34:27,829 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2024-11-08 16:34:27,833 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 16:34:27,833 INFO L85 PathProgramCache]: Analyzing trace with hash -945475189, now seen corresponding path program 2 times
[2024-11-08 16:34:27,833 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 16:34:27,837 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1222118679]
[2024-11-08 16:34:27,838 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 16:34:27,838 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 16:34:27,842 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-11-08 16:34:27,845 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2024-11-08 16:34:27,848 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-11-08 16:34:27,853 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2024-11-08 16:34:27,854 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 16:34:27,857 INFO L85 PathProgramCache]: Analyzing trace with hash -907666722, now seen corresponding path program 1 times
[2024-11-08 16:34:27,857 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 16:34:27,857 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1689026373]
[2024-11-08 16:34:27,858 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 16:34:27,858 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 16:34:27,869 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-11-08 16:34:27,902 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2024-11-08 16:34:27,902 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2024-11-08 16:34:27,902 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1689026373]
[2024-11-08 16:34:27,902 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1689026373] provided 1 perfect and 0 imperfect interpolant sequences
[2024-11-08 16:34:27,903 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2024-11-08 16:34:27,903 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2
[2024-11-08 16:34:27,905 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [479559385]
[2024-11-08 16:34:27,906 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2024-11-08 16:34:28,018 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2024-11-08 16:34:28,018 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2024-11-08 16:34:28,018 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2024-11-08 16:34:28,019 INFO L87 Difference]: Start difference. First operand 3888 states and 5230 transitions. cyclomatic complexity: 1349 Second operand has 3 states, 2 states have (on average 21.0) internal successors, (42), 3 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 16:34:28,109 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2024-11-08 16:34:28,109 INFO L93 Difference]: Finished difference Result 6782 states and 9040 transitions.
[2024-11-08 16:34:28,110 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6782 states and 9040 transitions.
[2024-11-08 16:34:28,147 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 6535
[2024-11-08 16:34:28,186 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6782 states to 6782 states and 9040 transitions.
[2024-11-08 16:34:28,187 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6782
[2024-11-08 16:34:28,194 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6782
[2024-11-08 16:34:28,194 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6782 states and 9040 transitions.
[2024-11-08 16:34:28,204 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2024-11-08 16:34:28,205 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6782 states and 9040 transitions.
[2024-11-08 16:34:28,213 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6782 states and 9040 transitions.
[2024-11-08 16:34:28,312 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6782 to 6782.
[2024-11-08 16:34:28,326 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6782 states, 6782 states have (on average 1.3329401356531996) internal successors, (9040), 6781 states have internal predecessors, (9040), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 16:34:28,345 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6782 states to 6782 states and 9040 transitions.
[2024-11-08 16:34:28,345 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6782 states and 9040 transitions.
[2024-11-08 16:34:28,346 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states.
[2024-11-08 16:34:28,346 INFO L425 stractBuchiCegarLoop]: Abstraction has 6782 states and 9040 transitions.
[2024-11-08 16:34:28,347 INFO L332 stractBuchiCegarLoop]: ======== Iteration 12 ============
[2024-11-08 16:34:28,347 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6782 states and 9040 transitions.
[2024-11-08 16:34:28,374 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 6535
[2024-11-08 16:34:28,375 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2024-11-08 16:34:28,375 INFO L119 BuchiIsEmpty]: Starting construction of run
[2024-11-08 16:34:28,375 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 16:34:28,375 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 16:34:28,376 INFO L745 eck$LassoCheckResult]: Stem: 38261#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~clk~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 38262#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~clk~0 := 0;~max_loop~0 := 8;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 38296#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 38286#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 38287#L305 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 38319#L305-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 38333#L310-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 38334#L315-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 38356#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 38355#L118 assume !(1 == ~P_1_pc~0); 38312#L118-2 is_P_1_triggered_~__retres1~0#1 := 0; 38313#L129 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 38307#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 38170#L491 assume !(0 != activate_threads_~tmp~1#1); 38171#L491-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 38322#L186 assume !(1 == ~P_2_pc~0); 38192#L186-2 is_P_2_triggered_~__retres1~1#1 := 0; 38193#L197 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 38325#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 38303#L499 assume !(0 != activate_threads_~tmp___0~1#1); 38304#L499-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 38237#L268 assume !(1 == ~C_1_pc~0); 38238#L268-2 assume !(2 == ~C_1_pc~0); 38362#L278-1 is_C_1_triggered_~__retres1~2#1 := 0; 38278#L289 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 38279#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 38239#L507 assume !(0 != activate_threads_~tmp___1~1#1); 38240#L507-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 38255#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 38377#L561-2 assume !false; 39438#L562 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 39439#L397
[2024-11-08 16:34:28,376 INFO L747 eck$LassoCheckResult]: Loop: 39439#L397 assume !false; 40106#L358 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 40105#L328 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 40104#L345 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 40103#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 40102#L362 assume 0 != eval_~tmp___2~0#1; 40101#L362-1 assume 0 == ~P_1_st~0;havoc eval_#t~nondet6#1;eval_~tmp~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 40100#L371 assume !(0 != eval_~tmp~0#1); 40099#L367 assume 0 == ~P_2_st~0;havoc eval_#t~nondet7#1;eval_~tmp___0~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 39351#L386 assume !(0 != eval_~tmp___0~0#1); 40098#L382 assume 0 == ~C_1_st~0;havoc eval_#t~nondet8#1;eval_~tmp___1~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 40091#L401 assume !(0 != eval_~tmp___1~0#1); 39439#L397
[2024-11-08 16:34:28,376 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 16:34:28,377 INFO L85 PathProgramCache]: Analyzing trace with hash 64203918, now seen corresponding path program 3 times
[2024-11-08 16:34:28,377 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 16:34:28,377 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1427361761]
[2024-11-08 16:34:28,377 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 16:34:28,378 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 16:34:28,391 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-11-08 16:34:28,392 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2024-11-08 16:34:28,398 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-11-08 16:34:28,412 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2024-11-08 16:34:28,414 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 16:34:28,415 INFO L85 PathProgramCache]: Analyzing trace with hash 755038119, now seen corresponding path program 1 times
[2024-11-08 16:34:28,415 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 16:34:28,415 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1247941439]
[2024-11-08 16:34:28,415 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 16:34:28,416 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 16:34:28,423 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-11-08 16:34:28,424 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2024-11-08 16:34:28,427 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-11-08 16:34:28,429 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2024-11-08 16:34:28,430 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 16:34:28,431 INFO L85 PathProgramCache]: Analyzing trace with hash 1927100596, now seen corresponding path program 1 times
[2024-11-08 16:34:28,431 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 16:34:28,431 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [714333032]
[2024-11-08 16:34:28,431 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 16:34:28,431 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 16:34:28,443 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-11-08 16:34:28,443 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2024-11-08 16:34:28,450 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-11-08 16:34:28,461 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2024-11-08 16:34:29,831 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-11-08 16:34:29,832 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2024-11-08 16:34:29,851 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-11-08 16:34:30,026 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 08.11 04:34:30 BoogieIcfgContainer
[2024-11-08 16:34:30,030 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer----------------------------
[2024-11-08 16:34:30,031 INFO L112 PluginConnector]: ------------------------Witness Printer----------------------------
[2024-11-08 16:34:30,031 INFO L270 PluginConnector]: Initializing Witness Printer...
[2024-11-08 16:34:30,031 INFO L274 PluginConnector]: Witness Printer initialized
[2024-11-08 16:34:30,032 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 08.11 04:34:23" (3/4) ...
[2024-11-08 16:34:30,039 INFO L139 WitnessPrinter]: Generating witness for non-termination counterexample
[2024-11-08 16:34:30,148 INFO L149 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2995450b-1a7f-4efe-a580-fe680ef040d7/bin/uautomizer-verify-jihMAELWvX/witness.graphml
[2024-11-08 16:34:30,149 INFO L131 PluginConnector]: ------------------------ END Witness Printer----------------------------
[2024-11-08 16:34:30,150 INFO L158 Benchmark]: Toolchain (without parser) took 8859.18ms. Allocated memory was 169.9MB in the beginning and 289.4MB in the end (delta: 119.5MB). Free memory was 138.3MB in the beginning and 149.4MB in the end (delta: -11.1MB). Peak memory consumption was 110.8MB. Max. memory is 16.1GB.
[2024-11-08 16:34:30,150 INFO L158 Benchmark]: CDTParser took 0.35ms. Allocated memory is still 113.2MB. Free memory is still 68.7MB. There was no memory consumed. Max. memory is 16.1GB.
[2024-11-08 16:34:30,154 INFO L158 Benchmark]: CACSL2BoogieTranslator took 490.05ms. Allocated memory is still 169.9MB. Free memory was 137.7MB in the beginning and 121.5MB in the end (delta: 16.1MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB.
[2024-11-08 16:34:30,154 INFO L158 Benchmark]: Boogie Procedure Inliner took 84.69ms. Allocated memory is still 169.9MB. Free memory was 121.5MB in the beginning and 118.8MB in the end (delta: 2.7MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB.
[2024-11-08 16:34:30,154 INFO L158 Benchmark]: Boogie Preprocessor took 121.47ms. Allocated memory is still 169.9MB. Free memory was 118.8MB in the beginning and 115.2MB in the end (delta: 3.6MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB.
[2024-11-08 16:34:30,155 INFO L158 Benchmark]: RCFGBuilder took 1069.23ms. Allocated memory is still 169.9MB. Free memory was 115.2MB in the beginning and 83.1MB in the end (delta: 32.1MB). Peak memory consumption was 31.5MB. Max. memory is 16.1GB.
[2024-11-08 16:34:30,156 INFO L158 Benchmark]: BuchiAutomizer took 6969.25ms. Allocated memory was 169.9MB in the beginning and 289.4MB in the end (delta: 119.5MB). Free memory was 83.1MB in the beginning and 154.6MB in the end (delta: -71.5MB). Peak memory consumption was 50.0MB. Max. memory is 16.1GB.
[2024-11-08 16:34:30,158 INFO L158 Benchmark]: Witness Printer took 117.80ms. Allocated memory is still 289.4MB. Free memory was 154.6MB in the beginning and 149.4MB in the end (delta: 5.2MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB.
[2024-11-08 16:34:30,160 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] #######################
--- Results ---
* Results from de.uni_freiburg.informatik.ultimate.core:
- StatisticsResult: Toolchain Benchmarks
Benchmark results are:
* CDTParser took 0.35ms. Allocated memory is still 113.2MB. Free memory is still 68.7MB. There was no memory consumed. Max. memory is 16.1GB.
* CACSL2BoogieTranslator took 490.05ms. Allocated memory is still 169.9MB. Free memory was 137.7MB in the beginning and 121.5MB in the end (delta: 16.1MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB.
* Boogie Procedure Inliner took 84.69ms. Allocated memory is still 169.9MB. Free memory was 121.5MB in the beginning and 118.8MB in the end (delta: 2.7MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB.
* Boogie Preprocessor took 121.47ms. Allocated memory is still 169.9MB. Free memory was 118.8MB in the beginning and 115.2MB in the end (delta: 3.6MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB.
* RCFGBuilder took 1069.23ms. Allocated memory is still 169.9MB. Free memory was 115.2MB in the beginning and 83.1MB in the end (delta: 32.1MB). Peak memory consumption was 31.5MB. Max. memory is 16.1GB.
* BuchiAutomizer took 6969.25ms. Allocated memory was 169.9MB in the beginning and 289.4MB in the end (delta: 119.5MB). Free memory was 83.1MB in the beginning and 154.6MB in the end (delta: -71.5MB). Peak memory consumption was 50.0MB. Max. memory is 16.1GB.
* Witness Printer took 117.80ms. Allocated memory is still 289.4MB. Free memory was 154.6MB in the beginning and 149.4MB in the end (delta: 5.2MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB.
* Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction:
- StatisticsResult: Constructed decomposition of program
Your program was decomposed into 11 terminating modules (11 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.11 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 6782 locations.
- StatisticsResult: Timing statistics
BüchiAutomizer plugin needed 6.7s and 12 iterations. TraceHistogramMax:1. Analysis of lassos took 4.1s. Construction of modules took 0.6s. Büchi inclusion checks took 1.6s. Highest rank in rank-based complementation 0. Minimization of det autom 11. Minimization of nondet autom 0. Automata minimization 0.6s AutomataMinimizationTime, 11 MinimizatonAttempts, 257 StatesRemovedByMinimization, 5 NontrivialMinimizations. Non-live state removal took 0.3s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 2777 SdHoareTripleChecker+Valid, 0.8s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 2777 mSDsluCounter, 6043 SdHoareTripleChecker+Invalid, 0.6s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 3206 mSDsCounter, 111 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 306 IncrementalHoareTripleChecker+Invalid, 417 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 111 mSolverCounterUnsat, 2837 mSDtfsCounter, 306 mSolverCounterSat, 0.1s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI2 SFLT0 conc2 concLT0 SILN1 SILU0 SILI6 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s
- TerminationAnalysisResult: Nontermination possible
Buchi Automizer proved that your program is nonterminating for some inputs
- LassoShapedNonTerminationArgument [Line: 357]: Nontermination argument in form of an infinite program execution.
Nontermination argument in form of an infinite program execution.
Stem:
[L25] int max_loop ;
[L26] int clk ;
[L27] int num ;
[L28] int i ;
[L29] int e ;
[L30] int timer ;
[L31] char data_0 ;
[L32] char data_1 ;
[L75] int P_1_pc;
[L76] int P_1_st ;
[L77] int P_1_i ;
[L78] int P_1_ev ;
[L133] int P_2_pc ;
[L134] int P_2_st ;
[L135] int P_2_i ;
[L136] int P_2_ev ;
[L201] int C_1_pc ;
[L202] int C_1_st ;
[L203] int C_1_i ;
[L204] int C_1_ev ;
[L205] int C_1_pr ;
VAL [C_1_ev=0, C_1_i=0, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=0, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=0, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=0, num=0, timer=0]
[L617] int count ;
[L618] int __retres2 ;
[L622] num = 0
[L623] i = 0
[L624] clk = 0
[L625] max_loop = 8
[L627] timer = 0
[L628] P_1_pc = 0
[L629] P_2_pc = 0
[L630] C_1_pc = 0
[L632] count = 0
[L633] CALL init_model()
[L609] P_1_i = 1
[L610] P_2_i = 1
[L611] C_1_i = 1
VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0]
[L633] RET init_model()
[L634] CALL start_simulation()
[L547] int kernel_st ;
[L548] int tmp ;
[L549] int tmp___0 ;
[L553] kernel_st = 0
[L554] FCALL update_channels()
[L555] CALL init_threads()
[L305] COND TRUE (int )P_1_i == 1
[L306] P_1_st = 0
VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0]
[L310] COND TRUE (int )P_2_i == 1
[L311] P_2_st = 0
VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0]
[L315] COND TRUE (int )C_1_i == 1
[L316] C_1_st = 0
VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0]
[L555] RET init_threads()
[L556] FCALL fire_delta_events()
[L557] CALL activate_threads()
[L483] int tmp ;
[L484] int tmp___0 ;
[L485] int tmp___1 ;
[L489] CALL, EXPR is_P_1_triggered()
[L115] int __retres1 ;
VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0]
[L118] COND FALSE !((int )P_1_pc == 1)
VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0]
[L128] __retres1 = 0
VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, __retres1=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0]
[L130] return (__retres1);
VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, \result=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0]
[L489] RET, EXPR is_P_1_triggered()
[L489] tmp = is_P_1_triggered()
[L491] COND FALSE !(\read(tmp))
VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0]
[L497] CALL, EXPR is_P_2_triggered()
[L183] int __retres1 ;
VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0]
[L186] COND FALSE !((int )P_2_pc == 1)
VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0]
[L196] __retres1 = 0
VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, __retres1=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0]
[L198] return (__retres1);
VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, \result=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0]
[L497] RET, EXPR is_P_2_triggered()
[L497] tmp___0 = is_P_2_triggered()
[L499] COND FALSE !(\read(tmp___0))
VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0]
[L505] CALL, EXPR is_C_1_triggered()
[L265] int __retres1 ;
VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0]
[L268] COND FALSE !((int )C_1_pc == 1)
VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0]
[L278] COND FALSE !((int )C_1_pc == 2)
VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0]
[L288] __retres1 = 0
VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, __retres1=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0]
[L290] return (__retres1);
VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, \result=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0]
[L505] RET, EXPR is_C_1_triggered()
[L505] tmp___1 = is_C_1_triggered()
[L507] COND FALSE !(\read(tmp___1))
VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0]
[L557] RET activate_threads()
[L558] FCALL reset_delta_events()
[L561] COND TRUE 1
VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0]
[L564] kernel_st = 1
[L565] CALL eval()
[L350] int tmp ;
[L351] int tmp___0 ;
[L352] int tmp___1 ;
[L353] int tmp___2 ;
VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0]
Loop:
[L357] COND TRUE 1
[L360] CALL, EXPR exists_runnable_thread()
[L325] int __retres1 ;
[L328] COND TRUE (int )P_1_st == 0
[L329] __retres1 = 1
[L346] return (__retres1);
[L360] RET, EXPR exists_runnable_thread()
[L360] tmp___2 = exists_runnable_thread()
[L362] COND TRUE \read(tmp___2)
[L367] COND TRUE (int )P_1_st == 0
[L369] tmp = __VERIFIER_nondet_int()
[L371] COND FALSE !(\read(tmp))
[L382] COND TRUE (int )P_2_st == 0
[L384] tmp___0 = __VERIFIER_nondet_int()
[L386] COND FALSE !(\read(tmp___0))
[L397] COND TRUE (int )C_1_st == 0
[L399] tmp___1 = __VERIFIER_nondet_int()
[L401] COND FALSE !(\read(tmp___1))
End of lasso representation.
- StatisticsResult: NonterminationArgumentStatistics
Fixpoint
- NonterminatingLassoResult [Line: 357]: Nonterminating execution
Found a nonterminating execution for the following lasso shaped sequence of statements.
Stem:
[L25] int max_loop ;
[L26] int clk ;
[L27] int num ;
[L28] int i ;
[L29] int e ;
[L30] int timer ;
[L31] char data_0 ;
[L32] char data_1 ;
[L75] int P_1_pc;
[L76] int P_1_st ;
[L77] int P_1_i ;
[L78] int P_1_ev ;
[L133] int P_2_pc ;
[L134] int P_2_st ;
[L135] int P_2_i ;
[L136] int P_2_ev ;
[L201] int C_1_pc ;
[L202] int C_1_st ;
[L203] int C_1_i ;
[L204] int C_1_ev ;
[L205] int C_1_pr ;
VAL [C_1_ev=0, C_1_i=0, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=0, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=0, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=0, num=0, timer=0]
[L617] int count ;
[L618] int __retres2 ;
[L622] num = 0
[L623] i = 0
[L624] clk = 0
[L625] max_loop = 8
[L627] timer = 0
[L628] P_1_pc = 0
[L629] P_2_pc = 0
[L630] C_1_pc = 0
[L632] count = 0
[L633] CALL init_model()
[L609] P_1_i = 1
[L610] P_2_i = 1
[L611] C_1_i = 1
VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0]
[L633] RET init_model()
[L634] CALL start_simulation()
[L547] int kernel_st ;
[L548] int tmp ;
[L549] int tmp___0 ;
[L553] kernel_st = 0
[L554] FCALL update_channels()
[L555] CALL init_threads()
[L305] COND TRUE (int )P_1_i == 1
[L306] P_1_st = 0
VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0]
[L310] COND TRUE (int )P_2_i == 1
[L311] P_2_st = 0
VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0]
[L315] COND TRUE (int )C_1_i == 1
[L316] C_1_st = 0
VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0]
[L555] RET init_threads()
[L556] FCALL fire_delta_events()
[L557] CALL activate_threads()
[L483] int tmp ;
[L484] int tmp___0 ;
[L485] int tmp___1 ;
[L489] CALL, EXPR is_P_1_triggered()
[L115] int __retres1 ;
VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0]
[L118] COND FALSE !((int )P_1_pc == 1)
VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0]
[L128] __retres1 = 0
VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, __retres1=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0]
[L130] return (__retres1);
VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, \result=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0]
[L489] RET, EXPR is_P_1_triggered()
[L489] tmp = is_P_1_triggered()
[L491] COND FALSE !(\read(tmp))
VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0]
[L497] CALL, EXPR is_P_2_triggered()
[L183] int __retres1 ;
VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0]
[L186] COND FALSE !((int )P_2_pc == 1)
VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0]
[L196] __retres1 = 0
VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, __retres1=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0]
[L198] return (__retres1);
VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, \result=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0]
[L497] RET, EXPR is_P_2_triggered()
[L497] tmp___0 = is_P_2_triggered()
[L499] COND FALSE !(\read(tmp___0))
VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0]
[L505] CALL, EXPR is_C_1_triggered()
[L265] int __retres1 ;
VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0]
[L268] COND FALSE !((int )C_1_pc == 1)
VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0]
[L278] COND FALSE !((int )C_1_pc == 2)
VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0]
[L288] __retres1 = 0
VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, __retres1=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0]
[L290] return (__retres1);
VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, \result=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0]
[L505] RET, EXPR is_C_1_triggered()
[L505] tmp___1 = is_C_1_triggered()
[L507] COND FALSE !(\read(tmp___1))
VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0]
[L557] RET activate_threads()
[L558] FCALL reset_delta_events()
[L561] COND TRUE 1
VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0]
[L564] kernel_st = 1
[L565] CALL eval()
[L350] int tmp ;
[L351] int tmp___0 ;
[L352] int tmp___1 ;
[L353] int tmp___2 ;
VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, clk=0, data_0=0, data_1=0, e=0, i=0, max_loop=8, num=0, timer=0]
Loop:
[L357] COND TRUE 1
[L360] CALL, EXPR exists_runnable_thread()
[L325] int __retres1 ;
[L328] COND TRUE (int )P_1_st == 0
[L329] __retres1 = 1
[L346] return (__retres1);
[L360] RET, EXPR exists_runnable_thread()
[L360] tmp___2 = exists_runnable_thread()
[L362] COND TRUE \read(tmp___2)
[L367] COND TRUE (int )P_1_st == 0
[L369] tmp = __VERIFIER_nondet_int()
[L371] COND FALSE !(\read(tmp))
[L382] COND TRUE (int )P_2_st == 0
[L384] tmp___0 = __VERIFIER_nondet_int()
[L386] COND FALSE !(\read(tmp___0))
[L397] COND TRUE (int )C_1_st == 0
[L399] tmp___1 = __VERIFIER_nondet_int()
[L401] COND FALSE !(\read(tmp___1))
End of lasso representation.
RESULT: Ultimate proved your program to be incorrect!
[2024-11-08 16:34:30,206 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2995450b-1a7f-4efe-a580-fe680ef040d7/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0
Received shutdown request...
--- End real Ultimate output ---
Execution finished normally
Writing output log to file Ultimate.log
Writing human readable error path to file UltimateCounterExample.errorpath
Result:
FALSE(TERM)