./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/seq-mthreaded/pals_lcr-var-start-time.6.1.ufo.BOUNDED-12.pals.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version a0165632 Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d89144d0-8224-4025-b821-05d2d1799c8c/bin/uautomizer-verify-jihMAELWvX/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d89144d0-8224-4025-b821-05d2d1799c8c/bin/uautomizer-verify-jihMAELWvX/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d89144d0-8224-4025-b821-05d2d1799c8c/bin/uautomizer-verify-jihMAELWvX/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d89144d0-8224-4025-b821-05d2d1799c8c/bin/uautomizer-verify-jihMAELWvX/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/seq-mthreaded/pals_lcr-var-start-time.6.1.ufo.BOUNDED-12.pals.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d89144d0-8224-4025-b821-05d2d1799c8c/bin/uautomizer-verify-jihMAELWvX/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d89144d0-8224-4025-b821-05d2d1799c8c/bin/uautomizer-verify-jihMAELWvX --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 5cbdd74a230613e4bdaea53735767d2cb8a557f2fb27b4c6d6d20587e28e4a0f --- Real Ultimate output --- This is Ultimate 0.2.5-dev-a016563 [2024-11-08 18:17:00,337 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-08 18:17:00,402 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d89144d0-8224-4025-b821-05d2d1799c8c/bin/uautomizer-verify-jihMAELWvX/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-11-08 18:17:00,407 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-08 18:17:00,407 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-08 18:17:00,444 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-08 18:17:00,447 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-08 18:17:00,447 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-08 18:17:00,448 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-08 18:17:00,448 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-08 18:17:00,449 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-08 18:17:00,449 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-08 18:17:00,449 INFO L153 SettingsManager]: * Use SBE=true [2024-11-08 18:17:00,454 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-11-08 18:17:00,454 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-11-08 18:17:00,455 INFO L153 SettingsManager]: * Use old map elimination=false [2024-11-08 18:17:00,455 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-11-08 18:17:00,455 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-11-08 18:17:00,455 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-11-08 18:17:00,456 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-08 18:17:00,456 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-11-08 18:17:00,458 INFO L153 SettingsManager]: * sizeof long=4 [2024-11-08 18:17:00,458 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-08 18:17:00,459 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-11-08 18:17:00,459 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-08 18:17:00,459 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-11-08 18:17:00,459 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-11-08 18:17:00,460 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-11-08 18:17:00,460 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-11-08 18:17:00,460 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-11-08 18:17:00,460 INFO L153 SettingsManager]: * sizeof long double=12 [2024-11-08 18:17:00,461 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-08 18:17:00,461 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-11-08 18:17:00,461 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-08 18:17:00,461 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-11-08 18:17:00,462 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-08 18:17:00,462 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-08 18:17:00,462 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-11-08 18:17:00,463 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-11-08 18:17:00,464 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d89144d0-8224-4025-b821-05d2d1799c8c/bin/uautomizer-verify-jihMAELWvX/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d89144d0-8224-4025-b821-05d2d1799c8c/bin/uautomizer-verify-jihMAELWvX Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 5cbdd74a230613e4bdaea53735767d2cb8a557f2fb27b4c6d6d20587e28e4a0f [2024-11-08 18:17:00,705 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-08 18:17:00,733 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-08 18:17:00,738 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-08 18:17:00,740 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-08 18:17:00,740 INFO L274 PluginConnector]: CDTParser initialized [2024-11-08 18:17:00,741 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d89144d0-8224-4025-b821-05d2d1799c8c/bin/uautomizer-verify-jihMAELWvX/../../sv-benchmarks/c/seq-mthreaded/pals_lcr-var-start-time.6.1.ufo.BOUNDED-12.pals.c Unable to find full path for "g++" [2024-11-08 18:17:02,764 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-11-08 18:17:03,015 INFO L384 CDTParser]: Found 1 translation units. [2024-11-08 18:17:03,015 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d89144d0-8224-4025-b821-05d2d1799c8c/sv-benchmarks/c/seq-mthreaded/pals_lcr-var-start-time.6.1.ufo.BOUNDED-12.pals.c [2024-11-08 18:17:03,034 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d89144d0-8224-4025-b821-05d2d1799c8c/bin/uautomizer-verify-jihMAELWvX/data/781e9f4e0/3c44e6b28dea45fc91d9e974fe8dea7c/FLAG359a46c31 [2024-11-08 18:17:03,367 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d89144d0-8224-4025-b821-05d2d1799c8c/bin/uautomizer-verify-jihMAELWvX/data/781e9f4e0/3c44e6b28dea45fc91d9e974fe8dea7c [2024-11-08 18:17:03,370 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-08 18:17:03,371 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-08 18:17:03,373 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-08 18:17:03,373 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-08 18:17:03,382 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-08 18:17:03,383 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 08.11 06:17:03" (1/1) ... [2024-11-08 18:17:03,384 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@7f44e95a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 06:17:03, skipping insertion in model container [2024-11-08 18:17:03,384 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 08.11 06:17:03" (1/1) ... [2024-11-08 18:17:03,423 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-08 18:17:03,710 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-08 18:17:03,724 INFO L200 MainTranslator]: Completed pre-run [2024-11-08 18:17:03,825 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-08 18:17:03,859 INFO L204 MainTranslator]: Completed translation [2024-11-08 18:17:03,860 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 06:17:03 WrapperNode [2024-11-08 18:17:03,860 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-08 18:17:03,861 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-08 18:17:03,862 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-08 18:17:03,862 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-08 18:17:03,870 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 06:17:03" (1/1) ... [2024-11-08 18:17:03,887 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 06:17:03" (1/1) ... [2024-11-08 18:17:03,930 INFO L138 Inliner]: procedures = 25, calls = 18, calls flagged for inlining = 13, calls inlined = 13, statements flattened = 435 [2024-11-08 18:17:03,930 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-08 18:17:03,931 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-08 18:17:03,931 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-08 18:17:03,931 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-08 18:17:03,947 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 06:17:03" (1/1) ... [2024-11-08 18:17:03,948 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 06:17:03" (1/1) ... [2024-11-08 18:17:03,951 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 06:17:03" (1/1) ... [2024-11-08 18:17:03,968 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-11-08 18:17:03,969 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 06:17:03" (1/1) ... [2024-11-08 18:17:03,969 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 06:17:03" (1/1) ... [2024-11-08 18:17:03,980 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 06:17:03" (1/1) ... [2024-11-08 18:17:03,994 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 06:17:03" (1/1) ... [2024-11-08 18:17:03,997 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 06:17:03" (1/1) ... [2024-11-08 18:17:03,999 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 06:17:03" (1/1) ... [2024-11-08 18:17:04,003 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-08 18:17:04,004 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-11-08 18:17:04,004 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-11-08 18:17:04,005 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-11-08 18:17:04,006 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 06:17:03" (1/1) ... [2024-11-08 18:17:04,017 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 18:17:04,028 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d89144d0-8224-4025-b821-05d2d1799c8c/bin/uautomizer-verify-jihMAELWvX/z3 [2024-11-08 18:17:04,042 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d89144d0-8224-4025-b821-05d2d1799c8c/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 18:17:04,048 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d89144d0-8224-4025-b821-05d2d1799c8c/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-11-08 18:17:04,081 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-08 18:17:04,082 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-11-08 18:17:04,082 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-08 18:17:04,082 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-08 18:17:04,229 INFO L238 CfgBuilder]: Building ICFG [2024-11-08 18:17:04,234 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-08 18:17:04,902 INFO L? ?]: Removed 52 outVars from TransFormulas that were not future-live. [2024-11-08 18:17:04,902 INFO L287 CfgBuilder]: Performing block encoding [2024-11-08 18:17:04,924 INFO L311 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-08 18:17:04,924 INFO L316 CfgBuilder]: Removed 0 assume(true) statements. [2024-11-08 18:17:04,924 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 08.11 06:17:04 BoogieIcfgContainer [2024-11-08 18:17:04,925 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-11-08 18:17:04,925 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-11-08 18:17:04,925 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-11-08 18:17:04,928 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-11-08 18:17:04,929 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-08 18:17:04,929 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 08.11 06:17:03" (1/3) ... [2024-11-08 18:17:04,930 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1473441e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 08.11 06:17:04, skipping insertion in model container [2024-11-08 18:17:04,930 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-08 18:17:04,930 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 06:17:03" (2/3) ... [2024-11-08 18:17:04,930 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1473441e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 08.11 06:17:04, skipping insertion in model container [2024-11-08 18:17:04,931 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-08 18:17:04,931 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 08.11 06:17:04" (3/3) ... [2024-11-08 18:17:04,932 INFO L332 chiAutomizerObserver]: Analyzing ICFG pals_lcr-var-start-time.6.1.ufo.BOUNDED-12.pals.c [2024-11-08 18:17:04,989 INFO L300 stractBuchiCegarLoop]: Interprodecural is true [2024-11-08 18:17:04,989 INFO L301 stractBuchiCegarLoop]: Hoare is None [2024-11-08 18:17:04,989 INFO L302 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-11-08 18:17:04,989 INFO L303 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-11-08 18:17:04,989 INFO L304 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-11-08 18:17:04,989 INFO L305 stractBuchiCegarLoop]: Difference is false [2024-11-08 18:17:04,989 INFO L306 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-11-08 18:17:04,990 INFO L310 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-11-08 18:17:04,995 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 122 states, 121 states have (on average 1.743801652892562) internal successors, (211), 121 states have internal predecessors, (211), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 18:17:05,017 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2024-11-08 18:17:05,017 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 18:17:05,018 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 18:17:05,026 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1] [2024-11-08 18:17:05,026 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 18:17:05,026 INFO L332 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-11-08 18:17:05,027 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 122 states, 121 states have (on average 1.743801652892562) internal successors, (211), 121 states have internal predecessors, (211), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 18:17:05,033 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2024-11-08 18:17:05,033 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 18:17:05,033 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 18:17:05,034 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1] [2024-11-08 18:17:05,034 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 18:17:05,043 INFO L745 eck$LassoCheckResult]: Stem: 22#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(50, 2);call #Ultimate.allocInit(12, 3);~nomsg~0 := -1;~r1~0 := 0;~p1~0 := 0;~p1_old~0 := 0;~p1_new~0 := 0;~id1~0 := 0;~st1~0 := 0;~send1~0 := 0;~mode1~0 := 0;~alive1~0 := 0;~p2~0 := 0;~p2_old~0 := 0;~p2_new~0 := 0;~id2~0 := 0;~st2~0 := 0;~send2~0 := 0;~mode2~0 := 0;~alive2~0 := 0;~p3~0 := 0;~p3_old~0 := 0;~p3_new~0 := 0;~id3~0 := 0;~st3~0 := 0;~send3~0 := 0;~mode3~0 := 0;~alive3~0 := 0;~p4~0 := 0;~p4_old~0 := 0;~p4_new~0 := 0;~id4~0 := 0;~st4~0 := 0;~send4~0 := 0;~mode4~0 := 0;~alive4~0 := 0;~p5~0 := 0;~p5_old~0 := 0;~p5_new~0 := 0;~id5~0 := 0;~st5~0 := 0;~send5~0 := 0;~mode5~0 := 0;~alive5~0 := 0;~p6~0 := 0;~p6_old~0 := 0;~p6_new~0 := 0;~id6~0 := 0;~st6~0 := 0;~send6~0 := 0;~mode6~0 := 0;~alive6~0 := 0; 30#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet4#1, main_#t~nondet5#1, main_#t~nondet6#1, main_#t~nondet7#1, main_#t~nondet8#1, main_#t~nondet9#1, main_#t~nondet10#1, main_#t~nondet11#1, main_#t~nondet12#1, main_#t~nondet13#1, main_#t~nondet14#1, main_#t~nondet15#1, main_#t~nondet16#1, main_#t~nondet17#1, main_#t~nondet18#1, main_#t~nondet19#1, main_#t~nondet20#1, main_#t~nondet21#1, main_#t~nondet22#1, main_#t~nondet23#1, main_#t~nondet24#1, main_#t~nondet25#1, main_#t~nondet26#1, main_#t~nondet27#1, main_#t~nondet28#1, main_#t~nondet29#1, main_#t~nondet30#1, main_#t~nondet31#1, main_#t~nondet32#1, main_#t~nondet33#1, main_#t~nondet34#1, main_#t~ret35#1, main_#t~ret36#1, main_#t~post37#1, main_~c1~0#1, main_~i2~0#1;havoc main_~c1~0#1;havoc main_~i2~0#1;main_~c1~0#1 := 0;havoc main_#t~nondet4#1;~r1~0 := main_#t~nondet4#1;havoc main_#t~nondet4#1;havoc main_#t~nondet5#1;~id1~0 := main_#t~nondet5#1;havoc main_#t~nondet5#1;havoc main_#t~nondet6#1;~st1~0 := main_#t~nondet6#1;havoc main_#t~nondet6#1;havoc main_#t~nondet7#1;~send1~0 := main_#t~nondet7#1;havoc main_#t~nondet7#1;havoc main_#t~nondet8#1;assume 0 == main_#t~nondet8#1 || 1 == main_#t~nondet8#1;~mode1~0 := (if 0 == main_#t~nondet8#1 % 256 then 0 else 1);havoc main_#t~nondet8#1;havoc main_#t~nondet9#1;assume 0 == main_#t~nondet9#1 || 1 == main_#t~nondet9#1;~alive1~0 := (if 0 == main_#t~nondet9#1 % 256 then 0 else 1);havoc main_#t~nondet9#1;havoc main_#t~nondet10#1;~id2~0 := main_#t~nondet10#1;havoc main_#t~nondet10#1;havoc main_#t~nondet11#1;~st2~0 := main_#t~nondet11#1;havoc main_#t~nondet11#1;havoc main_#t~nondet12#1;~send2~0 := main_#t~nondet12#1;havoc main_#t~nondet12#1;havoc main_#t~nondet13#1;assume 0 == main_#t~nondet13#1 || 1 == main_#t~nondet13#1;~mode2~0 := (if 0 == main_#t~nondet13#1 % 256 then 0 else 1);havoc main_#t~nondet13#1;havoc main_#t~nondet14#1;assume 0 == main_#t~nondet14#1 || 1 == main_#t~nondet14#1;~alive2~0 := (if 0 == main_#t~nondet14#1 % 256 then 0 else 1);havoc main_#t~nondet14#1;havoc main_#t~nondet15#1;~id3~0 := main_#t~nondet15#1;havoc main_#t~nondet15#1;havoc main_#t~nondet16#1;~st3~0 := main_#t~nondet16#1;havoc main_#t~nondet16#1;havoc main_#t~nondet17#1;~send3~0 := main_#t~nondet17#1;havoc main_#t~nondet17#1;havoc main_#t~nondet18#1;assume 0 == main_#t~nondet18#1 || 1 == main_#t~nondet18#1;~mode3~0 := (if 0 == main_#t~nondet18#1 % 256 then 0 else 1);havoc main_#t~nondet18#1;havoc main_#t~nondet19#1;assume 0 == main_#t~nondet19#1 || 1 == main_#t~nondet19#1;~alive3~0 := (if 0 == main_#t~nondet19#1 % 256 then 0 else 1);havoc main_#t~nondet19#1;havoc main_#t~nondet20#1;~id4~0 := main_#t~nondet20#1;havoc main_#t~nondet20#1;havoc main_#t~nondet21#1;~st4~0 := main_#t~nondet21#1;havoc main_#t~nondet21#1;havoc main_#t~nondet22#1;~send4~0 := main_#t~nondet22#1;havoc main_#t~nondet22#1;havoc main_#t~nondet23#1;assume 0 == main_#t~nondet23#1 || 1 == main_#t~nondet23#1;~mode4~0 := (if 0 == main_#t~nondet23#1 % 256 then 0 else 1);havoc main_#t~nondet23#1;havoc main_#t~nondet24#1;assume 0 == main_#t~nondet24#1 || 1 == main_#t~nondet24#1;~alive4~0 := (if 0 == main_#t~nondet24#1 % 256 then 0 else 1);havoc main_#t~nondet24#1;havoc main_#t~nondet25#1;~id5~0 := main_#t~nondet25#1;havoc main_#t~nondet25#1;havoc main_#t~nondet26#1;~st5~0 := main_#t~nondet26#1;havoc main_#t~nondet26#1;havoc main_#t~nondet27#1;~send5~0 := main_#t~nondet27#1;havoc main_#t~nondet27#1;havoc main_#t~nondet28#1;assume 0 == main_#t~nondet28#1 || 1 == main_#t~nondet28#1;~mode5~0 := (if 0 == main_#t~nondet28#1 % 256 then 0 else 1);havoc main_#t~nondet28#1;havoc main_#t~nondet29#1;assume 0 == main_#t~nondet29#1 || 1 == main_#t~nondet29#1;~alive5~0 := (if 0 == main_#t~nondet29#1 % 256 then 0 else 1);havoc main_#t~nondet29#1;havoc main_#t~nondet30#1;~id6~0 := main_#t~nondet30#1;havoc main_#t~nondet30#1;havoc main_#t~nondet31#1;~st6~0 := main_#t~nondet31#1;havoc main_#t~nondet31#1;havoc main_#t~nondet32#1;~send6~0 := main_#t~nondet32#1;havoc main_#t~nondet32#1;havoc main_#t~nondet33#1;assume 0 == main_#t~nondet33#1 || 1 == main_#t~nondet33#1;~mode6~0 := (if 0 == main_#t~nondet33#1 % 256 then 0 else 1);havoc main_#t~nondet33#1;havoc main_#t~nondet34#1;assume 0 == main_#t~nondet34#1 || 1 == main_#t~nondet34#1;~alive6~0 := (if 0 == main_#t~nondet34#1 % 256 then 0 else 1);havoc main_#t~nondet34#1;assume { :begin_inline_init } true;havoc init_#res#1;havoc init_~tmp~0#1;havoc init_~tmp~0#1; 114#L290true assume !(0 == ~r1~0);init_~tmp~0#1 := 0; 105#L290-1true init_#res#1 := init_~tmp~0#1; 82#init_returnLabel#1true main_#t~ret35#1 := init_#res#1;havoc init_~tmp~0#1;assume { :end_inline_init } true;main_~i2~0#1 := main_#t~ret35#1;havoc main_#t~ret35#1;assume { :begin_inline_assume_abort_if_not } true;assume_abort_if_not_#in~cond#1 := main_~i2~0#1;havoc assume_abort_if_not_~cond#1;assume_abort_if_not_~cond#1 := assume_abort_if_not_#in~cond#1; 34#L22true assume 0 == assume_abort_if_not_~cond#1;assume false; 89#L21true havoc assume_abort_if_not_~cond#1;havoc assume_abort_if_not_#in~cond#1;assume { :end_inline_assume_abort_if_not } true;~p1_old~0 := ~nomsg~0;~p1_new~0 := ~nomsg~0;~p2_old~0 := ~nomsg~0;~p2_new~0 := ~nomsg~0;~p3_old~0 := ~nomsg~0;~p3_new~0 := ~nomsg~0;~p4_old~0 := ~nomsg~0;~p4_new~0 := ~nomsg~0;~p5_old~0 := ~nomsg~0;~p5_new~0 := ~nomsg~0;~p6_old~0 := ~nomsg~0;~p6_new~0 := ~nomsg~0;main_~i2~0#1 := 0; 74#L531-3true [2024-11-08 18:17:05,044 INFO L747 eck$LassoCheckResult]: Loop: 74#L531-3true assume main_~i2~0#1 < 12; 10#L531-1true assume !!(main_~i2~0#1 < 12);assume { :begin_inline_node1 } true;havoc node1_~m1~0#1;havoc node1_~m1~0#1;node1_~m1~0#1 := ~nomsg~0; 106#L84true assume !(0 != ~mode1~0 % 256); 15#L104true assume 0 != ~alive1~0 % 256;~p1_new~0 := (if (if ~send1~0 != ~nomsg~0 && ~p1_new~0 == ~nomsg~0 then ~send1~0 else ~p1_new~0) % 256 <= 127 then (if ~send1~0 != ~nomsg~0 && ~p1_new~0 == ~nomsg~0 then ~send1~0 else ~p1_new~0) % 256 else (if ~send1~0 != ~nomsg~0 && ~p1_new~0 == ~nomsg~0 then ~send1~0 else ~p1_new~0) % 256 - 256); 52#L107-2true ~mode1~0 := 1; 19#L84-2true havoc node1_~m1~0#1;assume { :end_inline_node1 } true;assume { :begin_inline_node2 } true;havoc node2_~m2~0#1;havoc node2_~m2~0#1;node2_~m2~0#1 := ~nomsg~0; 20#L121true assume 0 != ~mode2~0 % 256;node2_~m2~0#1 := ~p1_old~0;~p1_old~0 := ~nomsg~0; 70#L124true assume !(node2_~m2~0#1 != ~nomsg~0); 29#L124-1true ~mode2~0 := 0; 7#L121-2true havoc node2_~m2~0#1;assume { :end_inline_node2 } true;assume { :begin_inline_node3 } true;havoc node3_~m3~0#1;havoc node3_~m3~0#1;node3_~m3~0#1 := ~nomsg~0; 38#L155true assume 0 != ~mode3~0 % 256;node3_~m3~0#1 := ~p2_old~0;~p2_old~0 := ~nomsg~0; 12#L158true assume !(node3_~m3~0#1 != ~nomsg~0); 84#L158-1true ~mode3~0 := 0; 90#L155-2true havoc node3_~m3~0#1;assume { :end_inline_node3 } true;assume { :begin_inline_node4 } true;havoc node4_~m4~0#1;havoc node4_~m4~0#1;node4_~m4~0#1 := ~nomsg~0; 77#L189true assume !(0 != ~mode4~0 % 256); 25#L206true assume 0 != ~alive4~0 % 256;~p4_new~0 := (if (if ~send4~0 != ~nomsg~0 && ~p4_new~0 == ~nomsg~0 then ~send4~0 else ~p4_new~0) % 256 <= 127 then (if ~send4~0 != ~nomsg~0 && ~p4_new~0 == ~nomsg~0 then ~send4~0 else ~p4_new~0) % 256 else (if ~send4~0 != ~nomsg~0 && ~p4_new~0 == ~nomsg~0 then ~send4~0 else ~p4_new~0) % 256 - 256); 93#L209-2true ~mode4~0 := 1; 39#L189-2true havoc node4_~m4~0#1;assume { :end_inline_node4 } true;assume { :begin_inline_node5 } true;havoc node5_~m5~0#1;havoc node5_~m5~0#1;node5_~m5~0#1 := ~nomsg~0; 53#L223true assume 0 != ~mode5~0 % 256;node5_~m5~0#1 := ~p4_old~0;~p4_old~0 := ~nomsg~0; 9#L226true assume !(node5_~m5~0#1 != ~nomsg~0); 33#L226-1true ~mode5~0 := 0; 44#L223-2true havoc node5_~m5~0#1;assume { :end_inline_node5 } true;assume { :begin_inline_node6 } true;havoc node6_~m6~0#1;havoc node6_~m6~0#1;node6_~m6~0#1 := ~nomsg~0; 110#L257true assume !(0 != ~mode6~0 % 256); 79#L274true assume 0 != ~alive6~0 % 256;~p6_new~0 := (if (if ~send6~0 != ~nomsg~0 && ~p6_new~0 == ~nomsg~0 then ~send6~0 else ~p6_new~0) % 256 <= 127 then (if ~send6~0 != ~nomsg~0 && ~p6_new~0 == ~nomsg~0 then ~send6~0 else ~p6_new~0) % 256 else (if ~send6~0 != ~nomsg~0 && ~p6_new~0 == ~nomsg~0 then ~send6~0 else ~p6_new~0) % 256 - 256); 113#L277-2true ~mode6~0 := 1; 32#L257-2true havoc node6_~m6~0#1;assume { :end_inline_node6 } true;~p1_old~0 := ~p1_new~0;~p1_new~0 := ~nomsg~0;~p2_old~0 := ~p2_new~0;~p2_new~0 := ~nomsg~0;~p3_old~0 := ~p3_new~0;~p3_new~0 := ~nomsg~0;~p4_old~0 := ~p4_new~0;~p4_new~0 := ~nomsg~0;~p5_old~0 := ~p5_new~0;~p5_new~0 := ~nomsg~0;~p6_old~0 := ~p6_new~0;~p6_new~0 := ~nomsg~0;assume { :begin_inline_check } true;havoc check_#res#1;havoc check_~tmp~1#1;havoc check_~tmp~1#1; 31#L463true assume !(~st1~0 + ~st2~0 + ~st3~0 + ~st4~0 + ~st5~0 + ~st6~0 <= 1);check_~tmp~1#1 := 0; 118#L463-1true check_#res#1 := check_~tmp~1#1; 14#check_returnLabel#1true main_#t~ret36#1 := check_#res#1;havoc check_~tmp~1#1;assume { :end_inline_check } true;main_~c1~0#1 := main_#t~ret36#1;havoc main_#t~ret36#1;assume { :begin_inline_assert } true;assert_#in~arg#1 := (if 0 == main_~c1~0#1 then 0 else 1);havoc assert_~arg#1;assert_~arg#1 := assert_#in~arg#1; 11#L564true assume !(0 == assert_~arg#1 % 256); 36#L559true havoc assert_~arg#1;havoc assert_#in~arg#1;assume { :end_inline_assert } true;main_#t~post37#1 := main_~i2~0#1;main_~i2~0#1 := 1 + main_#t~post37#1;havoc main_#t~post37#1; 74#L531-3true [2024-11-08 18:17:05,050 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:17:05,050 INFO L85 PathProgramCache]: Analyzing trace with hash 2035845626, now seen corresponding path program 1 times [2024-11-08 18:17:05,060 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 18:17:05,061 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2142038362] [2024-11-08 18:17:05,061 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:17:05,062 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 18:17:05,233 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 18:17:05,353 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 18:17:05,353 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 18:17:05,354 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2142038362] [2024-11-08 18:17:05,354 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2142038362] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 18:17:05,354 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 18:17:05,355 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-08 18:17:05,356 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1088448223] [2024-11-08 18:17:05,358 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 18:17:05,362 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 18:17:05,364 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:17:05,364 INFO L85 PathProgramCache]: Analyzing trace with hash -869354342, now seen corresponding path program 1 times [2024-11-08 18:17:05,364 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 18:17:05,364 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [686864379] [2024-11-08 18:17:05,365 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:17:05,365 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 18:17:05,485 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 18:17:05,831 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 18:17:05,831 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 18:17:05,832 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [686864379] [2024-11-08 18:17:05,832 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [686864379] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 18:17:05,832 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 18:17:05,832 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-08 18:17:05,833 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2025496633] [2024-11-08 18:17:05,833 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 18:17:05,834 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 18:17:05,835 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 18:17:05,875 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2024-11-08 18:17:05,876 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2024-11-08 18:17:05,879 INFO L87 Difference]: Start difference. First operand has 122 states, 121 states have (on average 1.743801652892562) internal successors, (211), 121 states have internal predecessors, (211), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 3.5) internal successors, (7), 2 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 18:17:05,903 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 18:17:05,904 INFO L93 Difference]: Finished difference Result 121 states and 208 transitions. [2024-11-08 18:17:05,905 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 121 states and 208 transitions. [2024-11-08 18:17:05,912 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 69 [2024-11-08 18:17:05,924 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 121 states to 116 states and 202 transitions. [2024-11-08 18:17:05,925 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 116 [2024-11-08 18:17:05,928 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 116 [2024-11-08 18:17:05,929 INFO L73 IsDeterministic]: Start isDeterministic. Operand 116 states and 202 transitions. [2024-11-08 18:17:05,931 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 18:17:05,931 INFO L218 hiAutomatonCegarLoop]: Abstraction has 116 states and 202 transitions. [2024-11-08 18:17:05,949 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 116 states and 202 transitions. [2024-11-08 18:17:05,969 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 116 to 116. [2024-11-08 18:17:05,971 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 116 states, 116 states have (on average 1.7413793103448276) internal successors, (202), 115 states have internal predecessors, (202), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 18:17:05,972 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 116 states to 116 states and 202 transitions. [2024-11-08 18:17:05,974 INFO L240 hiAutomatonCegarLoop]: Abstraction has 116 states and 202 transitions. [2024-11-08 18:17:05,975 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-11-08 18:17:05,979 INFO L425 stractBuchiCegarLoop]: Abstraction has 116 states and 202 transitions. [2024-11-08 18:17:05,979 INFO L332 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-11-08 18:17:05,979 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 116 states and 202 transitions. [2024-11-08 18:17:05,981 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 69 [2024-11-08 18:17:05,981 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 18:17:05,981 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 18:17:05,983 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1] [2024-11-08 18:17:05,983 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 18:17:05,984 INFO L745 eck$LassoCheckResult]: Stem: 294#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(50, 2);call #Ultimate.allocInit(12, 3);~nomsg~0 := -1;~r1~0 := 0;~p1~0 := 0;~p1_old~0 := 0;~p1_new~0 := 0;~id1~0 := 0;~st1~0 := 0;~send1~0 := 0;~mode1~0 := 0;~alive1~0 := 0;~p2~0 := 0;~p2_old~0 := 0;~p2_new~0 := 0;~id2~0 := 0;~st2~0 := 0;~send2~0 := 0;~mode2~0 := 0;~alive2~0 := 0;~p3~0 := 0;~p3_old~0 := 0;~p3_new~0 := 0;~id3~0 := 0;~st3~0 := 0;~send3~0 := 0;~mode3~0 := 0;~alive3~0 := 0;~p4~0 := 0;~p4_old~0 := 0;~p4_new~0 := 0;~id4~0 := 0;~st4~0 := 0;~send4~0 := 0;~mode4~0 := 0;~alive4~0 := 0;~p5~0 := 0;~p5_old~0 := 0;~p5_new~0 := 0;~id5~0 := 0;~st5~0 := 0;~send5~0 := 0;~mode5~0 := 0;~alive5~0 := 0;~p6~0 := 0;~p6_old~0 := 0;~p6_new~0 := 0;~id6~0 := 0;~st6~0 := 0;~send6~0 := 0;~mode6~0 := 0;~alive6~0 := 0; 295#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet4#1, main_#t~nondet5#1, main_#t~nondet6#1, main_#t~nondet7#1, main_#t~nondet8#1, main_#t~nondet9#1, main_#t~nondet10#1, main_#t~nondet11#1, main_#t~nondet12#1, main_#t~nondet13#1, main_#t~nondet14#1, main_#t~nondet15#1, main_#t~nondet16#1, main_#t~nondet17#1, main_#t~nondet18#1, main_#t~nondet19#1, main_#t~nondet20#1, main_#t~nondet21#1, main_#t~nondet22#1, main_#t~nondet23#1, main_#t~nondet24#1, main_#t~nondet25#1, main_#t~nondet26#1, main_#t~nondet27#1, main_#t~nondet28#1, main_#t~nondet29#1, main_#t~nondet30#1, main_#t~nondet31#1, main_#t~nondet32#1, main_#t~nondet33#1, main_#t~nondet34#1, main_#t~ret35#1, main_#t~ret36#1, main_#t~post37#1, main_~c1~0#1, main_~i2~0#1;havoc main_~c1~0#1;havoc main_~i2~0#1;main_~c1~0#1 := 0;havoc main_#t~nondet4#1;~r1~0 := main_#t~nondet4#1;havoc main_#t~nondet4#1;havoc main_#t~nondet5#1;~id1~0 := main_#t~nondet5#1;havoc main_#t~nondet5#1;havoc main_#t~nondet6#1;~st1~0 := main_#t~nondet6#1;havoc main_#t~nondet6#1;havoc main_#t~nondet7#1;~send1~0 := main_#t~nondet7#1;havoc main_#t~nondet7#1;havoc main_#t~nondet8#1;assume 0 == main_#t~nondet8#1 || 1 == main_#t~nondet8#1;~mode1~0 := (if 0 == main_#t~nondet8#1 % 256 then 0 else 1);havoc main_#t~nondet8#1;havoc main_#t~nondet9#1;assume 0 == main_#t~nondet9#1 || 1 == main_#t~nondet9#1;~alive1~0 := (if 0 == main_#t~nondet9#1 % 256 then 0 else 1);havoc main_#t~nondet9#1;havoc main_#t~nondet10#1;~id2~0 := main_#t~nondet10#1;havoc main_#t~nondet10#1;havoc main_#t~nondet11#1;~st2~0 := main_#t~nondet11#1;havoc main_#t~nondet11#1;havoc main_#t~nondet12#1;~send2~0 := main_#t~nondet12#1;havoc main_#t~nondet12#1;havoc main_#t~nondet13#1;assume 0 == main_#t~nondet13#1 || 1 == main_#t~nondet13#1;~mode2~0 := (if 0 == main_#t~nondet13#1 % 256 then 0 else 1);havoc main_#t~nondet13#1;havoc main_#t~nondet14#1;assume 0 == main_#t~nondet14#1 || 1 == main_#t~nondet14#1;~alive2~0 := (if 0 == main_#t~nondet14#1 % 256 then 0 else 1);havoc main_#t~nondet14#1;havoc main_#t~nondet15#1;~id3~0 := main_#t~nondet15#1;havoc main_#t~nondet15#1;havoc main_#t~nondet16#1;~st3~0 := main_#t~nondet16#1;havoc main_#t~nondet16#1;havoc main_#t~nondet17#1;~send3~0 := main_#t~nondet17#1;havoc main_#t~nondet17#1;havoc main_#t~nondet18#1;assume 0 == main_#t~nondet18#1 || 1 == main_#t~nondet18#1;~mode3~0 := (if 0 == main_#t~nondet18#1 % 256 then 0 else 1);havoc main_#t~nondet18#1;havoc main_#t~nondet19#1;assume 0 == main_#t~nondet19#1 || 1 == main_#t~nondet19#1;~alive3~0 := (if 0 == main_#t~nondet19#1 % 256 then 0 else 1);havoc main_#t~nondet19#1;havoc main_#t~nondet20#1;~id4~0 := main_#t~nondet20#1;havoc main_#t~nondet20#1;havoc main_#t~nondet21#1;~st4~0 := main_#t~nondet21#1;havoc main_#t~nondet21#1;havoc main_#t~nondet22#1;~send4~0 := main_#t~nondet22#1;havoc main_#t~nondet22#1;havoc main_#t~nondet23#1;assume 0 == main_#t~nondet23#1 || 1 == main_#t~nondet23#1;~mode4~0 := (if 0 == main_#t~nondet23#1 % 256 then 0 else 1);havoc main_#t~nondet23#1;havoc main_#t~nondet24#1;assume 0 == main_#t~nondet24#1 || 1 == main_#t~nondet24#1;~alive4~0 := (if 0 == main_#t~nondet24#1 % 256 then 0 else 1);havoc main_#t~nondet24#1;havoc main_#t~nondet25#1;~id5~0 := main_#t~nondet25#1;havoc main_#t~nondet25#1;havoc main_#t~nondet26#1;~st5~0 := main_#t~nondet26#1;havoc main_#t~nondet26#1;havoc main_#t~nondet27#1;~send5~0 := main_#t~nondet27#1;havoc main_#t~nondet27#1;havoc main_#t~nondet28#1;assume 0 == main_#t~nondet28#1 || 1 == main_#t~nondet28#1;~mode5~0 := (if 0 == main_#t~nondet28#1 % 256 then 0 else 1);havoc main_#t~nondet28#1;havoc main_#t~nondet29#1;assume 0 == main_#t~nondet29#1 || 1 == main_#t~nondet29#1;~alive5~0 := (if 0 == main_#t~nondet29#1 % 256 then 0 else 1);havoc main_#t~nondet29#1;havoc main_#t~nondet30#1;~id6~0 := main_#t~nondet30#1;havoc main_#t~nondet30#1;havoc main_#t~nondet31#1;~st6~0 := main_#t~nondet31#1;havoc main_#t~nondet31#1;havoc main_#t~nondet32#1;~send6~0 := main_#t~nondet32#1;havoc main_#t~nondet32#1;havoc main_#t~nondet33#1;assume 0 == main_#t~nondet33#1 || 1 == main_#t~nondet33#1;~mode6~0 := (if 0 == main_#t~nondet33#1 % 256 then 0 else 1);havoc main_#t~nondet33#1;havoc main_#t~nondet34#1;assume 0 == main_#t~nondet34#1 || 1 == main_#t~nondet34#1;~alive6~0 := (if 0 == main_#t~nondet34#1 % 256 then 0 else 1);havoc main_#t~nondet34#1;assume { :begin_inline_init } true;havoc init_#res#1;havoc init_~tmp~0#1;havoc init_~tmp~0#1; 308#L290 assume !(0 == ~r1~0);init_~tmp~0#1 := 0; 257#L290-1 init_#res#1 := init_~tmp~0#1; 364#init_returnLabel#1 main_#t~ret35#1 := init_#res#1;havoc init_~tmp~0#1;assume { :end_inline_init } true;main_~i2~0#1 := main_#t~ret35#1;havoc main_#t~ret35#1;assume { :begin_inline_assume_abort_if_not } true;assume_abort_if_not_#in~cond#1 := main_~i2~0#1;havoc assume_abort_if_not_~cond#1;assume_abort_if_not_~cond#1 := assume_abort_if_not_#in~cond#1; 314#L22 assume !(0 == assume_abort_if_not_~cond#1); 315#L21 havoc assume_abort_if_not_~cond#1;havoc assume_abort_if_not_#in~cond#1;assume { :end_inline_assume_abort_if_not } true;~p1_old~0 := ~nomsg~0;~p1_new~0 := ~nomsg~0;~p2_old~0 := ~nomsg~0;~p2_new~0 := ~nomsg~0;~p3_old~0 := ~nomsg~0;~p3_new~0 := ~nomsg~0;~p4_old~0 := ~nomsg~0;~p4_new~0 := ~nomsg~0;~p5_old~0 := ~nomsg~0;~p5_new~0 := ~nomsg~0;~p6_old~0 := ~nomsg~0;~p6_new~0 := ~nomsg~0;main_~i2~0#1 := 0; 318#L531-3 [2024-11-08 18:17:05,984 INFO L747 eck$LassoCheckResult]: Loop: 318#L531-3 assume main_~i2~0#1 < 12; 270#L531-1 assume !!(main_~i2~0#1 < 12);assume { :begin_inline_node1 } true;havoc node1_~m1~0#1;havoc node1_~m1~0#1;node1_~m1~0#1 := ~nomsg~0; 271#L84 assume !(0 != ~mode1~0 % 256); 279#L104 assume 0 != ~alive1~0 % 256;~p1_new~0 := (if (if ~send1~0 != ~nomsg~0 && ~p1_new~0 == ~nomsg~0 then ~send1~0 else ~p1_new~0) % 256 <= 127 then (if ~send1~0 != ~nomsg~0 && ~p1_new~0 == ~nomsg~0 then ~send1~0 else ~p1_new~0) % 256 else (if ~send1~0 != ~nomsg~0 && ~p1_new~0 == ~nomsg~0 then ~send1~0 else ~p1_new~0) % 256 - 256); 280#L107-2 ~mode1~0 := 1; 289#L84-2 havoc node1_~m1~0#1;assume { :end_inline_node1 } true;assume { :begin_inline_node2 } true;havoc node2_~m2~0#1;havoc node2_~m2~0#1;node2_~m2~0#1 := ~nomsg~0; 290#L121 assume !(0 != ~mode2~0 % 256); 291#L138 assume 0 != ~alive2~0 % 256;~p2_new~0 := (if (if ~send2~0 != ~nomsg~0 && ~p2_new~0 == ~nomsg~0 then ~send2~0 else ~p2_new~0) % 256 <= 127 then (if ~send2~0 != ~nomsg~0 && ~p2_new~0 == ~nomsg~0 then ~send2~0 else ~p2_new~0) % 256 else (if ~send2~0 != ~nomsg~0 && ~p2_new~0 == ~nomsg~0 then ~send2~0 else ~p2_new~0) % 256 - 256); 320#L141-2 ~mode2~0 := 1; 263#L121-2 havoc node2_~m2~0#1;assume { :end_inline_node2 } true;assume { :begin_inline_node3 } true;havoc node3_~m3~0#1;havoc node3_~m3~0#1;node3_~m3~0#1 := ~nomsg~0; 264#L155 assume !(0 != ~mode3~0 % 256); 321#L172 assume 0 != ~alive3~0 % 256;~p3_new~0 := (if (if ~send3~0 != ~nomsg~0 && ~p3_new~0 == ~nomsg~0 then ~send3~0 else ~p3_new~0) % 256 <= 127 then (if ~send3~0 != ~nomsg~0 && ~p3_new~0 == ~nomsg~0 then ~send3~0 else ~p3_new~0) % 256 else (if ~send3~0 != ~nomsg~0 && ~p3_new~0 == ~nomsg~0 then ~send3~0 else ~p3_new~0) % 256 - 256); 255#L175-2 ~mode3~0 := 1; 346#L155-2 havoc node3_~m3~0#1;assume { :end_inline_node3 } true;assume { :begin_inline_node4 } true;havoc node4_~m4~0#1;havoc node4_~m4~0#1;node4_~m4~0#1 := ~nomsg~0; 358#L189 assume 0 != ~mode4~0 % 256;node4_~m4~0#1 := ~p3_old~0;~p3_old~0 := ~nomsg~0; 359#L192 assume !(node4_~m4~0#1 != ~nomsg~0); 329#L192-1 ~mode4~0 := 0; 322#L189-2 havoc node4_~m4~0#1;assume { :end_inline_node4 } true;assume { :begin_inline_node5 } true;havoc node5_~m5~0#1;havoc node5_~m5~0#1;node5_~m5~0#1 := ~nomsg~0; 323#L223 assume 0 != ~mode5~0 % 256;node5_~m5~0#1 := ~p4_old~0;~p4_old~0 := ~nomsg~0; 267#L226 assume !(node5_~m5~0#1 != ~nomsg~0); 269#L226-1 ~mode5~0 := 0; 313#L223-2 havoc node5_~m5~0#1;assume { :end_inline_node5 } true;assume { :begin_inline_node6 } true;havoc node6_~m6~0#1;havoc node6_~m6~0#1;node6_~m6~0#1 := ~nomsg~0; 327#L257 assume 0 != ~mode6~0 % 256;node6_~m6~0#1 := ~p5_old~0;~p5_old~0 := ~nomsg~0; 338#L260 assume !(node6_~m6~0#1 != ~nomsg~0); 332#L260-1 ~mode6~0 := 0; 312#L257-2 havoc node6_~m6~0#1;assume { :end_inline_node6 } true;~p1_old~0 := ~p1_new~0;~p1_new~0 := ~nomsg~0;~p2_old~0 := ~p2_new~0;~p2_new~0 := ~nomsg~0;~p3_old~0 := ~p3_new~0;~p3_new~0 := ~nomsg~0;~p4_old~0 := ~p4_new~0;~p4_new~0 := ~nomsg~0;~p5_old~0 := ~p5_new~0;~p5_new~0 := ~nomsg~0;~p6_old~0 := ~p6_new~0;~p6_new~0 := ~nomsg~0;assume { :begin_inline_check } true;havoc check_#res#1;havoc check_~tmp~1#1;havoc check_~tmp~1#1; 309#L463 assume !(~st1~0 + ~st2~0 + ~st3~0 + ~st4~0 + ~st5~0 + ~st6~0 <= 1);check_~tmp~1#1 := 0; 310#L463-1 check_#res#1 := check_~tmp~1#1; 278#check_returnLabel#1 main_#t~ret36#1 := check_#res#1;havoc check_~tmp~1#1;assume { :end_inline_check } true;main_~c1~0#1 := main_#t~ret36#1;havoc main_#t~ret36#1;assume { :begin_inline_assert } true;assert_#in~arg#1 := (if 0 == main_~c1~0#1 then 0 else 1);havoc assert_~arg#1;assert_~arg#1 := assert_#in~arg#1; 272#L564 assume !(0 == assert_~arg#1 % 256); 273#L559 havoc assert_~arg#1;havoc assert_#in~arg#1;assume { :end_inline_assert } true;main_#t~post37#1 := main_~i2~0#1;main_~i2~0#1 := 1 + main_#t~post37#1;havoc main_#t~post37#1; 318#L531-3 [2024-11-08 18:17:05,984 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:17:05,985 INFO L85 PathProgramCache]: Analyzing trace with hash 2035845688, now seen corresponding path program 1 times [2024-11-08 18:17:05,985 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 18:17:05,985 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1859133464] [2024-11-08 18:17:05,985 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:17:05,986 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 18:17:06,007 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 18:17:06,101 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 18:17:06,102 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 18:17:06,102 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1859133464] [2024-11-08 18:17:06,102 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1859133464] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 18:17:06,102 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 18:17:06,103 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-08 18:17:06,103 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [897077637] [2024-11-08 18:17:06,103 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 18:17:06,103 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 18:17:06,104 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:17:06,104 INFO L85 PathProgramCache]: Analyzing trace with hash -147928550, now seen corresponding path program 1 times [2024-11-08 18:17:06,104 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 18:17:06,105 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [523726224] [2024-11-08 18:17:06,105 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:17:06,105 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 18:17:06,133 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 18:17:06,383 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 18:17:06,383 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 18:17:06,383 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [523726224] [2024-11-08 18:17:06,384 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [523726224] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 18:17:06,384 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 18:17:06,384 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-08 18:17:06,384 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1577307704] [2024-11-08 18:17:06,384 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 18:17:06,385 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 18:17:06,385 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 18:17:06,386 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-08 18:17:06,386 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-08 18:17:06,386 INFO L87 Difference]: Start difference. First operand 116 states and 202 transitions. cyclomatic complexity: 87 Second operand has 5 states, 5 states have (on average 1.4) internal successors, (7), 5 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 18:17:06,494 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 18:17:06,495 INFO L93 Difference]: Finished difference Result 119 states and 204 transitions. [2024-11-08 18:17:06,495 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 119 states and 204 transitions. [2024-11-08 18:17:06,496 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 69 [2024-11-08 18:17:06,497 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 119 states to 116 states and 161 transitions. [2024-11-08 18:17:06,498 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 116 [2024-11-08 18:17:06,498 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 116 [2024-11-08 18:17:06,498 INFO L73 IsDeterministic]: Start isDeterministic. Operand 116 states and 161 transitions. [2024-11-08 18:17:06,499 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 18:17:06,499 INFO L218 hiAutomatonCegarLoop]: Abstraction has 116 states and 161 transitions. [2024-11-08 18:17:06,499 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 116 states and 161 transitions. [2024-11-08 18:17:06,503 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 116 to 116. [2024-11-08 18:17:06,504 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 116 states, 116 states have (on average 1.3879310344827587) internal successors, (161), 115 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 18:17:06,505 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 116 states to 116 states and 161 transitions. [2024-11-08 18:17:06,505 INFO L240 hiAutomatonCegarLoop]: Abstraction has 116 states and 161 transitions. [2024-11-08 18:17:06,505 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-08 18:17:06,506 INFO L425 stractBuchiCegarLoop]: Abstraction has 116 states and 161 transitions. [2024-11-08 18:17:06,506 INFO L332 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-11-08 18:17:06,506 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 116 states and 161 transitions. [2024-11-08 18:17:06,508 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 69 [2024-11-08 18:17:06,508 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 18:17:06,508 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 18:17:06,509 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 18:17:06,510 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 18:17:06,510 INFO L745 eck$LassoCheckResult]: Stem: 539#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(50, 2);call #Ultimate.allocInit(12, 3);~nomsg~0 := -1;~r1~0 := 0;~p1~0 := 0;~p1_old~0 := 0;~p1_new~0 := 0;~id1~0 := 0;~st1~0 := 0;~send1~0 := 0;~mode1~0 := 0;~alive1~0 := 0;~p2~0 := 0;~p2_old~0 := 0;~p2_new~0 := 0;~id2~0 := 0;~st2~0 := 0;~send2~0 := 0;~mode2~0 := 0;~alive2~0 := 0;~p3~0 := 0;~p3_old~0 := 0;~p3_new~0 := 0;~id3~0 := 0;~st3~0 := 0;~send3~0 := 0;~mode3~0 := 0;~alive3~0 := 0;~p4~0 := 0;~p4_old~0 := 0;~p4_new~0 := 0;~id4~0 := 0;~st4~0 := 0;~send4~0 := 0;~mode4~0 := 0;~alive4~0 := 0;~p5~0 := 0;~p5_old~0 := 0;~p5_new~0 := 0;~id5~0 := 0;~st5~0 := 0;~send5~0 := 0;~mode5~0 := 0;~alive5~0 := 0;~p6~0 := 0;~p6_old~0 := 0;~p6_new~0 := 0;~id6~0 := 0;~st6~0 := 0;~send6~0 := 0;~mode6~0 := 0;~alive6~0 := 0; 540#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet4#1, main_#t~nondet5#1, main_#t~nondet6#1, main_#t~nondet7#1, main_#t~nondet8#1, main_#t~nondet9#1, main_#t~nondet10#1, main_#t~nondet11#1, main_#t~nondet12#1, main_#t~nondet13#1, main_#t~nondet14#1, main_#t~nondet15#1, main_#t~nondet16#1, main_#t~nondet17#1, main_#t~nondet18#1, main_#t~nondet19#1, main_#t~nondet20#1, main_#t~nondet21#1, main_#t~nondet22#1, main_#t~nondet23#1, main_#t~nondet24#1, main_#t~nondet25#1, main_#t~nondet26#1, main_#t~nondet27#1, main_#t~nondet28#1, main_#t~nondet29#1, main_#t~nondet30#1, main_#t~nondet31#1, main_#t~nondet32#1, main_#t~nondet33#1, main_#t~nondet34#1, main_#t~ret35#1, main_#t~ret36#1, main_#t~post37#1, main_~c1~0#1, main_~i2~0#1;havoc main_~c1~0#1;havoc main_~i2~0#1;main_~c1~0#1 := 0;havoc main_#t~nondet4#1;~r1~0 := main_#t~nondet4#1;havoc main_#t~nondet4#1;havoc main_#t~nondet5#1;~id1~0 := main_#t~nondet5#1;havoc main_#t~nondet5#1;havoc main_#t~nondet6#1;~st1~0 := main_#t~nondet6#1;havoc main_#t~nondet6#1;havoc main_#t~nondet7#1;~send1~0 := main_#t~nondet7#1;havoc main_#t~nondet7#1;havoc main_#t~nondet8#1;assume 0 == main_#t~nondet8#1 || 1 == main_#t~nondet8#1;~mode1~0 := (if 0 == main_#t~nondet8#1 % 256 then 0 else 1);havoc main_#t~nondet8#1;havoc main_#t~nondet9#1;assume 0 == main_#t~nondet9#1 || 1 == main_#t~nondet9#1;~alive1~0 := (if 0 == main_#t~nondet9#1 % 256 then 0 else 1);havoc main_#t~nondet9#1;havoc main_#t~nondet10#1;~id2~0 := main_#t~nondet10#1;havoc main_#t~nondet10#1;havoc main_#t~nondet11#1;~st2~0 := main_#t~nondet11#1;havoc main_#t~nondet11#1;havoc main_#t~nondet12#1;~send2~0 := main_#t~nondet12#1;havoc main_#t~nondet12#1;havoc main_#t~nondet13#1;assume 0 == main_#t~nondet13#1 || 1 == main_#t~nondet13#1;~mode2~0 := (if 0 == main_#t~nondet13#1 % 256 then 0 else 1);havoc main_#t~nondet13#1;havoc main_#t~nondet14#1;assume 0 == main_#t~nondet14#1 || 1 == main_#t~nondet14#1;~alive2~0 := (if 0 == main_#t~nondet14#1 % 256 then 0 else 1);havoc main_#t~nondet14#1;havoc main_#t~nondet15#1;~id3~0 := main_#t~nondet15#1;havoc main_#t~nondet15#1;havoc main_#t~nondet16#1;~st3~0 := main_#t~nondet16#1;havoc main_#t~nondet16#1;havoc main_#t~nondet17#1;~send3~0 := main_#t~nondet17#1;havoc main_#t~nondet17#1;havoc main_#t~nondet18#1;assume 0 == main_#t~nondet18#1 || 1 == main_#t~nondet18#1;~mode3~0 := (if 0 == main_#t~nondet18#1 % 256 then 0 else 1);havoc main_#t~nondet18#1;havoc main_#t~nondet19#1;assume 0 == main_#t~nondet19#1 || 1 == main_#t~nondet19#1;~alive3~0 := (if 0 == main_#t~nondet19#1 % 256 then 0 else 1);havoc main_#t~nondet19#1;havoc main_#t~nondet20#1;~id4~0 := main_#t~nondet20#1;havoc main_#t~nondet20#1;havoc main_#t~nondet21#1;~st4~0 := main_#t~nondet21#1;havoc main_#t~nondet21#1;havoc main_#t~nondet22#1;~send4~0 := main_#t~nondet22#1;havoc main_#t~nondet22#1;havoc main_#t~nondet23#1;assume 0 == main_#t~nondet23#1 || 1 == main_#t~nondet23#1;~mode4~0 := (if 0 == main_#t~nondet23#1 % 256 then 0 else 1);havoc main_#t~nondet23#1;havoc main_#t~nondet24#1;assume 0 == main_#t~nondet24#1 || 1 == main_#t~nondet24#1;~alive4~0 := (if 0 == main_#t~nondet24#1 % 256 then 0 else 1);havoc main_#t~nondet24#1;havoc main_#t~nondet25#1;~id5~0 := main_#t~nondet25#1;havoc main_#t~nondet25#1;havoc main_#t~nondet26#1;~st5~0 := main_#t~nondet26#1;havoc main_#t~nondet26#1;havoc main_#t~nondet27#1;~send5~0 := main_#t~nondet27#1;havoc main_#t~nondet27#1;havoc main_#t~nondet28#1;assume 0 == main_#t~nondet28#1 || 1 == main_#t~nondet28#1;~mode5~0 := (if 0 == main_#t~nondet28#1 % 256 then 0 else 1);havoc main_#t~nondet28#1;havoc main_#t~nondet29#1;assume 0 == main_#t~nondet29#1 || 1 == main_#t~nondet29#1;~alive5~0 := (if 0 == main_#t~nondet29#1 % 256 then 0 else 1);havoc main_#t~nondet29#1;havoc main_#t~nondet30#1;~id6~0 := main_#t~nondet30#1;havoc main_#t~nondet30#1;havoc main_#t~nondet31#1;~st6~0 := main_#t~nondet31#1;havoc main_#t~nondet31#1;havoc main_#t~nondet32#1;~send6~0 := main_#t~nondet32#1;havoc main_#t~nondet32#1;havoc main_#t~nondet33#1;assume 0 == main_#t~nondet33#1 || 1 == main_#t~nondet33#1;~mode6~0 := (if 0 == main_#t~nondet33#1 % 256 then 0 else 1);havoc main_#t~nondet33#1;havoc main_#t~nondet34#1;assume 0 == main_#t~nondet34#1 || 1 == main_#t~nondet34#1;~alive6~0 := (if 0 == main_#t~nondet34#1 % 256 then 0 else 1);havoc main_#t~nondet34#1;assume { :begin_inline_init } true;havoc init_#res#1;havoc init_~tmp~0#1;havoc init_~tmp~0#1; 553#L290 assume 0 == ~r1~0; 596#L291 assume (if ~alive1~0 % 256 % 4294967296 <= 2147483647 then ~alive1~0 % 256 % 4294967296 else ~alive1~0 % 256 % 4294967296 - 4294967296) + (if ~alive2~0 % 256 % 4294967296 <= 2147483647 then ~alive2~0 % 256 % 4294967296 else ~alive2~0 % 256 % 4294967296 - 4294967296) + (if ~alive3~0 % 256 % 4294967296 <= 2147483647 then ~alive3~0 % 256 % 4294967296 else ~alive3~0 % 256 % 4294967296 - 4294967296) + (if ~alive4~0 % 256 % 4294967296 <= 2147483647 then ~alive4~0 % 256 % 4294967296 else ~alive4~0 % 256 % 4294967296 - 4294967296) + (if ~alive5~0 % 256 % 4294967296 <= 2147483647 then ~alive5~0 % 256 % 4294967296 else ~alive5~0 % 256 % 4294967296 - 4294967296) + (if ~alive6~0 % 256 % 4294967296 <= 2147483647 then ~alive6~0 % 256 % 4294967296 else ~alive6~0 % 256 % 4294967296 - 4294967296) >= 1; 597#L292 assume ~id1~0 >= 0; 609#L293 assume 0 == ~st1~0; 614#L294 assume ~send1~0 == ~id1~0; 506#L295 assume 0 == (if ~mode1~0 % 256 % 4294967296 <= 2147483647 then ~mode1~0 % 256 % 4294967296 else ~mode1~0 % 256 % 4294967296 - 4294967296); 507#L296 assume ~id2~0 >= 0; 543#L297 assume 0 == ~st2~0; 541#L298 assume ~send2~0 == ~id2~0; 542#L299 assume 0 == (if ~mode2~0 % 256 % 4294967296 <= 2147483647 then ~mode2~0 % 256 % 4294967296 else ~mode2~0 % 256 % 4294967296 - 4294967296); 551#L300 assume ~id3~0 >= 0; 586#L301 assume 0 == ~st3~0; 601#L302 assume ~send3~0 == ~id3~0; 602#L303 assume 0 == (if ~mode3~0 % 256 % 4294967296 <= 2147483647 then ~mode3~0 % 256 % 4294967296 else ~mode3~0 % 256 % 4294967296 - 4294967296); 612#L304 assume ~id4~0 >= 0; 580#L305 assume 0 == ~st4~0; 581#L306 assume ~send4~0 == ~id4~0; 595#L307 assume 0 == (if ~mode4~0 % 256 % 4294967296 <= 2147483647 then ~mode4~0 % 256 % 4294967296 else ~mode4~0 % 256 % 4294967296 - 4294967296); 510#L308 assume ~id5~0 >= 0; 511#L309 assume 0 == ~st5~0; 591#L310 assume ~send5~0 == ~id5~0; 569#L311 assume 0 == (if ~mode5~0 % 256 % 4294967296 <= 2147483647 then ~mode5~0 % 256 % 4294967296 else ~mode5~0 % 256 % 4294967296 - 4294967296); 570#L312 assume ~id6~0 >= 0; 529#L313 assume 0 == ~st6~0; 530#L314 assume ~send6~0 == ~id6~0; 561#L315 assume 0 == (if ~mode6~0 % 256 % 4294967296 <= 2147483647 then ~mode6~0 % 256 % 4294967296 else ~mode6~0 % 256 % 4294967296 - 4294967296); 562#L316 assume ~id1~0 != ~id2~0; 504#L317 assume ~id1~0 != ~id3~0; 505#L318 assume ~id1~0 != ~id4~0; 615#L319 assume ~id1~0 != ~id5~0; 600#L320 assume ~id1~0 != ~id6~0; 582#L321 assume ~id2~0 != ~id3~0; 583#L322 assume ~id2~0 != ~id4~0; 500#L323 assume ~id2~0 != ~id5~0; 501#L324 assume ~id2~0 != ~id6~0; 522#L325 assume ~id3~0 != ~id4~0; 538#L326 assume ~id3~0 != ~id5~0; 527#L327 assume ~id3~0 != ~id6~0; 528#L328 assume ~id4~0 != ~id5~0; 547#L329 assume ~id4~0 != ~id6~0; 548#L330 assume ~id5~0 != ~id6~0;init_~tmp~0#1 := 1; 571#L290-1 init_#res#1 := init_~tmp~0#1; 610#init_returnLabel#1 main_#t~ret35#1 := init_#res#1;havoc init_~tmp~0#1;assume { :end_inline_init } true;main_~i2~0#1 := main_#t~ret35#1;havoc main_#t~ret35#1;assume { :begin_inline_assume_abort_if_not } true;assume_abort_if_not_#in~cond#1 := main_~i2~0#1;havoc assume_abort_if_not_~cond#1;assume_abort_if_not_~cond#1 := assume_abort_if_not_#in~cond#1; 559#L22 assume !(0 == assume_abort_if_not_~cond#1); 560#L21 havoc assume_abort_if_not_~cond#1;havoc assume_abort_if_not_#in~cond#1;assume { :end_inline_assume_abort_if_not } true;~p1_old~0 := ~nomsg~0;~p1_new~0 := ~nomsg~0;~p2_old~0 := ~nomsg~0;~p2_new~0 := ~nomsg~0;~p3_old~0 := ~nomsg~0;~p3_new~0 := ~nomsg~0;~p4_old~0 := ~nomsg~0;~p4_new~0 := ~nomsg~0;~p5_old~0 := ~nomsg~0;~p5_new~0 := ~nomsg~0;~p6_old~0 := ~nomsg~0;~p6_new~0 := ~nomsg~0;main_~i2~0#1 := 0; 563#L531-3 [2024-11-08 18:17:06,510 INFO L747 eck$LassoCheckResult]: Loop: 563#L531-3 assume main_~i2~0#1 < 12; 515#L531-1 assume !!(main_~i2~0#1 < 12);assume { :begin_inline_node1 } true;havoc node1_~m1~0#1;havoc node1_~m1~0#1;node1_~m1~0#1 := ~nomsg~0; 516#L84 assume 0 != ~mode1~0 % 256;~r1~0 := (if (1 + ~r1~0) % 256 <= 127 then (1 + ~r1~0) % 256 else (1 + ~r1~0) % 256 - 256);node1_~m1~0#1 := ~p6_old~0;~p6_old~0 := ~nomsg~0; 611#L88 assume !(node1_~m1~0#1 != ~nomsg~0); 550#L88-1 ~mode1~0 := 0; 534#L84-2 havoc node1_~m1~0#1;assume { :end_inline_node1 } true;assume { :begin_inline_node2 } true;havoc node2_~m2~0#1;havoc node2_~m2~0#1;node2_~m2~0#1 := ~nomsg~0; 535#L121 assume !(0 != ~mode2~0 % 256); 536#L138 assume 0 != ~alive2~0 % 256;~p2_new~0 := (if (if ~send2~0 != ~nomsg~0 && ~p2_new~0 == ~nomsg~0 then ~send2~0 else ~p2_new~0) % 256 <= 127 then (if ~send2~0 != ~nomsg~0 && ~p2_new~0 == ~nomsg~0 then ~send2~0 else ~p2_new~0) % 256 else (if ~send2~0 != ~nomsg~0 && ~p2_new~0 == ~nomsg~0 then ~send2~0 else ~p2_new~0) % 256 - 256); 565#L141-2 ~mode2~0 := 1; 508#L121-2 havoc node2_~m2~0#1;assume { :end_inline_node2 } true;assume { :begin_inline_node3 } true;havoc node3_~m3~0#1;havoc node3_~m3~0#1;node3_~m3~0#1 := ~nomsg~0; 509#L155 assume !(0 != ~mode3~0 % 256); 566#L172 assume 0 != ~alive3~0 % 256;~p3_new~0 := (if (if ~send3~0 != ~nomsg~0 && ~p3_new~0 == ~nomsg~0 then ~send3~0 else ~p3_new~0) % 256 <= 127 then (if ~send3~0 != ~nomsg~0 && ~p3_new~0 == ~nomsg~0 then ~send3~0 else ~p3_new~0) % 256 else (if ~send3~0 != ~nomsg~0 && ~p3_new~0 == ~nomsg~0 then ~send3~0 else ~p3_new~0) % 256 - 256); 503#L175-2 ~mode3~0 := 1; 592#L155-2 havoc node3_~m3~0#1;assume { :end_inline_node3 } true;assume { :begin_inline_node4 } true;havoc node4_~m4~0#1;havoc node4_~m4~0#1;node4_~m4~0#1 := ~nomsg~0; 604#L189 assume !(0 != ~mode4~0 % 256); 544#L206 assume 0 != ~alive4~0 % 256;~p4_new~0 := (if (if ~send4~0 != ~nomsg~0 && ~p4_new~0 == ~nomsg~0 then ~send4~0 else ~p4_new~0) % 256 <= 127 then (if ~send4~0 != ~nomsg~0 && ~p4_new~0 == ~nomsg~0 then ~send4~0 else ~p4_new~0) % 256 else (if ~send4~0 != ~nomsg~0 && ~p4_new~0 == ~nomsg~0 then ~send4~0 else ~p4_new~0) % 256 - 256); 546#L209-2 ~mode4~0 := 1; 567#L189-2 havoc node4_~m4~0#1;assume { :end_inline_node4 } true;assume { :begin_inline_node5 } true;havoc node5_~m5~0#1;havoc node5_~m5~0#1;node5_~m5~0#1 := ~nomsg~0; 568#L223 assume 0 != ~mode5~0 % 256;node5_~m5~0#1 := ~p4_old~0;~p4_old~0 := ~nomsg~0; 512#L226 assume !(node5_~m5~0#1 != ~nomsg~0); 514#L226-1 ~mode5~0 := 0; 558#L223-2 havoc node5_~m5~0#1;assume { :end_inline_node5 } true;assume { :begin_inline_node6 } true;havoc node6_~m6~0#1;havoc node6_~m6~0#1;node6_~m6~0#1 := ~nomsg~0; 573#L257 assume 0 != ~mode6~0 % 256;node6_~m6~0#1 := ~p5_old~0;~p5_old~0 := ~nomsg~0; 584#L260 assume !(node6_~m6~0#1 != ~nomsg~0); 578#L260-1 ~mode6~0 := 0; 557#L257-2 havoc node6_~m6~0#1;assume { :end_inline_node6 } true;~p1_old~0 := ~p1_new~0;~p1_new~0 := ~nomsg~0;~p2_old~0 := ~p2_new~0;~p2_new~0 := ~nomsg~0;~p3_old~0 := ~p3_new~0;~p3_new~0 := ~nomsg~0;~p4_old~0 := ~p4_new~0;~p4_new~0 := ~nomsg~0;~p5_old~0 := ~p5_new~0;~p5_new~0 := ~nomsg~0;~p6_old~0 := ~p6_new~0;~p6_new~0 := ~nomsg~0;assume { :begin_inline_check } true;havoc check_#res#1;havoc check_~tmp~1#1;havoc check_~tmp~1#1; 554#L463 assume !(~st1~0 + ~st2~0 + ~st3~0 + ~st4~0 + ~st5~0 + ~st6~0 <= 1);check_~tmp~1#1 := 0; 555#L463-1 check_#res#1 := check_~tmp~1#1; 523#check_returnLabel#1 main_#t~ret36#1 := check_#res#1;havoc check_~tmp~1#1;assume { :end_inline_check } true;main_~c1~0#1 := main_#t~ret36#1;havoc main_#t~ret36#1;assume { :begin_inline_assert } true;assert_#in~arg#1 := (if 0 == main_~c1~0#1 then 0 else 1);havoc assert_~arg#1;assert_~arg#1 := assert_#in~arg#1; 517#L564 assume !(0 == assert_~arg#1 % 256); 518#L559 havoc assert_~arg#1;havoc assert_#in~arg#1;assume { :end_inline_assert } true;main_#t~post37#1 := main_~i2~0#1;main_~i2~0#1 := 1 + main_#t~post37#1;havoc main_#t~post37#1; 563#L531-3 [2024-11-08 18:17:06,511 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:17:06,511 INFO L85 PathProgramCache]: Analyzing trace with hash -1766357374, now seen corresponding path program 1 times [2024-11-08 18:17:06,512 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 18:17:06,512 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [211317095] [2024-11-08 18:17:06,512 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:17:06,512 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 18:17:06,579 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:17:06,579 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 18:17:06,623 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:17:06,675 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 18:17:06,676 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:17:06,677 INFO L85 PathProgramCache]: Analyzing trace with hash 1395188634, now seen corresponding path program 1 times [2024-11-08 18:17:06,677 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 18:17:06,677 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1867750802] [2024-11-08 18:17:06,677 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:17:06,678 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 18:17:06,712 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 18:17:06,941 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 18:17:06,943 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 18:17:06,943 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1867750802] [2024-11-08 18:17:06,944 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1867750802] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 18:17:06,944 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 18:17:06,944 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-08 18:17:06,945 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [485435622] [2024-11-08 18:17:06,945 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 18:17:06,945 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 18:17:06,946 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 18:17:06,947 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-08 18:17:06,948 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-08 18:17:06,949 INFO L87 Difference]: Start difference. First operand 116 states and 161 transitions. cyclomatic complexity: 46 Second operand has 5 states, 5 states have (on average 6.2) internal successors, (31), 5 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 18:17:06,982 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 18:17:06,982 INFO L93 Difference]: Finished difference Result 119 states and 163 transitions. [2024-11-08 18:17:06,983 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 119 states and 163 transitions. [2024-11-08 18:17:06,984 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 69 [2024-11-08 18:17:06,986 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 119 states to 116 states and 159 transitions. [2024-11-08 18:17:06,987 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 116 [2024-11-08 18:17:06,987 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 116 [2024-11-08 18:17:06,988 INFO L73 IsDeterministic]: Start isDeterministic. Operand 116 states and 159 transitions. [2024-11-08 18:17:06,989 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 18:17:06,990 INFO L218 hiAutomatonCegarLoop]: Abstraction has 116 states and 159 transitions. [2024-11-08 18:17:06,990 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 116 states and 159 transitions. [2024-11-08 18:17:06,997 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 116 to 116. [2024-11-08 18:17:07,000 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 116 states, 116 states have (on average 1.3706896551724137) internal successors, (159), 115 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 18:17:07,003 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 116 states to 116 states and 159 transitions. [2024-11-08 18:17:07,003 INFO L240 hiAutomatonCegarLoop]: Abstraction has 116 states and 159 transitions. [2024-11-08 18:17:07,004 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-08 18:17:07,005 INFO L425 stractBuchiCegarLoop]: Abstraction has 116 states and 159 transitions. [2024-11-08 18:17:07,007 INFO L332 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-11-08 18:17:07,007 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 116 states and 159 transitions. [2024-11-08 18:17:07,008 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 69 [2024-11-08 18:17:07,008 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 18:17:07,008 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 18:17:07,012 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 18:17:07,012 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 18:17:07,012 INFO L745 eck$LassoCheckResult]: Stem: 782#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(50, 2);call #Ultimate.allocInit(12, 3);~nomsg~0 := -1;~r1~0 := 0;~p1~0 := 0;~p1_old~0 := 0;~p1_new~0 := 0;~id1~0 := 0;~st1~0 := 0;~send1~0 := 0;~mode1~0 := 0;~alive1~0 := 0;~p2~0 := 0;~p2_old~0 := 0;~p2_new~0 := 0;~id2~0 := 0;~st2~0 := 0;~send2~0 := 0;~mode2~0 := 0;~alive2~0 := 0;~p3~0 := 0;~p3_old~0 := 0;~p3_new~0 := 0;~id3~0 := 0;~st3~0 := 0;~send3~0 := 0;~mode3~0 := 0;~alive3~0 := 0;~p4~0 := 0;~p4_old~0 := 0;~p4_new~0 := 0;~id4~0 := 0;~st4~0 := 0;~send4~0 := 0;~mode4~0 := 0;~alive4~0 := 0;~p5~0 := 0;~p5_old~0 := 0;~p5_new~0 := 0;~id5~0 := 0;~st5~0 := 0;~send5~0 := 0;~mode5~0 := 0;~alive5~0 := 0;~p6~0 := 0;~p6_old~0 := 0;~p6_new~0 := 0;~id6~0 := 0;~st6~0 := 0;~send6~0 := 0;~mode6~0 := 0;~alive6~0 := 0; 783#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet4#1, main_#t~nondet5#1, main_#t~nondet6#1, main_#t~nondet7#1, main_#t~nondet8#1, main_#t~nondet9#1, main_#t~nondet10#1, main_#t~nondet11#1, main_#t~nondet12#1, main_#t~nondet13#1, main_#t~nondet14#1, main_#t~nondet15#1, main_#t~nondet16#1, main_#t~nondet17#1, main_#t~nondet18#1, main_#t~nondet19#1, main_#t~nondet20#1, main_#t~nondet21#1, main_#t~nondet22#1, main_#t~nondet23#1, main_#t~nondet24#1, main_#t~nondet25#1, main_#t~nondet26#1, main_#t~nondet27#1, main_#t~nondet28#1, main_#t~nondet29#1, main_#t~nondet30#1, main_#t~nondet31#1, main_#t~nondet32#1, main_#t~nondet33#1, main_#t~nondet34#1, main_#t~ret35#1, main_#t~ret36#1, main_#t~post37#1, main_~c1~0#1, main_~i2~0#1;havoc main_~c1~0#1;havoc main_~i2~0#1;main_~c1~0#1 := 0;havoc main_#t~nondet4#1;~r1~0 := main_#t~nondet4#1;havoc main_#t~nondet4#1;havoc main_#t~nondet5#1;~id1~0 := main_#t~nondet5#1;havoc main_#t~nondet5#1;havoc main_#t~nondet6#1;~st1~0 := main_#t~nondet6#1;havoc main_#t~nondet6#1;havoc main_#t~nondet7#1;~send1~0 := main_#t~nondet7#1;havoc main_#t~nondet7#1;havoc main_#t~nondet8#1;assume 0 == main_#t~nondet8#1 || 1 == main_#t~nondet8#1;~mode1~0 := (if 0 == main_#t~nondet8#1 % 256 then 0 else 1);havoc main_#t~nondet8#1;havoc main_#t~nondet9#1;assume 0 == main_#t~nondet9#1 || 1 == main_#t~nondet9#1;~alive1~0 := (if 0 == main_#t~nondet9#1 % 256 then 0 else 1);havoc main_#t~nondet9#1;havoc main_#t~nondet10#1;~id2~0 := main_#t~nondet10#1;havoc main_#t~nondet10#1;havoc main_#t~nondet11#1;~st2~0 := main_#t~nondet11#1;havoc main_#t~nondet11#1;havoc main_#t~nondet12#1;~send2~0 := main_#t~nondet12#1;havoc main_#t~nondet12#1;havoc main_#t~nondet13#1;assume 0 == main_#t~nondet13#1 || 1 == main_#t~nondet13#1;~mode2~0 := (if 0 == main_#t~nondet13#1 % 256 then 0 else 1);havoc main_#t~nondet13#1;havoc main_#t~nondet14#1;assume 0 == main_#t~nondet14#1 || 1 == main_#t~nondet14#1;~alive2~0 := (if 0 == main_#t~nondet14#1 % 256 then 0 else 1);havoc main_#t~nondet14#1;havoc main_#t~nondet15#1;~id3~0 := main_#t~nondet15#1;havoc main_#t~nondet15#1;havoc main_#t~nondet16#1;~st3~0 := main_#t~nondet16#1;havoc main_#t~nondet16#1;havoc main_#t~nondet17#1;~send3~0 := main_#t~nondet17#1;havoc main_#t~nondet17#1;havoc main_#t~nondet18#1;assume 0 == main_#t~nondet18#1 || 1 == main_#t~nondet18#1;~mode3~0 := (if 0 == main_#t~nondet18#1 % 256 then 0 else 1);havoc main_#t~nondet18#1;havoc main_#t~nondet19#1;assume 0 == main_#t~nondet19#1 || 1 == main_#t~nondet19#1;~alive3~0 := (if 0 == main_#t~nondet19#1 % 256 then 0 else 1);havoc main_#t~nondet19#1;havoc main_#t~nondet20#1;~id4~0 := main_#t~nondet20#1;havoc main_#t~nondet20#1;havoc main_#t~nondet21#1;~st4~0 := main_#t~nondet21#1;havoc main_#t~nondet21#1;havoc main_#t~nondet22#1;~send4~0 := main_#t~nondet22#1;havoc main_#t~nondet22#1;havoc main_#t~nondet23#1;assume 0 == main_#t~nondet23#1 || 1 == main_#t~nondet23#1;~mode4~0 := (if 0 == main_#t~nondet23#1 % 256 then 0 else 1);havoc main_#t~nondet23#1;havoc main_#t~nondet24#1;assume 0 == main_#t~nondet24#1 || 1 == main_#t~nondet24#1;~alive4~0 := (if 0 == main_#t~nondet24#1 % 256 then 0 else 1);havoc main_#t~nondet24#1;havoc main_#t~nondet25#1;~id5~0 := main_#t~nondet25#1;havoc main_#t~nondet25#1;havoc main_#t~nondet26#1;~st5~0 := main_#t~nondet26#1;havoc main_#t~nondet26#1;havoc main_#t~nondet27#1;~send5~0 := main_#t~nondet27#1;havoc main_#t~nondet27#1;havoc main_#t~nondet28#1;assume 0 == main_#t~nondet28#1 || 1 == main_#t~nondet28#1;~mode5~0 := (if 0 == main_#t~nondet28#1 % 256 then 0 else 1);havoc main_#t~nondet28#1;havoc main_#t~nondet29#1;assume 0 == main_#t~nondet29#1 || 1 == main_#t~nondet29#1;~alive5~0 := (if 0 == main_#t~nondet29#1 % 256 then 0 else 1);havoc main_#t~nondet29#1;havoc main_#t~nondet30#1;~id6~0 := main_#t~nondet30#1;havoc main_#t~nondet30#1;havoc main_#t~nondet31#1;~st6~0 := main_#t~nondet31#1;havoc main_#t~nondet31#1;havoc main_#t~nondet32#1;~send6~0 := main_#t~nondet32#1;havoc main_#t~nondet32#1;havoc main_#t~nondet33#1;assume 0 == main_#t~nondet33#1 || 1 == main_#t~nondet33#1;~mode6~0 := (if 0 == main_#t~nondet33#1 % 256 then 0 else 1);havoc main_#t~nondet33#1;havoc main_#t~nondet34#1;assume 0 == main_#t~nondet34#1 || 1 == main_#t~nondet34#1;~alive6~0 := (if 0 == main_#t~nondet34#1 % 256 then 0 else 1);havoc main_#t~nondet34#1;assume { :begin_inline_init } true;havoc init_#res#1;havoc init_~tmp~0#1;havoc init_~tmp~0#1; 796#L290 assume 0 == ~r1~0; 838#L291 assume (if ~alive1~0 % 256 % 4294967296 <= 2147483647 then ~alive1~0 % 256 % 4294967296 else ~alive1~0 % 256 % 4294967296 - 4294967296) + (if ~alive2~0 % 256 % 4294967296 <= 2147483647 then ~alive2~0 % 256 % 4294967296 else ~alive2~0 % 256 % 4294967296 - 4294967296) + (if ~alive3~0 % 256 % 4294967296 <= 2147483647 then ~alive3~0 % 256 % 4294967296 else ~alive3~0 % 256 % 4294967296 - 4294967296) + (if ~alive4~0 % 256 % 4294967296 <= 2147483647 then ~alive4~0 % 256 % 4294967296 else ~alive4~0 % 256 % 4294967296 - 4294967296) + (if ~alive5~0 % 256 % 4294967296 <= 2147483647 then ~alive5~0 % 256 % 4294967296 else ~alive5~0 % 256 % 4294967296 - 4294967296) + (if ~alive6~0 % 256 % 4294967296 <= 2147483647 then ~alive6~0 % 256 % 4294967296 else ~alive6~0 % 256 % 4294967296 - 4294967296) >= 1; 839#L292 assume ~id1~0 >= 0; 851#L293 assume 0 == ~st1~0; 857#L294 assume ~send1~0 == ~id1~0; 749#L295 assume 0 == (if ~mode1~0 % 256 % 4294967296 <= 2147483647 then ~mode1~0 % 256 % 4294967296 else ~mode1~0 % 256 % 4294967296 - 4294967296); 750#L296 assume ~id2~0 >= 0; 786#L297 assume 0 == ~st2~0; 784#L298 assume ~send2~0 == ~id2~0; 785#L299 assume 0 == (if ~mode2~0 % 256 % 4294967296 <= 2147483647 then ~mode2~0 % 256 % 4294967296 else ~mode2~0 % 256 % 4294967296 - 4294967296); 794#L300 assume ~id3~0 >= 0; 828#L301 assume 0 == ~st3~0; 843#L302 assume ~send3~0 == ~id3~0; 844#L303 assume 0 == (if ~mode3~0 % 256 % 4294967296 <= 2147483647 then ~mode3~0 % 256 % 4294967296 else ~mode3~0 % 256 % 4294967296 - 4294967296); 854#L304 assume ~id4~0 >= 0; 822#L305 assume 0 == ~st4~0; 823#L306 assume ~send4~0 == ~id4~0; 837#L307 assume 0 == (if ~mode4~0 % 256 % 4294967296 <= 2147483647 then ~mode4~0 % 256 % 4294967296 else ~mode4~0 % 256 % 4294967296 - 4294967296); 753#L308 assume ~id5~0 >= 0; 754#L309 assume 0 == ~st5~0; 833#L310 assume ~send5~0 == ~id5~0; 811#L311 assume 0 == (if ~mode5~0 % 256 % 4294967296 <= 2147483647 then ~mode5~0 % 256 % 4294967296 else ~mode5~0 % 256 % 4294967296 - 4294967296); 812#L312 assume ~id6~0 >= 0; 772#L313 assume 0 == ~st6~0; 773#L314 assume ~send6~0 == ~id6~0; 803#L315 assume 0 == (if ~mode6~0 % 256 % 4294967296 <= 2147483647 then ~mode6~0 % 256 % 4294967296 else ~mode6~0 % 256 % 4294967296 - 4294967296); 804#L316 assume ~id1~0 != ~id2~0; 747#L317 assume ~id1~0 != ~id3~0; 748#L318 assume ~id1~0 != ~id4~0; 858#L319 assume ~id1~0 != ~id5~0; 842#L320 assume ~id1~0 != ~id6~0; 824#L321 assume ~id2~0 != ~id3~0; 825#L322 assume ~id2~0 != ~id4~0; 743#L323 assume ~id2~0 != ~id5~0; 744#L324 assume ~id2~0 != ~id6~0; 765#L325 assume ~id3~0 != ~id4~0; 781#L326 assume ~id3~0 != ~id5~0; 770#L327 assume ~id3~0 != ~id6~0; 771#L328 assume ~id4~0 != ~id5~0; 790#L329 assume ~id4~0 != ~id6~0; 791#L330 assume ~id5~0 != ~id6~0;init_~tmp~0#1 := 1; 813#L290-1 init_#res#1 := init_~tmp~0#1; 852#init_returnLabel#1 main_#t~ret35#1 := init_#res#1;havoc init_~tmp~0#1;assume { :end_inline_init } true;main_~i2~0#1 := main_#t~ret35#1;havoc main_#t~ret35#1;assume { :begin_inline_assume_abort_if_not } true;assume_abort_if_not_#in~cond#1 := main_~i2~0#1;havoc assume_abort_if_not_~cond#1;assume_abort_if_not_~cond#1 := assume_abort_if_not_#in~cond#1; 801#L22 assume !(0 == assume_abort_if_not_~cond#1); 802#L21 havoc assume_abort_if_not_~cond#1;havoc assume_abort_if_not_#in~cond#1;assume { :end_inline_assume_abort_if_not } true;~p1_old~0 := ~nomsg~0;~p1_new~0 := ~nomsg~0;~p2_old~0 := ~nomsg~0;~p2_new~0 := ~nomsg~0;~p3_old~0 := ~nomsg~0;~p3_new~0 := ~nomsg~0;~p4_old~0 := ~nomsg~0;~p4_new~0 := ~nomsg~0;~p5_old~0 := ~nomsg~0;~p5_new~0 := ~nomsg~0;~p6_old~0 := ~nomsg~0;~p6_new~0 := ~nomsg~0;main_~i2~0#1 := 0; 805#L531-3 [2024-11-08 18:17:07,013 INFO L747 eck$LassoCheckResult]: Loop: 805#L531-3 assume main_~i2~0#1 < 12; 758#L531-1 assume !!(main_~i2~0#1 < 12);assume { :begin_inline_node1 } true;havoc node1_~m1~0#1;havoc node1_~m1~0#1;node1_~m1~0#1 := ~nomsg~0; 759#L84 assume 0 != ~mode1~0 % 256;~r1~0 := (if (1 + ~r1~0) % 256 <= 127 then (1 + ~r1~0) % 256 else (1 + ~r1~0) % 256 - 256);node1_~m1~0#1 := ~p6_old~0;~p6_old~0 := ~nomsg~0; 853#L88 assume !(node1_~m1~0#1 != ~nomsg~0); 793#L88-1 ~mode1~0 := 0; 777#L84-2 havoc node1_~m1~0#1;assume { :end_inline_node1 } true;assume { :begin_inline_node2 } true;havoc node2_~m2~0#1;havoc node2_~m2~0#1;node2_~m2~0#1 := ~nomsg~0; 778#L121 assume !(0 != ~mode2~0 % 256); 779#L138 assume 0 != ~alive2~0 % 256;~p2_new~0 := (if (if ~send2~0 != ~nomsg~0 && ~p2_new~0 == ~nomsg~0 then ~send2~0 else ~p2_new~0) % 256 <= 127 then (if ~send2~0 != ~nomsg~0 && ~p2_new~0 == ~nomsg~0 then ~send2~0 else ~p2_new~0) % 256 else (if ~send2~0 != ~nomsg~0 && ~p2_new~0 == ~nomsg~0 then ~send2~0 else ~p2_new~0) % 256 - 256); 807#L141-2 ~mode2~0 := 1; 751#L121-2 havoc node2_~m2~0#1;assume { :end_inline_node2 } true;assume { :begin_inline_node3 } true;havoc node3_~m3~0#1;havoc node3_~m3~0#1;node3_~m3~0#1 := ~nomsg~0; 752#L155 assume !(0 != ~mode3~0 % 256); 808#L172 assume 0 != ~alive3~0 % 256;~p3_new~0 := (if (if ~send3~0 != ~nomsg~0 && ~p3_new~0 == ~nomsg~0 then ~send3~0 else ~p3_new~0) % 256 <= 127 then (if ~send3~0 != ~nomsg~0 && ~p3_new~0 == ~nomsg~0 then ~send3~0 else ~p3_new~0) % 256 else (if ~send3~0 != ~nomsg~0 && ~p3_new~0 == ~nomsg~0 then ~send3~0 else ~p3_new~0) % 256 - 256); 746#L175-2 ~mode3~0 := 1; 834#L155-2 havoc node3_~m3~0#1;assume { :end_inline_node3 } true;assume { :begin_inline_node4 } true;havoc node4_~m4~0#1;havoc node4_~m4~0#1;node4_~m4~0#1 := ~nomsg~0; 846#L189 assume !(0 != ~mode4~0 % 256); 787#L206 assume 0 != ~alive4~0 % 256;~p4_new~0 := (if (if ~send4~0 != ~nomsg~0 && ~p4_new~0 == ~nomsg~0 then ~send4~0 else ~p4_new~0) % 256 <= 127 then (if ~send4~0 != ~nomsg~0 && ~p4_new~0 == ~nomsg~0 then ~send4~0 else ~p4_new~0) % 256 else (if ~send4~0 != ~nomsg~0 && ~p4_new~0 == ~nomsg~0 then ~send4~0 else ~p4_new~0) % 256 - 256); 789#L209-2 ~mode4~0 := 1; 809#L189-2 havoc node4_~m4~0#1;assume { :end_inline_node4 } true;assume { :begin_inline_node5 } true;havoc node5_~m5~0#1;havoc node5_~m5~0#1;node5_~m5~0#1 := ~nomsg~0; 810#L223 assume 0 != ~mode5~0 % 256;node5_~m5~0#1 := ~p4_old~0;~p4_old~0 := ~nomsg~0; 755#L226 assume !(node5_~m5~0#1 != ~nomsg~0); 757#L226-1 ~mode5~0 := 0; 800#L223-2 havoc node5_~m5~0#1;assume { :end_inline_node5 } true;assume { :begin_inline_node6 } true;havoc node6_~m6~0#1;havoc node6_~m6~0#1;node6_~m6~0#1 := ~nomsg~0; 815#L257 assume !(0 != ~mode6~0 % 256); 848#L274 assume 0 != ~alive6~0 % 256;~p6_new~0 := (if (if ~send6~0 != ~nomsg~0 && ~p6_new~0 == ~nomsg~0 then ~send6~0 else ~p6_new~0) % 256 <= 127 then (if ~send6~0 != ~nomsg~0 && ~p6_new~0 == ~nomsg~0 then ~send6~0 else ~p6_new~0) % 256 else (if ~send6~0 != ~nomsg~0 && ~p6_new~0 == ~nomsg~0 then ~send6~0 else ~p6_new~0) % 256 - 256); 849#L277-2 ~mode6~0 := 1; 799#L257-2 havoc node6_~m6~0#1;assume { :end_inline_node6 } true;~p1_old~0 := ~p1_new~0;~p1_new~0 := ~nomsg~0;~p2_old~0 := ~p2_new~0;~p2_new~0 := ~nomsg~0;~p3_old~0 := ~p3_new~0;~p3_new~0 := ~nomsg~0;~p4_old~0 := ~p4_new~0;~p4_new~0 := ~nomsg~0;~p5_old~0 := ~p5_new~0;~p5_new~0 := ~nomsg~0;~p6_old~0 := ~p6_new~0;~p6_new~0 := ~nomsg~0;assume { :begin_inline_check } true;havoc check_#res#1;havoc check_~tmp~1#1;havoc check_~tmp~1#1; 797#L463 assume ~st1~0 + ~st2~0 + ~st3~0 + ~st4~0 + ~st5~0 + ~st6~0 <= 1; 798#L464 assume ~r1~0 < 6;check_~tmp~1#1 := 1; 855#L463-1 check_#res#1 := check_~tmp~1#1; 766#check_returnLabel#1 main_#t~ret36#1 := check_#res#1;havoc check_~tmp~1#1;assume { :end_inline_check } true;main_~c1~0#1 := main_#t~ret36#1;havoc main_#t~ret36#1;assume { :begin_inline_assert } true;assert_#in~arg#1 := (if 0 == main_~c1~0#1 then 0 else 1);havoc assert_~arg#1;assert_~arg#1 := assert_#in~arg#1; 760#L564 assume !(0 == assert_~arg#1 % 256); 761#L559 havoc assert_~arg#1;havoc assert_#in~arg#1;assume { :end_inline_assert } true;main_#t~post37#1 := main_~i2~0#1;main_~i2~0#1 := 1 + main_#t~post37#1;havoc main_#t~post37#1; 805#L531-3 [2024-11-08 18:17:07,013 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:17:07,013 INFO L85 PathProgramCache]: Analyzing trace with hash -1766357374, now seen corresponding path program 2 times [2024-11-08 18:17:07,013 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 18:17:07,014 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [302580134] [2024-11-08 18:17:07,014 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:17:07,014 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 18:17:07,093 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:17:07,093 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 18:17:07,160 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:17:07,181 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 18:17:07,181 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:17:07,183 INFO L85 PathProgramCache]: Analyzing trace with hash -2034276525, now seen corresponding path program 1 times [2024-11-08 18:17:07,183 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 18:17:07,183 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1689683534] [2024-11-08 18:17:07,183 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:17:07,184 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 18:17:07,220 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:17:07,222 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 18:17:07,258 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:17:07,270 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 18:17:07,271 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:17:07,271 INFO L85 PathProgramCache]: Analyzing trace with hash -678123052, now seen corresponding path program 1 times [2024-11-08 18:17:07,273 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 18:17:07,273 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [296180402] [2024-11-08 18:17:07,274 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:17:07,274 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 18:17:07,304 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 18:17:07,403 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 18:17:07,403 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 18:17:07,403 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [296180402] [2024-11-08 18:17:07,404 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [296180402] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 18:17:07,404 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 18:17:07,405 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 18:17:07,405 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2088927683] [2024-11-08 18:17:07,405 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 18:17:10,895 INFO L204 LassoAnalysis]: Preferences: [2024-11-08 18:17:10,896 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-11-08 18:17:10,896 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-11-08 18:17:10,896 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-11-08 18:17:10,896 INFO L128 ssoRankerPreferences]: Use exernal solver: true [2024-11-08 18:17:10,897 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 18:17:10,897 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-11-08 18:17:10,897 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-11-08 18:17:10,897 INFO L132 ssoRankerPreferences]: Filename of dumped script: pals_lcr-var-start-time.6.1.ufo.BOUNDED-12.pals.c_Iteration4_Loop [2024-11-08 18:17:10,897 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-11-08 18:17:10,898 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-11-08 18:17:10,927 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:17:10,940 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:17:10,943 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:17:10,945 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:17:10,948 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:17:10,950 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:17:10,957 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:17:10,975 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:17:10,982 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:17:10,986 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:17:10,993 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:17:10,996 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:17:10,999 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:17:11,004 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:17:11,007 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:17:11,014 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:17:11,016 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:17:11,019 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:17:11,025 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:17:11,028 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:17:11,032 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:17:12,264 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:17:12,270 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:17:12,277 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:17:12,279 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:17:12,281 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:17:14,162 WARN L137 XnfTransformerHelper]: expecting exponential blowup for input size 23