./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/seq-mthreaded/pals_lcr.8.1.ufo.UNBOUNDED.pals.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version a0165632 Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2aa5c026-8a8d-4c06-b6eb-8e832694e9de/bin/uautomizer-verify-jihMAELWvX/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2aa5c026-8a8d-4c06-b6eb-8e832694e9de/bin/uautomizer-verify-jihMAELWvX/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2aa5c026-8a8d-4c06-b6eb-8e832694e9de/bin/uautomizer-verify-jihMAELWvX/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2aa5c026-8a8d-4c06-b6eb-8e832694e9de/bin/uautomizer-verify-jihMAELWvX/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/seq-mthreaded/pals_lcr.8.1.ufo.UNBOUNDED.pals.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2aa5c026-8a8d-4c06-b6eb-8e832694e9de/bin/uautomizer-verify-jihMAELWvX/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2aa5c026-8a8d-4c06-b6eb-8e832694e9de/bin/uautomizer-verify-jihMAELWvX --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash a3df27f87602fca8935d2269a873dfd3f1a5195383d477434680a0bc703d239a --- Real Ultimate output --- This is Ultimate 0.2.5-dev-a016563 [2024-11-08 18:53:39,722 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-08 18:53:39,803 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2aa5c026-8a8d-4c06-b6eb-8e832694e9de/bin/uautomizer-verify-jihMAELWvX/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-11-08 18:53:39,808 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-08 18:53:39,809 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-08 18:53:39,839 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-08 18:53:39,839 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-08 18:53:39,840 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-08 18:53:39,841 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-08 18:53:39,842 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-08 18:53:39,843 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-08 18:53:39,843 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-08 18:53:39,844 INFO L153 SettingsManager]: * Use SBE=true [2024-11-08 18:53:39,845 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-11-08 18:53:39,845 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-11-08 18:53:39,846 INFO L153 SettingsManager]: * Use old map elimination=false [2024-11-08 18:53:39,847 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-11-08 18:53:39,847 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-11-08 18:53:39,848 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-11-08 18:53:39,848 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-08 18:53:39,849 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-11-08 18:53:39,850 INFO L153 SettingsManager]: * sizeof long=4 [2024-11-08 18:53:39,854 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-08 18:53:39,855 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-11-08 18:53:39,855 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-08 18:53:39,856 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-11-08 18:53:39,856 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-11-08 18:53:39,857 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-11-08 18:53:39,857 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-11-08 18:53:39,857 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-11-08 18:53:39,858 INFO L153 SettingsManager]: * sizeof long double=12 [2024-11-08 18:53:39,858 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-08 18:53:39,858 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-11-08 18:53:39,859 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-08 18:53:39,859 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-11-08 18:53:39,859 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-08 18:53:39,860 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-08 18:53:39,864 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-11-08 18:53:39,865 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-11-08 18:53:39,867 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2aa5c026-8a8d-4c06-b6eb-8e832694e9de/bin/uautomizer-verify-jihMAELWvX/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2aa5c026-8a8d-4c06-b6eb-8e832694e9de/bin/uautomizer-verify-jihMAELWvX Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> a3df27f87602fca8935d2269a873dfd3f1a5195383d477434680a0bc703d239a [2024-11-08 18:53:40,220 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-08 18:53:40,262 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-08 18:53:40,266 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-08 18:53:40,268 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-08 18:53:40,269 INFO L274 PluginConnector]: CDTParser initialized [2024-11-08 18:53:40,271 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2aa5c026-8a8d-4c06-b6eb-8e832694e9de/bin/uautomizer-verify-jihMAELWvX/../../sv-benchmarks/c/seq-mthreaded/pals_lcr.8.1.ufo.UNBOUNDED.pals.c Unable to find full path for "g++" [2024-11-08 18:53:42,716 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-11-08 18:53:42,983 INFO L384 CDTParser]: Found 1 translation units. [2024-11-08 18:53:42,983 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2aa5c026-8a8d-4c06-b6eb-8e832694e9de/sv-benchmarks/c/seq-mthreaded/pals_lcr.8.1.ufo.UNBOUNDED.pals.c [2024-11-08 18:53:43,005 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2aa5c026-8a8d-4c06-b6eb-8e832694e9de/bin/uautomizer-verify-jihMAELWvX/data/635606fa7/154dc1ebc823400790825123a1346605/FLAGdf0651a97 [2024-11-08 18:53:43,024 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2aa5c026-8a8d-4c06-b6eb-8e832694e9de/bin/uautomizer-verify-jihMAELWvX/data/635606fa7/154dc1ebc823400790825123a1346605 [2024-11-08 18:53:43,027 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-08 18:53:43,029 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-08 18:53:43,033 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-08 18:53:43,034 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-08 18:53:43,041 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-08 18:53:43,042 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 08.11 06:53:43" (1/1) ... [2024-11-08 18:53:43,046 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@71ce38ad and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 06:53:43, skipping insertion in model container [2024-11-08 18:53:43,046 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 08.11 06:53:43" (1/1) ... [2024-11-08 18:53:43,104 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-08 18:53:43,526 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-08 18:53:43,549 INFO L200 MainTranslator]: Completed pre-run [2024-11-08 18:53:43,709 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-08 18:53:43,734 INFO L204 MainTranslator]: Completed translation [2024-11-08 18:53:43,735 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 06:53:43 WrapperNode [2024-11-08 18:53:43,735 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-08 18:53:43,737 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-08 18:53:43,737 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-08 18:53:43,737 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-08 18:53:43,747 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 06:53:43" (1/1) ... [2024-11-08 18:53:43,768 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 06:53:43" (1/1) ... [2024-11-08 18:53:43,831 INFO L138 Inliner]: procedures = 28, calls = 20, calls flagged for inlining = 15, calls inlined = 15, statements flattened = 505 [2024-11-08 18:53:43,831 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-08 18:53:43,832 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-08 18:53:43,832 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-08 18:53:43,833 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-08 18:53:43,848 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 06:53:43" (1/1) ... [2024-11-08 18:53:43,848 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 06:53:43" (1/1) ... [2024-11-08 18:53:43,853 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 06:53:43" (1/1) ... [2024-11-08 18:53:43,884 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-11-08 18:53:43,885 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 06:53:43" (1/1) ... [2024-11-08 18:53:43,886 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 06:53:43" (1/1) ... [2024-11-08 18:53:43,909 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 06:53:43" (1/1) ... [2024-11-08 18:53:43,926 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 06:53:43" (1/1) ... [2024-11-08 18:53:43,936 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 06:53:43" (1/1) ... [2024-11-08 18:53:43,943 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 06:53:43" (1/1) ... [2024-11-08 18:53:43,952 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-08 18:53:43,954 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-11-08 18:53:43,957 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-11-08 18:53:43,958 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-11-08 18:53:43,959 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 06:53:43" (1/1) ... [2024-11-08 18:53:43,969 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 18:53:43,984 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2aa5c026-8a8d-4c06-b6eb-8e832694e9de/bin/uautomizer-verify-jihMAELWvX/z3 [2024-11-08 18:53:44,001 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2aa5c026-8a8d-4c06-b6eb-8e832694e9de/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 18:53:44,003 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_2aa5c026-8a8d-4c06-b6eb-8e832694e9de/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-11-08 18:53:44,036 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-08 18:53:44,036 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-11-08 18:53:44,036 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-08 18:53:44,036 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-08 18:53:44,214 INFO L238 CfgBuilder]: Building ICFG [2024-11-08 18:53:44,217 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-08 18:53:45,187 INFO L? ?]: Removed 55 outVars from TransFormulas that were not future-live. [2024-11-08 18:53:45,188 INFO L287 CfgBuilder]: Performing block encoding [2024-11-08 18:53:45,215 INFO L311 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-08 18:53:45,216 INFO L316 CfgBuilder]: Removed 1 assume(true) statements. [2024-11-08 18:53:45,217 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 08.11 06:53:45 BoogieIcfgContainer [2024-11-08 18:53:45,217 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-11-08 18:53:45,218 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-11-08 18:53:45,219 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-11-08 18:53:45,223 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-11-08 18:53:45,224 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-08 18:53:45,224 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 08.11 06:53:43" (1/3) ... [2024-11-08 18:53:45,225 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@57963d55 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 08.11 06:53:45, skipping insertion in model container [2024-11-08 18:53:45,226 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-08 18:53:45,226 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 06:53:43" (2/3) ... [2024-11-08 18:53:45,226 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@57963d55 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 08.11 06:53:45, skipping insertion in model container [2024-11-08 18:53:45,226 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-08 18:53:45,227 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 08.11 06:53:45" (3/3) ... [2024-11-08 18:53:45,230 INFO L332 chiAutomizerObserver]: Analyzing ICFG pals_lcr.8.1.ufo.UNBOUNDED.pals.c [2024-11-08 18:53:45,317 INFO L300 stractBuchiCegarLoop]: Interprodecural is true [2024-11-08 18:53:45,317 INFO L301 stractBuchiCegarLoop]: Hoare is None [2024-11-08 18:53:45,317 INFO L302 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-11-08 18:53:45,317 INFO L303 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-11-08 18:53:45,318 INFO L304 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-11-08 18:53:45,318 INFO L305 stractBuchiCegarLoop]: Difference is false [2024-11-08 18:53:45,318 INFO L306 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-11-08 18:53:45,318 INFO L310 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-11-08 18:53:45,325 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 133 states, 132 states have (on average 1.7803030303030303) internal successors, (235), 132 states have internal predecessors, (235), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 18:53:45,357 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 62 [2024-11-08 18:53:45,357 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 18:53:45,357 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 18:53:45,368 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1] [2024-11-08 18:53:45,368 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 18:53:45,368 INFO L332 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-11-08 18:53:45,369 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 133 states, 132 states have (on average 1.7803030303030303) internal successors, (235), 132 states have internal predecessors, (235), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 18:53:45,380 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 62 [2024-11-08 18:53:45,381 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 18:53:45,381 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 18:53:45,382 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1] [2024-11-08 18:53:45,383 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 18:53:45,394 INFO L745 eck$LassoCheckResult]: Stem: 26#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(34, 2);call #Ultimate.allocInit(12, 3);~nomsg~0 := -1;~r1~0 := 0;~p1~0 := 0;~p1_old~0 := 0;~p1_new~0 := 0;~id1~0 := 0;~st1~0 := 0;~send1~0 := 0;~mode1~0 := 0;~p2~0 := 0;~p2_old~0 := 0;~p2_new~0 := 0;~id2~0 := 0;~st2~0 := 0;~send2~0 := 0;~mode2~0 := 0;~p3~0 := 0;~p3_old~0 := 0;~p3_new~0 := 0;~id3~0 := 0;~st3~0 := 0;~send3~0 := 0;~mode3~0 := 0;~p4~0 := 0;~p4_old~0 := 0;~p4_new~0 := 0;~id4~0 := 0;~st4~0 := 0;~send4~0 := 0;~mode4~0 := 0;~p5~0 := 0;~p5_old~0 := 0;~p5_new~0 := 0;~id5~0 := 0;~st5~0 := 0;~send5~0 := 0;~mode5~0 := 0;~p6~0 := 0;~p6_old~0 := 0;~p6_new~0 := 0;~id6~0 := 0;~st6~0 := 0;~send6~0 := 0;~mode6~0 := 0;~p7~0 := 0;~p7_old~0 := 0;~p7_new~0 := 0;~id7~0 := 0;~st7~0 := 0;~send7~0 := 0;~mode7~0 := 0;~p8~0 := 0;~p8_old~0 := 0;~p8_new~0 := 0;~id8~0 := 0;~st8~0 := 0;~send8~0 := 0;~mode8~0 := 0;~nodes~0.base, ~nodes~0.offset := ~nodes~0.base[0 := #funAddr~node1.base], ~nodes~0.offset[0 := #funAddr~node1.offset];~nodes~0.base, ~nodes~0.offset := ~nodes~0.base[1 := #funAddr~node2.base], ~nodes~0.offset[1 := #funAddr~node2.offset];~nodes~0.base, ~nodes~0.offset := ~nodes~0.base[2 := #funAddr~node3.base], ~nodes~0.offset[2 := #funAddr~node3.offset];~nodes~0.base, ~nodes~0.offset := ~nodes~0.base[3 := #funAddr~node4.base], ~nodes~0.offset[3 := #funAddr~node4.offset];~nodes~0.base, ~nodes~0.offset := ~nodes~0.base[4 := #funAddr~node5.base], ~nodes~0.offset[4 := #funAddr~node5.offset];~nodes~0.base, ~nodes~0.offset := ~nodes~0.base[5 := #funAddr~node6.base], ~nodes~0.offset[5 := #funAddr~node6.offset];~nodes~0.base, ~nodes~0.offset := ~nodes~0.base[6 := #funAddr~node7.base], ~nodes~0.offset[6 := #funAddr~node7.offset];~nodes~0.base, ~nodes~0.offset := ~nodes~0.base[7 := #funAddr~node8.base], ~nodes~0.offset[7 := #funAddr~node8.offset]; 39#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet4#1, main_#t~nondet5#1, main_#t~nondet6#1, main_#t~nondet7#1, main_#t~nondet8#1, main_#t~nondet9#1, main_#t~nondet10#1, main_#t~nondet11#1, main_#t~nondet12#1, main_#t~nondet13#1, main_#t~nondet14#1, main_#t~nondet15#1, main_#t~nondet16#1, main_#t~nondet17#1, main_#t~nondet18#1, main_#t~nondet19#1, main_#t~nondet20#1, main_#t~nondet21#1, main_#t~nondet22#1, main_#t~nondet23#1, main_#t~nondet24#1, main_#t~nondet25#1, main_#t~nondet26#1, main_#t~nondet27#1, main_#t~nondet28#1, main_#t~nondet29#1, main_#t~nondet30#1, main_#t~nondet31#1, main_#t~nondet32#1, main_#t~nondet33#1, main_#t~nondet34#1, main_#t~nondet35#1, main_#t~nondet36#1, main_#t~ret37#1, main_#t~ret38#1, main_~c1~0#1, main_~i2~0#1;havoc main_~c1~0#1;havoc main_~i2~0#1;main_~c1~0#1 := 0;havoc main_#t~nondet4#1;~r1~0 := main_#t~nondet4#1;havoc main_#t~nondet4#1;havoc main_#t~nondet5#1;~id1~0 := main_#t~nondet5#1;havoc main_#t~nondet5#1;havoc main_#t~nondet6#1;~st1~0 := main_#t~nondet6#1;havoc main_#t~nondet6#1;havoc main_#t~nondet7#1;~send1~0 := main_#t~nondet7#1;havoc main_#t~nondet7#1;havoc main_#t~nondet8#1;assume 0 == main_#t~nondet8#1 || 1 == main_#t~nondet8#1;~mode1~0 := (if 0 == main_#t~nondet8#1 % 256 then 0 else 1);havoc main_#t~nondet8#1;havoc main_#t~nondet9#1;~id2~0 := main_#t~nondet9#1;havoc main_#t~nondet9#1;havoc main_#t~nondet10#1;~st2~0 := main_#t~nondet10#1;havoc main_#t~nondet10#1;havoc main_#t~nondet11#1;~send2~0 := main_#t~nondet11#1;havoc main_#t~nondet11#1;havoc main_#t~nondet12#1;assume 0 == main_#t~nondet12#1 || 1 == main_#t~nondet12#1;~mode2~0 := (if 0 == main_#t~nondet12#1 % 256 then 0 else 1);havoc main_#t~nondet12#1;havoc main_#t~nondet13#1;~id3~0 := main_#t~nondet13#1;havoc main_#t~nondet13#1;havoc main_#t~nondet14#1;~st3~0 := main_#t~nondet14#1;havoc main_#t~nondet14#1;havoc main_#t~nondet15#1;~send3~0 := main_#t~nondet15#1;havoc main_#t~nondet15#1;havoc main_#t~nondet16#1;assume 0 == main_#t~nondet16#1 || 1 == main_#t~nondet16#1;~mode3~0 := (if 0 == main_#t~nondet16#1 % 256 then 0 else 1);havoc main_#t~nondet16#1;havoc main_#t~nondet17#1;~id4~0 := main_#t~nondet17#1;havoc main_#t~nondet17#1;havoc main_#t~nondet18#1;~st4~0 := main_#t~nondet18#1;havoc main_#t~nondet18#1;havoc main_#t~nondet19#1;~send4~0 := main_#t~nondet19#1;havoc main_#t~nondet19#1;havoc main_#t~nondet20#1;assume 0 == main_#t~nondet20#1 || 1 == main_#t~nondet20#1;~mode4~0 := (if 0 == main_#t~nondet20#1 % 256 then 0 else 1);havoc main_#t~nondet20#1;havoc main_#t~nondet21#1;~id5~0 := main_#t~nondet21#1;havoc main_#t~nondet21#1;havoc main_#t~nondet22#1;~st5~0 := main_#t~nondet22#1;havoc main_#t~nondet22#1;havoc main_#t~nondet23#1;~send5~0 := main_#t~nondet23#1;havoc main_#t~nondet23#1;havoc main_#t~nondet24#1;assume 0 == main_#t~nondet24#1 || 1 == main_#t~nondet24#1;~mode5~0 := (if 0 == main_#t~nondet24#1 % 256 then 0 else 1);havoc main_#t~nondet24#1;havoc main_#t~nondet25#1;~id6~0 := main_#t~nondet25#1;havoc main_#t~nondet25#1;havoc main_#t~nondet26#1;~st6~0 := main_#t~nondet26#1;havoc main_#t~nondet26#1;havoc main_#t~nondet27#1;~send6~0 := main_#t~nondet27#1;havoc main_#t~nondet27#1;havoc main_#t~nondet28#1;assume 0 == main_#t~nondet28#1 || 1 == main_#t~nondet28#1;~mode6~0 := (if 0 == main_#t~nondet28#1 % 256 then 0 else 1);havoc main_#t~nondet28#1;havoc main_#t~nondet29#1;~id7~0 := main_#t~nondet29#1;havoc main_#t~nondet29#1;havoc main_#t~nondet30#1;~st7~0 := main_#t~nondet30#1;havoc main_#t~nondet30#1;havoc main_#t~nondet31#1;~send7~0 := main_#t~nondet31#1;havoc main_#t~nondet31#1;havoc main_#t~nondet32#1;assume 0 == main_#t~nondet32#1 || 1 == main_#t~nondet32#1;~mode7~0 := (if 0 == main_#t~nondet32#1 % 256 then 0 else 1);havoc main_#t~nondet32#1;havoc main_#t~nondet33#1;~id8~0 := main_#t~nondet33#1;havoc main_#t~nondet33#1;havoc main_#t~nondet34#1;~st8~0 := main_#t~nondet34#1;havoc main_#t~nondet34#1;havoc main_#t~nondet35#1;~send8~0 := main_#t~nondet35#1;havoc main_#t~nondet35#1;havoc main_#t~nondet36#1;assume 0 == main_#t~nondet36#1 || 1 == main_#t~nondet36#1;~mode8~0 := (if 0 == main_#t~nondet36#1 % 256 then 0 else 1);havoc main_#t~nondet36#1;assume { :begin_inline_init } true;havoc init_#res#1;havoc init_~tmp~0#1;havoc init_~tmp~0#1; 73#L300true assume !(0 == (if ~r1~0 % 256 % 4294967296 <= 2147483647 then ~r1~0 % 256 % 4294967296 else ~r1~0 % 256 % 4294967296 - 4294967296));init_~tmp~0#1 := 0; 47#L300-1true init_#res#1 := init_~tmp~0#1; 99#init_returnLabel#1true main_#t~ret37#1 := init_#res#1;havoc init_~tmp~0#1;assume { :end_inline_init } true;main_~i2~0#1 := main_#t~ret37#1;havoc main_#t~ret37#1;assume { :begin_inline_assume_abort_if_not } true;assume_abort_if_not_#in~cond#1 := main_~i2~0#1;havoc assume_abort_if_not_~cond#1;assume_abort_if_not_~cond#1 := assume_abort_if_not_#in~cond#1; 41#L22true assume !(0 == assume_abort_if_not_~cond#1); 107#L21true havoc assume_abort_if_not_~cond#1;havoc assume_abort_if_not_#in~cond#1;assume { :end_inline_assume_abort_if_not } true;~p1_old~0 := ~nomsg~0;~p1_new~0 := ~nomsg~0;~p2_old~0 := ~nomsg~0;~p2_new~0 := ~nomsg~0;~p3_old~0 := ~nomsg~0;~p3_new~0 := ~nomsg~0;~p4_old~0 := ~nomsg~0;~p4_new~0 := ~nomsg~0;~p5_old~0 := ~nomsg~0;~p5_new~0 := ~nomsg~0;~p6_old~0 := ~nomsg~0;~p6_new~0 := ~nomsg~0;~p7_old~0 := ~nomsg~0;~p7_new~0 := ~nomsg~0;~p8_old~0 := ~nomsg~0;~p8_new~0 := ~nomsg~0;main_~i2~0#1 := 0; 53#L635-2true [2024-11-08 18:53:45,396 INFO L747 eck$LassoCheckResult]: Loop: 53#L635-2true assume !false;assume { :begin_inline_node1 } true;havoc node1_~m1~0#1;havoc node1_~m1~0#1;node1_~m1~0#1 := ~nomsg~0; 117#L92true assume !(0 != ~mode1~0 % 256);~p1_new~0 := (if (if ~send1~0 != ~nomsg~0 && ~p1_new~0 == ~nomsg~0 then ~send1~0 else ~p1_new~0) % 256 <= 127 then (if ~send1~0 != ~nomsg~0 && ~p1_new~0 == ~nomsg~0 then ~send1~0 else ~p1_new~0) % 256 else (if ~send1~0 != ~nomsg~0 && ~p1_new~0 == ~nomsg~0 then ~send1~0 else ~p1_new~0) % 256 - 256);~mode1~0 := 1; 67#L92-2true havoc node1_~m1~0#1;assume { :end_inline_node1 } true;assume { :begin_inline_node2 } true;havoc node2_~m2~0#1;havoc node2_~m2~0#1;node2_~m2~0#1 := ~nomsg~0; 17#L123true assume !(0 != ~mode2~0 % 256);~p2_new~0 := (if (if ~send2~0 != ~nomsg~0 && ~p2_new~0 == ~nomsg~0 then ~send2~0 else ~p2_new~0) % 256 <= 127 then (if ~send2~0 != ~nomsg~0 && ~p2_new~0 == ~nomsg~0 then ~send2~0 else ~p2_new~0) % 256 else (if ~send2~0 != ~nomsg~0 && ~p2_new~0 == ~nomsg~0 then ~send2~0 else ~p2_new~0) % 256 - 256);~mode2~0 := 1; 42#L123-2true havoc node2_~m2~0#1;assume { :end_inline_node2 } true;assume { :begin_inline_node3 } true;havoc node3_~m3~0#1;havoc node3_~m3~0#1;node3_~m3~0#1 := ~nomsg~0; 25#L148true assume !(0 != ~mode3~0 % 256);~p3_new~0 := (if (if ~send3~0 != ~nomsg~0 && ~p3_new~0 == ~nomsg~0 then ~send3~0 else ~p3_new~0) % 256 <= 127 then (if ~send3~0 != ~nomsg~0 && ~p3_new~0 == ~nomsg~0 then ~send3~0 else ~p3_new~0) % 256 else (if ~send3~0 != ~nomsg~0 && ~p3_new~0 == ~nomsg~0 then ~send3~0 else ~p3_new~0) % 256 - 256);~mode3~0 := 1; 37#L148-2true havoc node3_~m3~0#1;assume { :end_inline_node3 } true;assume { :begin_inline_node4 } true;havoc node4_~m4~0#1;havoc node4_~m4~0#1;node4_~m4~0#1 := ~nomsg~0; 57#L173true assume !(0 != ~mode4~0 % 256);~p4_new~0 := (if (if ~send4~0 != ~nomsg~0 && ~p4_new~0 == ~nomsg~0 then ~send4~0 else ~p4_new~0) % 256 <= 127 then (if ~send4~0 != ~nomsg~0 && ~p4_new~0 == ~nomsg~0 then ~send4~0 else ~p4_new~0) % 256 else (if ~send4~0 != ~nomsg~0 && ~p4_new~0 == ~nomsg~0 then ~send4~0 else ~p4_new~0) % 256 - 256);~mode4~0 := 1; 132#L173-2true havoc node4_~m4~0#1;assume { :end_inline_node4 } true;assume { :begin_inline_node5 } true;havoc node5_~m5~0#1;havoc node5_~m5~0#1;node5_~m5~0#1 := ~nomsg~0; 78#L198true assume !(0 != ~mode5~0 % 256);~p5_new~0 := (if (if ~send5~0 != ~nomsg~0 && ~p5_new~0 == ~nomsg~0 then ~send5~0 else ~p5_new~0) % 256 <= 127 then (if ~send5~0 != ~nomsg~0 && ~p5_new~0 == ~nomsg~0 then ~send5~0 else ~p5_new~0) % 256 else (if ~send5~0 != ~nomsg~0 && ~p5_new~0 == ~nomsg~0 then ~send5~0 else ~p5_new~0) % 256 - 256);~mode5~0 := 1; 84#L198-2true havoc node5_~m5~0#1;assume { :end_inline_node5 } true;assume { :begin_inline_node6 } true;havoc node6_~m6~0#1;havoc node6_~m6~0#1;node6_~m6~0#1 := ~nomsg~0; 71#L223true assume !(0 != ~mode6~0 % 256);~p6_new~0 := (if (if ~send6~0 != ~nomsg~0 && ~p6_new~0 == ~nomsg~0 then ~send6~0 else ~p6_new~0) % 256 <= 127 then (if ~send6~0 != ~nomsg~0 && ~p6_new~0 == ~nomsg~0 then ~send6~0 else ~p6_new~0) % 256 else (if ~send6~0 != ~nomsg~0 && ~p6_new~0 == ~nomsg~0 then ~send6~0 else ~p6_new~0) % 256 - 256);~mode6~0 := 1; 55#L223-2true havoc node6_~m6~0#1;assume { :end_inline_node6 } true;assume { :begin_inline_node7 } true;havoc node7_~m7~0#1;havoc node7_~m7~0#1;node7_~m7~0#1 := ~nomsg~0; 131#L248true assume !(0 != ~mode7~0 % 256);~p7_new~0 := (if (if ~send7~0 != ~nomsg~0 && ~p7_new~0 == ~nomsg~0 then ~send7~0 else ~p7_new~0) % 256 <= 127 then (if ~send7~0 != ~nomsg~0 && ~p7_new~0 == ~nomsg~0 then ~send7~0 else ~p7_new~0) % 256 else (if ~send7~0 != ~nomsg~0 && ~p7_new~0 == ~nomsg~0 then ~send7~0 else ~p7_new~0) % 256 - 256);~mode7~0 := 1; 32#L248-2true havoc node7_~m7~0#1;assume { :end_inline_node7 } true;assume { :begin_inline_node8 } true;havoc node8_~m8~0#1;havoc node8_~m8~0#1;node8_~m8~0#1 := ~nomsg~0; 65#L273true assume !(0 != ~mode8~0 % 256);~p8_new~0 := (if (if ~send8~0 != ~nomsg~0 && ~p8_new~0 == ~nomsg~0 then ~send8~0 else ~p8_new~0) % 256 <= 127 then (if ~send8~0 != ~nomsg~0 && ~p8_new~0 == ~nomsg~0 then ~send8~0 else ~p8_new~0) % 256 else (if ~send8~0 != ~nomsg~0 && ~p8_new~0 == ~nomsg~0 then ~send8~0 else ~p8_new~0) % 256 - 256);~mode8~0 := 1; 116#L273-2true havoc node8_~m8~0#1;assume { :end_inline_node8 } true;~p1_old~0 := ~p1_new~0;~p1_new~0 := ~nomsg~0;~p2_old~0 := ~p2_new~0;~p2_new~0 := ~nomsg~0;~p3_old~0 := ~p3_new~0;~p3_new~0 := ~nomsg~0;~p4_old~0 := ~p4_new~0;~p4_new~0 := ~nomsg~0;~p5_old~0 := ~p5_new~0;~p5_new~0 := ~nomsg~0;~p6_old~0 := ~p6_new~0;~p6_new~0 := ~nomsg~0;~p7_old~0 := ~p7_new~0;~p7_new~0 := ~nomsg~0;~p8_old~0 := ~p8_new~0;~p8_new~0 := ~nomsg~0;assume { :begin_inline_check } true;havoc check_#res#1;havoc check_~tmp~1#1;havoc check_~tmp~1#1; 85#L553true assume !(~st1~0 + ~st2~0 + ~st3~0 + ~st4~0 + ~st5~0 + ~st6~0 + ~st7~0 + ~st8~0 <= 1);check_~tmp~1#1 := 0; 100#L553-1true check_#res#1 := check_~tmp~1#1; 15#check_returnLabel#1true main_#t~ret38#1 := check_#res#1;havoc check_~tmp~1#1;assume { :end_inline_check } true;main_~c1~0#1 := main_#t~ret38#1;havoc main_#t~ret38#1;assume { :begin_inline_assert } true;assert_#in~arg#1 := (if 0 == main_~c1~0#1 then 0 else 1);havoc assert_~arg#1;assert_~arg#1 := assert_#in~arg#1; 21#L673true assume !(0 == assert_~arg#1 % 256); 29#L668true havoc assert_~arg#1;havoc assert_#in~arg#1;assume { :end_inline_assert } true; 53#L635-2true [2024-11-08 18:53:45,406 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:53:45,406 INFO L85 PathProgramCache]: Analyzing trace with hash -2144605008, now seen corresponding path program 1 times [2024-11-08 18:53:45,421 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 18:53:45,422 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1037740522] [2024-11-08 18:53:45,423 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:53:45,423 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 18:53:45,744 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 18:53:46,164 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 18:53:46,165 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 18:53:46,165 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1037740522] [2024-11-08 18:53:46,166 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1037740522] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 18:53:46,167 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 18:53:46,167 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-08 18:53:46,169 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [400952047] [2024-11-08 18:53:46,170 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 18:53:46,176 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 18:53:46,177 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:53:46,177 INFO L85 PathProgramCache]: Analyzing trace with hash -719911808, now seen corresponding path program 1 times [2024-11-08 18:53:46,178 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 18:53:46,178 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [140596665] [2024-11-08 18:53:46,178 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:53:46,179 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 18:53:46,294 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 18:53:46,781 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 18:53:46,782 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 18:53:46,782 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [140596665] [2024-11-08 18:53:46,782 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [140596665] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 18:53:46,783 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 18:53:46,783 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-08 18:53:46,783 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1732277914] [2024-11-08 18:53:46,784 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 18:53:46,785 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 18:53:46,788 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 18:53:46,831 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-08 18:53:46,832 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-08 18:53:46,835 INFO L87 Difference]: Start difference. First operand has 133 states, 132 states have (on average 1.7803030303030303) internal successors, (235), 132 states have internal predecessors, (235), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 5 states, 5 states have (on average 1.4) internal successors, (7), 5 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 18:53:47,094 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 18:53:47,094 INFO L93 Difference]: Finished difference Result 131 states and 229 transitions. [2024-11-08 18:53:47,096 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 131 states and 229 transitions. [2024-11-08 18:53:47,100 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 60 [2024-11-08 18:53:47,106 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 131 states to 127 states and 165 transitions. [2024-11-08 18:53:47,108 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 127 [2024-11-08 18:53:47,109 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 127 [2024-11-08 18:53:47,112 INFO L73 IsDeterministic]: Start isDeterministic. Operand 127 states and 165 transitions. [2024-11-08 18:53:47,113 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 18:53:47,114 INFO L218 hiAutomatonCegarLoop]: Abstraction has 127 states and 165 transitions. [2024-11-08 18:53:47,137 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 127 states and 165 transitions. [2024-11-08 18:53:47,162 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 127 to 127. [2024-11-08 18:53:47,166 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 127 states, 127 states have (on average 1.2992125984251968) internal successors, (165), 126 states have internal predecessors, (165), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 18:53:47,167 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 127 states to 127 states and 165 transitions. [2024-11-08 18:53:47,173 INFO L240 hiAutomatonCegarLoop]: Abstraction has 127 states and 165 transitions. [2024-11-08 18:53:47,175 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-08 18:53:47,182 INFO L425 stractBuchiCegarLoop]: Abstraction has 127 states and 165 transitions. [2024-11-08 18:53:47,183 INFO L332 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-11-08 18:53:47,183 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 127 states and 165 transitions. [2024-11-08 18:53:47,191 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 60 [2024-11-08 18:53:47,192 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 18:53:47,192 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 18:53:47,194 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 18:53:47,195 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 18:53:47,196 INFO L745 eck$LassoCheckResult]: Stem: 323#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(34, 2);call #Ultimate.allocInit(12, 3);~nomsg~0 := -1;~r1~0 := 0;~p1~0 := 0;~p1_old~0 := 0;~p1_new~0 := 0;~id1~0 := 0;~st1~0 := 0;~send1~0 := 0;~mode1~0 := 0;~p2~0 := 0;~p2_old~0 := 0;~p2_new~0 := 0;~id2~0 := 0;~st2~0 := 0;~send2~0 := 0;~mode2~0 := 0;~p3~0 := 0;~p3_old~0 := 0;~p3_new~0 := 0;~id3~0 := 0;~st3~0 := 0;~send3~0 := 0;~mode3~0 := 0;~p4~0 := 0;~p4_old~0 := 0;~p4_new~0 := 0;~id4~0 := 0;~st4~0 := 0;~send4~0 := 0;~mode4~0 := 0;~p5~0 := 0;~p5_old~0 := 0;~p5_new~0 := 0;~id5~0 := 0;~st5~0 := 0;~send5~0 := 0;~mode5~0 := 0;~p6~0 := 0;~p6_old~0 := 0;~p6_new~0 := 0;~id6~0 := 0;~st6~0 := 0;~send6~0 := 0;~mode6~0 := 0;~p7~0 := 0;~p7_old~0 := 0;~p7_new~0 := 0;~id7~0 := 0;~st7~0 := 0;~send7~0 := 0;~mode7~0 := 0;~p8~0 := 0;~p8_old~0 := 0;~p8_new~0 := 0;~id8~0 := 0;~st8~0 := 0;~send8~0 := 0;~mode8~0 := 0;~nodes~0.base, ~nodes~0.offset := ~nodes~0.base[0 := #funAddr~node1.base], ~nodes~0.offset[0 := #funAddr~node1.offset];~nodes~0.base, ~nodes~0.offset := ~nodes~0.base[1 := #funAddr~node2.base], ~nodes~0.offset[1 := #funAddr~node2.offset];~nodes~0.base, ~nodes~0.offset := ~nodes~0.base[2 := #funAddr~node3.base], ~nodes~0.offset[2 := #funAddr~node3.offset];~nodes~0.base, ~nodes~0.offset := ~nodes~0.base[3 := #funAddr~node4.base], ~nodes~0.offset[3 := #funAddr~node4.offset];~nodes~0.base, ~nodes~0.offset := ~nodes~0.base[4 := #funAddr~node5.base], ~nodes~0.offset[4 := #funAddr~node5.offset];~nodes~0.base, ~nodes~0.offset := ~nodes~0.base[5 := #funAddr~node6.base], ~nodes~0.offset[5 := #funAddr~node6.offset];~nodes~0.base, ~nodes~0.offset := ~nodes~0.base[6 := #funAddr~node7.base], ~nodes~0.offset[6 := #funAddr~node7.offset];~nodes~0.base, ~nodes~0.offset := ~nodes~0.base[7 := #funAddr~node8.base], ~nodes~0.offset[7 := #funAddr~node8.offset]; 324#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet4#1, main_#t~nondet5#1, main_#t~nondet6#1, main_#t~nondet7#1, main_#t~nondet8#1, main_#t~nondet9#1, main_#t~nondet10#1, main_#t~nondet11#1, main_#t~nondet12#1, main_#t~nondet13#1, main_#t~nondet14#1, main_#t~nondet15#1, main_#t~nondet16#1, main_#t~nondet17#1, main_#t~nondet18#1, main_#t~nondet19#1, main_#t~nondet20#1, main_#t~nondet21#1, main_#t~nondet22#1, main_#t~nondet23#1, main_#t~nondet24#1, main_#t~nondet25#1, main_#t~nondet26#1, main_#t~nondet27#1, main_#t~nondet28#1, main_#t~nondet29#1, main_#t~nondet30#1, main_#t~nondet31#1, main_#t~nondet32#1, main_#t~nondet33#1, main_#t~nondet34#1, main_#t~nondet35#1, main_#t~nondet36#1, main_#t~ret37#1, main_#t~ret38#1, main_~c1~0#1, main_~i2~0#1;havoc main_~c1~0#1;havoc main_~i2~0#1;main_~c1~0#1 := 0;havoc main_#t~nondet4#1;~r1~0 := main_#t~nondet4#1;havoc main_#t~nondet4#1;havoc main_#t~nondet5#1;~id1~0 := main_#t~nondet5#1;havoc main_#t~nondet5#1;havoc main_#t~nondet6#1;~st1~0 := main_#t~nondet6#1;havoc main_#t~nondet6#1;havoc main_#t~nondet7#1;~send1~0 := main_#t~nondet7#1;havoc main_#t~nondet7#1;havoc main_#t~nondet8#1;assume 0 == main_#t~nondet8#1 || 1 == main_#t~nondet8#1;~mode1~0 := (if 0 == main_#t~nondet8#1 % 256 then 0 else 1);havoc main_#t~nondet8#1;havoc main_#t~nondet9#1;~id2~0 := main_#t~nondet9#1;havoc main_#t~nondet9#1;havoc main_#t~nondet10#1;~st2~0 := main_#t~nondet10#1;havoc main_#t~nondet10#1;havoc main_#t~nondet11#1;~send2~0 := main_#t~nondet11#1;havoc main_#t~nondet11#1;havoc main_#t~nondet12#1;assume 0 == main_#t~nondet12#1 || 1 == main_#t~nondet12#1;~mode2~0 := (if 0 == main_#t~nondet12#1 % 256 then 0 else 1);havoc main_#t~nondet12#1;havoc main_#t~nondet13#1;~id3~0 := main_#t~nondet13#1;havoc main_#t~nondet13#1;havoc main_#t~nondet14#1;~st3~0 := main_#t~nondet14#1;havoc main_#t~nondet14#1;havoc main_#t~nondet15#1;~send3~0 := main_#t~nondet15#1;havoc main_#t~nondet15#1;havoc main_#t~nondet16#1;assume 0 == main_#t~nondet16#1 || 1 == main_#t~nondet16#1;~mode3~0 := (if 0 == main_#t~nondet16#1 % 256 then 0 else 1);havoc main_#t~nondet16#1;havoc main_#t~nondet17#1;~id4~0 := main_#t~nondet17#1;havoc main_#t~nondet17#1;havoc main_#t~nondet18#1;~st4~0 := main_#t~nondet18#1;havoc main_#t~nondet18#1;havoc main_#t~nondet19#1;~send4~0 := main_#t~nondet19#1;havoc main_#t~nondet19#1;havoc main_#t~nondet20#1;assume 0 == main_#t~nondet20#1 || 1 == main_#t~nondet20#1;~mode4~0 := (if 0 == main_#t~nondet20#1 % 256 then 0 else 1);havoc main_#t~nondet20#1;havoc main_#t~nondet21#1;~id5~0 := main_#t~nondet21#1;havoc main_#t~nondet21#1;havoc main_#t~nondet22#1;~st5~0 := main_#t~nondet22#1;havoc main_#t~nondet22#1;havoc main_#t~nondet23#1;~send5~0 := main_#t~nondet23#1;havoc main_#t~nondet23#1;havoc main_#t~nondet24#1;assume 0 == main_#t~nondet24#1 || 1 == main_#t~nondet24#1;~mode5~0 := (if 0 == main_#t~nondet24#1 % 256 then 0 else 1);havoc main_#t~nondet24#1;havoc main_#t~nondet25#1;~id6~0 := main_#t~nondet25#1;havoc main_#t~nondet25#1;havoc main_#t~nondet26#1;~st6~0 := main_#t~nondet26#1;havoc main_#t~nondet26#1;havoc main_#t~nondet27#1;~send6~0 := main_#t~nondet27#1;havoc main_#t~nondet27#1;havoc main_#t~nondet28#1;assume 0 == main_#t~nondet28#1 || 1 == main_#t~nondet28#1;~mode6~0 := (if 0 == main_#t~nondet28#1 % 256 then 0 else 1);havoc main_#t~nondet28#1;havoc main_#t~nondet29#1;~id7~0 := main_#t~nondet29#1;havoc main_#t~nondet29#1;havoc main_#t~nondet30#1;~st7~0 := main_#t~nondet30#1;havoc main_#t~nondet30#1;havoc main_#t~nondet31#1;~send7~0 := main_#t~nondet31#1;havoc main_#t~nondet31#1;havoc main_#t~nondet32#1;assume 0 == main_#t~nondet32#1 || 1 == main_#t~nondet32#1;~mode7~0 := (if 0 == main_#t~nondet32#1 % 256 then 0 else 1);havoc main_#t~nondet32#1;havoc main_#t~nondet33#1;~id8~0 := main_#t~nondet33#1;havoc main_#t~nondet33#1;havoc main_#t~nondet34#1;~st8~0 := main_#t~nondet34#1;havoc main_#t~nondet34#1;havoc main_#t~nondet35#1;~send8~0 := main_#t~nondet35#1;havoc main_#t~nondet35#1;havoc main_#t~nondet36#1;assume 0 == main_#t~nondet36#1 || 1 == main_#t~nondet36#1;~mode8~0 := (if 0 == main_#t~nondet36#1 % 256 then 0 else 1);havoc main_#t~nondet36#1;assume { :begin_inline_init } true;havoc init_#res#1;havoc init_~tmp~0#1;havoc init_~tmp~0#1; 343#L300 assume 0 == (if ~r1~0 % 256 % 4294967296 <= 2147483647 then ~r1~0 % 256 % 4294967296 else ~r1~0 % 256 % 4294967296 - 4294967296); 377#L301 assume ~id1~0 >= 0; 392#L302 assume 0 == ~st1~0; 393#L303 assume ~send1~0 == ~id1~0; 399#L304 assume 0 == (if ~mode1~0 % 256 % 4294967296 <= 2147483647 then ~mode1~0 % 256 % 4294967296 else ~mode1~0 % 256 % 4294967296 - 4294967296); 369#L305 assume ~id2~0 >= 0; 370#L306 assume 0 == ~st2~0; 387#L307 assume ~send2~0 == ~id2~0; 289#L308 assume 0 == (if ~mode2~0 % 256 % 4294967296 <= 2147483647 then ~mode2~0 % 256 % 4294967296 else ~mode2~0 % 256 % 4294967296 - 4294967296); 290#L309 assume ~id3~0 >= 0; 383#L310 assume 0 == ~st3~0; 356#L311 assume ~send3~0 == ~id3~0; 357#L312 assume 0 == (if ~mode3~0 % 256 % 4294967296 <= 2147483647 then ~mode3~0 % 256 % 4294967296 else ~mode3~0 % 256 % 4294967296 - 4294967296); 313#L313 assume ~id4~0 >= 0; 314#L314 assume 0 == ~st4~0; 347#L315 assume ~send4~0 == ~id4~0; 348#L316 assume 0 == (if ~mode4~0 % 256 % 4294967296 <= 2147483647 then ~mode4~0 % 256 % 4294967296 else ~mode4~0 % 256 % 4294967296 - 4294967296); 285#L317 assume ~id5~0 >= 0; 286#L318 assume 0 == ~st5~0; 403#L319 assume ~send5~0 == ~id5~0; 391#L320 assume 0 == (if ~mode5~0 % 256 % 4294967296 <= 2147483647 then ~mode5~0 % 256 % 4294967296 else ~mode5~0 % 256 % 4294967296 - 4294967296); 374#L321 assume ~id6~0 >= 0; 375#L322 assume 0 == ~st6~0; 283#L323 assume ~send6~0 == ~id6~0; 284#L324 assume 0 == (if ~mode6~0 % 256 % 4294967296 <= 2147483647 then ~mode6~0 % 256 % 4294967296 else ~mode6~0 % 256 % 4294967296 - 4294967296); 299#L325 assume ~id7~0 >= 0; 318#L326 assume 0 == ~st7~0; 306#L327 assume ~send7~0 == ~id7~0; 307#L328 assume 0 == (if ~mode7~0 % 256 % 4294967296 <= 2147483647 then ~mode7~0 % 256 % 4294967296 else ~mode7~0 % 256 % 4294967296 - 4294967296); 333#L329 assume ~id8~0 >= 0; 334#L330 assume 0 == ~st8~0; 287#L331 assume ~send8~0 == ~id8~0; 288#L332 assume 0 == (if ~mode8~0 % 256 % 4294967296 <= 2147483647 then ~mode8~0 % 256 % 4294967296 else ~mode8~0 % 256 % 4294967296 - 4294967296); 317#L333 assume ~id1~0 != ~id2~0; 331#L334 assume ~id1~0 != ~id3~0; 311#L335 assume ~id1~0 != ~id4~0; 312#L336 assume ~id1~0 != ~id5~0; 386#L337 assume ~id1~0 != ~id6~0; 360#L338 assume ~id1~0 != ~id7~0; 361#L339 assume ~id1~0 != ~id8~0; 401#L340 assume ~id2~0 != ~id3~0; 396#L341 assume ~id2~0 != ~id4~0; 335#L342 assume ~id2~0 != ~id5~0; 336#L343 assume ~id2~0 != ~id6~0; 325#L344 assume ~id2~0 != ~id7~0; 326#L345 assume ~id2~0 != ~id8~0; 351#L346 assume ~id3~0 != ~id4~0; 352#L347 assume ~id3~0 != ~id5~0; 402#L348 assume ~id3~0 != ~id6~0; 394#L349 assume ~id3~0 != ~id7~0; 395#L350 assume ~id3~0 != ~id8~0; 378#L351 assume ~id4~0 != ~id5~0; 379#L352 assume ~id4~0 != ~id6~0; 398#L353 assume ~id4~0 != ~id7~0; 367#L354 assume ~id4~0 != ~id8~0; 337#L355 assume ~id5~0 != ~id6~0; 338#L356 assume ~id5~0 != ~id7~0; 364#L357 assume ~id5~0 != ~id8~0; 297#L358 assume ~id6~0 != ~id7~0; 298#L359 assume ~id6~0 != ~id8~0; 300#L360 assume ~id7~0 != ~id8~0;init_~tmp~0#1 := 1; 301#L300-1 init_#res#1 := init_~tmp~0#1; 355#init_returnLabel#1 main_#t~ret37#1 := init_#res#1;havoc init_~tmp~0#1;assume { :end_inline_init } true;main_~i2~0#1 := main_#t~ret37#1;havoc main_#t~ret37#1;assume { :begin_inline_assume_abort_if_not } true;assume_abort_if_not_#in~cond#1 := main_~i2~0#1;havoc assume_abort_if_not_~cond#1;assume_abort_if_not_~cond#1 := assume_abort_if_not_#in~cond#1; 345#L22 assume !(0 == assume_abort_if_not_~cond#1); 346#L21 havoc assume_abort_if_not_~cond#1;havoc assume_abort_if_not_#in~cond#1;assume { :end_inline_assume_abort_if_not } true;~p1_old~0 := ~nomsg~0;~p1_new~0 := ~nomsg~0;~p2_old~0 := ~nomsg~0;~p2_new~0 := ~nomsg~0;~p3_old~0 := ~nomsg~0;~p3_new~0 := ~nomsg~0;~p4_old~0 := ~nomsg~0;~p4_new~0 := ~nomsg~0;~p5_old~0 := ~nomsg~0;~p5_new~0 := ~nomsg~0;~p6_old~0 := ~nomsg~0;~p6_new~0 := ~nomsg~0;~p7_old~0 := ~nomsg~0;~p7_new~0 := ~nomsg~0;~p8_old~0 := ~nomsg~0;~p8_new~0 := ~nomsg~0;main_~i2~0#1 := 0; 330#L635-2 [2024-11-08 18:53:47,196 INFO L747 eck$LassoCheckResult]: Loop: 330#L635-2 assume !false;assume { :begin_inline_node1 } true;havoc node1_~m1~0#1;havoc node1_~m1~0#1;node1_~m1~0#1 := ~nomsg~0; 362#L92 assume !(0 != ~mode1~0 % 256);~p1_new~0 := (if (if ~send1~0 != ~nomsg~0 && ~p1_new~0 == ~nomsg~0 then ~send1~0 else ~p1_new~0) % 256 <= 127 then (if ~send1~0 != ~nomsg~0 && ~p1_new~0 == ~nomsg~0 then ~send1~0 else ~p1_new~0) % 256 else (if ~send1~0 != ~nomsg~0 && ~p1_new~0 == ~nomsg~0 then ~send1~0 else ~p1_new~0) % 256 - 256);~mode1~0 := 1; 354#L92-2 havoc node1_~m1~0#1;assume { :end_inline_node1 } true;assume { :begin_inline_node2 } true;havoc node2_~m2~0#1;havoc node2_~m2~0#1;node2_~m2~0#1 := ~nomsg~0; 308#L123 assume !(0 != ~mode2~0 % 256);~p2_new~0 := (if (if ~send2~0 != ~nomsg~0 && ~p2_new~0 == ~nomsg~0 then ~send2~0 else ~p2_new~0) % 256 <= 127 then (if ~send2~0 != ~nomsg~0 && ~p2_new~0 == ~nomsg~0 then ~send2~0 else ~p2_new~0) % 256 else (if ~send2~0 != ~nomsg~0 && ~p2_new~0 == ~nomsg~0 then ~send2~0 else ~p2_new~0) % 256 - 256);~mode2~0 := 1; 310#L123-2 havoc node2_~m2~0#1;assume { :end_inline_node2 } true;assume { :begin_inline_node3 } true;havoc node3_~m3~0#1;havoc node3_~m3~0#1;node3_~m3~0#1 := ~nomsg~0; 320#L148 assume !(0 != ~mode3~0 % 256);~p3_new~0 := (if (if ~send3~0 != ~nomsg~0 && ~p3_new~0 == ~nomsg~0 then ~send3~0 else ~p3_new~0) % 256 <= 127 then (if ~send3~0 != ~nomsg~0 && ~p3_new~0 == ~nomsg~0 then ~send3~0 else ~p3_new~0) % 256 else (if ~send3~0 != ~nomsg~0 && ~p3_new~0 == ~nomsg~0 then ~send3~0 else ~p3_new~0) % 256 - 256);~mode3~0 := 1; 322#L148-2 havoc node3_~m3~0#1;assume { :end_inline_node3 } true;assume { :begin_inline_node4 } true;havoc node4_~m4~0#1;havoc node4_~m4~0#1;node4_~m4~0#1 := ~nomsg~0; 341#L173 assume !(0 != ~mode4~0 % 256);~p4_new~0 := (if (if ~send4~0 != ~nomsg~0 && ~p4_new~0 == ~nomsg~0 then ~send4~0 else ~p4_new~0) % 256 <= 127 then (if ~send4~0 != ~nomsg~0 && ~p4_new~0 == ~nomsg~0 then ~send4~0 else ~p4_new~0) % 256 else (if ~send4~0 != ~nomsg~0 && ~p4_new~0 == ~nomsg~0 then ~send4~0 else ~p4_new~0) % 256 - 256);~mode4~0 := 1; 315#L173-2 havoc node4_~m4~0#1;assume { :end_inline_node4 } true;assume { :begin_inline_node5 } true;havoc node5_~m5~0#1;havoc node5_~m5~0#1;node5_~m5~0#1 := ~nomsg~0; 381#L198 assume !(0 != ~mode5~0 % 256);~p5_new~0 := (if (if ~send5~0 != ~nomsg~0 && ~p5_new~0 == ~nomsg~0 then ~send5~0 else ~p5_new~0) % 256 <= 127 then (if ~send5~0 != ~nomsg~0 && ~p5_new~0 == ~nomsg~0 then ~send5~0 else ~p5_new~0) % 256 else (if ~send5~0 != ~nomsg~0 && ~p5_new~0 == ~nomsg~0 then ~send5~0 else ~p5_new~0) % 256 - 256);~mode5~0 := 1; 382#L198-2 havoc node5_~m5~0#1;assume { :end_inline_node5 } true;assume { :begin_inline_node6 } true;havoc node6_~m6~0#1;havoc node6_~m6~0#1;node6_~m6~0#1 := ~nomsg~0; 376#L223 assume !(0 != ~mode6~0 % 256);~p6_new~0 := (if (if ~send6~0 != ~nomsg~0 && ~p6_new~0 == ~nomsg~0 then ~send6~0 else ~p6_new~0) % 256 <= 127 then (if ~send6~0 != ~nomsg~0 && ~p6_new~0 == ~nomsg~0 then ~send6~0 else ~p6_new~0) % 256 else (if ~send6~0 != ~nomsg~0 && ~p6_new~0 == ~nomsg~0 then ~send6~0 else ~p6_new~0) % 256 - 256);~mode6~0 := 1; 344#L223-2 havoc node6_~m6~0#1;assume { :end_inline_node6 } true;assume { :begin_inline_node7 } true;havoc node7_~m7~0#1;havoc node7_~m7~0#1;node7_~m7~0#1 := ~nomsg~0; 363#L248 assume !(0 != ~mode7~0 % 256);~p7_new~0 := (if (if ~send7~0 != ~nomsg~0 && ~p7_new~0 == ~nomsg~0 then ~send7~0 else ~p7_new~0) % 256 <= 127 then (if ~send7~0 != ~nomsg~0 && ~p7_new~0 == ~nomsg~0 then ~send7~0 else ~p7_new~0) % 256 else (if ~send7~0 != ~nomsg~0 && ~p7_new~0 == ~nomsg~0 then ~send7~0 else ~p7_new~0) % 256 - 256);~mode7~0 := 1; 319#L248-2 havoc node7_~m7~0#1;assume { :end_inline_node7 } true;assume { :begin_inline_node8 } true;havoc node8_~m8~0#1;havoc node8_~m8~0#1;node8_~m8~0#1 := ~nomsg~0; 332#L273 assume !(0 != ~mode8~0 % 256);~p8_new~0 := (if (if ~send8~0 != ~nomsg~0 && ~p8_new~0 == ~nomsg~0 then ~send8~0 else ~p8_new~0) % 256 <= 127 then (if ~send8~0 != ~nomsg~0 && ~p8_new~0 == ~nomsg~0 then ~send8~0 else ~p8_new~0) % 256 else (if ~send8~0 != ~nomsg~0 && ~p8_new~0 == ~nomsg~0 then ~send8~0 else ~p8_new~0) % 256 - 256);~mode8~0 := 1; 342#L273-2 havoc node8_~m8~0#1;assume { :end_inline_node8 } true;~p1_old~0 := ~p1_new~0;~p1_new~0 := ~nomsg~0;~p2_old~0 := ~p2_new~0;~p2_new~0 := ~nomsg~0;~p3_old~0 := ~p3_new~0;~p3_new~0 := ~nomsg~0;~p4_old~0 := ~p4_new~0;~p4_new~0 := ~nomsg~0;~p5_old~0 := ~p5_new~0;~p5_new~0 := ~nomsg~0;~p6_old~0 := ~p6_new~0;~p6_new~0 := ~nomsg~0;~p7_old~0 := ~p7_new~0;~p7_new~0 := ~nomsg~0;~p8_old~0 := ~p8_new~0;~p8_new~0 := ~nomsg~0;assume { :begin_inline_check } true;havoc check_#res#1;havoc check_~tmp~1#1;havoc check_~tmp~1#1; 388#L553 assume !(~st1~0 + ~st2~0 + ~st3~0 + ~st4~0 + ~st5~0 + ~st6~0 + ~st7~0 + ~st8~0 <= 1);check_~tmp~1#1 := 0; 295#L553-1 check_#res#1 := check_~tmp~1#1; 304#check_returnLabel#1 main_#t~ret38#1 := check_#res#1;havoc check_~tmp~1#1;assume { :end_inline_check } true;main_~c1~0#1 := main_#t~ret38#1;havoc main_#t~ret38#1;assume { :begin_inline_assert } true;assert_#in~arg#1 := (if 0 == main_~c1~0#1 then 0 else 1);havoc assert_~arg#1;assert_~arg#1 := assert_#in~arg#1; 305#L673 assume !(0 == assert_~arg#1 % 256); 316#L668 havoc assert_~arg#1;havoc assert_#in~arg#1;assume { :end_inline_assert } true; 330#L635-2 [2024-11-08 18:53:47,197 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:53:47,203 INFO L85 PathProgramCache]: Analyzing trace with hash 354076320, now seen corresponding path program 1 times [2024-11-08 18:53:47,204 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 18:53:47,204 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [251262875] [2024-11-08 18:53:47,204 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:53:47,205 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 18:53:47,330 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:53:47,330 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 18:53:47,407 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:53:47,481 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 18:53:47,482 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:53:47,483 INFO L85 PathProgramCache]: Analyzing trace with hash -719911808, now seen corresponding path program 2 times [2024-11-08 18:53:47,483 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 18:53:47,484 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [698106572] [2024-11-08 18:53:47,484 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:53:47,484 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 18:53:47,627 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 18:53:48,009 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 18:53:48,010 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 18:53:48,011 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [698106572] [2024-11-08 18:53:48,011 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [698106572] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 18:53:48,012 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 18:53:48,014 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-08 18:53:48,014 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [316322133] [2024-11-08 18:53:48,014 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 18:53:48,015 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 18:53:48,015 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 18:53:48,016 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-08 18:53:48,017 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-08 18:53:48,017 INFO L87 Difference]: Start difference. First operand 127 states and 165 transitions. cyclomatic complexity: 39 Second operand has 5 states, 5 states have (on average 4.4) internal successors, (22), 5 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 18:53:48,078 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 18:53:48,079 INFO L93 Difference]: Finished difference Result 130 states and 167 transitions. [2024-11-08 18:53:48,079 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 130 states and 167 transitions. [2024-11-08 18:53:48,081 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 60 [2024-11-08 18:53:48,086 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 130 states to 127 states and 162 transitions. [2024-11-08 18:53:48,086 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 127 [2024-11-08 18:53:48,087 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 127 [2024-11-08 18:53:48,087 INFO L73 IsDeterministic]: Start isDeterministic. Operand 127 states and 162 transitions. [2024-11-08 18:53:48,090 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 18:53:48,091 INFO L218 hiAutomatonCegarLoop]: Abstraction has 127 states and 162 transitions. [2024-11-08 18:53:48,092 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 127 states and 162 transitions. [2024-11-08 18:53:48,100 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 127 to 127. [2024-11-08 18:53:48,101 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 127 states, 127 states have (on average 1.2755905511811023) internal successors, (162), 126 states have internal predecessors, (162), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 18:53:48,102 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 127 states to 127 states and 162 transitions. [2024-11-08 18:53:48,102 INFO L240 hiAutomatonCegarLoop]: Abstraction has 127 states and 162 transitions. [2024-11-08 18:53:48,103 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-08 18:53:48,104 INFO L425 stractBuchiCegarLoop]: Abstraction has 127 states and 162 transitions. [2024-11-08 18:53:48,104 INFO L332 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-11-08 18:53:48,104 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 127 states and 162 transitions. [2024-11-08 18:53:48,106 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 60 [2024-11-08 18:53:48,107 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 18:53:48,107 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 18:53:48,109 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 18:53:48,110 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 18:53:48,110 INFO L745 eck$LassoCheckResult]: Stem: 588#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(34, 2);call #Ultimate.allocInit(12, 3);~nomsg~0 := -1;~r1~0 := 0;~p1~0 := 0;~p1_old~0 := 0;~p1_new~0 := 0;~id1~0 := 0;~st1~0 := 0;~send1~0 := 0;~mode1~0 := 0;~p2~0 := 0;~p2_old~0 := 0;~p2_new~0 := 0;~id2~0 := 0;~st2~0 := 0;~send2~0 := 0;~mode2~0 := 0;~p3~0 := 0;~p3_old~0 := 0;~p3_new~0 := 0;~id3~0 := 0;~st3~0 := 0;~send3~0 := 0;~mode3~0 := 0;~p4~0 := 0;~p4_old~0 := 0;~p4_new~0 := 0;~id4~0 := 0;~st4~0 := 0;~send4~0 := 0;~mode4~0 := 0;~p5~0 := 0;~p5_old~0 := 0;~p5_new~0 := 0;~id5~0 := 0;~st5~0 := 0;~send5~0 := 0;~mode5~0 := 0;~p6~0 := 0;~p6_old~0 := 0;~p6_new~0 := 0;~id6~0 := 0;~st6~0 := 0;~send6~0 := 0;~mode6~0 := 0;~p7~0 := 0;~p7_old~0 := 0;~p7_new~0 := 0;~id7~0 := 0;~st7~0 := 0;~send7~0 := 0;~mode7~0 := 0;~p8~0 := 0;~p8_old~0 := 0;~p8_new~0 := 0;~id8~0 := 0;~st8~0 := 0;~send8~0 := 0;~mode8~0 := 0;~nodes~0.base, ~nodes~0.offset := ~nodes~0.base[0 := #funAddr~node1.base], ~nodes~0.offset[0 := #funAddr~node1.offset];~nodes~0.base, ~nodes~0.offset := ~nodes~0.base[1 := #funAddr~node2.base], ~nodes~0.offset[1 := #funAddr~node2.offset];~nodes~0.base, ~nodes~0.offset := ~nodes~0.base[2 := #funAddr~node3.base], ~nodes~0.offset[2 := #funAddr~node3.offset];~nodes~0.base, ~nodes~0.offset := ~nodes~0.base[3 := #funAddr~node4.base], ~nodes~0.offset[3 := #funAddr~node4.offset];~nodes~0.base, ~nodes~0.offset := ~nodes~0.base[4 := #funAddr~node5.base], ~nodes~0.offset[4 := #funAddr~node5.offset];~nodes~0.base, ~nodes~0.offset := ~nodes~0.base[5 := #funAddr~node6.base], ~nodes~0.offset[5 := #funAddr~node6.offset];~nodes~0.base, ~nodes~0.offset := ~nodes~0.base[6 := #funAddr~node7.base], ~nodes~0.offset[6 := #funAddr~node7.offset];~nodes~0.base, ~nodes~0.offset := ~nodes~0.base[7 := #funAddr~node8.base], ~nodes~0.offset[7 := #funAddr~node8.offset]; 589#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet4#1, main_#t~nondet5#1, main_#t~nondet6#1, main_#t~nondet7#1, main_#t~nondet8#1, main_#t~nondet9#1, main_#t~nondet10#1, main_#t~nondet11#1, main_#t~nondet12#1, main_#t~nondet13#1, main_#t~nondet14#1, main_#t~nondet15#1, main_#t~nondet16#1, main_#t~nondet17#1, main_#t~nondet18#1, main_#t~nondet19#1, main_#t~nondet20#1, main_#t~nondet21#1, main_#t~nondet22#1, main_#t~nondet23#1, main_#t~nondet24#1, main_#t~nondet25#1, main_#t~nondet26#1, main_#t~nondet27#1, main_#t~nondet28#1, main_#t~nondet29#1, main_#t~nondet30#1, main_#t~nondet31#1, main_#t~nondet32#1, main_#t~nondet33#1, main_#t~nondet34#1, main_#t~nondet35#1, main_#t~nondet36#1, main_#t~ret37#1, main_#t~ret38#1, main_~c1~0#1, main_~i2~0#1;havoc main_~c1~0#1;havoc main_~i2~0#1;main_~c1~0#1 := 0;havoc main_#t~nondet4#1;~r1~0 := main_#t~nondet4#1;havoc main_#t~nondet4#1;havoc main_#t~nondet5#1;~id1~0 := main_#t~nondet5#1;havoc main_#t~nondet5#1;havoc main_#t~nondet6#1;~st1~0 := main_#t~nondet6#1;havoc main_#t~nondet6#1;havoc main_#t~nondet7#1;~send1~0 := main_#t~nondet7#1;havoc main_#t~nondet7#1;havoc main_#t~nondet8#1;assume 0 == main_#t~nondet8#1 || 1 == main_#t~nondet8#1;~mode1~0 := (if 0 == main_#t~nondet8#1 % 256 then 0 else 1);havoc main_#t~nondet8#1;havoc main_#t~nondet9#1;~id2~0 := main_#t~nondet9#1;havoc main_#t~nondet9#1;havoc main_#t~nondet10#1;~st2~0 := main_#t~nondet10#1;havoc main_#t~nondet10#1;havoc main_#t~nondet11#1;~send2~0 := main_#t~nondet11#1;havoc main_#t~nondet11#1;havoc main_#t~nondet12#1;assume 0 == main_#t~nondet12#1 || 1 == main_#t~nondet12#1;~mode2~0 := (if 0 == main_#t~nondet12#1 % 256 then 0 else 1);havoc main_#t~nondet12#1;havoc main_#t~nondet13#1;~id3~0 := main_#t~nondet13#1;havoc main_#t~nondet13#1;havoc main_#t~nondet14#1;~st3~0 := main_#t~nondet14#1;havoc main_#t~nondet14#1;havoc main_#t~nondet15#1;~send3~0 := main_#t~nondet15#1;havoc main_#t~nondet15#1;havoc main_#t~nondet16#1;assume 0 == main_#t~nondet16#1 || 1 == main_#t~nondet16#1;~mode3~0 := (if 0 == main_#t~nondet16#1 % 256 then 0 else 1);havoc main_#t~nondet16#1;havoc main_#t~nondet17#1;~id4~0 := main_#t~nondet17#1;havoc main_#t~nondet17#1;havoc main_#t~nondet18#1;~st4~0 := main_#t~nondet18#1;havoc main_#t~nondet18#1;havoc main_#t~nondet19#1;~send4~0 := main_#t~nondet19#1;havoc main_#t~nondet19#1;havoc main_#t~nondet20#1;assume 0 == main_#t~nondet20#1 || 1 == main_#t~nondet20#1;~mode4~0 := (if 0 == main_#t~nondet20#1 % 256 then 0 else 1);havoc main_#t~nondet20#1;havoc main_#t~nondet21#1;~id5~0 := main_#t~nondet21#1;havoc main_#t~nondet21#1;havoc main_#t~nondet22#1;~st5~0 := main_#t~nondet22#1;havoc main_#t~nondet22#1;havoc main_#t~nondet23#1;~send5~0 := main_#t~nondet23#1;havoc main_#t~nondet23#1;havoc main_#t~nondet24#1;assume 0 == main_#t~nondet24#1 || 1 == main_#t~nondet24#1;~mode5~0 := (if 0 == main_#t~nondet24#1 % 256 then 0 else 1);havoc main_#t~nondet24#1;havoc main_#t~nondet25#1;~id6~0 := main_#t~nondet25#1;havoc main_#t~nondet25#1;havoc main_#t~nondet26#1;~st6~0 := main_#t~nondet26#1;havoc main_#t~nondet26#1;havoc main_#t~nondet27#1;~send6~0 := main_#t~nondet27#1;havoc main_#t~nondet27#1;havoc main_#t~nondet28#1;assume 0 == main_#t~nondet28#1 || 1 == main_#t~nondet28#1;~mode6~0 := (if 0 == main_#t~nondet28#1 % 256 then 0 else 1);havoc main_#t~nondet28#1;havoc main_#t~nondet29#1;~id7~0 := main_#t~nondet29#1;havoc main_#t~nondet29#1;havoc main_#t~nondet30#1;~st7~0 := main_#t~nondet30#1;havoc main_#t~nondet30#1;havoc main_#t~nondet31#1;~send7~0 := main_#t~nondet31#1;havoc main_#t~nondet31#1;havoc main_#t~nondet32#1;assume 0 == main_#t~nondet32#1 || 1 == main_#t~nondet32#1;~mode7~0 := (if 0 == main_#t~nondet32#1 % 256 then 0 else 1);havoc main_#t~nondet32#1;havoc main_#t~nondet33#1;~id8~0 := main_#t~nondet33#1;havoc main_#t~nondet33#1;havoc main_#t~nondet34#1;~st8~0 := main_#t~nondet34#1;havoc main_#t~nondet34#1;havoc main_#t~nondet35#1;~send8~0 := main_#t~nondet35#1;havoc main_#t~nondet35#1;havoc main_#t~nondet36#1;assume 0 == main_#t~nondet36#1 || 1 == main_#t~nondet36#1;~mode8~0 := (if 0 == main_#t~nondet36#1 % 256 then 0 else 1);havoc main_#t~nondet36#1;assume { :begin_inline_init } true;havoc init_#res#1;havoc init_~tmp~0#1;havoc init_~tmp~0#1; 608#L300 assume 0 == (if ~r1~0 % 256 % 4294967296 <= 2147483647 then ~r1~0 % 256 % 4294967296 else ~r1~0 % 256 % 4294967296 - 4294967296); 642#L301 assume ~id1~0 >= 0; 657#L302 assume 0 == ~st1~0; 658#L303 assume ~send1~0 == ~id1~0; 664#L304 assume 0 == (if ~mode1~0 % 256 % 4294967296 <= 2147483647 then ~mode1~0 % 256 % 4294967296 else ~mode1~0 % 256 % 4294967296 - 4294967296); 634#L305 assume ~id2~0 >= 0; 635#L306 assume 0 == ~st2~0; 652#L307 assume ~send2~0 == ~id2~0; 557#L308 assume 0 == (if ~mode2~0 % 256 % 4294967296 <= 2147483647 then ~mode2~0 % 256 % 4294967296 else ~mode2~0 % 256 % 4294967296 - 4294967296); 558#L309 assume ~id3~0 >= 0; 648#L310 assume 0 == ~st3~0; 621#L311 assume ~send3~0 == ~id3~0; 622#L312 assume 0 == (if ~mode3~0 % 256 % 4294967296 <= 2147483647 then ~mode3~0 % 256 % 4294967296 else ~mode3~0 % 256 % 4294967296 - 4294967296); 578#L313 assume ~id4~0 >= 0; 579#L314 assume 0 == ~st4~0; 612#L315 assume ~send4~0 == ~id4~0; 613#L316 assume 0 == (if ~mode4~0 % 256 % 4294967296 <= 2147483647 then ~mode4~0 % 256 % 4294967296 else ~mode4~0 % 256 % 4294967296 - 4294967296); 550#L317 assume ~id5~0 >= 0; 551#L318 assume 0 == ~st5~0; 668#L319 assume ~send5~0 == ~id5~0; 656#L320 assume 0 == (if ~mode5~0 % 256 % 4294967296 <= 2147483647 then ~mode5~0 % 256 % 4294967296 else ~mode5~0 % 256 % 4294967296 - 4294967296); 639#L321 assume ~id6~0 >= 0; 640#L322 assume 0 == ~st6~0; 548#L323 assume ~send6~0 == ~id6~0; 549#L324 assume 0 == (if ~mode6~0 % 256 % 4294967296 <= 2147483647 then ~mode6~0 % 256 % 4294967296 else ~mode6~0 % 256 % 4294967296 - 4294967296); 564#L325 assume ~id7~0 >= 0; 583#L326 assume 0 == ~st7~0; 571#L327 assume ~send7~0 == ~id7~0; 572#L328 assume 0 == (if ~mode7~0 % 256 % 4294967296 <= 2147483647 then ~mode7~0 % 256 % 4294967296 else ~mode7~0 % 256 % 4294967296 - 4294967296); 598#L329 assume ~id8~0 >= 0; 599#L330 assume 0 == ~st8~0; 552#L331 assume ~send8~0 == ~id8~0; 553#L332 assume 0 == (if ~mode8~0 % 256 % 4294967296 <= 2147483647 then ~mode8~0 % 256 % 4294967296 else ~mode8~0 % 256 % 4294967296 - 4294967296); 582#L333 assume ~id1~0 != ~id2~0; 596#L334 assume ~id1~0 != ~id3~0; 576#L335 assume ~id1~0 != ~id4~0; 577#L336 assume ~id1~0 != ~id5~0; 651#L337 assume ~id1~0 != ~id6~0; 625#L338 assume ~id1~0 != ~id7~0; 626#L339 assume ~id1~0 != ~id8~0; 666#L340 assume ~id2~0 != ~id3~0; 661#L341 assume ~id2~0 != ~id4~0; 600#L342 assume ~id2~0 != ~id5~0; 601#L343 assume ~id2~0 != ~id6~0; 590#L344 assume ~id2~0 != ~id7~0; 591#L345 assume ~id2~0 != ~id8~0; 616#L346 assume ~id3~0 != ~id4~0; 617#L347 assume ~id3~0 != ~id5~0; 667#L348 assume ~id3~0 != ~id6~0; 659#L349 assume ~id3~0 != ~id7~0; 660#L350 assume ~id3~0 != ~id8~0; 643#L351 assume ~id4~0 != ~id5~0; 644#L352 assume ~id4~0 != ~id6~0; 663#L353 assume ~id4~0 != ~id7~0; 632#L354 assume ~id4~0 != ~id8~0; 602#L355 assume ~id5~0 != ~id6~0; 603#L356 assume ~id5~0 != ~id7~0; 629#L357 assume ~id5~0 != ~id8~0; 562#L358 assume ~id6~0 != ~id7~0; 563#L359 assume ~id6~0 != ~id8~0; 565#L360 assume ~id7~0 != ~id8~0;init_~tmp~0#1 := 1; 566#L300-1 init_#res#1 := init_~tmp~0#1; 620#init_returnLabel#1 main_#t~ret37#1 := init_#res#1;havoc init_~tmp~0#1;assume { :end_inline_init } true;main_~i2~0#1 := main_#t~ret37#1;havoc main_#t~ret37#1;assume { :begin_inline_assume_abort_if_not } true;assume_abort_if_not_#in~cond#1 := main_~i2~0#1;havoc assume_abort_if_not_~cond#1;assume_abort_if_not_~cond#1 := assume_abort_if_not_#in~cond#1; 610#L22 assume !(0 == assume_abort_if_not_~cond#1); 611#L21 havoc assume_abort_if_not_~cond#1;havoc assume_abort_if_not_#in~cond#1;assume { :end_inline_assume_abort_if_not } true;~p1_old~0 := ~nomsg~0;~p1_new~0 := ~nomsg~0;~p2_old~0 := ~nomsg~0;~p2_new~0 := ~nomsg~0;~p3_old~0 := ~nomsg~0;~p3_new~0 := ~nomsg~0;~p4_old~0 := ~nomsg~0;~p4_new~0 := ~nomsg~0;~p5_old~0 := ~nomsg~0;~p5_new~0 := ~nomsg~0;~p6_old~0 := ~nomsg~0;~p6_new~0 := ~nomsg~0;~p7_old~0 := ~nomsg~0;~p7_new~0 := ~nomsg~0;~p8_old~0 := ~nomsg~0;~p8_new~0 := ~nomsg~0;main_~i2~0#1 := 0; 595#L635-2 [2024-11-08 18:53:48,111 INFO L747 eck$LassoCheckResult]: Loop: 595#L635-2 assume !false;assume { :begin_inline_node1 } true;havoc node1_~m1~0#1;havoc node1_~m1~0#1;node1_~m1~0#1 := ~nomsg~0; 627#L92 assume !(0 != ~mode1~0 % 256);~p1_new~0 := (if (if ~send1~0 != ~nomsg~0 && ~p1_new~0 == ~nomsg~0 then ~send1~0 else ~p1_new~0) % 256 <= 127 then (if ~send1~0 != ~nomsg~0 && ~p1_new~0 == ~nomsg~0 then ~send1~0 else ~p1_new~0) % 256 else (if ~send1~0 != ~nomsg~0 && ~p1_new~0 == ~nomsg~0 then ~send1~0 else ~p1_new~0) % 256 - 256);~mode1~0 := 1; 619#L92-2 havoc node1_~m1~0#1;assume { :end_inline_node1 } true;assume { :begin_inline_node2 } true;havoc node2_~m2~0#1;havoc node2_~m2~0#1;node2_~m2~0#1 := ~nomsg~0; 573#L123 assume !(0 != ~mode2~0 % 256);~p2_new~0 := (if (if ~send2~0 != ~nomsg~0 && ~p2_new~0 == ~nomsg~0 then ~send2~0 else ~p2_new~0) % 256 <= 127 then (if ~send2~0 != ~nomsg~0 && ~p2_new~0 == ~nomsg~0 then ~send2~0 else ~p2_new~0) % 256 else (if ~send2~0 != ~nomsg~0 && ~p2_new~0 == ~nomsg~0 then ~send2~0 else ~p2_new~0) % 256 - 256);~mode2~0 := 1; 575#L123-2 havoc node2_~m2~0#1;assume { :end_inline_node2 } true;assume { :begin_inline_node3 } true;havoc node3_~m3~0#1;havoc node3_~m3~0#1;node3_~m3~0#1 := ~nomsg~0; 585#L148 assume !(0 != ~mode3~0 % 256);~p3_new~0 := (if (if ~send3~0 != ~nomsg~0 && ~p3_new~0 == ~nomsg~0 then ~send3~0 else ~p3_new~0) % 256 <= 127 then (if ~send3~0 != ~nomsg~0 && ~p3_new~0 == ~nomsg~0 then ~send3~0 else ~p3_new~0) % 256 else (if ~send3~0 != ~nomsg~0 && ~p3_new~0 == ~nomsg~0 then ~send3~0 else ~p3_new~0) % 256 - 256);~mode3~0 := 1; 587#L148-2 havoc node3_~m3~0#1;assume { :end_inline_node3 } true;assume { :begin_inline_node4 } true;havoc node4_~m4~0#1;havoc node4_~m4~0#1;node4_~m4~0#1 := ~nomsg~0; 606#L173 assume !(0 != ~mode4~0 % 256);~p4_new~0 := (if (if ~send4~0 != ~nomsg~0 && ~p4_new~0 == ~nomsg~0 then ~send4~0 else ~p4_new~0) % 256 <= 127 then (if ~send4~0 != ~nomsg~0 && ~p4_new~0 == ~nomsg~0 then ~send4~0 else ~p4_new~0) % 256 else (if ~send4~0 != ~nomsg~0 && ~p4_new~0 == ~nomsg~0 then ~send4~0 else ~p4_new~0) % 256 - 256);~mode4~0 := 1; 580#L173-2 havoc node4_~m4~0#1;assume { :end_inline_node4 } true;assume { :begin_inline_node5 } true;havoc node5_~m5~0#1;havoc node5_~m5~0#1;node5_~m5~0#1 := ~nomsg~0; 646#L198 assume !(0 != ~mode5~0 % 256);~p5_new~0 := (if (if ~send5~0 != ~nomsg~0 && ~p5_new~0 == ~nomsg~0 then ~send5~0 else ~p5_new~0) % 256 <= 127 then (if ~send5~0 != ~nomsg~0 && ~p5_new~0 == ~nomsg~0 then ~send5~0 else ~p5_new~0) % 256 else (if ~send5~0 != ~nomsg~0 && ~p5_new~0 == ~nomsg~0 then ~send5~0 else ~p5_new~0) % 256 - 256);~mode5~0 := 1; 647#L198-2 havoc node5_~m5~0#1;assume { :end_inline_node5 } true;assume { :begin_inline_node6 } true;havoc node6_~m6~0#1;havoc node6_~m6~0#1;node6_~m6~0#1 := ~nomsg~0; 641#L223 assume !(0 != ~mode6~0 % 256);~p6_new~0 := (if (if ~send6~0 != ~nomsg~0 && ~p6_new~0 == ~nomsg~0 then ~send6~0 else ~p6_new~0) % 256 <= 127 then (if ~send6~0 != ~nomsg~0 && ~p6_new~0 == ~nomsg~0 then ~send6~0 else ~p6_new~0) % 256 else (if ~send6~0 != ~nomsg~0 && ~p6_new~0 == ~nomsg~0 then ~send6~0 else ~p6_new~0) % 256 - 256);~mode6~0 := 1; 609#L223-2 havoc node6_~m6~0#1;assume { :end_inline_node6 } true;assume { :begin_inline_node7 } true;havoc node7_~m7~0#1;havoc node7_~m7~0#1;node7_~m7~0#1 := ~nomsg~0; 628#L248 assume !(0 != ~mode7~0 % 256);~p7_new~0 := (if (if ~send7~0 != ~nomsg~0 && ~p7_new~0 == ~nomsg~0 then ~send7~0 else ~p7_new~0) % 256 <= 127 then (if ~send7~0 != ~nomsg~0 && ~p7_new~0 == ~nomsg~0 then ~send7~0 else ~p7_new~0) % 256 else (if ~send7~0 != ~nomsg~0 && ~p7_new~0 == ~nomsg~0 then ~send7~0 else ~p7_new~0) % 256 - 256);~mode7~0 := 1; 584#L248-2 havoc node7_~m7~0#1;assume { :end_inline_node7 } true;assume { :begin_inline_node8 } true;havoc node8_~m8~0#1;havoc node8_~m8~0#1;node8_~m8~0#1 := ~nomsg~0; 597#L273 assume !(0 != ~mode8~0 % 256);~p8_new~0 := (if (if ~send8~0 != ~nomsg~0 && ~p8_new~0 == ~nomsg~0 then ~send8~0 else ~p8_new~0) % 256 <= 127 then (if ~send8~0 != ~nomsg~0 && ~p8_new~0 == ~nomsg~0 then ~send8~0 else ~p8_new~0) % 256 else (if ~send8~0 != ~nomsg~0 && ~p8_new~0 == ~nomsg~0 then ~send8~0 else ~p8_new~0) % 256 - 256);~mode8~0 := 1; 607#L273-2 havoc node8_~m8~0#1;assume { :end_inline_node8 } true;~p1_old~0 := ~p1_new~0;~p1_new~0 := ~nomsg~0;~p2_old~0 := ~p2_new~0;~p2_new~0 := ~nomsg~0;~p3_old~0 := ~p3_new~0;~p3_new~0 := ~nomsg~0;~p4_old~0 := ~p4_new~0;~p4_new~0 := ~nomsg~0;~p5_old~0 := ~p5_new~0;~p5_new~0 := ~nomsg~0;~p6_old~0 := ~p6_new~0;~p6_new~0 := ~nomsg~0;~p7_old~0 := ~p7_new~0;~p7_new~0 := ~nomsg~0;~p8_old~0 := ~p8_new~0;~p8_new~0 := ~nomsg~0;assume { :begin_inline_check } true;havoc check_#res#1;havoc check_~tmp~1#1;havoc check_~tmp~1#1; 653#L553 assume ~st1~0 + ~st2~0 + ~st3~0 + ~st4~0 + ~st5~0 + ~st6~0 + ~st7~0 + ~st8~0 <= 1; 654#L554 assume (if ~r1~0 % 256 % 4294967296 <= 2147483647 then ~r1~0 % 256 % 4294967296 else ~r1~0 % 256 % 4294967296 - 4294967296) >= 8; 559#$Ultimate##298 assume (if ~r1~0 % 256 % 4294967296 <= 2147483647 then ~r1~0 % 256 % 4294967296 else ~r1~0 % 256 % 4294967296 - 4294967296) < 8;check_~tmp~1#1 := 1; 560#L553-1 check_#res#1 := check_~tmp~1#1; 569#check_returnLabel#1 main_#t~ret38#1 := check_#res#1;havoc check_~tmp~1#1;assume { :end_inline_check } true;main_~c1~0#1 := main_#t~ret38#1;havoc main_#t~ret38#1;assume { :begin_inline_assert } true;assert_#in~arg#1 := (if 0 == main_~c1~0#1 then 0 else 1);havoc assert_~arg#1;assert_~arg#1 := assert_#in~arg#1; 570#L673 assume !(0 == assert_~arg#1 % 256); 581#L668 havoc assert_~arg#1;havoc assert_#in~arg#1;assume { :end_inline_assert } true; 595#L635-2 [2024-11-08 18:53:48,112 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:53:48,113 INFO L85 PathProgramCache]: Analyzing trace with hash 354076320, now seen corresponding path program 2 times [2024-11-08 18:53:48,113 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 18:53:48,113 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1583946399] [2024-11-08 18:53:48,114 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:53:48,114 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 18:53:48,216 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:53:48,217 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 18:53:48,277 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:53:48,319 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 18:53:48,320 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:53:48,320 INFO L85 PathProgramCache]: Analyzing trace with hash -1761385584, now seen corresponding path program 1 times [2024-11-08 18:53:48,321 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 18:53:48,321 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [202376067] [2024-11-08 18:53:48,321 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:53:48,322 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 18:53:48,344 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 18:53:48,404 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 18:53:48,405 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 18:53:48,405 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [202376067] [2024-11-08 18:53:48,405 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [202376067] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 18:53:48,405 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 18:53:48,405 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 18:53:48,406 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2123599074] [2024-11-08 18:53:48,406 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 18:53:48,406 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 18:53:48,407 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 18:53:48,407 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 18:53:48,409 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 18:53:48,410 INFO L87 Difference]: Start difference. First operand 127 states and 162 transitions. cyclomatic complexity: 36 Second operand has 3 states, 3 states have (on average 8.0) internal successors, (24), 3 states have internal predecessors, (24), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 18:53:48,484 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 18:53:48,484 INFO L93 Difference]: Finished difference Result 181 states and 246 transitions. [2024-11-08 18:53:48,484 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 181 states and 246 transitions. [2024-11-08 18:53:48,486 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 114 [2024-11-08 18:53:48,491 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 181 states to 181 states and 246 transitions. [2024-11-08 18:53:48,494 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 181 [2024-11-08 18:53:48,494 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 181 [2024-11-08 18:53:48,495 INFO L73 IsDeterministic]: Start isDeterministic. Operand 181 states and 246 transitions. [2024-11-08 18:53:48,496 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 18:53:48,499 INFO L218 hiAutomatonCegarLoop]: Abstraction has 181 states and 246 transitions. [2024-11-08 18:53:48,500 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 181 states and 246 transitions. [2024-11-08 18:53:48,509 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 181 to 179. [2024-11-08 18:53:48,510 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 179 states, 179 states have (on average 1.3575418994413408) internal successors, (243), 178 states have internal predecessors, (243), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 18:53:48,511 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 179 states to 179 states and 243 transitions. [2024-11-08 18:53:48,512 INFO L240 hiAutomatonCegarLoop]: Abstraction has 179 states and 243 transitions. [2024-11-08 18:53:48,512 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 18:53:48,513 INFO L425 stractBuchiCegarLoop]: Abstraction has 179 states and 243 transitions. [2024-11-08 18:53:48,514 INFO L332 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-11-08 18:53:48,514 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 179 states and 243 transitions. [2024-11-08 18:53:48,516 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 112 [2024-11-08 18:53:48,516 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 18:53:48,516 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 18:53:48,519 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 18:53:48,519 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 18:53:48,519 INFO L745 eck$LassoCheckResult]: Stem: 901#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(34, 2);call #Ultimate.allocInit(12, 3);~nomsg~0 := -1;~r1~0 := 0;~p1~0 := 0;~p1_old~0 := 0;~p1_new~0 := 0;~id1~0 := 0;~st1~0 := 0;~send1~0 := 0;~mode1~0 := 0;~p2~0 := 0;~p2_old~0 := 0;~p2_new~0 := 0;~id2~0 := 0;~st2~0 := 0;~send2~0 := 0;~mode2~0 := 0;~p3~0 := 0;~p3_old~0 := 0;~p3_new~0 := 0;~id3~0 := 0;~st3~0 := 0;~send3~0 := 0;~mode3~0 := 0;~p4~0 := 0;~p4_old~0 := 0;~p4_new~0 := 0;~id4~0 := 0;~st4~0 := 0;~send4~0 := 0;~mode4~0 := 0;~p5~0 := 0;~p5_old~0 := 0;~p5_new~0 := 0;~id5~0 := 0;~st5~0 := 0;~send5~0 := 0;~mode5~0 := 0;~p6~0 := 0;~p6_old~0 := 0;~p6_new~0 := 0;~id6~0 := 0;~st6~0 := 0;~send6~0 := 0;~mode6~0 := 0;~p7~0 := 0;~p7_old~0 := 0;~p7_new~0 := 0;~id7~0 := 0;~st7~0 := 0;~send7~0 := 0;~mode7~0 := 0;~p8~0 := 0;~p8_old~0 := 0;~p8_new~0 := 0;~id8~0 := 0;~st8~0 := 0;~send8~0 := 0;~mode8~0 := 0;~nodes~0.base, ~nodes~0.offset := ~nodes~0.base[0 := #funAddr~node1.base], ~nodes~0.offset[0 := #funAddr~node1.offset];~nodes~0.base, ~nodes~0.offset := ~nodes~0.base[1 := #funAddr~node2.base], ~nodes~0.offset[1 := #funAddr~node2.offset];~nodes~0.base, ~nodes~0.offset := ~nodes~0.base[2 := #funAddr~node3.base], ~nodes~0.offset[2 := #funAddr~node3.offset];~nodes~0.base, ~nodes~0.offset := ~nodes~0.base[3 := #funAddr~node4.base], ~nodes~0.offset[3 := #funAddr~node4.offset];~nodes~0.base, ~nodes~0.offset := ~nodes~0.base[4 := #funAddr~node5.base], ~nodes~0.offset[4 := #funAddr~node5.offset];~nodes~0.base, ~nodes~0.offset := ~nodes~0.base[5 := #funAddr~node6.base], ~nodes~0.offset[5 := #funAddr~node6.offset];~nodes~0.base, ~nodes~0.offset := ~nodes~0.base[6 := #funAddr~node7.base], ~nodes~0.offset[6 := #funAddr~node7.offset];~nodes~0.base, ~nodes~0.offset := ~nodes~0.base[7 := #funAddr~node8.base], ~nodes~0.offset[7 := #funAddr~node8.offset]; 902#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet4#1, main_#t~nondet5#1, main_#t~nondet6#1, main_#t~nondet7#1, main_#t~nondet8#1, main_#t~nondet9#1, main_#t~nondet10#1, main_#t~nondet11#1, main_#t~nondet12#1, main_#t~nondet13#1, main_#t~nondet14#1, main_#t~nondet15#1, main_#t~nondet16#1, main_#t~nondet17#1, main_#t~nondet18#1, main_#t~nondet19#1, main_#t~nondet20#1, main_#t~nondet21#1, main_#t~nondet22#1, main_#t~nondet23#1, main_#t~nondet24#1, main_#t~nondet25#1, main_#t~nondet26#1, main_#t~nondet27#1, main_#t~nondet28#1, main_#t~nondet29#1, main_#t~nondet30#1, main_#t~nondet31#1, main_#t~nondet32#1, main_#t~nondet33#1, main_#t~nondet34#1, main_#t~nondet35#1, main_#t~nondet36#1, main_#t~ret37#1, main_#t~ret38#1, main_~c1~0#1, main_~i2~0#1;havoc main_~c1~0#1;havoc main_~i2~0#1;main_~c1~0#1 := 0;havoc main_#t~nondet4#1;~r1~0 := main_#t~nondet4#1;havoc main_#t~nondet4#1;havoc main_#t~nondet5#1;~id1~0 := main_#t~nondet5#1;havoc main_#t~nondet5#1;havoc main_#t~nondet6#1;~st1~0 := main_#t~nondet6#1;havoc main_#t~nondet6#1;havoc main_#t~nondet7#1;~send1~0 := main_#t~nondet7#1;havoc main_#t~nondet7#1;havoc main_#t~nondet8#1;assume 0 == main_#t~nondet8#1 || 1 == main_#t~nondet8#1;~mode1~0 := (if 0 == main_#t~nondet8#1 % 256 then 0 else 1);havoc main_#t~nondet8#1;havoc main_#t~nondet9#1;~id2~0 := main_#t~nondet9#1;havoc main_#t~nondet9#1;havoc main_#t~nondet10#1;~st2~0 := main_#t~nondet10#1;havoc main_#t~nondet10#1;havoc main_#t~nondet11#1;~send2~0 := main_#t~nondet11#1;havoc main_#t~nondet11#1;havoc main_#t~nondet12#1;assume 0 == main_#t~nondet12#1 || 1 == main_#t~nondet12#1;~mode2~0 := (if 0 == main_#t~nondet12#1 % 256 then 0 else 1);havoc main_#t~nondet12#1;havoc main_#t~nondet13#1;~id3~0 := main_#t~nondet13#1;havoc main_#t~nondet13#1;havoc main_#t~nondet14#1;~st3~0 := main_#t~nondet14#1;havoc main_#t~nondet14#1;havoc main_#t~nondet15#1;~send3~0 := main_#t~nondet15#1;havoc main_#t~nondet15#1;havoc main_#t~nondet16#1;assume 0 == main_#t~nondet16#1 || 1 == main_#t~nondet16#1;~mode3~0 := (if 0 == main_#t~nondet16#1 % 256 then 0 else 1);havoc main_#t~nondet16#1;havoc main_#t~nondet17#1;~id4~0 := main_#t~nondet17#1;havoc main_#t~nondet17#1;havoc main_#t~nondet18#1;~st4~0 := main_#t~nondet18#1;havoc main_#t~nondet18#1;havoc main_#t~nondet19#1;~send4~0 := main_#t~nondet19#1;havoc main_#t~nondet19#1;havoc main_#t~nondet20#1;assume 0 == main_#t~nondet20#1 || 1 == main_#t~nondet20#1;~mode4~0 := (if 0 == main_#t~nondet20#1 % 256 then 0 else 1);havoc main_#t~nondet20#1;havoc main_#t~nondet21#1;~id5~0 := main_#t~nondet21#1;havoc main_#t~nondet21#1;havoc main_#t~nondet22#1;~st5~0 := main_#t~nondet22#1;havoc main_#t~nondet22#1;havoc main_#t~nondet23#1;~send5~0 := main_#t~nondet23#1;havoc main_#t~nondet23#1;havoc main_#t~nondet24#1;assume 0 == main_#t~nondet24#1 || 1 == main_#t~nondet24#1;~mode5~0 := (if 0 == main_#t~nondet24#1 % 256 then 0 else 1);havoc main_#t~nondet24#1;havoc main_#t~nondet25#1;~id6~0 := main_#t~nondet25#1;havoc main_#t~nondet25#1;havoc main_#t~nondet26#1;~st6~0 := main_#t~nondet26#1;havoc main_#t~nondet26#1;havoc main_#t~nondet27#1;~send6~0 := main_#t~nondet27#1;havoc main_#t~nondet27#1;havoc main_#t~nondet28#1;assume 0 == main_#t~nondet28#1 || 1 == main_#t~nondet28#1;~mode6~0 := (if 0 == main_#t~nondet28#1 % 256 then 0 else 1);havoc main_#t~nondet28#1;havoc main_#t~nondet29#1;~id7~0 := main_#t~nondet29#1;havoc main_#t~nondet29#1;havoc main_#t~nondet30#1;~st7~0 := main_#t~nondet30#1;havoc main_#t~nondet30#1;havoc main_#t~nondet31#1;~send7~0 := main_#t~nondet31#1;havoc main_#t~nondet31#1;havoc main_#t~nondet32#1;assume 0 == main_#t~nondet32#1 || 1 == main_#t~nondet32#1;~mode7~0 := (if 0 == main_#t~nondet32#1 % 256 then 0 else 1);havoc main_#t~nondet32#1;havoc main_#t~nondet33#1;~id8~0 := main_#t~nondet33#1;havoc main_#t~nondet33#1;havoc main_#t~nondet34#1;~st8~0 := main_#t~nondet34#1;havoc main_#t~nondet34#1;havoc main_#t~nondet35#1;~send8~0 := main_#t~nondet35#1;havoc main_#t~nondet35#1;havoc main_#t~nondet36#1;assume 0 == main_#t~nondet36#1 || 1 == main_#t~nondet36#1;~mode8~0 := (if 0 == main_#t~nondet36#1 % 256 then 0 else 1);havoc main_#t~nondet36#1;assume { :begin_inline_init } true;havoc init_#res#1;havoc init_~tmp~0#1;havoc init_~tmp~0#1; 921#L300 assume 0 == (if ~r1~0 % 256 % 4294967296 <= 2147483647 then ~r1~0 % 256 % 4294967296 else ~r1~0 % 256 % 4294967296 - 4294967296); 956#L301 assume ~id1~0 >= 0; 973#L302 assume 0 == ~st1~0; 974#L303 assume ~send1~0 == ~id1~0; 982#L304 assume 0 == (if ~mode1~0 % 256 % 4294967296 <= 2147483647 then ~mode1~0 % 256 % 4294967296 else ~mode1~0 % 256 % 4294967296 - 4294967296); 948#L305 assume ~id2~0 >= 0; 949#L306 assume 0 == ~st2~0; 966#L307 assume ~send2~0 == ~id2~0; 871#L308 assume 0 == (if ~mode2~0 % 256 % 4294967296 <= 2147483647 then ~mode2~0 % 256 % 4294967296 else ~mode2~0 % 256 % 4294967296 - 4294967296); 872#L309 assume ~id3~0 >= 0; 962#L310 assume 0 == ~st3~0; 934#L311 assume ~send3~0 == ~id3~0; 935#L312 assume 0 == (if ~mode3~0 % 256 % 4294967296 <= 2147483647 then ~mode3~0 % 256 % 4294967296 else ~mode3~0 % 256 % 4294967296 - 4294967296); 891#L313 assume ~id4~0 >= 0; 892#L314 assume 0 == ~st4~0; 927#L315 assume ~send4~0 == ~id4~0; 928#L316 assume 0 == (if ~mode4~0 % 256 % 4294967296 <= 2147483647 then ~mode4~0 % 256 % 4294967296 else ~mode4~0 % 256 % 4294967296 - 4294967296); 864#L317 assume ~id5~0 >= 0; 865#L318 assume 0 == ~st5~0; 985#L319 assume ~send5~0 == ~id5~0; 972#L320 assume 0 == (if ~mode5~0 % 256 % 4294967296 <= 2147483647 then ~mode5~0 % 256 % 4294967296 else ~mode5~0 % 256 % 4294967296 - 4294967296); 953#L321 assume ~id6~0 >= 0; 954#L322 assume 0 == ~st6~0; 862#L323 assume ~send6~0 == ~id6~0; 863#L324 assume 0 == (if ~mode6~0 % 256 % 4294967296 <= 2147483647 then ~mode6~0 % 256 % 4294967296 else ~mode6~0 % 256 % 4294967296 - 4294967296); 877#L325 assume ~id7~0 >= 0; 896#L326 assume 0 == ~st7~0; 884#L327 assume ~send7~0 == ~id7~0; 885#L328 assume 0 == (if ~mode7~0 % 256 % 4294967296 <= 2147483647 then ~mode7~0 % 256 % 4294967296 else ~mode7~0 % 256 % 4294967296 - 4294967296); 911#L329 assume ~id8~0 >= 0; 912#L330 assume 0 == ~st8~0; 866#L331 assume ~send8~0 == ~id8~0; 867#L332 assume 0 == (if ~mode8~0 % 256 % 4294967296 <= 2147483647 then ~mode8~0 % 256 % 4294967296 else ~mode8~0 % 256 % 4294967296 - 4294967296); 895#L333 assume ~id1~0 != ~id2~0; 909#L334 assume ~id1~0 != ~id3~0; 889#L335 assume ~id1~0 != ~id4~0; 890#L336 assume ~id1~0 != ~id5~0; 965#L337 assume ~id1~0 != ~id6~0; 939#L338 assume ~id1~0 != ~id7~0; 940#L339 assume ~id1~0 != ~id8~0; 983#L340 assume ~id2~0 != ~id3~0; 977#L341 assume ~id2~0 != ~id4~0; 913#L342 assume ~id2~0 != ~id5~0; 914#L343 assume ~id2~0 != ~id6~0; 903#L344 assume ~id2~0 != ~id7~0; 904#L345 assume ~id2~0 != ~id8~0; 929#L346 assume ~id3~0 != ~id4~0; 930#L347 assume ~id3~0 != ~id5~0; 984#L348 assume ~id3~0 != ~id6~0; 975#L349 assume ~id3~0 != ~id7~0; 976#L350 assume ~id3~0 != ~id8~0; 957#L351 assume ~id4~0 != ~id5~0; 958#L352 assume ~id4~0 != ~id6~0; 979#L353 assume ~id4~0 != ~id7~0; 945#L354 assume ~id4~0 != ~id8~0; 917#L355 assume ~id5~0 != ~id6~0; 918#L356 assume ~id5~0 != ~id7~0; 942#L357 assume ~id5~0 != ~id8~0; 875#L358 assume ~id6~0 != ~id7~0; 876#L359 assume ~id6~0 != ~id8~0; 878#L360 assume ~id7~0 != ~id8~0;init_~tmp~0#1 := 1; 879#L300-1 init_#res#1 := init_~tmp~0#1; 933#init_returnLabel#1 main_#t~ret37#1 := init_#res#1;havoc init_~tmp~0#1;assume { :end_inline_init } true;main_~i2~0#1 := main_#t~ret37#1;havoc main_#t~ret37#1;assume { :begin_inline_assume_abort_if_not } true;assume_abort_if_not_#in~cond#1 := main_~i2~0#1;havoc assume_abort_if_not_~cond#1;assume_abort_if_not_~cond#1 := assume_abort_if_not_#in~cond#1; 923#L22 assume !(0 == assume_abort_if_not_~cond#1); 924#L21 havoc assume_abort_if_not_~cond#1;havoc assume_abort_if_not_#in~cond#1;assume { :end_inline_assume_abort_if_not } true;~p1_old~0 := ~nomsg~0;~p1_new~0 := ~nomsg~0;~p2_old~0 := ~nomsg~0;~p2_new~0 := ~nomsg~0;~p3_old~0 := ~nomsg~0;~p3_new~0 := ~nomsg~0;~p4_old~0 := ~nomsg~0;~p4_new~0 := ~nomsg~0;~p5_old~0 := ~nomsg~0;~p5_new~0 := ~nomsg~0;~p6_old~0 := ~nomsg~0;~p6_new~0 := ~nomsg~0;~p7_old~0 := ~nomsg~0;~p7_new~0 := ~nomsg~0;~p8_old~0 := ~nomsg~0;~p8_new~0 := ~nomsg~0;main_~i2~0#1 := 0; 980#L635-2 [2024-11-08 18:53:48,520 INFO L747 eck$LassoCheckResult]: Loop: 980#L635-2 assume !false;assume { :begin_inline_node1 } true;havoc node1_~m1~0#1;havoc node1_~m1~0#1;node1_~m1~0#1 := ~nomsg~0; 1031#L92 assume !(0 != ~mode1~0 % 256);~p1_new~0 := (if (if ~send1~0 != ~nomsg~0 && ~p1_new~0 == ~nomsg~0 then ~send1~0 else ~p1_new~0) % 256 <= 127 then (if ~send1~0 != ~nomsg~0 && ~p1_new~0 == ~nomsg~0 then ~send1~0 else ~p1_new~0) % 256 else (if ~send1~0 != ~nomsg~0 && ~p1_new~0 == ~nomsg~0 then ~send1~0 else ~p1_new~0) % 256 - 256);~mode1~0 := 1; 932#L92-2 havoc node1_~m1~0#1;assume { :end_inline_node1 } true;assume { :begin_inline_node2 } true;havoc node2_~m2~0#1;havoc node2_~m2~0#1;node2_~m2~0#1 := ~nomsg~0; 1027#L123 assume !(0 != ~mode2~0 % 256);~p2_new~0 := (if (if ~send2~0 != ~nomsg~0 && ~p2_new~0 == ~nomsg~0 then ~send2~0 else ~p2_new~0) % 256 <= 127 then (if ~send2~0 != ~nomsg~0 && ~p2_new~0 == ~nomsg~0 then ~send2~0 else ~p2_new~0) % 256 else (if ~send2~0 != ~nomsg~0 && ~p2_new~0 == ~nomsg~0 then ~send2~0 else ~p2_new~0) % 256 - 256);~mode2~0 := 1; 1023#L123-2 havoc node2_~m2~0#1;assume { :end_inline_node2 } true;assume { :begin_inline_node3 } true;havoc node3_~m3~0#1;havoc node3_~m3~0#1;node3_~m3~0#1 := ~nomsg~0; 1021#L148 assume !(0 != ~mode3~0 % 256);~p3_new~0 := (if (if ~send3~0 != ~nomsg~0 && ~p3_new~0 == ~nomsg~0 then ~send3~0 else ~p3_new~0) % 256 <= 127 then (if ~send3~0 != ~nomsg~0 && ~p3_new~0 == ~nomsg~0 then ~send3~0 else ~p3_new~0) % 256 else (if ~send3~0 != ~nomsg~0 && ~p3_new~0 == ~nomsg~0 then ~send3~0 else ~p3_new~0) % 256 - 256);~mode3~0 := 1; 1017#L148-2 havoc node3_~m3~0#1;assume { :end_inline_node3 } true;assume { :begin_inline_node4 } true;havoc node4_~m4~0#1;havoc node4_~m4~0#1;node4_~m4~0#1 := ~nomsg~0; 1015#L173 assume !(0 != ~mode4~0 % 256);~p4_new~0 := (if (if ~send4~0 != ~nomsg~0 && ~p4_new~0 == ~nomsg~0 then ~send4~0 else ~p4_new~0) % 256 <= 127 then (if ~send4~0 != ~nomsg~0 && ~p4_new~0 == ~nomsg~0 then ~send4~0 else ~p4_new~0) % 256 else (if ~send4~0 != ~nomsg~0 && ~p4_new~0 == ~nomsg~0 then ~send4~0 else ~p4_new~0) % 256 - 256);~mode4~0 := 1; 988#L173-2 havoc node4_~m4~0#1;assume { :end_inline_node4 } true;assume { :begin_inline_node5 } true;havoc node5_~m5~0#1;havoc node5_~m5~0#1;node5_~m5~0#1 := ~nomsg~0; 960#L198 assume !(0 != ~mode5~0 % 256);~p5_new~0 := (if (if ~send5~0 != ~nomsg~0 && ~p5_new~0 == ~nomsg~0 then ~send5~0 else ~p5_new~0) % 256 <= 127 then (if ~send5~0 != ~nomsg~0 && ~p5_new~0 == ~nomsg~0 then ~send5~0 else ~p5_new~0) % 256 else (if ~send5~0 != ~nomsg~0 && ~p5_new~0 == ~nomsg~0 then ~send5~0 else ~p5_new~0) % 256 - 256);~mode5~0 := 1; 961#L198-2 havoc node5_~m5~0#1;assume { :end_inline_node5 } true;assume { :begin_inline_node6 } true;havoc node6_~m6~0#1;havoc node6_~m6~0#1;node6_~m6~0#1 := ~nomsg~0; 967#L223 assume !(0 != ~mode6~0 % 256);~p6_new~0 := (if (if ~send6~0 != ~nomsg~0 && ~p6_new~0 == ~nomsg~0 then ~send6~0 else ~p6_new~0) % 256 <= 127 then (if ~send6~0 != ~nomsg~0 && ~p6_new~0 == ~nomsg~0 then ~send6~0 else ~p6_new~0) % 256 else (if ~send6~0 != ~nomsg~0 && ~p6_new~0 == ~nomsg~0 then ~send6~0 else ~p6_new~0) % 256 - 256);~mode6~0 := 1; 1001#L223-2 havoc node6_~m6~0#1;assume { :end_inline_node6 } true;assume { :begin_inline_node7 } true;havoc node7_~m7~0#1;havoc node7_~m7~0#1;node7_~m7~0#1 := ~nomsg~0; 999#L248 assume !(0 != ~mode7~0 % 256);~p7_new~0 := (if (if ~send7~0 != ~nomsg~0 && ~p7_new~0 == ~nomsg~0 then ~send7~0 else ~p7_new~0) % 256 <= 127 then (if ~send7~0 != ~nomsg~0 && ~p7_new~0 == ~nomsg~0 then ~send7~0 else ~p7_new~0) % 256 else (if ~send7~0 != ~nomsg~0 && ~p7_new~0 == ~nomsg~0 then ~send7~0 else ~p7_new~0) % 256 - 256);~mode7~0 := 1; 995#L248-2 havoc node7_~m7~0#1;assume { :end_inline_node7 } true;assume { :begin_inline_node8 } true;havoc node8_~m8~0#1;havoc node8_~m8~0#1;node8_~m8~0#1 := ~nomsg~0; 993#L273 assume !(0 != ~mode8~0 % 256);~p8_new~0 := (if (if ~send8~0 != ~nomsg~0 && ~p8_new~0 == ~nomsg~0 then ~send8~0 else ~p8_new~0) % 256 <= 127 then (if ~send8~0 != ~nomsg~0 && ~p8_new~0 == ~nomsg~0 then ~send8~0 else ~p8_new~0) % 256 else (if ~send8~0 != ~nomsg~0 && ~p8_new~0 == ~nomsg~0 then ~send8~0 else ~p8_new~0) % 256 - 256);~mode8~0 := 1; 991#L273-2 havoc node8_~m8~0#1;assume { :end_inline_node8 } true;~p1_old~0 := ~p1_new~0;~p1_new~0 := ~nomsg~0;~p2_old~0 := ~p2_new~0;~p2_new~0 := ~nomsg~0;~p3_old~0 := ~p3_new~0;~p3_new~0 := ~nomsg~0;~p4_old~0 := ~p4_new~0;~p4_new~0 := ~nomsg~0;~p5_old~0 := ~p5_new~0;~p5_new~0 := ~nomsg~0;~p6_old~0 := ~p6_new~0;~p6_new~0 := ~nomsg~0;~p7_old~0 := ~p7_new~0;~p7_new~0 := ~nomsg~0;~p8_old~0 := ~p8_new~0;~p8_new~0 := ~nomsg~0;assume { :begin_inline_check } true;havoc check_#res#1;havoc check_~tmp~1#1;havoc check_~tmp~1#1; 990#L553 assume ~st1~0 + ~st2~0 + ~st3~0 + ~st4~0 + ~st5~0 + ~st6~0 + ~st7~0 + ~st8~0 <= 1; 989#L554 assume !((if ~r1~0 % 256 % 4294967296 <= 2147483647 then ~r1~0 % 256 % 4294967296 else ~r1~0 % 256 % 4294967296 - 4294967296) >= 8); 986#L557 assume 0 == ~st1~0 + ~st2~0 + ~st3~0 + ~st4~0 + ~st5~0 + ~st6~0 + ~st7~0 + ~st8~0; 987#$Ultimate##298 assume (if ~r1~0 % 256 % 4294967296 <= 2147483647 then ~r1~0 % 256 % 4294967296 else ~r1~0 % 256 % 4294967296 - 4294967296) < 8;check_~tmp~1#1 := 1; 1035#L553-1 check_#res#1 := check_~tmp~1#1; 1034#check_returnLabel#1 main_#t~ret38#1 := check_#res#1;havoc check_~tmp~1#1;assume { :end_inline_check } true;main_~c1~0#1 := main_#t~ret38#1;havoc main_#t~ret38#1;assume { :begin_inline_assert } true;assert_#in~arg#1 := (if 0 == main_~c1~0#1 then 0 else 1);havoc assert_~arg#1;assert_~arg#1 := assert_#in~arg#1; 1033#L673 assume !(0 == assert_~arg#1 % 256); 1032#L668 havoc assert_~arg#1;havoc assert_#in~arg#1;assume { :end_inline_assert } true; 980#L635-2 [2024-11-08 18:53:48,521 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:53:48,521 INFO L85 PathProgramCache]: Analyzing trace with hash 354076320, now seen corresponding path program 3 times [2024-11-08 18:53:48,521 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 18:53:48,522 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1403154352] [2024-11-08 18:53:48,522 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:53:48,522 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 18:53:48,614 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:53:48,614 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 18:53:48,664 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:53:48,700 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 18:53:48,701 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:53:48,701 INFO L85 PathProgramCache]: Analyzing trace with hash -1416775258, now seen corresponding path program 1 times [2024-11-08 18:53:48,701 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 18:53:48,701 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [721277002] [2024-11-08 18:53:48,702 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:53:48,702 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 18:53:48,782 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:53:48,783 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 18:53:48,899 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:53:48,906 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 18:53:48,906 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:53:48,907 INFO L85 PathProgramCache]: Analyzing trace with hash -470264857, now seen corresponding path program 1 times [2024-11-08 18:53:48,907 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 18:53:48,907 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [700801214] [2024-11-08 18:53:48,908 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:53:48,908 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 18:53:49,037 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:53:49,038 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 18:53:49,142 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:53:49,186 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 18:53:58,888 INFO L204 LassoAnalysis]: Preferences: [2024-11-08 18:53:58,889 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-11-08 18:53:58,889 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-11-08 18:53:58,889 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-11-08 18:53:58,889 INFO L128 ssoRankerPreferences]: Use exernal solver: true [2024-11-08 18:53:58,890 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 18:53:58,890 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-11-08 18:53:58,890 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-11-08 18:53:58,890 INFO L132 ssoRankerPreferences]: Filename of dumped script: pals_lcr.8.1.ufo.UNBOUNDED.pals.c_Iteration4_Loop [2024-11-08 18:53:58,890 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-11-08 18:53:58,891 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-11-08 18:53:58,969 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:53:58,986 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:53:58,991 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:53:58,994 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:53:58,999 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:53:59,004 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:53:59,012 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:53:59,016 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:53:59,021 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:53:59,025 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:53:59,029 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:53:59,039 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:53:59,044 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:53:59,049 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:53:59,056 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:53:59,065 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:53:59,070 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:53:59,074 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:54:04,645 WARN L286 SmtUtils]: Spent 5.55s on a formula simplification. DAG size of input: 353 DAG size of output: 197 (called from [L 270] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.mapelimination.MapEliminator.setFormulaAndSimplify) [2024-11-08 18:54:04,646 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:54:04,651 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:54:04,656 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:54:04,666 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:54:04,670 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:54:04,674 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:54:04,685 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:54:04,689 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:54:04,694 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:54:04,699 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:54:04,705 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:54:04,710 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:54:04,715 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:54:04,721 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:54:04,726 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:54:04,735 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:54:04,744 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:54:04,749 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:54:04,753 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:54:04,757 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:54:04,761 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:54:04,768 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:54:10,419 WARN L286 SmtUtils]: Spent 5.36s on a formula simplification. DAG size of input: 469 DAG size of output: 399 (called from [L 68] de.uni_freiburg.informatik.ultimate.icfgtransformer.transformulatransformers.SimplifyPreprocessor.process) [2024-11-08 18:54:10,722 WARN L137 XnfTransformerHelper]: expecting exponential blowup for input size 48