./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/loop-invgen/string_concat-noarr.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version a0165632 Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8264667-cc34-41ae-a2e3-109642306c6c/bin/uautomizer-verify-jihMAELWvX/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8264667-cc34-41ae-a2e3-109642306c6c/bin/uautomizer-verify-jihMAELWvX/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8264667-cc34-41ae-a2e3-109642306c6c/bin/uautomizer-verify-jihMAELWvX/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8264667-cc34-41ae-a2e3-109642306c6c/bin/uautomizer-verify-jihMAELWvX/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/loop-invgen/string_concat-noarr.i -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8264667-cc34-41ae-a2e3-109642306c6c/bin/uautomizer-verify-jihMAELWvX/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8264667-cc34-41ae-a2e3-109642306c6c/bin/uautomizer-verify-jihMAELWvX --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 30a4b942034eaa47a8fcc8fdf4549d1d63a9a60d59b585da2a353c9626604750 --- Real Ultimate output --- This is Ultimate 0.2.5-dev-a016563 [2024-11-08 18:04:56,548 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-08 18:04:56,651 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8264667-cc34-41ae-a2e3-109642306c6c/bin/uautomizer-verify-jihMAELWvX/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-11-08 18:04:56,655 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-08 18:04:56,656 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-08 18:04:56,680 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-08 18:04:56,680 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-08 18:04:56,681 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-08 18:04:56,681 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-08 18:04:56,682 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-08 18:04:56,683 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-08 18:04:56,683 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-08 18:04:56,684 INFO L153 SettingsManager]: * Use SBE=true [2024-11-08 18:04:56,684 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-11-08 18:04:56,684 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-11-08 18:04:56,685 INFO L153 SettingsManager]: * Use old map elimination=false [2024-11-08 18:04:56,685 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-11-08 18:04:56,686 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-11-08 18:04:56,690 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-11-08 18:04:56,690 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-08 18:04:56,690 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-11-08 18:04:56,691 INFO L153 SettingsManager]: * sizeof long=4 [2024-11-08 18:04:56,691 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-08 18:04:56,692 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-11-08 18:04:56,692 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-08 18:04:56,692 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-11-08 18:04:56,693 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-11-08 18:04:56,693 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-11-08 18:04:56,693 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-11-08 18:04:56,694 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-11-08 18:04:56,698 INFO L153 SettingsManager]: * sizeof long double=12 [2024-11-08 18:04:56,698 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-08 18:04:56,699 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-11-08 18:04:56,699 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-08 18:04:56,699 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-11-08 18:04:56,700 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-08 18:04:56,700 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-08 18:04:56,700 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-11-08 18:04:56,701 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-11-08 18:04:56,702 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8264667-cc34-41ae-a2e3-109642306c6c/bin/uautomizer-verify-jihMAELWvX/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8264667-cc34-41ae-a2e3-109642306c6c/bin/uautomizer-verify-jihMAELWvX Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 30a4b942034eaa47a8fcc8fdf4549d1d63a9a60d59b585da2a353c9626604750 [2024-11-08 18:04:56,986 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-08 18:04:57,011 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-08 18:04:57,016 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-08 18:04:57,018 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-08 18:04:57,018 INFO L274 PluginConnector]: CDTParser initialized [2024-11-08 18:04:57,020 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8264667-cc34-41ae-a2e3-109642306c6c/bin/uautomizer-verify-jihMAELWvX/../../sv-benchmarks/c/loop-invgen/string_concat-noarr.i Unable to find full path for "g++" [2024-11-08 18:04:59,095 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-11-08 18:04:59,281 INFO L384 CDTParser]: Found 1 translation units. [2024-11-08 18:04:59,285 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8264667-cc34-41ae-a2e3-109642306c6c/sv-benchmarks/c/loop-invgen/string_concat-noarr.i [2024-11-08 18:04:59,297 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8264667-cc34-41ae-a2e3-109642306c6c/bin/uautomizer-verify-jihMAELWvX/data/6a3005366/6fa5e4e2b3864892b2e7562ded4fab89/FLAG98c5be681 [2024-11-08 18:04:59,671 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8264667-cc34-41ae-a2e3-109642306c6c/bin/uautomizer-verify-jihMAELWvX/data/6a3005366/6fa5e4e2b3864892b2e7562ded4fab89 [2024-11-08 18:04:59,674 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-08 18:04:59,675 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-08 18:04:59,676 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-08 18:04:59,676 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-08 18:04:59,683 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-08 18:04:59,684 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 08.11 06:04:59" (1/1) ... [2024-11-08 18:04:59,687 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@7e2f7709 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 06:04:59, skipping insertion in model container [2024-11-08 18:04:59,687 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 08.11 06:04:59" (1/1) ... [2024-11-08 18:04:59,714 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-08 18:04:59,965 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-08 18:04:59,981 INFO L200 MainTranslator]: Completed pre-run [2024-11-08 18:05:00,000 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-08 18:05:00,020 INFO L204 MainTranslator]: Completed translation [2024-11-08 18:05:00,021 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 06:05:00 WrapperNode [2024-11-08 18:05:00,021 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-08 18:05:00,023 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-08 18:05:00,023 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-08 18:05:00,023 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-08 18:05:00,031 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 06:05:00" (1/1) ... [2024-11-08 18:05:00,038 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 06:05:00" (1/1) ... [2024-11-08 18:05:00,055 INFO L138 Inliner]: procedures = 16, calls = 8, calls flagged for inlining = 4, calls inlined = 4, statements flattened = 52 [2024-11-08 18:05:00,056 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-08 18:05:00,056 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-08 18:05:00,057 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-08 18:05:00,057 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-08 18:05:00,068 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 06:05:00" (1/1) ... [2024-11-08 18:05:00,069 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 06:05:00" (1/1) ... [2024-11-08 18:05:00,070 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 06:05:00" (1/1) ... [2024-11-08 18:05:00,085 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-11-08 18:05:00,087 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 06:05:00" (1/1) ... [2024-11-08 18:05:00,088 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 06:05:00" (1/1) ... [2024-11-08 18:05:00,090 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 06:05:00" (1/1) ... [2024-11-08 18:05:00,094 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 06:05:00" (1/1) ... [2024-11-08 18:05:00,097 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 06:05:00" (1/1) ... [2024-11-08 18:05:00,098 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 06:05:00" (1/1) ... [2024-11-08 18:05:00,100 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-08 18:05:00,101 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-11-08 18:05:00,101 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-11-08 18:05:00,105 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-11-08 18:05:00,106 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 06:05:00" (1/1) ... [2024-11-08 18:05:00,113 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 18:05:00,125 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8264667-cc34-41ae-a2e3-109642306c6c/bin/uautomizer-verify-jihMAELWvX/z3 [2024-11-08 18:05:00,140 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8264667-cc34-41ae-a2e3-109642306c6c/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 18:05:00,144 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8264667-cc34-41ae-a2e3-109642306c6c/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-11-08 18:05:00,173 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-08 18:05:00,173 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-11-08 18:05:00,173 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-08 18:05:00,173 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-08 18:05:00,242 INFO L238 CfgBuilder]: Building ICFG [2024-11-08 18:05:00,244 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-08 18:05:00,351 INFO L? ?]: Removed 9 outVars from TransFormulas that were not future-live. [2024-11-08 18:05:00,352 INFO L287 CfgBuilder]: Performing block encoding [2024-11-08 18:05:00,364 INFO L311 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-08 18:05:00,364 INFO L316 CfgBuilder]: Removed 2 assume(true) statements. [2024-11-08 18:05:00,364 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 08.11 06:05:00 BoogieIcfgContainer [2024-11-08 18:05:00,365 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-11-08 18:05:00,366 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-11-08 18:05:00,366 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-11-08 18:05:00,370 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-11-08 18:05:00,371 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-08 18:05:00,371 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 08.11 06:04:59" (1/3) ... [2024-11-08 18:05:00,372 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@2b85f6be and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 08.11 06:05:00, skipping insertion in model container [2024-11-08 18:05:00,372 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-08 18:05:00,372 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 06:05:00" (2/3) ... [2024-11-08 18:05:00,373 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@2b85f6be and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 08.11 06:05:00, skipping insertion in model container [2024-11-08 18:05:00,373 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-08 18:05:00,373 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 08.11 06:05:00" (3/3) ... [2024-11-08 18:05:00,375 INFO L332 chiAutomizerObserver]: Analyzing ICFG string_concat-noarr.i [2024-11-08 18:05:00,430 INFO L300 stractBuchiCegarLoop]: Interprodecural is true [2024-11-08 18:05:00,430 INFO L301 stractBuchiCegarLoop]: Hoare is None [2024-11-08 18:05:00,430 INFO L302 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-11-08 18:05:00,431 INFO L303 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-11-08 18:05:00,431 INFO L304 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-11-08 18:05:00,431 INFO L305 stractBuchiCegarLoop]: Difference is false [2024-11-08 18:05:00,431 INFO L306 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-11-08 18:05:00,431 INFO L310 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-11-08 18:05:00,436 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 18 states, 17 states have (on average 1.4705882352941178) internal successors, (25), 17 states have internal predecessors, (25), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 18:05:00,454 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 5 [2024-11-08 18:05:00,455 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 18:05:00,455 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 18:05:00,460 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1] [2024-11-08 18:05:00,461 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2024-11-08 18:05:00,461 INFO L332 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-11-08 18:05:00,461 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 18 states, 17 states have (on average 1.4705882352941178) internal successors, (25), 17 states have internal predecessors, (25), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 18:05:00,463 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 5 [2024-11-08 18:05:00,463 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 18:05:00,463 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 18:05:00,464 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1] [2024-11-08 18:05:00,464 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2024-11-08 18:05:00,471 INFO L745 eck$LassoCheckResult]: Stem: 13#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 6#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~post2#1, main_#t~nondet3#1, main_#t~post4#1, main_#t~post5#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 5#L26true main_~i~0#1 := 0; 16#L29-2true [2024-11-08 18:05:00,472 INFO L747 eck$LassoCheckResult]: Loop: 16#L29-2true havoc main_#t~nondet1#1; 4#L29true assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 16#L29-2true [2024-11-08 18:05:00,478 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:05:00,478 INFO L85 PathProgramCache]: Analyzing trace with hash 29857, now seen corresponding path program 1 times [2024-11-08 18:05:00,488 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 18:05:00,488 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1529617353] [2024-11-08 18:05:00,489 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:05:00,489 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 18:05:00,581 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:05:00,582 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 18:05:00,594 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:05:00,614 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 18:05:00,617 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:05:00,618 INFO L85 PathProgramCache]: Analyzing trace with hash 1222, now seen corresponding path program 1 times [2024-11-08 18:05:00,618 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 18:05:00,618 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [501992441] [2024-11-08 18:05:00,618 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:05:00,619 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 18:05:00,629 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:05:00,629 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 18:05:00,633 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:05:00,635 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 18:05:00,636 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:05:00,637 INFO L85 PathProgramCache]: Analyzing trace with hash 28692838, now seen corresponding path program 1 times [2024-11-08 18:05:00,637 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 18:05:00,637 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1085921853] [2024-11-08 18:05:00,637 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:05:00,638 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 18:05:00,656 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:05:00,658 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 18:05:00,669 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:05:00,675 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 18:05:00,764 INFO L204 LassoAnalysis]: Preferences: [2024-11-08 18:05:00,765 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-11-08 18:05:00,765 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-11-08 18:05:00,765 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-11-08 18:05:00,766 INFO L128 ssoRankerPreferences]: Use exernal solver: true [2024-11-08 18:05:00,766 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 18:05:00,766 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-11-08 18:05:00,766 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-11-08 18:05:00,766 INFO L132 ssoRankerPreferences]: Filename of dumped script: string_concat-noarr.i_Iteration1_Loop [2024-11-08 18:05:00,766 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-11-08 18:05:00,767 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-11-08 18:05:00,782 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:05:00,799 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:05:00,807 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:05:00,860 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-11-08 18:05:00,864 INFO L365 LassoAnalysis]: Checking for nontermination... [2024-11-08 18:05:00,867 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 18:05:00,867 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8264667-cc34-41ae-a2e3-109642306c6c/bin/uautomizer-verify-jihMAELWvX/z3 [2024-11-08 18:05:00,871 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8264667-cc34-41ae-a2e3-109642306c6c/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 18:05:00,873 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8264667-cc34-41ae-a2e3-109642306c6c/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2024-11-08 18:05:00,874 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-08 18:05:00,874 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-08 18:05:00,900 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8264667-cc34-41ae-a2e3-109642306c6c/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Ended with exit code 0 [2024-11-08 18:05:00,901 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 18:05:00,902 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8264667-cc34-41ae-a2e3-109642306c6c/bin/uautomizer-verify-jihMAELWvX/z3 [2024-11-08 18:05:00,903 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8264667-cc34-41ae-a2e3-109642306c6c/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 18:05:00,904 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8264667-cc34-41ae-a2e3-109642306c6c/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2024-11-08 18:05:00,905 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2024-11-08 18:05:00,905 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-08 18:05:00,939 INFO L405 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2024-11-08 18:05:00,943 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8264667-cc34-41ae-a2e3-109642306c6c/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Forceful destruction successful, exit code 0 [2024-11-08 18:05:00,943 INFO L204 LassoAnalysis]: Preferences: [2024-11-08 18:05:00,944 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-11-08 18:05:00,944 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-11-08 18:05:00,944 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-11-08 18:05:00,944 INFO L128 ssoRankerPreferences]: Use exernal solver: false [2024-11-08 18:05:00,944 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 18:05:00,944 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-11-08 18:05:00,944 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-11-08 18:05:00,944 INFO L132 ssoRankerPreferences]: Filename of dumped script: string_concat-noarr.i_Iteration1_Loop [2024-11-08 18:05:00,945 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-11-08 18:05:00,945 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-11-08 18:05:00,946 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:05:00,959 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:05:00,965 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 18:05:01,006 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-11-08 18:05:01,011 INFO L451 LassoAnalysis]: Using template 'affine'. [2024-11-08 18:05:01,013 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 18:05:01,013 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8264667-cc34-41ae-a2e3-109642306c6c/bin/uautomizer-verify-jihMAELWvX/z3 [2024-11-08 18:05:01,015 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8264667-cc34-41ae-a2e3-109642306c6c/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 18:05:01,017 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8264667-cc34-41ae-a2e3-109642306c6c/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2024-11-08 18:05:01,018 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-08 18:05:01,033 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-08 18:05:01,034 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-08 18:05:01,034 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-08 18:05:01,034 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-08 18:05:01,035 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-08 18:05:01,042 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-08 18:05:01,042 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-08 18:05:01,050 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2024-11-08 18:05:01,056 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2024-11-08 18:05:01,056 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2024-11-08 18:05:01,058 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 18:05:01,058 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8264667-cc34-41ae-a2e3-109642306c6c/bin/uautomizer-verify-jihMAELWvX/z3 [2024-11-08 18:05:01,062 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8264667-cc34-41ae-a2e3-109642306c6c/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 18:05:01,075 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8264667-cc34-41ae-a2e3-109642306c6c/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2024-11-08 18:05:01,075 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2024-11-08 18:05:01,075 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2024-11-08 18:05:01,076 INFO L474 LassoAnalysis]: Proved termination. [2024-11-08 18:05:01,077 INFO L476 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~i~0#1) = -2*ULTIMATE.start_main_~i~0#1 + 1999999 Supporting invariants [] [2024-11-08 18:05:01,094 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8264667-cc34-41ae-a2e3-109642306c6c/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Ended with exit code 0 [2024-11-08 18:05:01,099 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2024-11-08 18:05:01,133 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:05:01,168 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 18:05:01,172 INFO L255 TraceCheckSpWp]: Trace formula consists of 20 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-11-08 18:05:01,173 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-08 18:05:01,195 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 18:05:01,197 WARN L253 TraceCheckSpWp]: Trace formula consists of 7 conjuncts, 4 conjuncts are in the unsatisfiable core [2024-11-08 18:05:01,197 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-08 18:05:01,207 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 18:05:01,248 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 1 loop predicates [2024-11-08 18:05:01,250 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand has 18 states, 17 states have (on average 1.4705882352941178) internal successors, (25), 17 states have internal predecessors, (25), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 1.6666666666666667) internal successors, (5), 3 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 18:05:01,318 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand has 18 states, 17 states have (on average 1.4705882352941178) internal successors, (25), 17 states have internal predecessors, (25), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0). Second operand has 3 states, 3 states have (on average 1.6666666666666667) internal successors, (5), 3 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 41 states and 58 transitions. Complement of second has 6 states. [2024-11-08 18:05:01,321 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 4 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2024-11-08 18:05:01,327 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 1.6666666666666667) internal successors, (5), 3 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 18:05:01,332 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 34 transitions. [2024-11-08 18:05:01,335 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 34 transitions. Stem has 3 letters. Loop has 2 letters. [2024-11-08 18:05:01,336 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-08 18:05:01,336 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 34 transitions. Stem has 5 letters. Loop has 2 letters. [2024-11-08 18:05:01,336 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-08 18:05:01,336 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 34 transitions. Stem has 3 letters. Loop has 4 letters. [2024-11-08 18:05:01,337 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-08 18:05:01,337 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 41 states and 58 transitions. [2024-11-08 18:05:01,342 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2 [2024-11-08 18:05:01,345 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 41 states to 18 states and 23 transitions. [2024-11-08 18:05:01,346 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10 [2024-11-08 18:05:01,346 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12 [2024-11-08 18:05:01,347 INFO L73 IsDeterministic]: Start isDeterministic. Operand 18 states and 23 transitions. [2024-11-08 18:05:01,347 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-08 18:05:01,347 INFO L218 hiAutomatonCegarLoop]: Abstraction has 18 states and 23 transitions. [2024-11-08 18:05:01,361 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18 states and 23 transitions. [2024-11-08 18:05:01,367 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18 to 16. [2024-11-08 18:05:01,368 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16 states, 16 states have (on average 1.3125) internal successors, (21), 15 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 18:05:01,368 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16 states to 16 states and 21 transitions. [2024-11-08 18:05:01,370 INFO L240 hiAutomatonCegarLoop]: Abstraction has 16 states and 21 transitions. [2024-11-08 18:05:01,370 INFO L425 stractBuchiCegarLoop]: Abstraction has 16 states and 21 transitions. [2024-11-08 18:05:01,370 INFO L332 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-11-08 18:05:01,370 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 16 states and 21 transitions. [2024-11-08 18:05:01,371 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2024-11-08 18:05:01,371 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 18:05:01,371 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 18:05:01,372 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1] [2024-11-08 18:05:01,372 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2024-11-08 18:05:01,372 INFO L745 eck$LassoCheckResult]: Stem: 102#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 103#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~post2#1, main_#t~nondet3#1, main_#t~post4#1, main_#t~post5#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 109#L26 main_~i~0#1 := 0; 110#L29-2 havoc main_#t~nondet1#1; 104#L29 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 97#L29-3 assume main_~i~0#1 >= 100; 98#L32 [2024-11-08 18:05:01,372 INFO L747 eck$LassoCheckResult]: Loop: 98#L32 assume true; 98#L32 [2024-11-08 18:05:01,373 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:05:01,373 INFO L85 PathProgramCache]: Analyzing trace with hash 889477935, now seen corresponding path program 1 times [2024-11-08 18:05:01,373 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 18:05:01,374 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1280029628] [2024-11-08 18:05:01,374 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:05:01,374 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 18:05:01,382 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 18:05:01,436 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 18:05:01,436 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 18:05:01,437 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1280029628] [2024-11-08 18:05:01,437 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1280029628] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 18:05:01,438 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 18:05:01,438 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-08 18:05:01,438 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1811021501] [2024-11-08 18:05:01,439 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 18:05:01,441 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 18:05:01,442 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:05:01,442 INFO L85 PathProgramCache]: Analyzing trace with hash 91, now seen corresponding path program 1 times [2024-11-08 18:05:01,442 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 18:05:01,442 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1363108062] [2024-11-08 18:05:01,443 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:05:01,443 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 18:05:01,446 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:05:01,446 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 18:05:01,447 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:05:01,447 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 18:05:01,451 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 18:05:01,453 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 18:05:01,454 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 18:05:01,455 INFO L87 Difference]: Start difference. First operand 16 states and 21 transitions. cyclomatic complexity: 8 Second operand has 3 states, 2 states have (on average 3.0) internal successors, (6), 3 states have internal predecessors, (6), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 18:05:01,481 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 18:05:01,481 INFO L93 Difference]: Finished difference Result 26 states and 32 transitions. [2024-11-08 18:05:01,482 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 26 states and 32 transitions. [2024-11-08 18:05:01,484 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2 [2024-11-08 18:05:01,485 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 26 states to 26 states and 32 transitions. [2024-11-08 18:05:01,485 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16 [2024-11-08 18:05:01,486 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 16 [2024-11-08 18:05:01,487 INFO L73 IsDeterministic]: Start isDeterministic. Operand 26 states and 32 transitions. [2024-11-08 18:05:01,487 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-08 18:05:01,487 INFO L218 hiAutomatonCegarLoop]: Abstraction has 26 states and 32 transitions. [2024-11-08 18:05:01,487 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26 states and 32 transitions. [2024-11-08 18:05:01,489 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26 to 18. [2024-11-08 18:05:01,490 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 18 states, 18 states have (on average 1.2777777777777777) internal successors, (23), 17 states have internal predecessors, (23), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 18:05:01,491 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18 states to 18 states and 23 transitions. [2024-11-08 18:05:01,492 INFO L240 hiAutomatonCegarLoop]: Abstraction has 18 states and 23 transitions. [2024-11-08 18:05:01,492 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 18:05:01,493 INFO L425 stractBuchiCegarLoop]: Abstraction has 18 states and 23 transitions. [2024-11-08 18:05:01,495 INFO L332 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-11-08 18:05:01,495 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 18 states and 23 transitions. [2024-11-08 18:05:01,496 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2024-11-08 18:05:01,496 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 18:05:01,496 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 18:05:01,496 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [2, 1, 1, 1, 1, 1, 1] [2024-11-08 18:05:01,499 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2024-11-08 18:05:01,499 INFO L745 eck$LassoCheckResult]: Stem: 153#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 154#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~post2#1, main_#t~nondet3#1, main_#t~post4#1, main_#t~post5#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 157#L26 main_~i~0#1 := 0; 158#L29-2 havoc main_#t~nondet1#1; 151#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 152#L29-2 havoc main_#t~nondet1#1; 149#L29 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 150#L29-3 assume main_~i~0#1 >= 100; 159#L32 [2024-11-08 18:05:01,499 INFO L747 eck$LassoCheckResult]: Loop: 159#L32 assume true; 159#L32 [2024-11-08 18:05:01,500 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:05:01,500 INFO L85 PathProgramCache]: Analyzing trace with hash 89853002, now seen corresponding path program 1 times [2024-11-08 18:05:01,500 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 18:05:01,500 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2124937080] [2024-11-08 18:05:01,501 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:05:01,501 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 18:05:01,525 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 18:05:01,599 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 18:05:01,600 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 18:05:01,600 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2124937080] [2024-11-08 18:05:01,600 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2124937080] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-08 18:05:01,600 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [608062395] [2024-11-08 18:05:01,601 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:05:01,601 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-08 18:05:01,601 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8264667-cc34-41ae-a2e3-109642306c6c/bin/uautomizer-verify-jihMAELWvX/z3 [2024-11-08 18:05:01,603 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8264667-cc34-41ae-a2e3-109642306c6c/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-08 18:05:01,605 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8264667-cc34-41ae-a2e3-109642306c6c/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Waiting until timeout for monitored process [2024-11-08 18:05:01,651 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 18:05:01,652 INFO L255 TraceCheckSpWp]: Trace formula consists of 28 conjuncts, 3 conjuncts are in the unsatisfiable core [2024-11-08 18:05:01,653 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-08 18:05:01,684 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 18:05:01,684 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-08 18:05:01,733 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 18:05:01,734 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [608062395] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-08 18:05:01,734 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-08 18:05:01,734 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 6 [2024-11-08 18:05:01,735 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [367031458] [2024-11-08 18:05:01,735 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-08 18:05:01,735 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 18:05:01,736 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:05:01,736 INFO L85 PathProgramCache]: Analyzing trace with hash 91, now seen corresponding path program 2 times [2024-11-08 18:05:01,736 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 18:05:01,737 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [672640812] [2024-11-08 18:05:01,737 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:05:01,737 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 18:05:01,740 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:05:01,740 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 18:05:01,741 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:05:01,741 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 18:05:01,747 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 18:05:01,747 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2024-11-08 18:05:01,748 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=21, Unknown=0, NotChecked=0, Total=42 [2024-11-08 18:05:01,748 INFO L87 Difference]: Start difference. First operand 18 states and 23 transitions. cyclomatic complexity: 8 Second operand has 7 states, 6 states have (on average 2.8333333333333335) internal successors, (17), 7 states have internal predecessors, (17), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 18:05:01,816 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 18:05:01,817 INFO L93 Difference]: Finished difference Result 60 states and 75 transitions. [2024-11-08 18:05:01,817 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 60 states and 75 transitions. [2024-11-08 18:05:01,819 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 5 [2024-11-08 18:05:01,820 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 60 states to 60 states and 75 transitions. [2024-11-08 18:05:01,820 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 33 [2024-11-08 18:05:01,821 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 33 [2024-11-08 18:05:01,821 INFO L73 IsDeterministic]: Start isDeterministic. Operand 60 states and 75 transitions. [2024-11-08 18:05:01,821 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-08 18:05:01,821 INFO L218 hiAutomatonCegarLoop]: Abstraction has 60 states and 75 transitions. [2024-11-08 18:05:01,822 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 60 states and 75 transitions. [2024-11-08 18:05:01,824 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 60 to 24. [2024-11-08 18:05:01,824 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 24 states, 24 states have (on average 1.4583333333333333) internal successors, (35), 23 states have internal predecessors, (35), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 18:05:01,825 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24 states to 24 states and 35 transitions. [2024-11-08 18:05:01,825 INFO L240 hiAutomatonCegarLoop]: Abstraction has 24 states and 35 transitions. [2024-11-08 18:05:01,826 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-11-08 18:05:01,826 INFO L425 stractBuchiCegarLoop]: Abstraction has 24 states and 35 transitions. [2024-11-08 18:05:01,827 INFO L332 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-11-08 18:05:01,827 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 24 states and 35 transitions. [2024-11-08 18:05:01,828 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2024-11-08 18:05:01,828 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 18:05:01,828 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 18:05:01,830 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 18:05:01,830 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2024-11-08 18:05:01,830 INFO L745 eck$LassoCheckResult]: Stem: 282#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 283#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~post2#1, main_#t~nondet3#1, main_#t~post4#1, main_#t~post5#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 286#L26 main_~i~0#1 := 0; 287#L29-2 havoc main_#t~nondet1#1; 279#L29 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 275#L29-3 assume !(main_~i~0#1 >= 100);main_~j~0#1 := 0; 276#L35-2 havoc main_#t~nondet3#1; 284#L35 assume !(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1; 289#L35-3 assume main_~j~0#1 >= 100; 288#L32 [2024-11-08 18:05:01,830 INFO L747 eck$LassoCheckResult]: Loop: 288#L32 assume true; 288#L32 [2024-11-08 18:05:01,831 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:05:01,831 INFO L85 PathProgramCache]: Analyzing trace with hash -1510939440, now seen corresponding path program 1 times [2024-11-08 18:05:01,831 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 18:05:01,832 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2018038757] [2024-11-08 18:05:01,832 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:05:01,832 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 18:05:01,840 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 18:05:01,880 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 18:05:01,880 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 18:05:01,880 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2018038757] [2024-11-08 18:05:01,880 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2018038757] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 18:05:01,881 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 18:05:01,881 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-08 18:05:01,881 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1542759767] [2024-11-08 18:05:01,881 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 18:05:01,881 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 18:05:01,882 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:05:01,882 INFO L85 PathProgramCache]: Analyzing trace with hash 91, now seen corresponding path program 3 times [2024-11-08 18:05:01,882 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 18:05:01,882 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1848362925] [2024-11-08 18:05:01,883 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:05:01,884 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 18:05:01,886 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:05:01,890 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 18:05:01,891 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:05:01,892 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 18:05:01,895 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 18:05:01,896 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 18:05:01,896 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 18:05:01,897 INFO L87 Difference]: Start difference. First operand 24 states and 35 transitions. cyclomatic complexity: 14 Second operand has 3 states, 2 states have (on average 4.5) internal successors, (9), 3 states have internal predecessors, (9), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 18:05:01,907 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 18:05:01,907 INFO L93 Difference]: Finished difference Result 27 states and 37 transitions. [2024-11-08 18:05:01,907 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 27 states and 37 transitions. [2024-11-08 18:05:01,909 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2024-11-08 18:05:01,911 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 27 states to 22 states and 28 transitions. [2024-11-08 18:05:01,911 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9 [2024-11-08 18:05:01,911 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9 [2024-11-08 18:05:01,912 INFO L73 IsDeterministic]: Start isDeterministic. Operand 22 states and 28 transitions. [2024-11-08 18:05:01,912 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-08 18:05:01,913 INFO L218 hiAutomatonCegarLoop]: Abstraction has 22 states and 28 transitions. [2024-11-08 18:05:01,913 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22 states and 28 transitions. [2024-11-08 18:05:01,915 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22 to 21. [2024-11-08 18:05:01,915 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21 states, 21 states have (on average 1.2857142857142858) internal successors, (27), 20 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 18:05:01,916 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21 states to 21 states and 27 transitions. [2024-11-08 18:05:01,916 INFO L240 hiAutomatonCegarLoop]: Abstraction has 21 states and 27 transitions. [2024-11-08 18:05:01,917 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 18:05:01,919 INFO L425 stractBuchiCegarLoop]: Abstraction has 21 states and 27 transitions. [2024-11-08 18:05:01,919 INFO L332 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-11-08 18:05:01,919 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 21 states and 27 transitions. [2024-11-08 18:05:01,920 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2024-11-08 18:05:01,921 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 18:05:01,921 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 18:05:01,921 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 18:05:01,921 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2024-11-08 18:05:01,922 INFO L745 eck$LassoCheckResult]: Stem: 339#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 340#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~post2#1, main_#t~nondet3#1, main_#t~post4#1, main_#t~post5#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 342#L26 main_~i~0#1 := 0; 343#L29-2 havoc main_#t~nondet1#1; 337#L29 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 334#L29-3 assume !(main_~i~0#1 >= 100);main_~j~0#1 := 0; 335#L35-2 havoc main_#t~nondet3#1; 341#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 346#L35-2 havoc main_#t~nondet3#1; 345#L35 assume !(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1; 344#L35-3 assume main_~j~0#1 >= 100; 333#L32 [2024-11-08 18:05:01,922 INFO L747 eck$LassoCheckResult]: Loop: 333#L32 assume true; 333#L32 [2024-11-08 18:05:01,924 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:05:01,925 INFO L85 PathProgramCache]: Analyzing trace with hash -313805845, now seen corresponding path program 1 times [2024-11-08 18:05:01,925 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 18:05:01,925 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1194805928] [2024-11-08 18:05:01,925 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:05:01,926 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 18:05:01,941 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 18:05:02,020 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 18:05:02,020 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 18:05:02,021 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1194805928] [2024-11-08 18:05:02,021 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1194805928] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-08 18:05:02,021 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1016992758] [2024-11-08 18:05:02,021 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:05:02,022 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-08 18:05:02,022 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8264667-cc34-41ae-a2e3-109642306c6c/bin/uautomizer-verify-jihMAELWvX/z3 [2024-11-08 18:05:02,024 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8264667-cc34-41ae-a2e3-109642306c6c/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-08 18:05:02,027 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8264667-cc34-41ae-a2e3-109642306c6c/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Waiting until timeout for monitored process [2024-11-08 18:05:02,069 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 18:05:02,070 INFO L255 TraceCheckSpWp]: Trace formula consists of 35 conjuncts, 3 conjuncts are in the unsatisfiable core [2024-11-08 18:05:02,071 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-08 18:05:02,095 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 18:05:02,096 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-08 18:05:02,131 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 18:05:02,131 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1016992758] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-08 18:05:02,132 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-08 18:05:02,132 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 6 [2024-11-08 18:05:02,132 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [816942717] [2024-11-08 18:05:02,132 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-08 18:05:02,133 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 18:05:02,136 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:05:02,136 INFO L85 PathProgramCache]: Analyzing trace with hash 91, now seen corresponding path program 4 times [2024-11-08 18:05:02,136 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 18:05:02,137 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [711127948] [2024-11-08 18:05:02,137 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:05:02,137 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 18:05:02,141 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:05:02,142 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 18:05:02,143 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:05:02,143 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 18:05:02,151 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 18:05:02,152 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2024-11-08 18:05:02,152 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=21, Unknown=0, NotChecked=0, Total=42 [2024-11-08 18:05:02,152 INFO L87 Difference]: Start difference. First operand 21 states and 27 transitions. cyclomatic complexity: 9 Second operand has 7 states, 6 states have (on average 3.3333333333333335) internal successors, (20), 7 states have internal predecessors, (20), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 18:05:02,180 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 18:05:02,180 INFO L93 Difference]: Finished difference Result 34 states and 40 transitions. [2024-11-08 18:05:02,180 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 34 states and 40 transitions. [2024-11-08 18:05:02,181 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2024-11-08 18:05:02,184 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 34 states to 28 states and 34 transitions. [2024-11-08 18:05:02,184 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9 [2024-11-08 18:05:02,185 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9 [2024-11-08 18:05:02,185 INFO L73 IsDeterministic]: Start isDeterministic. Operand 28 states and 34 transitions. [2024-11-08 18:05:02,185 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-08 18:05:02,185 INFO L218 hiAutomatonCegarLoop]: Abstraction has 28 states and 34 transitions. [2024-11-08 18:05:02,185 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28 states and 34 transitions. [2024-11-08 18:05:02,186 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28 to 27. [2024-11-08 18:05:02,188 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 27 states, 27 states have (on average 1.2222222222222223) internal successors, (33), 26 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 18:05:02,189 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27 states to 27 states and 33 transitions. [2024-11-08 18:05:02,189 INFO L240 hiAutomatonCegarLoop]: Abstraction has 27 states and 33 transitions. [2024-11-08 18:05:02,189 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-11-08 18:05:02,190 INFO L425 stractBuchiCegarLoop]: Abstraction has 27 states and 33 transitions. [2024-11-08 18:05:02,192 INFO L332 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-11-08 18:05:02,192 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 27 states and 33 transitions. [2024-11-08 18:05:02,192 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2024-11-08 18:05:02,193 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 18:05:02,193 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 18:05:02,193 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [5, 4, 1, 1, 1, 1, 1] [2024-11-08 18:05:02,193 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2024-11-08 18:05:02,193 INFO L745 eck$LassoCheckResult]: Stem: 461#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 462#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~post2#1, main_#t~nondet3#1, main_#t~post4#1, main_#t~post5#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 468#L26 main_~i~0#1 := 0; 469#L29-2 havoc main_#t~nondet1#1; 464#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 465#L29-2 havoc main_#t~nondet1#1; 473#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 480#L29-2 havoc main_#t~nondet1#1; 479#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 478#L29-2 havoc main_#t~nondet1#1; 475#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 474#L29-2 havoc main_#t~nondet1#1; 463#L29 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 457#L29-3 assume main_~i~0#1 >= 100; 458#L32 [2024-11-08 18:05:02,194 INFO L747 eck$LassoCheckResult]: Loop: 458#L32 assume true; 458#L32 [2024-11-08 18:05:02,195 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:05:02,195 INFO L85 PathProgramCache]: Analyzing trace with hash 183680795, now seen corresponding path program 2 times [2024-11-08 18:05:02,195 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 18:05:02,195 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1201059235] [2024-11-08 18:05:02,196 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:05:02,196 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 18:05:02,211 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 18:05:02,346 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 18:05:02,347 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 18:05:02,347 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1201059235] [2024-11-08 18:05:02,347 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1201059235] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-08 18:05:02,347 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [572271260] [2024-11-08 18:05:02,348 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-08 18:05:02,348 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-08 18:05:02,348 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8264667-cc34-41ae-a2e3-109642306c6c/bin/uautomizer-verify-jihMAELWvX/z3 [2024-11-08 18:05:02,349 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8264667-cc34-41ae-a2e3-109642306c6c/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-08 18:05:02,351 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8264667-cc34-41ae-a2e3-109642306c6c/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Waiting until timeout for monitored process [2024-11-08 18:05:02,393 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2024-11-08 18:05:02,393 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-08 18:05:02,394 INFO L255 TraceCheckSpWp]: Trace formula consists of 43 conjuncts, 6 conjuncts are in the unsatisfiable core [2024-11-08 18:05:02,395 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-08 18:05:02,440 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 18:05:02,441 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-08 18:05:02,561 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 18:05:02,561 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [572271260] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-08 18:05:02,562 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-08 18:05:02,562 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6] total 12 [2024-11-08 18:05:02,562 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1306397766] [2024-11-08 18:05:02,562 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-08 18:05:02,562 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 18:05:02,563 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:05:02,563 INFO L85 PathProgramCache]: Analyzing trace with hash 91, now seen corresponding path program 5 times [2024-11-08 18:05:02,563 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 18:05:02,563 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1422053177] [2024-11-08 18:05:02,563 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:05:02,563 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 18:05:02,568 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:05:02,569 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 18:05:02,570 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:05:02,570 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 18:05:02,572 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 18:05:02,573 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2024-11-08 18:05:02,573 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=78, Invalid=78, Unknown=0, NotChecked=0, Total=156 [2024-11-08 18:05:02,574 INFO L87 Difference]: Start difference. First operand 27 states and 33 transitions. cyclomatic complexity: 9 Second operand has 13 states, 12 states have (on average 2.4166666666666665) internal successors, (29), 13 states have internal predecessors, (29), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 18:05:02,745 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 18:05:02,745 INFO L93 Difference]: Finished difference Result 152 states and 171 transitions. [2024-11-08 18:05:02,745 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 152 states and 171 transitions. [2024-11-08 18:05:02,747 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 7 [2024-11-08 18:05:02,748 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 152 states to 140 states and 159 transitions. [2024-11-08 18:05:02,749 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27 [2024-11-08 18:05:02,749 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 27 [2024-11-08 18:05:02,749 INFO L73 IsDeterministic]: Start isDeterministic. Operand 140 states and 159 transitions. [2024-11-08 18:05:02,749 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-08 18:05:02,749 INFO L218 hiAutomatonCegarLoop]: Abstraction has 140 states and 159 transitions. [2024-11-08 18:05:02,750 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 140 states and 159 transitions. [2024-11-08 18:05:02,752 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 140 to 39. [2024-11-08 18:05:02,753 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 39 states, 39 states have (on average 1.3076923076923077) internal successors, (51), 38 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 18:05:02,753 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39 states to 39 states and 51 transitions. [2024-11-08 18:05:02,753 INFO L240 hiAutomatonCegarLoop]: Abstraction has 39 states and 51 transitions. [2024-11-08 18:05:02,756 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2024-11-08 18:05:02,756 INFO L425 stractBuchiCegarLoop]: Abstraction has 39 states and 51 transitions. [2024-11-08 18:05:02,757 INFO L332 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-11-08 18:05:02,757 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 39 states and 51 transitions. [2024-11-08 18:05:02,757 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2024-11-08 18:05:02,758 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 18:05:02,759 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 18:05:02,760 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [5, 4, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 18:05:02,760 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2024-11-08 18:05:02,760 INFO L745 eck$LassoCheckResult]: Stem: 734#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 735#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~post2#1, main_#t~nondet3#1, main_#t~post4#1, main_#t~post5#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 740#L26 main_~i~0#1 := 0; 741#L29-2 havoc main_#t~nondet1#1; 743#L29 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 732#L29-3 assume !(main_~i~0#1 >= 100);main_~j~0#1 := 0; 733#L35-2 havoc main_#t~nondet3#1; 739#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 746#L35-2 havoc main_#t~nondet3#1; 768#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 767#L35-2 havoc main_#t~nondet3#1; 766#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 765#L35-2 havoc main_#t~nondet3#1; 764#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 763#L35-2 havoc main_#t~nondet3#1; 745#L35 assume !(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1; 742#L35-3 assume main_~j~0#1 >= 100; 731#L32 [2024-11-08 18:05:02,760 INFO L747 eck$LassoCheckResult]: Loop: 731#L32 assume true; 731#L32 [2024-11-08 18:05:02,761 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:05:02,761 INFO L85 PathProgramCache]: Analyzing trace with hash -736968516, now seen corresponding path program 2 times [2024-11-08 18:05:02,761 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 18:05:02,762 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1852919592] [2024-11-08 18:05:02,762 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:05:02,762 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 18:05:02,777 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 18:05:02,930 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 18:05:02,931 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 18:05:02,931 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1852919592] [2024-11-08 18:05:02,931 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1852919592] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-08 18:05:02,931 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [831282162] [2024-11-08 18:05:02,932 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-08 18:05:02,932 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-08 18:05:02,932 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8264667-cc34-41ae-a2e3-109642306c6c/bin/uautomizer-verify-jihMAELWvX/z3 [2024-11-08 18:05:02,934 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8264667-cc34-41ae-a2e3-109642306c6c/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-08 18:05:02,936 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8264667-cc34-41ae-a2e3-109642306c6c/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Waiting until timeout for monitored process [2024-11-08 18:05:02,982 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2024-11-08 18:05:02,983 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-08 18:05:02,983 INFO L255 TraceCheckSpWp]: Trace formula consists of 56 conjuncts, 6 conjuncts are in the unsatisfiable core [2024-11-08 18:05:02,985 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-08 18:05:03,025 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 18:05:03,026 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-08 18:05:03,127 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 18:05:03,127 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [831282162] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-08 18:05:03,127 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-08 18:05:03,127 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6] total 12 [2024-11-08 18:05:03,128 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [307442785] [2024-11-08 18:05:03,128 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-08 18:05:03,128 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 18:05:03,128 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:05:03,129 INFO L85 PathProgramCache]: Analyzing trace with hash 91, now seen corresponding path program 6 times [2024-11-08 18:05:03,129 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 18:05:03,129 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [873372215] [2024-11-08 18:05:03,129 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:05:03,129 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 18:05:03,131 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:05:03,131 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 18:05:03,132 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:05:03,132 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 18:05:03,135 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 18:05:03,135 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2024-11-08 18:05:03,136 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=78, Invalid=78, Unknown=0, NotChecked=0, Total=156 [2024-11-08 18:05:03,136 INFO L87 Difference]: Start difference. First operand 39 states and 51 transitions. cyclomatic complexity: 15 Second operand has 13 states, 12 states have (on average 2.6666666666666665) internal successors, (32), 13 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 18:05:03,166 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 18:05:03,166 INFO L93 Difference]: Finished difference Result 64 states and 76 transitions. [2024-11-08 18:05:03,166 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 64 states and 76 transitions. [2024-11-08 18:05:03,167 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2024-11-08 18:05:03,168 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 64 states to 52 states and 64 transitions. [2024-11-08 18:05:03,168 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9 [2024-11-08 18:05:03,168 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9 [2024-11-08 18:05:03,168 INFO L73 IsDeterministic]: Start isDeterministic. Operand 52 states and 64 transitions. [2024-11-08 18:05:03,169 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-08 18:05:03,169 INFO L218 hiAutomatonCegarLoop]: Abstraction has 52 states and 64 transitions. [2024-11-08 18:05:03,169 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 52 states and 64 transitions. [2024-11-08 18:05:03,171 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 52 to 51. [2024-11-08 18:05:03,171 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 51 states, 51 states have (on average 1.2352941176470589) internal successors, (63), 50 states have internal predecessors, (63), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 18:05:03,172 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51 states to 51 states and 63 transitions. [2024-11-08 18:05:03,172 INFO L240 hiAutomatonCegarLoop]: Abstraction has 51 states and 63 transitions. [2024-11-08 18:05:03,172 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2024-11-08 18:05:03,173 INFO L425 stractBuchiCegarLoop]: Abstraction has 51 states and 63 transitions. [2024-11-08 18:05:03,173 INFO L332 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-11-08 18:05:03,173 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 51 states and 63 transitions. [2024-11-08 18:05:03,174 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2024-11-08 18:05:03,174 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 18:05:03,174 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 18:05:03,174 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [11, 10, 1, 1, 1, 1, 1] [2024-11-08 18:05:03,174 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2024-11-08 18:05:03,175 INFO L745 eck$LassoCheckResult]: Stem: 952#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 953#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~post2#1, main_#t~nondet3#1, main_#t~post4#1, main_#t~post5#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 956#L26 main_~i~0#1 := 0; 957#L29-2 havoc main_#t~nondet1#1; 950#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 951#L29-2 havoc main_#t~nondet1#1; 961#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 980#L29-2 havoc main_#t~nondet1#1; 979#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 978#L29-2 havoc main_#t~nondet1#1; 977#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 976#L29-2 havoc main_#t~nondet1#1; 975#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 974#L29-2 havoc main_#t~nondet1#1; 973#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 972#L29-2 havoc main_#t~nondet1#1; 971#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 970#L29-2 havoc main_#t~nondet1#1; 969#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 968#L29-2 havoc main_#t~nondet1#1; 967#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 966#L29-2 havoc main_#t~nondet1#1; 965#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 964#L29-2 havoc main_#t~nondet1#1; 949#L29 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 945#L29-3 assume main_~i~0#1 >= 100; 946#L32 [2024-11-08 18:05:03,175 INFO L747 eck$LassoCheckResult]: Loop: 946#L32 assume true; 946#L32 [2024-11-08 18:05:03,175 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:05:03,175 INFO L85 PathProgramCache]: Analyzing trace with hash -1224191363, now seen corresponding path program 3 times [2024-11-08 18:05:03,175 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 18:05:03,176 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1977856315] [2024-11-08 18:05:03,176 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:05:03,176 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 18:05:03,187 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 18:05:03,372 INFO L134 CoverageAnalysis]: Checked inductivity of 110 backedges. 0 proven. 110 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 18:05:03,373 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 18:05:03,373 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1977856315] [2024-11-08 18:05:03,373 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1977856315] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-08 18:05:03,373 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1225142368] [2024-11-08 18:05:03,373 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-11-08 18:05:03,374 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-08 18:05:03,374 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8264667-cc34-41ae-a2e3-109642306c6c/bin/uautomizer-verify-jihMAELWvX/z3 [2024-11-08 18:05:03,376 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8264667-cc34-41ae-a2e3-109642306c6c/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-08 18:05:03,388 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8264667-cc34-41ae-a2e3-109642306c6c/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Waiting until timeout for monitored process [2024-11-08 18:05:03,436 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 11 check-sat command(s) [2024-11-08 18:05:03,436 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-08 18:05:03,437 INFO L255 TraceCheckSpWp]: Trace formula consists of 73 conjuncts, 12 conjuncts are in the unsatisfiable core [2024-11-08 18:05:03,438 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-08 18:05:03,521 INFO L134 CoverageAnalysis]: Checked inductivity of 110 backedges. 0 proven. 110 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 18:05:03,521 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-08 18:05:03,834 INFO L134 CoverageAnalysis]: Checked inductivity of 110 backedges. 0 proven. 110 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 18:05:03,834 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1225142368] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-08 18:05:03,834 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-08 18:05:03,835 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12, 12] total 24 [2024-11-08 18:05:03,835 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1463856269] [2024-11-08 18:05:03,836 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-08 18:05:03,836 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 18:05:03,836 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:05:03,837 INFO L85 PathProgramCache]: Analyzing trace with hash 91, now seen corresponding path program 7 times [2024-11-08 18:05:03,837 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 18:05:03,837 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1223393251] [2024-11-08 18:05:03,837 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:05:03,837 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 18:05:03,839 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:05:03,839 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 18:05:03,840 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:05:03,841 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 18:05:03,844 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 18:05:03,845 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2024-11-08 18:05:03,845 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=300, Invalid=300, Unknown=0, NotChecked=0, Total=600 [2024-11-08 18:05:03,845 INFO L87 Difference]: Start difference. First operand 51 states and 63 transitions. cyclomatic complexity: 15 Second operand has 25 states, 24 states have (on average 2.2083333333333335) internal successors, (53), 25 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 18:05:04,107 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 18:05:04,108 INFO L93 Difference]: Finished difference Result 518 states and 555 transitions. [2024-11-08 18:05:04,108 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 518 states and 555 transitions. [2024-11-08 18:05:04,112 INFO L131 ngComponentsAnalysis]: Automaton has 13 accepting balls. 13 [2024-11-08 18:05:04,115 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 518 states to 494 states and 531 transitions. [2024-11-08 18:05:04,115 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 45 [2024-11-08 18:05:04,115 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 45 [2024-11-08 18:05:04,115 INFO L73 IsDeterministic]: Start isDeterministic. Operand 494 states and 531 transitions. [2024-11-08 18:05:04,116 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-08 18:05:04,116 INFO L218 hiAutomatonCegarLoop]: Abstraction has 494 states and 531 transitions. [2024-11-08 18:05:04,117 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 494 states and 531 transitions. [2024-11-08 18:05:04,123 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 494 to 75. [2024-11-08 18:05:04,123 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 75 states, 75 states have (on average 1.32) internal successors, (99), 74 states have internal predecessors, (99), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 18:05:04,124 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 75 states to 75 states and 99 transitions. [2024-11-08 18:05:04,124 INFO L240 hiAutomatonCegarLoop]: Abstraction has 75 states and 99 transitions. [2024-11-08 18:05:04,125 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2024-11-08 18:05:04,125 INFO L425 stractBuchiCegarLoop]: Abstraction has 75 states and 99 transitions. [2024-11-08 18:05:04,125 INFO L332 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-11-08 18:05:04,125 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 75 states and 99 transitions. [2024-11-08 18:05:04,126 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2024-11-08 18:05:04,126 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 18:05:04,126 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 18:05:04,127 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [11, 10, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 18:05:04,127 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2024-11-08 18:05:04,127 INFO L745 eck$LassoCheckResult]: Stem: 1696#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 1697#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~post2#1, main_#t~nondet3#1, main_#t~post4#1, main_#t~post5#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 1702#L26 main_~i~0#1 := 0; 1703#L29-2 havoc main_#t~nondet1#1; 1705#L29 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 1694#L29-3 assume !(main_~i~0#1 >= 100);main_~j~0#1 := 0; 1695#L35-2 havoc main_#t~nondet3#1; 1701#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 1708#L35-2 havoc main_#t~nondet3#1; 1766#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 1765#L35-2 havoc main_#t~nondet3#1; 1764#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 1763#L35-2 havoc main_#t~nondet3#1; 1762#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 1761#L35-2 havoc main_#t~nondet3#1; 1760#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 1759#L35-2 havoc main_#t~nondet3#1; 1758#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 1757#L35-2 havoc main_#t~nondet3#1; 1756#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 1755#L35-2 havoc main_#t~nondet3#1; 1754#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 1753#L35-2 havoc main_#t~nondet3#1; 1752#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 1751#L35-2 havoc main_#t~nondet3#1; 1750#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 1749#L35-2 havoc main_#t~nondet3#1; 1707#L35 assume !(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1; 1704#L35-3 assume main_~j~0#1 >= 100; 1693#L32 [2024-11-08 18:05:04,127 INFO L747 eck$LassoCheckResult]: Loop: 1693#L32 assume true; 1693#L32 [2024-11-08 18:05:04,128 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:05:04,128 INFO L85 PathProgramCache]: Analyzing trace with hash 367298590, now seen corresponding path program 3 times [2024-11-08 18:05:04,128 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 18:05:04,128 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1241915085] [2024-11-08 18:05:04,128 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:05:04,128 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 18:05:04,139 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 18:05:04,311 INFO L134 CoverageAnalysis]: Checked inductivity of 110 backedges. 0 proven. 110 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 18:05:04,311 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 18:05:04,312 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1241915085] [2024-11-08 18:05:04,312 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1241915085] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-08 18:05:04,312 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [438602366] [2024-11-08 18:05:04,312 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-11-08 18:05:04,312 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-08 18:05:04,312 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8264667-cc34-41ae-a2e3-109642306c6c/bin/uautomizer-verify-jihMAELWvX/z3 [2024-11-08 18:05:04,315 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8264667-cc34-41ae-a2e3-109642306c6c/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-08 18:05:04,318 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8264667-cc34-41ae-a2e3-109642306c6c/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Waiting until timeout for monitored process [2024-11-08 18:05:04,390 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 11 check-sat command(s) [2024-11-08 18:05:04,390 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-08 18:05:04,391 INFO L255 TraceCheckSpWp]: Trace formula consists of 98 conjuncts, 12 conjuncts are in the unsatisfiable core [2024-11-08 18:05:04,397 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-08 18:05:04,463 INFO L134 CoverageAnalysis]: Checked inductivity of 110 backedges. 0 proven. 110 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 18:05:04,464 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-08 18:05:04,749 INFO L134 CoverageAnalysis]: Checked inductivity of 110 backedges. 0 proven. 110 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 18:05:04,749 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [438602366] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-08 18:05:04,749 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-08 18:05:04,749 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12, 12] total 24 [2024-11-08 18:05:04,750 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1508464721] [2024-11-08 18:05:04,750 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-08 18:05:04,752 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 18:05:04,752 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:05:04,752 INFO L85 PathProgramCache]: Analyzing trace with hash 91, now seen corresponding path program 8 times [2024-11-08 18:05:04,753 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 18:05:04,753 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1046233599] [2024-11-08 18:05:04,753 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:05:04,753 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 18:05:04,755 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:05:04,755 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 18:05:04,757 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:05:04,757 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 18:05:04,764 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 18:05:04,765 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2024-11-08 18:05:04,765 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=300, Invalid=300, Unknown=0, NotChecked=0, Total=600 [2024-11-08 18:05:04,765 INFO L87 Difference]: Start difference. First operand 75 states and 99 transitions. cyclomatic complexity: 27 Second operand has 25 states, 24 states have (on average 2.3333333333333335) internal successors, (56), 25 states have internal predecessors, (56), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 18:05:04,812 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 18:05:04,813 INFO L93 Difference]: Finished difference Result 124 states and 148 transitions. [2024-11-08 18:05:04,813 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 124 states and 148 transitions. [2024-11-08 18:05:04,814 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2024-11-08 18:05:04,815 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 124 states to 100 states and 124 transitions. [2024-11-08 18:05:04,815 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9 [2024-11-08 18:05:04,816 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9 [2024-11-08 18:05:04,816 INFO L73 IsDeterministic]: Start isDeterministic. Operand 100 states and 124 transitions. [2024-11-08 18:05:04,816 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-08 18:05:04,816 INFO L218 hiAutomatonCegarLoop]: Abstraction has 100 states and 124 transitions. [2024-11-08 18:05:04,817 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 100 states and 124 transitions. [2024-11-08 18:05:04,820 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 100 to 99. [2024-11-08 18:05:04,824 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 99 states, 99 states have (on average 1.2424242424242424) internal successors, (123), 98 states have internal predecessors, (123), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 18:05:04,825 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 99 states to 99 states and 123 transitions. [2024-11-08 18:05:04,825 INFO L240 hiAutomatonCegarLoop]: Abstraction has 99 states and 123 transitions. [2024-11-08 18:05:04,829 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2024-11-08 18:05:04,829 INFO L425 stractBuchiCegarLoop]: Abstraction has 99 states and 123 transitions. [2024-11-08 18:05:04,830 INFO L332 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-11-08 18:05:04,831 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 99 states and 123 transitions. [2024-11-08 18:05:04,832 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2024-11-08 18:05:04,832 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 18:05:04,833 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 18:05:04,833 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [23, 22, 1, 1, 1, 1, 1] [2024-11-08 18:05:04,834 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2024-11-08 18:05:04,834 INFO L745 eck$LassoCheckResult]: Stem: 2094#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 2095#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~post2#1, main_#t~nondet3#1, main_#t~post4#1, main_#t~post5#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 2098#L26 main_~i~0#1 := 0; 2099#L29-2 havoc main_#t~nondet1#1; 2092#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2093#L29-2 havoc main_#t~nondet1#1; 2103#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2146#L29-2 havoc main_#t~nondet1#1; 2145#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2144#L29-2 havoc main_#t~nondet1#1; 2143#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2142#L29-2 havoc main_#t~nondet1#1; 2141#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2140#L29-2 havoc main_#t~nondet1#1; 2139#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2138#L29-2 havoc main_#t~nondet1#1; 2137#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2136#L29-2 havoc main_#t~nondet1#1; 2135#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2134#L29-2 havoc main_#t~nondet1#1; 2133#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2132#L29-2 havoc main_#t~nondet1#1; 2131#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2130#L29-2 havoc main_#t~nondet1#1; 2129#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2128#L29-2 havoc main_#t~nondet1#1; 2127#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2126#L29-2 havoc main_#t~nondet1#1; 2125#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2124#L29-2 havoc main_#t~nondet1#1; 2123#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2122#L29-2 havoc main_#t~nondet1#1; 2121#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2120#L29-2 havoc main_#t~nondet1#1; 2119#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2118#L29-2 havoc main_#t~nondet1#1; 2117#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2116#L29-2 havoc main_#t~nondet1#1; 2115#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2114#L29-2 havoc main_#t~nondet1#1; 2113#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2112#L29-2 havoc main_#t~nondet1#1; 2111#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2110#L29-2 havoc main_#t~nondet1#1; 2109#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2108#L29-2 havoc main_#t~nondet1#1; 2107#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2106#L29-2 havoc main_#t~nondet1#1; 2091#L29 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 2087#L29-3 assume main_~i~0#1 >= 100; 2088#L32 [2024-11-08 18:05:04,834 INFO L747 eck$LassoCheckResult]: Loop: 2088#L32 assume true; 2088#L32 [2024-11-08 18:05:04,834 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:05:04,834 INFO L85 PathProgramCache]: Analyzing trace with hash -900992959, now seen corresponding path program 4 times [2024-11-08 18:05:04,835 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 18:05:04,835 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [905141428] [2024-11-08 18:05:04,835 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:05:04,835 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 18:05:04,859 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 18:05:05,461 INFO L134 CoverageAnalysis]: Checked inductivity of 506 backedges. 0 proven. 506 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 18:05:05,461 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 18:05:05,462 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [905141428] [2024-11-08 18:05:05,462 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [905141428] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-08 18:05:05,463 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2094844191] [2024-11-08 18:05:05,463 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2024-11-08 18:05:05,467 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-08 18:05:05,467 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8264667-cc34-41ae-a2e3-109642306c6c/bin/uautomizer-verify-jihMAELWvX/z3 [2024-11-08 18:05:05,470 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8264667-cc34-41ae-a2e3-109642306c6c/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-08 18:05:05,474 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8264667-cc34-41ae-a2e3-109642306c6c/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Waiting until timeout for monitored process [2024-11-08 18:05:05,537 INFO L227 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2024-11-08 18:05:05,537 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-08 18:05:05,538 INFO L255 TraceCheckSpWp]: Trace formula consists of 133 conjuncts, 24 conjuncts are in the unsatisfiable core [2024-11-08 18:05:05,540 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-08 18:05:05,656 INFO L134 CoverageAnalysis]: Checked inductivity of 506 backedges. 0 proven. 506 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 18:05:05,657 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-08 18:05:06,679 INFO L134 CoverageAnalysis]: Checked inductivity of 506 backedges. 0 proven. 506 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 18:05:06,679 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2094844191] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-08 18:05:06,680 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-08 18:05:06,680 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 24, 24] total 48 [2024-11-08 18:05:06,680 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [822779442] [2024-11-08 18:05:06,680 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-08 18:05:06,681 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 18:05:06,683 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:05:06,683 INFO L85 PathProgramCache]: Analyzing trace with hash 91, now seen corresponding path program 9 times [2024-11-08 18:05:06,683 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 18:05:06,683 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1435008978] [2024-11-08 18:05:06,683 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:05:06,684 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 18:05:06,685 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:05:06,686 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 18:05:06,687 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:05:06,687 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 18:05:06,689 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 18:05:06,691 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2024-11-08 18:05:06,692 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1176, Invalid=1176, Unknown=0, NotChecked=0, Total=2352 [2024-11-08 18:05:06,692 INFO L87 Difference]: Start difference. First operand 99 states and 123 transitions. cyclomatic complexity: 27 Second operand has 49 states, 48 states have (on average 2.1041666666666665) internal successors, (101), 49 states have internal predecessors, (101), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 18:05:07,362 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 18:05:07,362 INFO L93 Difference]: Finished difference Result 1898 states and 1971 transitions. [2024-11-08 18:05:07,362 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1898 states and 1971 transitions. [2024-11-08 18:05:07,378 INFO L131 ngComponentsAnalysis]: Automaton has 25 accepting balls. 25 [2024-11-08 18:05:07,388 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1898 states to 1850 states and 1923 transitions. [2024-11-08 18:05:07,388 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 81 [2024-11-08 18:05:07,388 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 81 [2024-11-08 18:05:07,389 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1850 states and 1923 transitions. [2024-11-08 18:05:07,389 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-08 18:05:07,389 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1850 states and 1923 transitions. [2024-11-08 18:05:07,391 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1850 states and 1923 transitions. [2024-11-08 18:05:07,404 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1850 to 147. [2024-11-08 18:05:07,404 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 147 states, 147 states have (on average 1.3265306122448979) internal successors, (195), 146 states have internal predecessors, (195), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 18:05:07,406 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 147 states to 147 states and 195 transitions. [2024-11-08 18:05:07,406 INFO L240 hiAutomatonCegarLoop]: Abstraction has 147 states and 195 transitions. [2024-11-08 18:05:07,406 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2024-11-08 18:05:07,407 INFO L425 stractBuchiCegarLoop]: Abstraction has 147 states and 195 transitions. [2024-11-08 18:05:07,407 INFO L332 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-11-08 18:05:07,407 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 147 states and 195 transitions. [2024-11-08 18:05:07,409 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2024-11-08 18:05:07,409 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 18:05:07,409 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 18:05:07,410 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [23, 22, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 18:05:07,411 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2024-11-08 18:05:07,411 INFO L745 eck$LassoCheckResult]: Stem: 4437#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 4438#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~post2#1, main_#t~nondet3#1, main_#t~post4#1, main_#t~post5#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 4440#L26 main_~i~0#1 := 0; 4441#L29-2 havoc main_#t~nondet1#1; 4445#L29 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 4432#L29-3 assume !(main_~i~0#1 >= 100);main_~j~0#1 := 0; 4433#L35-2 havoc main_#t~nondet3#1; 4439#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4444#L35-2 havoc main_#t~nondet3#1; 4576#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4575#L35-2 havoc main_#t~nondet3#1; 4574#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4573#L35-2 havoc main_#t~nondet3#1; 4572#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4571#L35-2 havoc main_#t~nondet3#1; 4570#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4569#L35-2 havoc main_#t~nondet3#1; 4568#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4567#L35-2 havoc main_#t~nondet3#1; 4566#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4565#L35-2 havoc main_#t~nondet3#1; 4564#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4563#L35-2 havoc main_#t~nondet3#1; 4562#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4561#L35-2 havoc main_#t~nondet3#1; 4560#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4559#L35-2 havoc main_#t~nondet3#1; 4558#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4557#L35-2 havoc main_#t~nondet3#1; 4556#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4555#L35-2 havoc main_#t~nondet3#1; 4554#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4553#L35-2 havoc main_#t~nondet3#1; 4552#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4551#L35-2 havoc main_#t~nondet3#1; 4550#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4549#L35-2 havoc main_#t~nondet3#1; 4548#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4547#L35-2 havoc main_#t~nondet3#1; 4546#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4545#L35-2 havoc main_#t~nondet3#1; 4544#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4543#L35-2 havoc main_#t~nondet3#1; 4542#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4541#L35-2 havoc main_#t~nondet3#1; 4540#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4539#L35-2 havoc main_#t~nondet3#1; 4538#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4537#L35-2 havoc main_#t~nondet3#1; 4536#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4535#L35-2 havoc main_#t~nondet3#1; 4443#L35 assume !(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1; 4442#L35-3 assume main_~j~0#1 >= 100; 4431#L32 [2024-11-08 18:05:07,411 INFO L747 eck$LassoCheckResult]: Loop: 4431#L32 assume true; 4431#L32 [2024-11-08 18:05:07,412 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:05:07,412 INFO L85 PathProgramCache]: Analyzing trace with hash -1818849822, now seen corresponding path program 4 times [2024-11-08 18:05:07,412 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 18:05:07,412 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1002446084] [2024-11-08 18:05:07,413 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:05:07,413 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 18:05:07,445 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 18:05:08,005 INFO L134 CoverageAnalysis]: Checked inductivity of 506 backedges. 0 proven. 506 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 18:05:08,005 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 18:05:08,006 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1002446084] [2024-11-08 18:05:08,006 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1002446084] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-08 18:05:08,006 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [60976381] [2024-11-08 18:05:08,006 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2024-11-08 18:05:08,006 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-08 18:05:08,007 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8264667-cc34-41ae-a2e3-109642306c6c/bin/uautomizer-verify-jihMAELWvX/z3 [2024-11-08 18:05:08,008 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8264667-cc34-41ae-a2e3-109642306c6c/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-08 18:05:08,010 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8264667-cc34-41ae-a2e3-109642306c6c/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Waiting until timeout for monitored process [2024-11-08 18:05:08,080 INFO L227 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2024-11-08 18:05:08,081 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-08 18:05:08,082 INFO L255 TraceCheckSpWp]: Trace formula consists of 182 conjuncts, 24 conjuncts are in the unsatisfiable core [2024-11-08 18:05:08,085 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-08 18:05:08,199 INFO L134 CoverageAnalysis]: Checked inductivity of 506 backedges. 0 proven. 506 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 18:05:08,199 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-08 18:05:09,097 INFO L134 CoverageAnalysis]: Checked inductivity of 506 backedges. 0 proven. 506 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 18:05:09,097 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [60976381] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-08 18:05:09,097 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-08 18:05:09,097 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 24, 24] total 48 [2024-11-08 18:05:09,098 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1809037597] [2024-11-08 18:05:09,098 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-08 18:05:09,098 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 18:05:09,099 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:05:09,099 INFO L85 PathProgramCache]: Analyzing trace with hash 91, now seen corresponding path program 10 times [2024-11-08 18:05:09,099 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 18:05:09,099 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1560645593] [2024-11-08 18:05:09,099 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:05:09,099 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 18:05:09,101 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:05:09,102 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 18:05:09,102 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:05:09,103 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 18:05:09,105 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 18:05:09,106 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2024-11-08 18:05:09,107 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1176, Invalid=1176, Unknown=0, NotChecked=0, Total=2352 [2024-11-08 18:05:09,107 INFO L87 Difference]: Start difference. First operand 147 states and 195 transitions. cyclomatic complexity: 51 Second operand has 49 states, 48 states have (on average 2.1666666666666665) internal successors, (104), 49 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 18:05:09,192 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 18:05:09,193 INFO L93 Difference]: Finished difference Result 244 states and 292 transitions. [2024-11-08 18:05:09,193 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 244 states and 292 transitions. [2024-11-08 18:05:09,195 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2024-11-08 18:05:09,196 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 244 states to 196 states and 244 transitions. [2024-11-08 18:05:09,196 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9 [2024-11-08 18:05:09,196 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9 [2024-11-08 18:05:09,196 INFO L73 IsDeterministic]: Start isDeterministic. Operand 196 states and 244 transitions. [2024-11-08 18:05:09,196 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-08 18:05:09,196 INFO L218 hiAutomatonCegarLoop]: Abstraction has 196 states and 244 transitions. [2024-11-08 18:05:09,197 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 196 states and 244 transitions. [2024-11-08 18:05:09,200 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 196 to 195. [2024-11-08 18:05:09,200 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 195 states, 195 states have (on average 1.2461538461538462) internal successors, (243), 194 states have internal predecessors, (243), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 18:05:09,202 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 195 states to 195 states and 243 transitions. [2024-11-08 18:05:09,202 INFO L240 hiAutomatonCegarLoop]: Abstraction has 195 states and 243 transitions. [2024-11-08 18:05:09,202 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2024-11-08 18:05:09,203 INFO L425 stractBuchiCegarLoop]: Abstraction has 195 states and 243 transitions. [2024-11-08 18:05:09,203 INFO L332 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-11-08 18:05:09,203 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 195 states and 243 transitions. [2024-11-08 18:05:09,204 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2024-11-08 18:05:09,204 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 18:05:09,204 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 18:05:09,206 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [47, 46, 1, 1, 1, 1, 1] [2024-11-08 18:05:09,206 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2024-11-08 18:05:09,207 INFO L745 eck$LassoCheckResult]: Stem: 5192#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 5193#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~post2#1, main_#t~nondet3#1, main_#t~post4#1, main_#t~post5#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 5196#L26 main_~i~0#1 := 0; 5197#L29-2 havoc main_#t~nondet1#1; 5190#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5191#L29-2 havoc main_#t~nondet1#1; 5201#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5292#L29-2 havoc main_#t~nondet1#1; 5291#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5290#L29-2 havoc main_#t~nondet1#1; 5289#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5288#L29-2 havoc main_#t~nondet1#1; 5287#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5286#L29-2 havoc main_#t~nondet1#1; 5285#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5284#L29-2 havoc main_#t~nondet1#1; 5283#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5282#L29-2 havoc main_#t~nondet1#1; 5281#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5280#L29-2 havoc main_#t~nondet1#1; 5279#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5278#L29-2 havoc main_#t~nondet1#1; 5277#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5276#L29-2 havoc main_#t~nondet1#1; 5275#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5274#L29-2 havoc main_#t~nondet1#1; 5273#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5272#L29-2 havoc main_#t~nondet1#1; 5271#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5270#L29-2 havoc main_#t~nondet1#1; 5269#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5268#L29-2 havoc main_#t~nondet1#1; 5267#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5266#L29-2 havoc main_#t~nondet1#1; 5265#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5264#L29-2 havoc main_#t~nondet1#1; 5263#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5262#L29-2 havoc main_#t~nondet1#1; 5261#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5260#L29-2 havoc main_#t~nondet1#1; 5259#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5258#L29-2 havoc main_#t~nondet1#1; 5257#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5256#L29-2 havoc main_#t~nondet1#1; 5255#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5254#L29-2 havoc main_#t~nondet1#1; 5253#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5252#L29-2 havoc main_#t~nondet1#1; 5251#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5250#L29-2 havoc main_#t~nondet1#1; 5249#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5248#L29-2 havoc main_#t~nondet1#1; 5247#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5246#L29-2 havoc main_#t~nondet1#1; 5245#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5244#L29-2 havoc main_#t~nondet1#1; 5243#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5242#L29-2 havoc main_#t~nondet1#1; 5241#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5240#L29-2 havoc main_#t~nondet1#1; 5239#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5238#L29-2 havoc main_#t~nondet1#1; 5237#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5236#L29-2 havoc main_#t~nondet1#1; 5235#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5234#L29-2 havoc main_#t~nondet1#1; 5233#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5232#L29-2 havoc main_#t~nondet1#1; 5231#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5230#L29-2 havoc main_#t~nondet1#1; 5229#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5228#L29-2 havoc main_#t~nondet1#1; 5227#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5226#L29-2 havoc main_#t~nondet1#1; 5225#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5224#L29-2 havoc main_#t~nondet1#1; 5223#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5222#L29-2 havoc main_#t~nondet1#1; 5221#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5220#L29-2 havoc main_#t~nondet1#1; 5219#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5218#L29-2 havoc main_#t~nondet1#1; 5217#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5216#L29-2 havoc main_#t~nondet1#1; 5215#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5214#L29-2 havoc main_#t~nondet1#1; 5213#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5212#L29-2 havoc main_#t~nondet1#1; 5211#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5210#L29-2 havoc main_#t~nondet1#1; 5209#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5208#L29-2 havoc main_#t~nondet1#1; 5207#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5206#L29-2 havoc main_#t~nondet1#1; 5205#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5204#L29-2 havoc main_#t~nondet1#1; 5189#L29 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 5185#L29-3 assume main_~i~0#1 >= 100; 5186#L32 [2024-11-08 18:05:09,207 INFO L747 eck$LassoCheckResult]: Loop: 5186#L32 assume true; 5186#L32 [2024-11-08 18:05:09,208 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:05:09,208 INFO L85 PathProgramCache]: Analyzing trace with hash 1121126345, now seen corresponding path program 5 times [2024-11-08 18:05:09,208 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 18:05:09,208 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [552850273] [2024-11-08 18:05:09,208 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:05:09,209 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 18:05:09,233 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 18:05:10,953 INFO L134 CoverageAnalysis]: Checked inductivity of 2162 backedges. 0 proven. 2162 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 18:05:10,954 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 18:05:10,954 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [552850273] [2024-11-08 18:05:10,954 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [552850273] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-08 18:05:10,954 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1059203956] [2024-11-08 18:05:10,954 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2024-11-08 18:05:10,955 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-08 18:05:10,955 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8264667-cc34-41ae-a2e3-109642306c6c/bin/uautomizer-verify-jihMAELWvX/z3 [2024-11-08 18:05:10,959 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8264667-cc34-41ae-a2e3-109642306c6c/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-08 18:05:10,966 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8264667-cc34-41ae-a2e3-109642306c6c/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Waiting until timeout for monitored process [2024-11-08 18:05:11,073 INFO L227 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 47 check-sat command(s) [2024-11-08 18:05:11,074 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-08 18:05:11,076 INFO L255 TraceCheckSpWp]: Trace formula consists of 253 conjuncts, 48 conjuncts are in the unsatisfiable core [2024-11-08 18:05:11,083 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-08 18:05:11,279 INFO L134 CoverageAnalysis]: Checked inductivity of 2162 backedges. 0 proven. 2162 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 18:05:11,280 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-08 18:05:14,576 INFO L134 CoverageAnalysis]: Checked inductivity of 2162 backedges. 0 proven. 2162 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 18:05:14,576 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1059203956] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-08 18:05:14,576 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-08 18:05:14,576 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [48, 48, 48] total 96 [2024-11-08 18:05:14,577 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [234303324] [2024-11-08 18:05:14,577 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-08 18:05:14,577 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 18:05:14,578 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:05:14,578 INFO L85 PathProgramCache]: Analyzing trace with hash 91, now seen corresponding path program 11 times [2024-11-08 18:05:14,578 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 18:05:14,578 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1679550114] [2024-11-08 18:05:14,578 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:05:14,578 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 18:05:14,580 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:05:14,580 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 18:05:14,581 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:05:14,581 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 18:05:14,585 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 18:05:14,587 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 97 interpolants. [2024-11-08 18:05:14,590 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=4656, Invalid=4656, Unknown=0, NotChecked=0, Total=9312 [2024-11-08 18:05:14,590 INFO L87 Difference]: Start difference. First operand 195 states and 243 transitions. cyclomatic complexity: 51 Second operand has 97 states, 96 states have (on average 2.0520833333333335) internal successors, (197), 97 states have internal predecessors, (197), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 18:05:17,184 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 18:05:17,184 INFO L93 Difference]: Finished difference Result 7250 states and 7395 transitions. [2024-11-08 18:05:17,184 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7250 states and 7395 transitions. [2024-11-08 18:05:17,235 INFO L131 ngComponentsAnalysis]: Automaton has 49 accepting balls. 49 [2024-11-08 18:05:17,268 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7250 states to 7154 states and 7299 transitions. [2024-11-08 18:05:17,268 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 153 [2024-11-08 18:05:17,269 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 153 [2024-11-08 18:05:17,269 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7154 states and 7299 transitions. [2024-11-08 18:05:17,274 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-08 18:05:17,274 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7154 states and 7299 transitions. [2024-11-08 18:05:17,280 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7154 states and 7299 transitions. [2024-11-08 18:05:17,313 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7154 to 291. [2024-11-08 18:05:17,314 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 291 states, 291 states have (on average 1.3298969072164948) internal successors, (387), 290 states have internal predecessors, (387), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 18:05:17,315 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 291 states to 291 states and 387 transitions. [2024-11-08 18:05:17,316 INFO L240 hiAutomatonCegarLoop]: Abstraction has 291 states and 387 transitions. [2024-11-08 18:05:17,317 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 96 states. [2024-11-08 18:05:17,318 INFO L425 stractBuchiCegarLoop]: Abstraction has 291 states and 387 transitions. [2024-11-08 18:05:17,318 INFO L332 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-11-08 18:05:17,318 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 291 states and 387 transitions. [2024-11-08 18:05:17,320 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2024-11-08 18:05:17,320 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 18:05:17,321 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 18:05:17,325 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [47, 46, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 18:05:17,329 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2024-11-08 18:05:17,329 INFO L745 eck$LassoCheckResult]: Stem: 13316#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 13317#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~post2#1, main_#t~nondet3#1, main_#t~post4#1, main_#t~post5#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 13322#L26 main_~i~0#1 := 0; 13323#L29-2 havoc main_#t~nondet1#1; 13325#L29 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 13314#L29-3 assume !(main_~i~0#1 >= 100);main_~j~0#1 := 0; 13315#L35-2 havoc main_#t~nondet3#1; 13321#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13328#L35-2 havoc main_#t~nondet3#1; 13602#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13601#L35-2 havoc main_#t~nondet3#1; 13600#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13599#L35-2 havoc main_#t~nondet3#1; 13598#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13597#L35-2 havoc main_#t~nondet3#1; 13596#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13595#L35-2 havoc main_#t~nondet3#1; 13594#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13593#L35-2 havoc main_#t~nondet3#1; 13592#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13591#L35-2 havoc main_#t~nondet3#1; 13590#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13589#L35-2 havoc main_#t~nondet3#1; 13588#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13587#L35-2 havoc main_#t~nondet3#1; 13586#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13585#L35-2 havoc main_#t~nondet3#1; 13584#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13583#L35-2 havoc main_#t~nondet3#1; 13582#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13581#L35-2 havoc main_#t~nondet3#1; 13580#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13579#L35-2 havoc main_#t~nondet3#1; 13578#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13577#L35-2 havoc main_#t~nondet3#1; 13576#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13575#L35-2 havoc main_#t~nondet3#1; 13574#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13573#L35-2 havoc main_#t~nondet3#1; 13572#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13571#L35-2 havoc main_#t~nondet3#1; 13570#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13569#L35-2 havoc main_#t~nondet3#1; 13568#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13567#L35-2 havoc main_#t~nondet3#1; 13566#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13565#L35-2 havoc main_#t~nondet3#1; 13564#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13563#L35-2 havoc main_#t~nondet3#1; 13562#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13561#L35-2 havoc main_#t~nondet3#1; 13560#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13559#L35-2 havoc main_#t~nondet3#1; 13558#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13557#L35-2 havoc main_#t~nondet3#1; 13556#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13555#L35-2 havoc main_#t~nondet3#1; 13554#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13553#L35-2 havoc main_#t~nondet3#1; 13552#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13551#L35-2 havoc main_#t~nondet3#1; 13550#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13549#L35-2 havoc main_#t~nondet3#1; 13548#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13547#L35-2 havoc main_#t~nondet3#1; 13546#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13545#L35-2 havoc main_#t~nondet3#1; 13544#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13543#L35-2 havoc main_#t~nondet3#1; 13542#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13541#L35-2 havoc main_#t~nondet3#1; 13540#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13539#L35-2 havoc main_#t~nondet3#1; 13538#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13537#L35-2 havoc main_#t~nondet3#1; 13536#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13535#L35-2 havoc main_#t~nondet3#1; 13534#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13533#L35-2 havoc main_#t~nondet3#1; 13532#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13531#L35-2 havoc main_#t~nondet3#1; 13530#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13529#L35-2 havoc main_#t~nondet3#1; 13528#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13527#L35-2 havoc main_#t~nondet3#1; 13526#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13525#L35-2 havoc main_#t~nondet3#1; 13524#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13523#L35-2 havoc main_#t~nondet3#1; 13522#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13521#L35-2 havoc main_#t~nondet3#1; 13520#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13519#L35-2 havoc main_#t~nondet3#1; 13518#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13517#L35-2 havoc main_#t~nondet3#1; 13516#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13515#L35-2 havoc main_#t~nondet3#1; 13514#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13513#L35-2 havoc main_#t~nondet3#1; 13327#L35 assume !(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1; 13324#L35-3 assume main_~j~0#1 >= 100; 13313#L32 [2024-11-08 18:05:17,330 INFO L747 eck$LassoCheckResult]: Loop: 13313#L32 assume true; 13313#L32 [2024-11-08 18:05:17,330 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:05:17,330 INFO L85 PathProgramCache]: Analyzing trace with hash -1462602390, now seen corresponding path program 5 times [2024-11-08 18:05:17,330 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 18:05:17,330 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1503692778] [2024-11-08 18:05:17,331 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:05:17,331 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 18:05:17,388 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 18:05:19,229 INFO L134 CoverageAnalysis]: Checked inductivity of 2162 backedges. 0 proven. 2162 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 18:05:19,230 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 18:05:19,230 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1503692778] [2024-11-08 18:05:19,230 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1503692778] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-08 18:05:19,230 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1212673663] [2024-11-08 18:05:19,230 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2024-11-08 18:05:19,230 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-08 18:05:19,230 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8264667-cc34-41ae-a2e3-109642306c6c/bin/uautomizer-verify-jihMAELWvX/z3 [2024-11-08 18:05:19,232 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8264667-cc34-41ae-a2e3-109642306c6c/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-08 18:05:19,234 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8264667-cc34-41ae-a2e3-109642306c6c/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Waiting until timeout for monitored process [2024-11-08 18:05:19,355 INFO L227 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 47 check-sat command(s) [2024-11-08 18:05:19,355 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-08 18:05:19,357 INFO L255 TraceCheckSpWp]: Trace formula consists of 350 conjuncts, 48 conjuncts are in the unsatisfiable core [2024-11-08 18:05:19,365 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-08 18:05:19,589 INFO L134 CoverageAnalysis]: Checked inductivity of 2162 backedges. 0 proven. 2162 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 18:05:19,589 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-08 18:05:22,487 INFO L134 CoverageAnalysis]: Checked inductivity of 2162 backedges. 0 proven. 2162 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 18:05:22,487 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1212673663] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-08 18:05:22,488 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-08 18:05:22,488 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [48, 48, 48] total 96 [2024-11-08 18:05:22,488 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1830425097] [2024-11-08 18:05:22,488 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-08 18:05:22,488 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 18:05:22,489 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:05:22,489 INFO L85 PathProgramCache]: Analyzing trace with hash 91, now seen corresponding path program 12 times [2024-11-08 18:05:22,489 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 18:05:22,489 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [107981453] [2024-11-08 18:05:22,490 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:05:22,490 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 18:05:22,491 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:05:22,491 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 18:05:22,492 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:05:22,493 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 18:05:22,500 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 18:05:22,502 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 97 interpolants. [2024-11-08 18:05:22,504 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=4656, Invalid=4656, Unknown=0, NotChecked=0, Total=9312 [2024-11-08 18:05:22,505 INFO L87 Difference]: Start difference. First operand 291 states and 387 transitions. cyclomatic complexity: 99 Second operand has 97 states, 96 states have (on average 2.0833333333333335) internal successors, (200), 97 states have internal predecessors, (200), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 18:05:22,827 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 18:05:22,828 INFO L93 Difference]: Finished difference Result 484 states and 580 transitions. [2024-11-08 18:05:22,828 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 484 states and 580 transitions. [2024-11-08 18:05:22,831 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2024-11-08 18:05:22,832 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 484 states to 388 states and 484 transitions. [2024-11-08 18:05:22,832 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9 [2024-11-08 18:05:22,833 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9 [2024-11-08 18:05:22,833 INFO L73 IsDeterministic]: Start isDeterministic. Operand 388 states and 484 transitions. [2024-11-08 18:05:22,833 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-08 18:05:22,833 INFO L218 hiAutomatonCegarLoop]: Abstraction has 388 states and 484 transitions. [2024-11-08 18:05:22,834 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 388 states and 484 transitions. [2024-11-08 18:05:22,837 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 388 to 387. [2024-11-08 18:05:22,838 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 387 states, 387 states have (on average 1.248062015503876) internal successors, (483), 386 states have internal predecessors, (483), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 18:05:22,839 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 387 states to 387 states and 483 transitions. [2024-11-08 18:05:22,839 INFO L240 hiAutomatonCegarLoop]: Abstraction has 387 states and 483 transitions. [2024-11-08 18:05:22,841 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 96 states. [2024-11-08 18:05:22,843 INFO L425 stractBuchiCegarLoop]: Abstraction has 387 states and 483 transitions. [2024-11-08 18:05:22,843 INFO L332 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2024-11-08 18:05:22,844 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 387 states and 483 transitions. [2024-11-08 18:05:22,845 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2024-11-08 18:05:22,846 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 18:05:22,846 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 18:05:22,848 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [95, 94, 1, 1, 1, 1, 1] [2024-11-08 18:05:22,852 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2024-11-08 18:05:22,852 INFO L745 eck$LassoCheckResult]: Stem: 14794#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 14795#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~post2#1, main_#t~nondet3#1, main_#t~post4#1, main_#t~post5#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 14798#L26 main_~i~0#1 := 0; 14799#L29-2 havoc main_#t~nondet1#1; 14792#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14793#L29-2 havoc main_#t~nondet1#1; 14803#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14990#L29-2 havoc main_#t~nondet1#1; 14989#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14988#L29-2 havoc main_#t~nondet1#1; 14987#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14986#L29-2 havoc main_#t~nondet1#1; 14985#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14984#L29-2 havoc main_#t~nondet1#1; 14983#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14982#L29-2 havoc main_#t~nondet1#1; 14981#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14980#L29-2 havoc main_#t~nondet1#1; 14979#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14978#L29-2 havoc main_#t~nondet1#1; 14977#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14976#L29-2 havoc main_#t~nondet1#1; 14975#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14974#L29-2 havoc main_#t~nondet1#1; 14973#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14972#L29-2 havoc main_#t~nondet1#1; 14971#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14970#L29-2 havoc main_#t~nondet1#1; 14969#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14968#L29-2 havoc main_#t~nondet1#1; 14967#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14966#L29-2 havoc main_#t~nondet1#1; 14965#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14964#L29-2 havoc main_#t~nondet1#1; 14963#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14962#L29-2 havoc main_#t~nondet1#1; 14961#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14960#L29-2 havoc main_#t~nondet1#1; 14959#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14958#L29-2 havoc main_#t~nondet1#1; 14957#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14956#L29-2 havoc main_#t~nondet1#1; 14955#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14954#L29-2 havoc main_#t~nondet1#1; 14953#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14952#L29-2 havoc main_#t~nondet1#1; 14951#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14950#L29-2 havoc main_#t~nondet1#1; 14949#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14948#L29-2 havoc main_#t~nondet1#1; 14947#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14946#L29-2 havoc main_#t~nondet1#1; 14945#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14944#L29-2 havoc main_#t~nondet1#1; 14943#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14942#L29-2 havoc main_#t~nondet1#1; 14941#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14940#L29-2 havoc main_#t~nondet1#1; 14939#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14938#L29-2 havoc main_#t~nondet1#1; 14937#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14936#L29-2 havoc main_#t~nondet1#1; 14935#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14934#L29-2 havoc main_#t~nondet1#1; 14933#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14932#L29-2 havoc main_#t~nondet1#1; 14931#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14930#L29-2 havoc main_#t~nondet1#1; 14929#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14928#L29-2 havoc main_#t~nondet1#1; 14927#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14926#L29-2 havoc main_#t~nondet1#1; 14925#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14924#L29-2 havoc main_#t~nondet1#1; 14923#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14922#L29-2 havoc main_#t~nondet1#1; 14921#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14920#L29-2 havoc main_#t~nondet1#1; 14919#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14918#L29-2 havoc main_#t~nondet1#1; 14917#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14916#L29-2 havoc main_#t~nondet1#1; 14915#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14914#L29-2 havoc main_#t~nondet1#1; 14913#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14912#L29-2 havoc main_#t~nondet1#1; 14911#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14910#L29-2 havoc main_#t~nondet1#1; 14909#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14908#L29-2 havoc main_#t~nondet1#1; 14907#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14906#L29-2 havoc main_#t~nondet1#1; 14905#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14904#L29-2 havoc main_#t~nondet1#1; 14903#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14902#L29-2 havoc main_#t~nondet1#1; 14901#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14900#L29-2 havoc main_#t~nondet1#1; 14899#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14898#L29-2 havoc main_#t~nondet1#1; 14897#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14896#L29-2 havoc main_#t~nondet1#1; 14895#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14894#L29-2 havoc main_#t~nondet1#1; 14893#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14892#L29-2 havoc main_#t~nondet1#1; 14891#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14890#L29-2 havoc main_#t~nondet1#1; 14889#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14888#L29-2 havoc main_#t~nondet1#1; 14887#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14886#L29-2 havoc main_#t~nondet1#1; 14885#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14884#L29-2 havoc main_#t~nondet1#1; 14883#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14882#L29-2 havoc main_#t~nondet1#1; 14881#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14880#L29-2 havoc main_#t~nondet1#1; 14879#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14878#L29-2 havoc main_#t~nondet1#1; 14877#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14876#L29-2 havoc main_#t~nondet1#1; 14875#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14874#L29-2 havoc main_#t~nondet1#1; 14873#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14872#L29-2 havoc main_#t~nondet1#1; 14871#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14870#L29-2 havoc main_#t~nondet1#1; 14869#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14868#L29-2 havoc main_#t~nondet1#1; 14867#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14866#L29-2 havoc main_#t~nondet1#1; 14865#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14864#L29-2 havoc main_#t~nondet1#1; 14863#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14862#L29-2 havoc main_#t~nondet1#1; 14861#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14860#L29-2 havoc main_#t~nondet1#1; 14859#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14858#L29-2 havoc main_#t~nondet1#1; 14857#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14856#L29-2 havoc main_#t~nondet1#1; 14855#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14854#L29-2 havoc main_#t~nondet1#1; 14853#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14852#L29-2 havoc main_#t~nondet1#1; 14851#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14850#L29-2 havoc main_#t~nondet1#1; 14849#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14848#L29-2 havoc main_#t~nondet1#1; 14847#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14846#L29-2 havoc main_#t~nondet1#1; 14845#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14844#L29-2 havoc main_#t~nondet1#1; 14843#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14842#L29-2 havoc main_#t~nondet1#1; 14841#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14840#L29-2 havoc main_#t~nondet1#1; 14839#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14838#L29-2 havoc main_#t~nondet1#1; 14837#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14836#L29-2 havoc main_#t~nondet1#1; 14835#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14834#L29-2 havoc main_#t~nondet1#1; 14833#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14832#L29-2 havoc main_#t~nondet1#1; 14831#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14830#L29-2 havoc main_#t~nondet1#1; 14829#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14828#L29-2 havoc main_#t~nondet1#1; 14827#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14826#L29-2 havoc main_#t~nondet1#1; 14825#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14824#L29-2 havoc main_#t~nondet1#1; 14823#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14822#L29-2 havoc main_#t~nondet1#1; 14821#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14820#L29-2 havoc main_#t~nondet1#1; 14819#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14818#L29-2 havoc main_#t~nondet1#1; 14817#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14816#L29-2 havoc main_#t~nondet1#1; 14815#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14814#L29-2 havoc main_#t~nondet1#1; 14813#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14812#L29-2 havoc main_#t~nondet1#1; 14811#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14810#L29-2 havoc main_#t~nondet1#1; 14809#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14808#L29-2 havoc main_#t~nondet1#1; 14807#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14806#L29-2 havoc main_#t~nondet1#1; 14791#L29 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 14787#L29-3 assume main_~i~0#1 >= 100; 14788#L32 [2024-11-08 18:05:22,853 INFO L747 eck$LassoCheckResult]: Loop: 14788#L32 assume true; 14788#L32 [2024-11-08 18:05:22,853 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:05:22,853 INFO L85 PathProgramCache]: Analyzing trace with hash -1026513191, now seen corresponding path program 6 times [2024-11-08 18:05:22,853 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 18:05:22,853 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [381958992] [2024-11-08 18:05:22,853 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:05:22,853 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 18:05:22,921 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 18:05:28,406 INFO L134 CoverageAnalysis]: Checked inductivity of 8930 backedges. 0 proven. 8930 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 18:05:28,406 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 18:05:28,406 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [381958992] [2024-11-08 18:05:28,406 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [381958992] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-08 18:05:28,406 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [912490364] [2024-11-08 18:05:28,407 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2024-11-08 18:05:28,407 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-08 18:05:28,407 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8264667-cc34-41ae-a2e3-109642306c6c/bin/uautomizer-verify-jihMAELWvX/z3 [2024-11-08 18:05:28,409 INFO L229 MonitoredProcess]: Starting monitored process 16 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8264667-cc34-41ae-a2e3-109642306c6c/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-08 18:05:28,410 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8264667-cc34-41ae-a2e3-109642306c6c/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (16)] Waiting until timeout for monitored process [2024-11-08 18:05:28,588 INFO L227 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 95 check-sat command(s) [2024-11-08 18:05:28,588 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-08 18:05:28,592 INFO L255 TraceCheckSpWp]: Trace formula consists of 493 conjuncts, 96 conjuncts are in the unsatisfiable core [2024-11-08 18:05:28,597 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-08 18:05:28,956 INFO L134 CoverageAnalysis]: Checked inductivity of 8930 backedges. 0 proven. 8930 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 18:05:28,956 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-08 18:05:33,888 INFO L134 CoverageAnalysis]: Checked inductivity of 8930 backedges. 0 proven. 8930 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 18:05:33,888 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [912490364] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-08 18:05:33,888 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-08 18:05:33,889 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [96, 96, 96] total 102 [2024-11-08 18:05:33,889 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1159609624] [2024-11-08 18:05:33,889 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-08 18:05:33,890 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 18:05:33,891 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:05:33,891 INFO L85 PathProgramCache]: Analyzing trace with hash 91, now seen corresponding path program 13 times [2024-11-08 18:05:33,891 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 18:05:33,891 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1920594437] [2024-11-08 18:05:33,891 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:05:33,892 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 18:05:33,893 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:05:33,893 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 18:05:33,894 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:05:33,894 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 18:05:33,896 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 18:05:33,897 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 103 interpolants. [2024-11-08 18:05:33,899 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5253, Invalid=5253, Unknown=0, NotChecked=0, Total=10506 [2024-11-08 18:05:33,900 INFO L87 Difference]: Start difference. First operand 387 states and 483 transitions. cyclomatic complexity: 99 Second operand has 103 states, 102 states have (on average 2.0588235294117645) internal successors, (210), 103 states have internal predecessors, (210), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 18:05:36,785 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 18:05:36,785 INFO L93 Difference]: Finished difference Result 10592 states and 10701 transitions. [2024-11-08 18:05:36,786 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10592 states and 10701 transitions. [2024-11-08 18:05:36,861 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 7 [2024-11-08 18:05:36,896 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10592 states to 10580 states and 10689 transitions. [2024-11-08 18:05:36,897 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27 [2024-11-08 18:05:36,897 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 27 [2024-11-08 18:05:36,897 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10580 states and 10689 transitions. [2024-11-08 18:05:36,906 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-08 18:05:36,906 INFO L218 hiAutomatonCegarLoop]: Abstraction has 10580 states and 10689 transitions. [2024-11-08 18:05:36,915 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10580 states and 10689 transitions. [2024-11-08 18:05:36,956 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10580 to 399. [2024-11-08 18:05:36,957 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 399 states, 399 states have (on average 1.255639097744361) internal successors, (501), 398 states have internal predecessors, (501), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 18:05:36,958 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 399 states to 399 states and 501 transitions. [2024-11-08 18:05:36,958 INFO L240 hiAutomatonCegarLoop]: Abstraction has 399 states and 501 transitions. [2024-11-08 18:05:36,962 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 102 states. [2024-11-08 18:05:36,962 INFO L425 stractBuchiCegarLoop]: Abstraction has 399 states and 501 transitions. [2024-11-08 18:05:36,963 INFO L332 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2024-11-08 18:05:36,963 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 399 states and 501 transitions. [2024-11-08 18:05:36,965 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2024-11-08 18:05:36,965 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 18:05:36,965 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 18:05:36,967 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [95, 94, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 18:05:36,967 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2024-11-08 18:05:36,967 INFO L745 eck$LassoCheckResult]: Stem: 27034#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 27035#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~post2#1, main_#t~nondet3#1, main_#t~post4#1, main_#t~post5#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 27040#L26 main_~i~0#1 := 0; 27041#L29-2 havoc main_#t~nondet1#1; 27043#L29 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 27032#L29-3 assume !(main_~i~0#1 >= 100);main_~j~0#1 := 0; 27033#L35-2 havoc main_#t~nondet3#1; 27039#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27046#L35-2 havoc main_#t~nondet3#1; 27428#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27427#L35-2 havoc main_#t~nondet3#1; 27426#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27425#L35-2 havoc main_#t~nondet3#1; 27424#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27423#L35-2 havoc main_#t~nondet3#1; 27422#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27421#L35-2 havoc main_#t~nondet3#1; 27420#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27419#L35-2 havoc main_#t~nondet3#1; 27418#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27417#L35-2 havoc main_#t~nondet3#1; 27416#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27415#L35-2 havoc main_#t~nondet3#1; 27414#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27413#L35-2 havoc main_#t~nondet3#1; 27412#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27411#L35-2 havoc main_#t~nondet3#1; 27410#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27409#L35-2 havoc main_#t~nondet3#1; 27408#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27407#L35-2 havoc main_#t~nondet3#1; 27406#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27405#L35-2 havoc main_#t~nondet3#1; 27404#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27403#L35-2 havoc main_#t~nondet3#1; 27402#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27401#L35-2 havoc main_#t~nondet3#1; 27400#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27399#L35-2 havoc main_#t~nondet3#1; 27398#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27397#L35-2 havoc main_#t~nondet3#1; 27396#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27395#L35-2 havoc main_#t~nondet3#1; 27394#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27393#L35-2 havoc main_#t~nondet3#1; 27392#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27391#L35-2 havoc main_#t~nondet3#1; 27390#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27389#L35-2 havoc main_#t~nondet3#1; 27388#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27387#L35-2 havoc main_#t~nondet3#1; 27386#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27385#L35-2 havoc main_#t~nondet3#1; 27384#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27383#L35-2 havoc main_#t~nondet3#1; 27382#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27381#L35-2 havoc main_#t~nondet3#1; 27380#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27379#L35-2 havoc main_#t~nondet3#1; 27378#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27377#L35-2 havoc main_#t~nondet3#1; 27376#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27375#L35-2 havoc main_#t~nondet3#1; 27374#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27373#L35-2 havoc main_#t~nondet3#1; 27372#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27371#L35-2 havoc main_#t~nondet3#1; 27370#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27369#L35-2 havoc main_#t~nondet3#1; 27368#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27367#L35-2 havoc main_#t~nondet3#1; 27366#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27365#L35-2 havoc main_#t~nondet3#1; 27364#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27363#L35-2 havoc main_#t~nondet3#1; 27362#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27361#L35-2 havoc main_#t~nondet3#1; 27360#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27359#L35-2 havoc main_#t~nondet3#1; 27358#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27357#L35-2 havoc main_#t~nondet3#1; 27356#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27355#L35-2 havoc main_#t~nondet3#1; 27354#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27353#L35-2 havoc main_#t~nondet3#1; 27352#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27351#L35-2 havoc main_#t~nondet3#1; 27350#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27349#L35-2 havoc main_#t~nondet3#1; 27348#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27347#L35-2 havoc main_#t~nondet3#1; 27346#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27345#L35-2 havoc main_#t~nondet3#1; 27344#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27343#L35-2 havoc main_#t~nondet3#1; 27342#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27341#L35-2 havoc main_#t~nondet3#1; 27340#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27339#L35-2 havoc main_#t~nondet3#1; 27338#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27337#L35-2 havoc main_#t~nondet3#1; 27336#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27335#L35-2 havoc main_#t~nondet3#1; 27334#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27333#L35-2 havoc main_#t~nondet3#1; 27332#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27331#L35-2 havoc main_#t~nondet3#1; 27330#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27329#L35-2 havoc main_#t~nondet3#1; 27328#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27327#L35-2 havoc main_#t~nondet3#1; 27326#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27325#L35-2 havoc main_#t~nondet3#1; 27324#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27323#L35-2 havoc main_#t~nondet3#1; 27322#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27321#L35-2 havoc main_#t~nondet3#1; 27320#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27319#L35-2 havoc main_#t~nondet3#1; 27318#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27317#L35-2 havoc main_#t~nondet3#1; 27316#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27315#L35-2 havoc main_#t~nondet3#1; 27314#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27313#L35-2 havoc main_#t~nondet3#1; 27312#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27311#L35-2 havoc main_#t~nondet3#1; 27310#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27309#L35-2 havoc main_#t~nondet3#1; 27308#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27307#L35-2 havoc main_#t~nondet3#1; 27306#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27305#L35-2 havoc main_#t~nondet3#1; 27304#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27303#L35-2 havoc main_#t~nondet3#1; 27302#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27301#L35-2 havoc main_#t~nondet3#1; 27300#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27299#L35-2 havoc main_#t~nondet3#1; 27298#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27297#L35-2 havoc main_#t~nondet3#1; 27296#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27295#L35-2 havoc main_#t~nondet3#1; 27294#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27293#L35-2 havoc main_#t~nondet3#1; 27292#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27291#L35-2 havoc main_#t~nondet3#1; 27290#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27289#L35-2 havoc main_#t~nondet3#1; 27288#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27287#L35-2 havoc main_#t~nondet3#1; 27286#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27285#L35-2 havoc main_#t~nondet3#1; 27284#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27283#L35-2 havoc main_#t~nondet3#1; 27282#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27281#L35-2 havoc main_#t~nondet3#1; 27280#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27279#L35-2 havoc main_#t~nondet3#1; 27278#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27277#L35-2 havoc main_#t~nondet3#1; 27276#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27275#L35-2 havoc main_#t~nondet3#1; 27274#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27273#L35-2 havoc main_#t~nondet3#1; 27272#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27271#L35-2 havoc main_#t~nondet3#1; 27270#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27269#L35-2 havoc main_#t~nondet3#1; 27268#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27267#L35-2 havoc main_#t~nondet3#1; 27266#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27265#L35-2 havoc main_#t~nondet3#1; 27264#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27263#L35-2 havoc main_#t~nondet3#1; 27262#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27261#L35-2 havoc main_#t~nondet3#1; 27260#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27259#L35-2 havoc main_#t~nondet3#1; 27258#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27257#L35-2 havoc main_#t~nondet3#1; 27256#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27255#L35-2 havoc main_#t~nondet3#1; 27254#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27253#L35-2 havoc main_#t~nondet3#1; 27252#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27251#L35-2 havoc main_#t~nondet3#1; 27250#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27249#L35-2 havoc main_#t~nondet3#1; 27248#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27247#L35-2 havoc main_#t~nondet3#1; 27246#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27245#L35-2 havoc main_#t~nondet3#1; 27244#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27243#L35-2 havoc main_#t~nondet3#1; 27045#L35 assume !(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1; 27042#L35-3 assume main_~j~0#1 >= 100; 27031#L32 [2024-11-08 18:05:36,968 INFO L747 eck$LassoCheckResult]: Loop: 27031#L32 assume true; 27031#L32 [2024-11-08 18:05:36,968 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:05:36,968 INFO L85 PathProgramCache]: Analyzing trace with hash -510020486, now seen corresponding path program 6 times [2024-11-08 18:05:36,968 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 18:05:36,968 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [195269477] [2024-11-08 18:05:36,968 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:05:36,969 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 18:05:37,073 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 18:05:42,660 INFO L134 CoverageAnalysis]: Checked inductivity of 8930 backedges. 0 proven. 8930 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 18:05:42,660 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 18:05:42,661 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [195269477] [2024-11-08 18:05:42,661 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [195269477] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-08 18:05:42,661 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [83803840] [2024-11-08 18:05:42,661 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2024-11-08 18:05:42,661 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-08 18:05:42,662 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8264667-cc34-41ae-a2e3-109642306c6c/bin/uautomizer-verify-jihMAELWvX/z3 [2024-11-08 18:05:42,664 INFO L229 MonitoredProcess]: Starting monitored process 17 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8264667-cc34-41ae-a2e3-109642306c6c/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-08 18:05:42,670 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8264667-cc34-41ae-a2e3-109642306c6c/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (17)] Waiting until timeout for monitored process [2024-11-08 18:05:42,926 INFO L227 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 95 check-sat command(s) [2024-11-08 18:05:42,926 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-08 18:05:42,930 INFO L255 TraceCheckSpWp]: Trace formula consists of 686 conjuncts, 96 conjuncts are in the unsatisfiable core [2024-11-08 18:05:42,936 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-08 18:05:43,295 INFO L134 CoverageAnalysis]: Checked inductivity of 8930 backedges. 0 proven. 8930 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 18:05:43,295 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-08 18:05:47,903 INFO L134 CoverageAnalysis]: Checked inductivity of 8930 backedges. 0 proven. 8930 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 18:05:47,903 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [83803840] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-08 18:05:47,904 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-08 18:05:47,904 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [96, 96, 96] total 102 [2024-11-08 18:05:47,904 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1969753855] [2024-11-08 18:05:47,904 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-08 18:05:47,905 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 18:05:47,905 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:05:47,905 INFO L85 PathProgramCache]: Analyzing trace with hash 91, now seen corresponding path program 14 times [2024-11-08 18:05:47,905 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 18:05:47,905 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1417757604] [2024-11-08 18:05:47,906 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:05:47,906 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 18:05:47,908 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:05:47,908 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 18:05:47,908 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:05:47,909 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 18:05:47,911 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 18:05:47,913 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 103 interpolants. [2024-11-08 18:05:47,915 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5253, Invalid=5253, Unknown=0, NotChecked=0, Total=10506 [2024-11-08 18:05:47,916 INFO L87 Difference]: Start difference. First operand 399 states and 501 transitions. cyclomatic complexity: 105 Second operand has 103 states, 102 states have (on average 2.088235294117647) internal successors, (213), 103 states have internal predecessors, (213), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 18:05:48,083 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 18:05:48,083 INFO L93 Difference]: Finished difference Result 424 states and 526 transitions. [2024-11-08 18:05:48,083 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 424 states and 526 transitions. [2024-11-08 18:05:48,085 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2024-11-08 18:05:48,087 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 424 states to 412 states and 514 transitions. [2024-11-08 18:05:48,087 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9 [2024-11-08 18:05:48,087 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9 [2024-11-08 18:05:48,087 INFO L73 IsDeterministic]: Start isDeterministic. Operand 412 states and 514 transitions. [2024-11-08 18:05:48,088 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-08 18:05:48,088 INFO L218 hiAutomatonCegarLoop]: Abstraction has 412 states and 514 transitions. [2024-11-08 18:05:48,088 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 412 states and 514 transitions. [2024-11-08 18:05:48,093 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 412 to 411. [2024-11-08 18:05:48,096 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 411 states, 411 states have (on average 1.2481751824817517) internal successors, (513), 410 states have internal predecessors, (513), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 18:05:48,097 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 411 states to 411 states and 513 transitions. [2024-11-08 18:05:48,097 INFO L240 hiAutomatonCegarLoop]: Abstraction has 411 states and 513 transitions. [2024-11-08 18:05:48,098 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 102 states. [2024-11-08 18:05:48,098 INFO L425 stractBuchiCegarLoop]: Abstraction has 411 states and 513 transitions. [2024-11-08 18:05:48,099 INFO L332 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2024-11-08 18:05:48,100 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 411 states and 513 transitions. [2024-11-08 18:05:48,101 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2024-11-08 18:05:48,101 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 18:05:48,101 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 18:05:48,104 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [101, 100, 1, 1, 1, 1, 1] [2024-11-08 18:05:48,104 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2024-11-08 18:05:48,104 INFO L745 eck$LassoCheckResult]: Stem: 29139#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 29140#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~post2#1, main_#t~nondet3#1, main_#t~post4#1, main_#t~post5#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 29146#L26 main_~i~0#1 := 0; 29147#L29-2 havoc main_#t~nondet1#1; 29142#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29143#L29-2 havoc main_#t~nondet1#1; 29149#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29350#L29-2 havoc main_#t~nondet1#1; 29349#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29348#L29-2 havoc main_#t~nondet1#1; 29347#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29346#L29-2 havoc main_#t~nondet1#1; 29345#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29344#L29-2 havoc main_#t~nondet1#1; 29343#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29342#L29-2 havoc main_#t~nondet1#1; 29341#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29340#L29-2 havoc main_#t~nondet1#1; 29339#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29338#L29-2 havoc main_#t~nondet1#1; 29337#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29336#L29-2 havoc main_#t~nondet1#1; 29335#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29334#L29-2 havoc main_#t~nondet1#1; 29333#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29332#L29-2 havoc main_#t~nondet1#1; 29331#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29330#L29-2 havoc main_#t~nondet1#1; 29329#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29328#L29-2 havoc main_#t~nondet1#1; 29327#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29326#L29-2 havoc main_#t~nondet1#1; 29325#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29324#L29-2 havoc main_#t~nondet1#1; 29323#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29322#L29-2 havoc main_#t~nondet1#1; 29321#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29320#L29-2 havoc main_#t~nondet1#1; 29319#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29318#L29-2 havoc main_#t~nondet1#1; 29317#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29316#L29-2 havoc main_#t~nondet1#1; 29315#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29314#L29-2 havoc main_#t~nondet1#1; 29313#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29312#L29-2 havoc main_#t~nondet1#1; 29311#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29310#L29-2 havoc main_#t~nondet1#1; 29309#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29308#L29-2 havoc main_#t~nondet1#1; 29307#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29306#L29-2 havoc main_#t~nondet1#1; 29305#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29304#L29-2 havoc main_#t~nondet1#1; 29303#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29302#L29-2 havoc main_#t~nondet1#1; 29301#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29300#L29-2 havoc main_#t~nondet1#1; 29299#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29298#L29-2 havoc main_#t~nondet1#1; 29297#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29296#L29-2 havoc main_#t~nondet1#1; 29295#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29294#L29-2 havoc main_#t~nondet1#1; 29293#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29292#L29-2 havoc main_#t~nondet1#1; 29291#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29290#L29-2 havoc main_#t~nondet1#1; 29289#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29288#L29-2 havoc main_#t~nondet1#1; 29287#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29286#L29-2 havoc main_#t~nondet1#1; 29285#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29284#L29-2 havoc main_#t~nondet1#1; 29283#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29282#L29-2 havoc main_#t~nondet1#1; 29281#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29280#L29-2 havoc main_#t~nondet1#1; 29279#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29278#L29-2 havoc main_#t~nondet1#1; 29277#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29276#L29-2 havoc main_#t~nondet1#1; 29275#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29274#L29-2 havoc main_#t~nondet1#1; 29273#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29272#L29-2 havoc main_#t~nondet1#1; 29271#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29270#L29-2 havoc main_#t~nondet1#1; 29269#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29268#L29-2 havoc main_#t~nondet1#1; 29267#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29266#L29-2 havoc main_#t~nondet1#1; 29265#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29264#L29-2 havoc main_#t~nondet1#1; 29263#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29262#L29-2 havoc main_#t~nondet1#1; 29261#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29260#L29-2 havoc main_#t~nondet1#1; 29259#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29258#L29-2 havoc main_#t~nondet1#1; 29257#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29256#L29-2 havoc main_#t~nondet1#1; 29255#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29254#L29-2 havoc main_#t~nondet1#1; 29253#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29252#L29-2 havoc main_#t~nondet1#1; 29251#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29250#L29-2 havoc main_#t~nondet1#1; 29249#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29248#L29-2 havoc main_#t~nondet1#1; 29247#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29246#L29-2 havoc main_#t~nondet1#1; 29245#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29244#L29-2 havoc main_#t~nondet1#1; 29243#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29242#L29-2 havoc main_#t~nondet1#1; 29241#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29240#L29-2 havoc main_#t~nondet1#1; 29239#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29238#L29-2 havoc main_#t~nondet1#1; 29237#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29236#L29-2 havoc main_#t~nondet1#1; 29235#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29234#L29-2 havoc main_#t~nondet1#1; 29233#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29232#L29-2 havoc main_#t~nondet1#1; 29231#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29230#L29-2 havoc main_#t~nondet1#1; 29229#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29228#L29-2 havoc main_#t~nondet1#1; 29227#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29226#L29-2 havoc main_#t~nondet1#1; 29225#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29224#L29-2 havoc main_#t~nondet1#1; 29223#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29222#L29-2 havoc main_#t~nondet1#1; 29221#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29220#L29-2 havoc main_#t~nondet1#1; 29219#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29218#L29-2 havoc main_#t~nondet1#1; 29217#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29216#L29-2 havoc main_#t~nondet1#1; 29215#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29214#L29-2 havoc main_#t~nondet1#1; 29213#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29212#L29-2 havoc main_#t~nondet1#1; 29211#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29210#L29-2 havoc main_#t~nondet1#1; 29209#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29208#L29-2 havoc main_#t~nondet1#1; 29207#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29206#L29-2 havoc main_#t~nondet1#1; 29205#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29204#L29-2 havoc main_#t~nondet1#1; 29203#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29202#L29-2 havoc main_#t~nondet1#1; 29201#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29200#L29-2 havoc main_#t~nondet1#1; 29199#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29198#L29-2 havoc main_#t~nondet1#1; 29197#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29196#L29-2 havoc main_#t~nondet1#1; 29195#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29194#L29-2 havoc main_#t~nondet1#1; 29193#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29192#L29-2 havoc main_#t~nondet1#1; 29191#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29190#L29-2 havoc main_#t~nondet1#1; 29189#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29188#L29-2 havoc main_#t~nondet1#1; 29187#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29186#L29-2 havoc main_#t~nondet1#1; 29185#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29184#L29-2 havoc main_#t~nondet1#1; 29183#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29182#L29-2 havoc main_#t~nondet1#1; 29181#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29180#L29-2 havoc main_#t~nondet1#1; 29179#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29178#L29-2 havoc main_#t~nondet1#1; 29177#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29176#L29-2 havoc main_#t~nondet1#1; 29175#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29174#L29-2 havoc main_#t~nondet1#1; 29173#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29172#L29-2 havoc main_#t~nondet1#1; 29171#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29170#L29-2 havoc main_#t~nondet1#1; 29169#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29168#L29-2 havoc main_#t~nondet1#1; 29167#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29166#L29-2 havoc main_#t~nondet1#1; 29165#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29164#L29-2 havoc main_#t~nondet1#1; 29163#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29162#L29-2 havoc main_#t~nondet1#1; 29161#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29160#L29-2 havoc main_#t~nondet1#1; 29157#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29156#L29-2 havoc main_#t~nondet1#1; 29155#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29154#L29-2 havoc main_#t~nondet1#1; 29153#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29152#L29-2 havoc main_#t~nondet1#1; 29141#L29 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 29135#L29-3 assume main_~i~0#1 >= 100; 29136#L32 [2024-11-08 18:05:48,105 INFO L747 eck$LassoCheckResult]: Loop: 29136#L32 assume true; 29136#L32 [2024-11-08 18:05:48,105 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:05:48,105 INFO L85 PathProgramCache]: Analyzing trace with hash -880636613, now seen corresponding path program 7 times [2024-11-08 18:05:48,105 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 18:05:48,106 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [749228647] [2024-11-08 18:05:48,106 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:05:48,106 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 18:05:48,163 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:05:48,163 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 18:05:48,218 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:05:48,238 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 18:05:48,239 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:05:48,239 INFO L85 PathProgramCache]: Analyzing trace with hash 91, now seen corresponding path program 15 times [2024-11-08 18:05:48,239 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 18:05:48,239 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2135321298] [2024-11-08 18:05:48,239 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:05:48,239 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 18:05:48,240 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:05:48,241 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 18:05:48,244 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:05:48,245 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 18:05:48,245 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 18:05:48,245 INFO L85 PathProgramCache]: Analyzing trace with hash -1529931167, now seen corresponding path program 1 times [2024-11-08 18:05:48,245 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 18:05:48,246 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1002694320] [2024-11-08 18:05:48,246 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 18:05:48,246 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 18:05:48,313 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:05:48,315 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 18:05:48,366 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:05:48,377 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 18:05:55,553 WARN L286 SmtUtils]: Spent 7.11s on a formula simplification. DAG size of input: 735 DAG size of output: 630 (called from [L 276] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.cfg.transitions.TransFormulaUtils.sequentialComposition) [2024-11-08 18:06:00,725 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:06:00,725 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 18:06:00,803 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 18:06:01,011 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 08.11 06:06:01 BoogieIcfgContainer [2024-11-08 18:06:01,011 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2024-11-08 18:06:01,011 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2024-11-08 18:06:01,011 INFO L270 PluginConnector]: Initializing Witness Printer... [2024-11-08 18:06:01,012 INFO L274 PluginConnector]: Witness Printer initialized [2024-11-08 18:06:01,013 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 08.11 06:05:00" (3/4) ... [2024-11-08 18:06:01,015 INFO L139 WitnessPrinter]: Generating witness for non-termination counterexample [2024-11-08 18:06:01,097 INFO L149 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8264667-cc34-41ae-a2e3-109642306c6c/bin/uautomizer-verify-jihMAELWvX/witness.graphml [2024-11-08 18:06:01,097 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2024-11-08 18:06:01,098 INFO L158 Benchmark]: Toolchain (without parser) took 61422.65ms. Allocated memory was 142.6MB in the beginning and 482.3MB in the end (delta: 339.7MB). Free memory was 105.4MB in the beginning and 409.5MB in the end (delta: -304.2MB). Peak memory consumption was 37.6MB. Max. memory is 16.1GB. [2024-11-08 18:06:01,098 INFO L158 Benchmark]: CDTParser took 0.28ms. Allocated memory is still 142.6MB. Free memory was 88.4MB in the beginning and 88.2MB in the end (delta: 178.3kB). There was no memory consumed. Max. memory is 16.1GB. [2024-11-08 18:06:01,099 INFO L158 Benchmark]: CACSL2BoogieTranslator took 346.08ms. Allocated memory is still 142.6MB. Free memory was 104.9MB in the beginning and 92.8MB in the end (delta: 12.1MB). Peak memory consumption was 12.6MB. Max. memory is 16.1GB. [2024-11-08 18:06:01,099 INFO L158 Benchmark]: Boogie Procedure Inliner took 33.45ms. Allocated memory is still 142.6MB. Free memory was 92.8MB in the beginning and 91.2MB in the end (delta: 1.6MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2024-11-08 18:06:01,099 INFO L158 Benchmark]: Boogie Preprocessor took 43.49ms. Allocated memory is still 142.6MB. Free memory was 91.2MB in the beginning and 89.8MB in the end (delta: 1.4MB). There was no memory consumed. Max. memory is 16.1GB. [2024-11-08 18:06:01,100 INFO L158 Benchmark]: RCFGBuilder took 264.13ms. Allocated memory is still 142.6MB. Free memory was 89.8MB in the beginning and 79.8MB in the end (delta: 10.0MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. [2024-11-08 18:06:01,100 INFO L158 Benchmark]: BuchiAutomizer took 60645.24ms. Allocated memory was 142.6MB in the beginning and 482.3MB in the end (delta: 339.7MB). Free memory was 79.3MB in the beginning and 415.8MB in the end (delta: -336.5MB). Peak memory consumption was 6.1MB. Max. memory is 16.1GB. [2024-11-08 18:06:01,101 INFO L158 Benchmark]: Witness Printer took 85.79ms. Allocated memory is still 482.3MB. Free memory was 415.8MB in the beginning and 409.5MB in the end (delta: 6.3MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. [2024-11-08 18:06:01,102 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.28ms. Allocated memory is still 142.6MB. Free memory was 88.4MB in the beginning and 88.2MB in the end (delta: 178.3kB). There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 346.08ms. Allocated memory is still 142.6MB. Free memory was 104.9MB in the beginning and 92.8MB in the end (delta: 12.1MB). Peak memory consumption was 12.6MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 33.45ms. Allocated memory is still 142.6MB. Free memory was 92.8MB in the beginning and 91.2MB in the end (delta: 1.6MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * Boogie Preprocessor took 43.49ms. Allocated memory is still 142.6MB. Free memory was 91.2MB in the beginning and 89.8MB in the end (delta: 1.4MB). There was no memory consumed. Max. memory is 16.1GB. * RCFGBuilder took 264.13ms. Allocated memory is still 142.6MB. Free memory was 89.8MB in the beginning and 79.8MB in the end (delta: 10.0MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. * BuchiAutomizer took 60645.24ms. Allocated memory was 142.6MB in the beginning and 482.3MB in the end (delta: 339.7MB). Free memory was 79.3MB in the beginning and 415.8MB in the end (delta: -336.5MB). Peak memory consumption was 6.1MB. Max. memory is 16.1GB. * Witness Printer took 85.79ms. Allocated memory is still 482.3MB. Free memory was 415.8MB in the beginning and 409.5MB in the end (delta: 6.3MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 15 terminating modules (14 trivial, 1 deterministic, 0 nondeterministic) and one nonterminating remainder module.One deterministic module has affine ranking function (((long long) -2 * i) + 1999999) and consists of 4 locations. 14 modules have a trivial ranking function, the largest among these consists of 103 locations. The remainder module has 411 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 60.4s and 16 iterations. TraceHistogramMax:101. Analysis of lassos took 52.1s. Construction of modules took 2.2s. Büchi inclusion checks took 5.8s. Highest rank in rank-based complementation 3. Minimization of det autom 0. Minimization of nondet autom 15. Automata minimization 0.2s AutomataMinimizationTime, 15 MinimizatonAttempts, 19320 StatesRemovedByMinimization, 15 NontrivialMinimizations. Non-live state removal took 0.2s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [1, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 4118 SdHoareTripleChecker+Valid, 2.8s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 4117 mSDsluCounter, 1576 SdHoareTripleChecker+Invalid, 2.3s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 1428 mSDsCounter, 1221 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 1672 IncrementalHoareTripleChecker+Invalid, 2893 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 1221 mSolverCounterUnsat, 148 mSDtfsCounter, 1672 mSolverCounterSat, 0.1s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI0 SFLT1 conc0 concLT0 SILN14 SILU0 SILI0 SILT0 lasso0 LassoPreprocessingBenchmarks: Lassos: inital10 mio100 ax100 hnf100 lsp100 ukn100 mio100 lsp100 div100 bol100 ite100 ukn100 eq160 hnf93 smp100 dnf100 smp100 tf113 neg100 sie100 LassoTerminationAnalysisBenchmarks: ConstraintsSatisfiability: sat Degree: 0 Time: 63ms VariablesStem: 0 VariablesLoop: 2 DisjunctsStem: 1 DisjunctsLoop: 1 SupportingInvariants: 0 MotzkinApplications: 2 LassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 1 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 24]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L25] int i, j; [L27] i = 0 VAL [i=0] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=1] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=2] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=3] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=4] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=5] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=6] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=7] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=8] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=9] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=10] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=11] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=12] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=13] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=14] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=15] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=16] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=17] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=18] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=19] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=20] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=21] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=22] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=23] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=24] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=25] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=26] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=27] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=28] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=29] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=30] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=31] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=32] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=33] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=34] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=35] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=36] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=37] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=38] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=39] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=40] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=41] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=42] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=43] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=44] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=45] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=46] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=47] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=48] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=49] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=50] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=51] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=52] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=53] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=54] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=55] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=56] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=57] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=58] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=59] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=60] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=61] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=62] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=63] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=64] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=65] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=66] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=67] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=68] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=69] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=70] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=71] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=72] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=73] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=74] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=75] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=76] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=77] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=78] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=79] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=80] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=81] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=82] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=83] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=84] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=85] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=86] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=87] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=88] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=89] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=90] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=91] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=92] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=93] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=94] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=95] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=96] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=97] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=98] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=99] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=100] [L29] COND FALSE !(__VERIFIER_nondet_int() && i < 1000000) [L32] COND TRUE i >= 100 Loop: [L32] STUCK: goto STUCK; End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 24]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L25] int i, j; [L27] i = 0 VAL [i=0] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=1] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=2] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=3] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=4] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=5] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=6] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=7] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=8] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=9] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=10] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=11] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=12] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=13] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=14] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=15] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=16] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=17] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=18] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=19] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=20] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=21] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=22] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=23] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=24] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=25] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=26] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=27] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=28] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=29] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=30] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=31] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=32] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=33] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=34] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=35] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=36] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=37] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=38] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=39] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=40] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=41] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=42] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=43] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=44] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=45] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=46] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=47] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=48] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=49] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=50] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=51] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=52] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=53] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=54] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=55] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=56] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=57] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=58] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=59] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=60] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=61] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=62] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=63] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=64] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=65] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=66] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=67] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=68] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=69] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=70] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=71] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=72] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=73] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=74] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=75] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=76] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=77] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=78] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=79] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=80] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=81] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=82] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=83] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=84] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=85] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=86] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=87] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=88] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=89] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=90] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=91] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=92] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=93] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=94] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=95] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=96] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=97] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=98] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=99] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=100] [L29] COND FALSE !(__VERIFIER_nondet_int() && i < 1000000) [L32] COND TRUE i >= 100 Loop: [L32] STUCK: goto STUCK; End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2024-11-08 18:06:01,153 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8264667-cc34-41ae-a2e3-109642306c6c/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (17)] Forceful destruction successful, exit code 0 [2024-11-08 18:06:01,342 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8264667-cc34-41ae-a2e3-109642306c6c/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (16)] Forceful destruction successful, exit code 0 [2024-11-08 18:06:01,542 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8264667-cc34-41ae-a2e3-109642306c6c/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Forceful destruction successful, exit code 0 [2024-11-08 18:06:01,745 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8264667-cc34-41ae-a2e3-109642306c6c/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Forceful destruction successful, exit code 0 [2024-11-08 18:06:01,945 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8264667-cc34-41ae-a2e3-109642306c6c/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Forceful destruction successful, exit code 0 [2024-11-08 18:06:02,145 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8264667-cc34-41ae-a2e3-109642306c6c/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Forceful destruction successful, exit code 0 [2024-11-08 18:06:02,345 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8264667-cc34-41ae-a2e3-109642306c6c/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Forceful destruction successful, exit code 0 [2024-11-08 18:06:02,553 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8264667-cc34-41ae-a2e3-109642306c6c/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Ended with exit code 0 [2024-11-08 18:06:02,754 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8264667-cc34-41ae-a2e3-109642306c6c/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Ended with exit code 0 [2024-11-08 18:06:02,945 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8264667-cc34-41ae-a2e3-109642306c6c/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Forceful destruction successful, exit code 0 [2024-11-08 18:06:03,146 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8264667-cc34-41ae-a2e3-109642306c6c/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Ended with exit code 0 [2024-11-08 18:06:03,345 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8264667-cc34-41ae-a2e3-109642306c6c/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Forceful destruction successful, exit code 0 [2024-11-08 18:06:03,542 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8264667-cc34-41ae-a2e3-109642306c6c/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Forceful destruction successful, exit code 0 [2024-11-08 18:06:03,748 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c8264667-cc34-41ae-a2e3-109642306c6c/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)