./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.07.cil.c --full-output --architecture 32bit
--------------------------------------------------------------------------------
Checking for termination
Using default analysis
Version a0165632
Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_84c3f80a-f186-401a-8c5e-005f63e9e38f/bin/uautomizer-verify-jihMAELWvX/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_84c3f80a-f186-401a-8c5e-005f63e9e38f/bin/uautomizer-verify-jihMAELWvX/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_84c3f80a-f186-401a-8c5e-005f63e9e38f/bin/uautomizer-verify-jihMAELWvX/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_84c3f80a-f186-401a-8c5e-005f63e9e38f/bin/uautomizer-verify-jihMAELWvX/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.07.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_84c3f80a-f186-401a-8c5e-005f63e9e38f/bin/uautomizer-verify-jihMAELWvX/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_84c3f80a-f186-401a-8c5e-005f63e9e38f/bin/uautomizer-verify-jihMAELWvX --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) )
--witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 022987cd4c8c671e376c5c3e5a08e2f1b98444b4d5d48bc73787bff74aa0de0f
--- Real Ultimate output ---
This is Ultimate 0.2.5-dev-a016563
[2024-11-08 18:32:21,856 INFO L188 SettingsManager]: Resetting all preferences to default values...
[2024-11-08 18:32:21,957 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_84c3f80a-f186-401a-8c5e-005f63e9e38f/bin/uautomizer-verify-jihMAELWvX/config/svcomp-Termination-32bit-Automizer_Default.epf
[2024-11-08 18:32:21,964 WARN L101 SettingsManager]: Preference file contains the following unknown settings:
[2024-11-08 18:32:21,965 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class
[2024-11-08 18:32:22,000 INFO L130 SettingsManager]: Preferences different from defaults after loading the file:
[2024-11-08 18:32:22,001 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults:
[2024-11-08 18:32:22,001 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR;
[2024-11-08 18:32:22,002 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults:
[2024-11-08 18:32:22,002 INFO L153 SettingsManager]: * Use memory slicer=true
[2024-11-08 18:32:22,002 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults:
[2024-11-08 18:32:22,003 INFO L153 SettingsManager]: * Create parallel compositions if possible=false
[2024-11-08 18:32:22,005 INFO L153 SettingsManager]: * Use SBE=true
[2024-11-08 18:32:22,007 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults:
[2024-11-08 18:32:22,008 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3
[2024-11-08 18:32:22,008 INFO L153 SettingsManager]: * Use old map elimination=false
[2024-11-08 18:32:22,008 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false
[2024-11-08 18:32:22,009 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true
[2024-11-08 18:32:22,009 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES
[2024-11-08 18:32:22,009 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults:
[2024-11-08 18:32:22,010 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME
[2024-11-08 18:32:22,016 INFO L153 SettingsManager]: * sizeof long=4
[2024-11-08 18:32:22,016 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true
[2024-11-08 18:32:22,017 INFO L153 SettingsManager]: * sizeof POINTER=4
[2024-11-08 18:32:22,017 INFO L153 SettingsManager]: * Check division by zero=IGNORE
[2024-11-08 18:32:22,017 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME
[2024-11-08 18:32:22,017 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME
[2024-11-08 18:32:22,018 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME
[2024-11-08 18:32:22,018 INFO L153 SettingsManager]: * Allow undefined functions=false
[2024-11-08 18:32:22,019 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false
[2024-11-08 18:32:22,020 INFO L153 SettingsManager]: * sizeof long double=12
[2024-11-08 18:32:22,020 INFO L153 SettingsManager]: * Check if freed pointer was valid=false
[2024-11-08 18:32:22,020 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false
[2024-11-08 18:32:22,021 INFO L153 SettingsManager]: * Use constant arrays=true
[2024-11-08 18:32:22,021 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults:
[2024-11-08 18:32:22,021 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements
[2024-11-08 18:32:22,021 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults:
[2024-11-08 18:32:22,022 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL
[2024-11-08 18:32:22,022 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults:
[2024-11-08 18:32:22,022 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR
WARNING: An illegal reflective access operation has occurred
WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_84c3f80a-f186-401a-8c5e-005f63e9e38f/bin/uautomizer-verify-jihMAELWvX/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int)
WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1
WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations
WARNING: All illegal access operations will be denied in a future release
Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main
Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_84c3f80a-f186-401a-8c5e-005f63e9e38f/bin/uautomizer-verify-jihMAELWvX
Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness
Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false
Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) )
Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer
Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit
Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 022987cd4c8c671e376c5c3e5a08e2f1b98444b4d5d48bc73787bff74aa0de0f
[2024-11-08 18:32:22,313 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp
[2024-11-08 18:32:22,340 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized
[2024-11-08 18:32:22,342 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected.
[2024-11-08 18:32:22,344 INFO L270 PluginConnector]: Initializing CDTParser...
[2024-11-08 18:32:22,344 INFO L274 PluginConnector]: CDTParser initialized
[2024-11-08 18:32:22,346 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_84c3f80a-f186-401a-8c5e-005f63e9e38f/bin/uautomizer-verify-jihMAELWvX/../../sv-benchmarks/c/systemc/transmitter.07.cil.c
Unable to find full path for "g++"
[2024-11-08 18:32:24,416 INFO L533 CDTParser]: Created temporary CDT project at NULL
[2024-11-08 18:32:24,623 INFO L384 CDTParser]: Found 1 translation units.
[2024-11-08 18:32:24,624 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_84c3f80a-f186-401a-8c5e-005f63e9e38f/sv-benchmarks/c/systemc/transmitter.07.cil.c
[2024-11-08 18:32:24,637 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_84c3f80a-f186-401a-8c5e-005f63e9e38f/bin/uautomizer-verify-jihMAELWvX/data/333ccdb7a/3293811b77b94e99b914fa514e34a59e/FLAGfa51b4be1
[2024-11-08 18:32:24,653 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_84c3f80a-f186-401a-8c5e-005f63e9e38f/bin/uautomizer-verify-jihMAELWvX/data/333ccdb7a/3293811b77b94e99b914fa514e34a59e
[2024-11-08 18:32:24,656 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] #######################
[2024-11-08 18:32:24,658 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements.
[2024-11-08 18:32:24,659 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator----------------------------
[2024-11-08 18:32:24,660 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator...
[2024-11-08 18:32:24,666 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized
[2024-11-08 18:32:24,666 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 08.11 06:32:24" (1/1) ...
[2024-11-08 18:32:24,668 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@fb1b493 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 06:32:24, skipping insertion in model container
[2024-11-08 18:32:24,668 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 08.11 06:32:24" (1/1) ...
[2024-11-08 18:32:24,713 INFO L175 MainTranslator]: Built tables and reachable declarations
[2024-11-08 18:32:25,031 INFO L210 PostProcessor]: Analyzing one entry point: main
[2024-11-08 18:32:25,045 INFO L200 MainTranslator]: Completed pre-run
[2024-11-08 18:32:25,126 INFO L210 PostProcessor]: Analyzing one entry point: main
[2024-11-08 18:32:25,159 INFO L204 MainTranslator]: Completed translation
[2024-11-08 18:32:25,160 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 06:32:25 WrapperNode
[2024-11-08 18:32:25,160 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator----------------------------
[2024-11-08 18:32:25,161 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner----------------------------
[2024-11-08 18:32:25,161 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner...
[2024-11-08 18:32:25,162 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized
[2024-11-08 18:32:25,170 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 06:32:25" (1/1) ...
[2024-11-08 18:32:25,187 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 06:32:25" (1/1) ...
[2024-11-08 18:32:25,267 INFO L138 Inliner]: procedures = 42, calls = 52, calls flagged for inlining = 47, calls inlined = 125, statements flattened = 1850
[2024-11-08 18:32:25,268 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner----------------------------
[2024-11-08 18:32:25,269 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor----------------------------
[2024-11-08 18:32:25,269 INFO L270 PluginConnector]: Initializing Boogie Preprocessor...
[2024-11-08 18:32:25,269 INFO L274 PluginConnector]: Boogie Preprocessor initialized
[2024-11-08 18:32:25,282 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 06:32:25" (1/1) ...
[2024-11-08 18:32:25,283 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 06:32:25" (1/1) ...
[2024-11-08 18:32:25,294 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 06:32:25" (1/1) ...
[2024-11-08 18:32:25,337 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0].
[2024-11-08 18:32:25,341 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 06:32:25" (1/1) ...
[2024-11-08 18:32:25,342 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 06:32:25" (1/1) ...
[2024-11-08 18:32:25,376 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 06:32:25" (1/1) ...
[2024-11-08 18:32:25,418 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 06:32:25" (1/1) ...
[2024-11-08 18:32:25,426 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 06:32:25" (1/1) ...
[2024-11-08 18:32:25,435 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 06:32:25" (1/1) ...
[2024-11-08 18:32:25,450 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor----------------------------
[2024-11-08 18:32:25,455 INFO L112 PluginConnector]: ------------------------RCFGBuilder----------------------------
[2024-11-08 18:32:25,455 INFO L270 PluginConnector]: Initializing RCFGBuilder...
[2024-11-08 18:32:25,455 INFO L274 PluginConnector]: RCFGBuilder initialized
[2024-11-08 18:32:25,457 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 06:32:25" (1/1) ...
[2024-11-08 18:32:25,471 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000
[2024-11-08 18:32:25,486 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_84c3f80a-f186-401a-8c5e-005f63e9e38f/bin/uautomizer-verify-jihMAELWvX/z3
[2024-11-08 18:32:25,506 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_84c3f80a-f186-401a-8c5e-005f63e9e38f/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null)
[2024-11-08 18:32:25,509 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_84c3f80a-f186-401a-8c5e-005f63e9e38f/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process
[2024-11-08 18:32:25,552 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit
[2024-11-08 18:32:25,552 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0
[2024-11-08 18:32:25,552 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start
[2024-11-08 18:32:25,552 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start
[2024-11-08 18:32:25,676 INFO L238 CfgBuilder]: Building ICFG
[2024-11-08 18:32:25,678 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation
[2024-11-08 18:32:27,458 INFO L? ?]: Removed 360 outVars from TransFormulas that were not future-live.
[2024-11-08 18:32:27,458 INFO L287 CfgBuilder]: Performing block encoding
[2024-11-08 18:32:27,487 INFO L311 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start)
[2024-11-08 18:32:27,487 INFO L316 CfgBuilder]: Removed 11 assume(true) statements.
[2024-11-08 18:32:27,488 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 08.11 06:32:27 BoogieIcfgContainer
[2024-11-08 18:32:27,488 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder----------------------------
[2024-11-08 18:32:27,489 INFO L112 PluginConnector]: ------------------------BuchiAutomizer----------------------------
[2024-11-08 18:32:27,489 INFO L270 PluginConnector]: Initializing BuchiAutomizer...
[2024-11-08 18:32:27,493 INFO L274 PluginConnector]: BuchiAutomizer initialized
[2024-11-08 18:32:27,494 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis
[2024-11-08 18:32:27,494 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 08.11 06:32:24" (1/3) ...
[2024-11-08 18:32:27,495 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@24bb69fc and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 08.11 06:32:27, skipping insertion in model container
[2024-11-08 18:32:27,496 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis
[2024-11-08 18:32:27,496 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 06:32:25" (2/3) ...
[2024-11-08 18:32:27,496 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@24bb69fc and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 08.11 06:32:27, skipping insertion in model container
[2024-11-08 18:32:27,496 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis
[2024-11-08 18:32:27,496 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 08.11 06:32:27" (3/3) ...
[2024-11-08 18:32:27,498 INFO L332 chiAutomizerObserver]: Analyzing ICFG transmitter.07.cil.c
[2024-11-08 18:32:27,568 INFO L300 stractBuchiCegarLoop]: Interprodecural is true
[2024-11-08 18:32:27,569 INFO L301 stractBuchiCegarLoop]: Hoare is None
[2024-11-08 18:32:27,569 INFO L302 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates
[2024-11-08 18:32:27,569 INFO L303 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE
[2024-11-08 18:32:27,569 INFO L304 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION
[2024-11-08 18:32:27,569 INFO L305 stractBuchiCegarLoop]: Difference is false
[2024-11-08 18:32:27,570 INFO L306 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA
[2024-11-08 18:32:27,570 INFO L310 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ========
[2024-11-08 18:32:27,581 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 784 states, 783 states have (on average 1.5172413793103448) internal successors, (1188), 783 states have internal predecessors, (1188), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 18:32:27,646 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 679
[2024-11-08 18:32:27,647 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2024-11-08 18:32:27,647 INFO L119 BuchiIsEmpty]: Starting construction of run
[2024-11-08 18:32:27,659 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 18:32:27,659 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 18:32:27,659 INFO L332 stractBuchiCegarLoop]: ======== Iteration 1 ============
[2024-11-08 18:32:27,662 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 784 states, 783 states have (on average 1.5172413793103448) internal successors, (1188), 783 states have internal predecessors, (1188), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 18:32:27,701 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 679
[2024-11-08 18:32:27,701 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2024-11-08 18:32:27,701 INFO L119 BuchiIsEmpty]: Starting construction of run
[2024-11-08 18:32:27,706 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 18:32:27,706 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 18:32:27,717 INFO L745 eck$LassoCheckResult]: Stem: 107#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 718#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 570#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 715#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 650#L521true assume !(1 == ~m_i~0);~m_st~0 := 2; 612#L521-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 643#L526-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 193#L531-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 549#L536-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 240#L541-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 138#L546-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 601#L551-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 122#L556-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 689#L754true assume !(0 == ~M_E~0); 737#L754-2true assume !(0 == ~T1_E~0); 509#L759-1true assume !(0 == ~T2_E~0); 376#L764-1true assume !(0 == ~T3_E~0); 339#L769-1true assume !(0 == ~T4_E~0); 377#L774-1true assume !(0 == ~T5_E~0); 636#L779-1true assume 0 == ~T6_E~0;~T6_E~0 := 1; 519#L784-1true assume !(0 == ~T7_E~0); 337#L789-1true assume !(0 == ~E_1~0); 424#L794-1true assume !(0 == ~E_2~0); 765#L799-1true assume !(0 == ~E_3~0); 346#L804-1true assume !(0 == ~E_4~0); 372#L809-1true assume !(0 == ~E_5~0); 550#L814-1true assume !(0 == ~E_6~0); 9#L819-1true assume 0 == ~E_7~0;~E_7~0 := 1; 171#L824-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 137#L361true assume 1 == ~m_pc~0; 676#L362true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 712#L372true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 499#is_master_triggered_returnLabel#1true activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 633#L930true assume !(0 != activate_threads_~tmp~1#1); 272#L930-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 134#L380true assume !(1 == ~t1_pc~0); 766#L380-2true is_transmit1_triggered_~__retres1~1#1 := 0; 644#L391true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 770#L938true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 460#L938-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 438#L399true assume 1 == ~t2_pc~0; 638#L400true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 654#L410true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 179#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 175#L946true assume !(0 != activate_threads_~tmp___1~0#1); 414#L946-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13#L418true assume !(1 == ~t3_pc~0); 698#L418-2true is_transmit3_triggered_~__retres1~3#1 := 0; 552#L429true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 777#L954true assume !(0 != activate_threads_~tmp___2~0#1); 361#L954-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 691#L437true assume 1 == ~t4_pc~0; 755#L438true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 494#L448true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 47#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 209#L962true assume !(0 != activate_threads_~tmp___3~0#1); 592#L962-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 478#L456true assume !(1 == ~t5_pc~0); 330#L456-2true is_transmit5_triggered_~__retres1~5#1 := 0; 681#L467true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 502#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 410#L970true assume !(0 != activate_threads_~tmp___4~0#1); 734#L970-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 45#L475true assume 1 == ~t6_pc~0; 221#L476true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 66#L486true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 169#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 402#L978true assume !(0 != activate_threads_~tmp___5~0#1); 351#L978-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 547#L494true assume 1 == ~t7_pc~0; 304#L495true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 316#L505true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 731#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 378#L986true assume !(0 != activate_threads_~tmp___6~0#1); 761#L986-2true havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 668#L837true assume !(1 == ~M_E~0); 569#L837-2true assume !(1 == ~T1_E~0); 433#L842-1true assume !(1 == ~T2_E~0); 216#L847-1true assume !(1 == ~T3_E~0); 265#L852-1true assume !(1 == ~T4_E~0); 781#L857-1true assume 1 == ~T5_E~0;~T5_E~0 := 2; 182#L862-1true assume !(1 == ~T6_E~0); 189#L867-1true assume !(1 == ~T7_E~0); 239#L872-1true assume !(1 == ~E_1~0); 391#L877-1true assume !(1 == ~E_2~0); 578#L882-1true assume !(1 == ~E_3~0); 707#L887-1true assume !(1 == ~E_4~0); 454#L892-1true assume !(1 == ~E_5~0); 660#L897-1true assume 1 == ~E_6~0;~E_6~0 := 2; 199#L902-1true assume !(1 == ~E_7~0); 477#L907-1true assume { :end_inline_reset_delta_events } true; 230#L1148-2true
[2024-11-08 18:32:27,720 INFO L747 eck$LassoCheckResult]: Loop: 230#L1148-2true assume !false; 10#L1149true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 422#L729-1true assume !true; 455#eval_returnLabel#1true havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 271#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 146#L754-3true assume 0 == ~M_E~0;~M_E~0 := 1; 16#L754-5true assume !(0 == ~T1_E~0); 530#L759-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 225#L764-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 616#L769-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 362#L774-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 94#L779-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 14#L784-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 774#L789-3true assume 0 == ~E_1~0;~E_1~0 := 1; 11#L794-3true assume !(0 == ~E_2~0); 35#L799-3true assume 0 == ~E_3~0;~E_3~0 := 1; 150#L804-3true assume 0 == ~E_4~0;~E_4~0 := 1; 293#L809-3true assume 0 == ~E_5~0;~E_5~0 := 1; 33#L814-3true assume 0 == ~E_6~0;~E_6~0 := 1; 526#L819-3true assume 0 == ~E_7~0;~E_7~0 := 1; 487#L824-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 236#L361-24true assume !(1 == ~m_pc~0); 532#L361-26true is_master_triggered_~__retres1~0#1 := 0; 301#L372-8true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 59#is_master_triggered_returnLabel#9true activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 553#L930-24true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 584#L930-26true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 343#L380-24true assume 1 == ~t1_pc~0; 585#L381-8true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 625#L391-8true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 297#is_transmit1_triggered_returnLabel#9true activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 144#L938-24true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 439#L938-26true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 505#L399-24true assume !(1 == ~t2_pc~0); 154#L399-26true is_transmit2_triggered_~__retres1~2#1 := 0; 110#L410-8true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 381#is_transmit2_triggered_returnLabel#9true activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 264#L946-24true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 142#L946-26true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 624#L418-24true assume 1 == ~t3_pc~0; 551#L419-8true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 185#L429-8true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 591#is_transmit3_triggered_returnLabel#9true activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 96#L954-24true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 412#L954-26true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 556#L437-24true assume !(1 == ~t4_pc~0); 784#L437-26true is_transmit4_triggered_~__retres1~4#1 := 0; 740#L448-8true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 263#is_transmit4_triggered_returnLabel#9true activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 88#L962-24true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 350#L962-26true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 645#L456-24true assume !(1 == ~t5_pc~0); 738#L456-26true is_transmit5_triggered_~__retres1~5#1 := 0; 307#L467-8true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 533#is_transmit5_triggered_returnLabel#9true activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 574#L970-24true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 273#L970-26true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 769#L475-24true assume 1 == ~t6_pc~0; 15#L476-8true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 315#L486-8true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 85#is_transmit6_triggered_returnLabel#9true activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 347#L978-24true assume !(0 != activate_threads_~tmp___5~0#1); 6#L978-26true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 309#L494-24true assume 1 == ~t7_pc~0; 248#L495-8true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 174#L505-8true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 257#is_transmit7_triggered_returnLabel#9true activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 140#L986-24true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 490#L986-26true havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 515#L837-3true assume 1 == ~M_E~0;~M_E~0 := 2; 670#L837-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 269#L842-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 608#L847-3true assume !(1 == ~T3_E~0); 408#L852-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 313#L857-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 746#L862-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 703#L867-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 247#L872-3true assume 1 == ~E_1~0;~E_1~0 := 2; 306#L877-3true assume 1 == ~E_2~0;~E_2~0 := 2; 728#L882-3true assume 1 == ~E_3~0;~E_3~0 := 2; 354#L887-3true assume !(1 == ~E_4~0); 104#L892-3true assume 1 == ~E_5~0;~E_5~0 := 2; 514#L897-3true assume 1 == ~E_6~0;~E_6~0 := 2; 773#L902-3true assume 1 == ~E_7~0;~E_7~0 := 2; 196#L907-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 581#L569-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 365#L611-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 155#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 686#L1167true assume !(0 == start_simulation_~tmp~3#1); 233#L1167-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 745#L569-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 254#L611-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 19#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 308#L1122true assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 222#L1129true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 282#stop_simulation_returnLabel#1true start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 121#L1180true assume !(0 != start_simulation_~tmp___0~1#1); 230#L1148-2true
[2024-11-08 18:32:27,735 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 18:32:27,736 INFO L85 PathProgramCache]: Analyzing trace with hash -171938705, now seen corresponding path program 1 times
[2024-11-08 18:32:27,755 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 18:32:27,756 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [687017607]
[2024-11-08 18:32:27,758 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 18:32:27,759 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 18:32:27,927 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-11-08 18:32:28,184 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2024-11-08 18:32:28,185 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2024-11-08 18:32:28,185 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [687017607]
[2024-11-08 18:32:28,186 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [687017607] provided 1 perfect and 0 imperfect interpolant sequences
[2024-11-08 18:32:28,187 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2024-11-08 18:32:28,188 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2024-11-08 18:32:28,190 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2111728434]
[2024-11-08 18:32:28,194 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2024-11-08 18:32:28,199 INFO L750 eck$LassoCheckResult]: stem already infeasible
[2024-11-08 18:32:28,201 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 18:32:28,202 INFO L85 PathProgramCache]: Analyzing trace with hash -181380521, now seen corresponding path program 1 times
[2024-11-08 18:32:28,202 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 18:32:28,202 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [906529064]
[2024-11-08 18:32:28,203 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 18:32:28,203 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 18:32:28,238 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-11-08 18:32:28,299 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2024-11-08 18:32:28,299 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2024-11-08 18:32:28,299 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [906529064]
[2024-11-08 18:32:28,300 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [906529064] provided 1 perfect and 0 imperfect interpolant sequences
[2024-11-08 18:32:28,300 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2024-11-08 18:32:28,300 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2
[2024-11-08 18:32:28,300 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1397220686]
[2024-11-08 18:32:28,300 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2024-11-08 18:32:28,302 INFO L762 eck$LassoCheckResult]: loop already infeasible
[2024-11-08 18:32:28,304 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2024-11-08 18:32:28,343 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2024-11-08 18:32:28,344 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2024-11-08 18:32:28,346 INFO L87 Difference]: Start difference. First operand has 784 states, 783 states have (on average 1.5172413793103448) internal successors, (1188), 783 states have internal predecessors, (1188), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 18:32:28,419 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2024-11-08 18:32:28,420 INFO L93 Difference]: Finished difference Result 782 states and 1162 transitions.
[2024-11-08 18:32:28,421 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 782 states and 1162 transitions.
[2024-11-08 18:32:28,431 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 675
[2024-11-08 18:32:28,442 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 782 states to 776 states and 1156 transitions.
[2024-11-08 18:32:28,443 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 776
[2024-11-08 18:32:28,445 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 776
[2024-11-08 18:32:28,446 INFO L73 IsDeterministic]: Start isDeterministic. Operand 776 states and 1156 transitions.
[2024-11-08 18:32:28,449 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2024-11-08 18:32:28,449 INFO L218 hiAutomatonCegarLoop]: Abstraction has 776 states and 1156 transitions.
[2024-11-08 18:32:28,471 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 776 states and 1156 transitions.
[2024-11-08 18:32:28,529 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 776 to 776.
[2024-11-08 18:32:28,535 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 776 states, 776 states have (on average 1.4896907216494846) internal successors, (1156), 775 states have internal predecessors, (1156), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 18:32:28,541 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 776 states to 776 states and 1156 transitions.
[2024-11-08 18:32:28,542 INFO L240 hiAutomatonCegarLoop]: Abstraction has 776 states and 1156 transitions.
[2024-11-08 18:32:28,544 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states.
[2024-11-08 18:32:28,549 INFO L425 stractBuchiCegarLoop]: Abstraction has 776 states and 1156 transitions.
[2024-11-08 18:32:28,550 INFO L332 stractBuchiCegarLoop]: ======== Iteration 2 ============
[2024-11-08 18:32:28,551 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 776 states and 1156 transitions.
[2024-11-08 18:32:28,556 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 675
[2024-11-08 18:32:28,558 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2024-11-08 18:32:28,559 INFO L119 BuchiIsEmpty]: Starting construction of run
[2024-11-08 18:32:28,562 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 18:32:28,566 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 18:32:28,567 INFO L745 eck$LassoCheckResult]: Stem: 1790#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 1791#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 2318#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2319#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2338#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 2330#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2331#L526-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1939#L531-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1940#L536-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2009#L541-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1853#L546-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1854#L551-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 1820#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1821#L754 assume !(0 == ~M_E~0); 2346#L754-2 assume !(0 == ~T1_E~0); 2288#L759-1 assume !(0 == ~T2_E~0); 2170#L764-1 assume !(0 == ~T3_E~0); 2135#L769-1 assume !(0 == ~T4_E~0); 2136#L774-1 assume !(0 == ~T5_E~0); 2171#L779-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2293#L784-1 assume !(0 == ~T7_E~0); 2132#L789-1 assume !(0 == ~E_1~0); 2133#L794-1 assume !(0 == ~E_2~0); 2207#L799-1 assume !(0 == ~E_3~0); 2143#L804-1 assume !(0 == ~E_4~0); 2144#L809-1 assume !(0 == ~E_5~0); 2165#L814-1 assume !(0 == ~E_6~0); 1591#L819-1 assume 0 == ~E_7~0;~E_7~0 := 1; 1592#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1850#L361 assume 1 == ~m_pc~0; 1851#L362 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 2314#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2274#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2275#L930 assume !(0 != activate_threads_~tmp~1#1); 2052#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1844#L380 assume !(1 == ~t1_pc~0); 1845#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2213#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1613#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1614#L938 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2233#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2214#L399 assume 1 == ~t2_pc~0; 2215#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1762#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1922#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1915#L946 assume !(0 != activate_threads_~tmp___1~0#1); 1916#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1599#L418 assume !(1 == ~t3_pc~0); 1578#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1579#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1589#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1590#L954 assume !(0 != activate_threads_~tmp___2~0#1); 2155#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2156#L437 assume 1 == ~t4_pc~0; 2347#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2269#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1672#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1673#L962 assume !(0 != activate_threads_~tmp___3~0#1); 1968#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2251#L456 assume !(1 == ~t5_pc~0); 1776#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1775#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2278#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2196#L970 assume !(0 != activate_threads_~tmp___4~0#1); 2197#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1666#L475 assume 1 == ~t6_pc~0; 1667#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1708#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1709#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1908#L978 assume !(0 != activate_threads_~tmp___5~0#1); 2148#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2149#L494 assume 1 == ~t7_pc~0; 2097#L495 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1893#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2108#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2172#L986 assume !(0 != activate_threads_~tmp___6~0#1); 2173#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2343#L837 assume !(1 == ~M_E~0); 2317#L837-2 assume !(1 == ~T1_E~0); 2210#L842-1 assume !(1 == ~T2_E~0); 1975#L847-1 assume !(1 == ~T3_E~0); 1976#L852-1 assume !(1 == ~T4_E~0); 2042#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1928#L862-1 assume !(1 == ~T6_E~0); 1929#L867-1 assume !(1 == ~T7_E~0); 1935#L872-1 assume !(1 == ~E_1~0); 2008#L877-1 assume !(1 == ~E_2~0); 2185#L882-1 assume !(1 == ~E_3~0); 2322#L887-1 assume !(1 == ~E_4~0); 2229#L892-1 assume !(1 == ~E_5~0); 2230#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 1951#L902-1 assume !(1 == ~E_7~0); 1952#L907-1 assume { :end_inline_reset_delta_events } true; 1819#L1148-2
[2024-11-08 18:32:28,568 INFO L747 eck$LassoCheckResult]: Loop: 1819#L1148-2 assume !false; 1593#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1594#L729-1 assume !false; 2205#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1792#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1793#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1941#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1837#L626 assume !(0 != eval_~tmp~0#1); 1839#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2051#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1866#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1605#L754-5 assume !(0 == ~T1_E~0); 1606#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1987#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1988#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2157#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1765#L779-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1600#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1601#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1595#L794-3 assume !(0 == ~E_2~0); 1596#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1647#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1873#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1643#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1644#L819-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2261#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2005#L361-24 assume 1 == ~m_pc~0; 1749#L362-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1750#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1695#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1696#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2306#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2140#L380-24 assume !(1 == ~t1_pc~0); 1677#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 1678#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2087#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1862#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1863#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2216#L399-24 assume 1 == ~t2_pc~0; 2281#L400-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1797#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1798#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2041#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1859#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1860#L418-24 assume 1 == ~t3_pc~0; 2305#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1642#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1932#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1768#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1769#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2199#L437-24 assume 1 == ~t4_pc~0; 2265#L438-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2266#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2040#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1752#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1753#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2147#L456-24 assume 1 == ~t5_pc~0; 2121#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2101#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2102#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2300#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2053#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2054#L475-24 assume 1 == ~t6_pc~0; 1602#L476-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1603#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1745#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1746#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 1584#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1585#L494-24 assume 1 == ~t7_pc~0; 2024#L495-8 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1913#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1914#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1856#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1857#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2264#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2291#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2048#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2049#L847-3 assume !(1 == ~T3_E~0); 2195#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2105#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2106#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2348#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2022#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2023#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2100#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2151#L887-3 assume !(1 == ~E_4~0); 1784#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1785#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2290#L902-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1945#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1946#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1598#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1882#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 1883#L1167 assume !(0 == start_simulation_~tmp~3#1); 2000#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 2001#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1806#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1611#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 1612#L1122 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 1982#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1983#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 1818#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 1819#L1148-2
[2024-11-08 18:32:28,569 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 18:32:28,571 INFO L85 PathProgramCache]: Analyzing trace with hash 598794861, now seen corresponding path program 1 times
[2024-11-08 18:32:28,571 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 18:32:28,571 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1303696803]
[2024-11-08 18:32:28,572 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 18:32:28,572 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 18:32:28,602 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-11-08 18:32:28,700 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2024-11-08 18:32:28,700 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2024-11-08 18:32:28,701 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1303696803]
[2024-11-08 18:32:28,702 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1303696803] provided 1 perfect and 0 imperfect interpolant sequences
[2024-11-08 18:32:28,703 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2024-11-08 18:32:28,703 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2024-11-08 18:32:28,703 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [468554103]
[2024-11-08 18:32:28,703 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2024-11-08 18:32:28,704 INFO L750 eck$LassoCheckResult]: stem already infeasible
[2024-11-08 18:32:28,704 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 18:32:28,706 INFO L85 PathProgramCache]: Analyzing trace with hash 1429271342, now seen corresponding path program 1 times
[2024-11-08 18:32:28,706 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 18:32:28,707 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [113749268]
[2024-11-08 18:32:28,707 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 18:32:28,707 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 18:32:28,750 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-11-08 18:32:28,811 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2024-11-08 18:32:28,812 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2024-11-08 18:32:28,812 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [113749268]
[2024-11-08 18:32:28,812 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [113749268] provided 1 perfect and 0 imperfect interpolant sequences
[2024-11-08 18:32:28,813 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2024-11-08 18:32:28,813 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2024-11-08 18:32:28,813 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [544721819]
[2024-11-08 18:32:28,815 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2024-11-08 18:32:28,816 INFO L762 eck$LassoCheckResult]: loop already infeasible
[2024-11-08 18:32:28,816 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2024-11-08 18:32:28,816 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2024-11-08 18:32:28,817 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2024-11-08 18:32:28,817 INFO L87 Difference]: Start difference. First operand 776 states and 1156 transitions. cyclomatic complexity: 381 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 18:32:28,848 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2024-11-08 18:32:28,849 INFO L93 Difference]: Finished difference Result 776 states and 1155 transitions.
[2024-11-08 18:32:28,849 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 776 states and 1155 transitions.
[2024-11-08 18:32:28,856 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 675
[2024-11-08 18:32:28,860 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 776 states to 776 states and 1155 transitions.
[2024-11-08 18:32:28,861 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 776
[2024-11-08 18:32:28,862 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 776
[2024-11-08 18:32:28,863 INFO L73 IsDeterministic]: Start isDeterministic. Operand 776 states and 1155 transitions.
[2024-11-08 18:32:28,884 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2024-11-08 18:32:28,886 INFO L218 hiAutomatonCegarLoop]: Abstraction has 776 states and 1155 transitions.
[2024-11-08 18:32:28,888 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 776 states and 1155 transitions.
[2024-11-08 18:32:28,906 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 776 to 776.
[2024-11-08 18:32:28,908 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 776 states, 776 states have (on average 1.4884020618556701) internal successors, (1155), 775 states have internal predecessors, (1155), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 18:32:28,911 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 776 states to 776 states and 1155 transitions.
[2024-11-08 18:32:28,913 INFO L240 hiAutomatonCegarLoop]: Abstraction has 776 states and 1155 transitions.
[2024-11-08 18:32:28,914 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states.
[2024-11-08 18:32:28,915 INFO L425 stractBuchiCegarLoop]: Abstraction has 776 states and 1155 transitions.
[2024-11-08 18:32:28,915 INFO L332 stractBuchiCegarLoop]: ======== Iteration 3 ============
[2024-11-08 18:32:28,915 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 776 states and 1155 transitions.
[2024-11-08 18:32:28,921 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 675
[2024-11-08 18:32:28,921 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2024-11-08 18:32:28,922 INFO L119 BuchiIsEmpty]: Starting construction of run
[2024-11-08 18:32:28,926 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 18:32:28,927 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 18:32:28,928 INFO L745 eck$LassoCheckResult]: Stem: 3349#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 3350#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 3877#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3878#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3897#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 3889#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3890#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3498#L531-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3499#L536-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3568#L541-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3412#L546-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3413#L551-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 3379#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3380#L754 assume !(0 == ~M_E~0); 3905#L754-2 assume !(0 == ~T1_E~0); 3847#L759-1 assume !(0 == ~T2_E~0); 3729#L764-1 assume !(0 == ~T3_E~0); 3694#L769-1 assume !(0 == ~T4_E~0); 3695#L774-1 assume !(0 == ~T5_E~0); 3730#L779-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3852#L784-1 assume !(0 == ~T7_E~0); 3691#L789-1 assume !(0 == ~E_1~0); 3692#L794-1 assume !(0 == ~E_2~0); 3766#L799-1 assume !(0 == ~E_3~0); 3702#L804-1 assume !(0 == ~E_4~0); 3703#L809-1 assume !(0 == ~E_5~0); 3724#L814-1 assume !(0 == ~E_6~0); 3150#L819-1 assume 0 == ~E_7~0;~E_7~0 := 1; 3151#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3409#L361 assume 1 == ~m_pc~0; 3410#L362 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3873#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3833#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3834#L930 assume !(0 != activate_threads_~tmp~1#1); 3611#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3403#L380 assume !(1 == ~t1_pc~0); 3404#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3772#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3172#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3173#L938 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3792#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3773#L399 assume 1 == ~t2_pc~0; 3774#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3321#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3481#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3474#L946 assume !(0 != activate_threads_~tmp___1~0#1); 3475#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3158#L418 assume !(1 == ~t3_pc~0); 3137#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3138#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3148#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3149#L954 assume !(0 != activate_threads_~tmp___2~0#1); 3714#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3715#L437 assume 1 == ~t4_pc~0; 3906#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3828#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3231#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3232#L962 assume !(0 != activate_threads_~tmp___3~0#1); 3527#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3810#L456 assume !(1 == ~t5_pc~0); 3335#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3334#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3837#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3755#L970 assume !(0 != activate_threads_~tmp___4~0#1); 3756#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3225#L475 assume 1 == ~t6_pc~0; 3226#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3267#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3268#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3467#L978 assume !(0 != activate_threads_~tmp___5~0#1); 3707#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3708#L494 assume 1 == ~t7_pc~0; 3656#L495 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3452#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3667#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3731#L986 assume !(0 != activate_threads_~tmp___6~0#1); 3732#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3902#L837 assume !(1 == ~M_E~0); 3876#L837-2 assume !(1 == ~T1_E~0); 3769#L842-1 assume !(1 == ~T2_E~0); 3534#L847-1 assume !(1 == ~T3_E~0); 3535#L852-1 assume !(1 == ~T4_E~0); 3601#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3487#L862-1 assume !(1 == ~T6_E~0); 3488#L867-1 assume !(1 == ~T7_E~0); 3494#L872-1 assume !(1 == ~E_1~0); 3567#L877-1 assume !(1 == ~E_2~0); 3744#L882-1 assume !(1 == ~E_3~0); 3881#L887-1 assume !(1 == ~E_4~0); 3788#L892-1 assume !(1 == ~E_5~0); 3789#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 3510#L902-1 assume !(1 == ~E_7~0); 3511#L907-1 assume { :end_inline_reset_delta_events } true; 3378#L1148-2
[2024-11-08 18:32:28,929 INFO L747 eck$LassoCheckResult]: Loop: 3378#L1148-2 assume !false; 3152#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3153#L729-1 assume !false; 3764#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 3351#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 3352#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 3500#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3396#L626 assume !(0 != eval_~tmp~0#1); 3398#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3610#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3425#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3164#L754-5 assume !(0 == ~T1_E~0); 3165#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3546#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3547#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3716#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3324#L779-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3159#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3160#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3154#L794-3 assume !(0 == ~E_2~0); 3155#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3206#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3432#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3202#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3203#L819-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3820#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3564#L361-24 assume 1 == ~m_pc~0; 3308#L362-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3309#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3254#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3255#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3865#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3699#L380-24 assume !(1 == ~t1_pc~0); 3236#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 3237#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3646#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3421#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3422#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3775#L399-24 assume 1 == ~t2_pc~0; 3840#L400-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3356#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3357#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3600#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3418#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3419#L418-24 assume !(1 == ~t3_pc~0); 3200#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 3201#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3491#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3327#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3328#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3758#L437-24 assume 1 == ~t4_pc~0; 3824#L438-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3825#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3599#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3311#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3312#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3706#L456-24 assume 1 == ~t5_pc~0; 3680#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3660#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3661#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3859#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3612#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3613#L475-24 assume 1 == ~t6_pc~0; 3161#L476-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3162#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3304#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3305#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 3143#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3144#L494-24 assume !(1 == ~t7_pc~0); 3492#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 3472#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3473#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3415#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3416#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3823#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3850#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3607#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3608#L847-3 assume !(1 == ~T3_E~0); 3754#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3664#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3665#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3907#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3581#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3582#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3659#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3710#L887-3 assume !(1 == ~E_4~0); 3343#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3344#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3849#L902-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3504#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 3505#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 3157#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 3441#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 3442#L1167 assume !(0 == start_simulation_~tmp~3#1); 3559#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 3560#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 3365#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 3170#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 3171#L1122 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 3541#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3542#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 3377#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 3378#L1148-2
[2024-11-08 18:32:28,930 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 18:32:28,930 INFO L85 PathProgramCache]: Analyzing trace with hash 1185071083, now seen corresponding path program 1 times
[2024-11-08 18:32:28,933 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 18:32:28,934 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [522196711]
[2024-11-08 18:32:28,934 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 18:32:28,934 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 18:32:28,954 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-11-08 18:32:29,000 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2024-11-08 18:32:29,000 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2024-11-08 18:32:29,000 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [522196711]
[2024-11-08 18:32:29,001 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [522196711] provided 1 perfect and 0 imperfect interpolant sequences
[2024-11-08 18:32:29,001 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2024-11-08 18:32:29,001 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2024-11-08 18:32:29,001 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1156304865]
[2024-11-08 18:32:29,001 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2024-11-08 18:32:29,002 INFO L750 eck$LassoCheckResult]: stem already infeasible
[2024-11-08 18:32:29,002 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 18:32:29,003 INFO L85 PathProgramCache]: Analyzing trace with hash -1341026324, now seen corresponding path program 1 times
[2024-11-08 18:32:29,003 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 18:32:29,003 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [597780873]
[2024-11-08 18:32:29,003 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 18:32:29,004 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 18:32:29,022 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-11-08 18:32:29,108 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2024-11-08 18:32:29,109 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2024-11-08 18:32:29,109 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [597780873]
[2024-11-08 18:32:29,109 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [597780873] provided 1 perfect and 0 imperfect interpolant sequences
[2024-11-08 18:32:29,109 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2024-11-08 18:32:29,109 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2024-11-08 18:32:29,110 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [886444635]
[2024-11-08 18:32:29,110 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2024-11-08 18:32:29,110 INFO L762 eck$LassoCheckResult]: loop already infeasible
[2024-11-08 18:32:29,110 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2024-11-08 18:32:29,111 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2024-11-08 18:32:29,111 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2024-11-08 18:32:29,111 INFO L87 Difference]: Start difference. First operand 776 states and 1155 transitions. cyclomatic complexity: 380 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 18:32:29,137 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2024-11-08 18:32:29,137 INFO L93 Difference]: Finished difference Result 776 states and 1154 transitions.
[2024-11-08 18:32:29,137 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 776 states and 1154 transitions.
[2024-11-08 18:32:29,144 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 675
[2024-11-08 18:32:29,148 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 776 states to 776 states and 1154 transitions.
[2024-11-08 18:32:29,149 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 776
[2024-11-08 18:32:29,149 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 776
[2024-11-08 18:32:29,150 INFO L73 IsDeterministic]: Start isDeterministic. Operand 776 states and 1154 transitions.
[2024-11-08 18:32:29,151 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2024-11-08 18:32:29,152 INFO L218 hiAutomatonCegarLoop]: Abstraction has 776 states and 1154 transitions.
[2024-11-08 18:32:29,153 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 776 states and 1154 transitions.
[2024-11-08 18:32:29,165 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 776 to 776.
[2024-11-08 18:32:29,167 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 776 states, 776 states have (on average 1.4871134020618557) internal successors, (1154), 775 states have internal predecessors, (1154), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 18:32:29,170 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 776 states to 776 states and 1154 transitions.
[2024-11-08 18:32:29,171 INFO L240 hiAutomatonCegarLoop]: Abstraction has 776 states and 1154 transitions.
[2024-11-08 18:32:29,172 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states.
[2024-11-08 18:32:29,173 INFO L425 stractBuchiCegarLoop]: Abstraction has 776 states and 1154 transitions.
[2024-11-08 18:32:29,173 INFO L332 stractBuchiCegarLoop]: ======== Iteration 4 ============
[2024-11-08 18:32:29,173 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 776 states and 1154 transitions.
[2024-11-08 18:32:29,178 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 675
[2024-11-08 18:32:29,178 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2024-11-08 18:32:29,178 INFO L119 BuchiIsEmpty]: Starting construction of run
[2024-11-08 18:32:29,182 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 18:32:29,183 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 18:32:29,183 INFO L745 eck$LassoCheckResult]: Stem: 4908#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 4909#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 5436#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5437#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5456#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 5448#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5449#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5057#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5058#L536-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5127#L541-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4971#L546-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4972#L551-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4938#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4939#L754 assume !(0 == ~M_E~0); 5464#L754-2 assume !(0 == ~T1_E~0); 5406#L759-1 assume !(0 == ~T2_E~0); 5288#L764-1 assume !(0 == ~T3_E~0); 5254#L769-1 assume !(0 == ~T4_E~0); 5255#L774-1 assume !(0 == ~T5_E~0); 5289#L779-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5411#L784-1 assume !(0 == ~T7_E~0); 5251#L789-1 assume !(0 == ~E_1~0); 5252#L794-1 assume !(0 == ~E_2~0); 5325#L799-1 assume !(0 == ~E_3~0); 5261#L804-1 assume !(0 == ~E_4~0); 5262#L809-1 assume !(0 == ~E_5~0); 5283#L814-1 assume !(0 == ~E_6~0); 4711#L819-1 assume 0 == ~E_7~0;~E_7~0 := 1; 4712#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4968#L361 assume 1 == ~m_pc~0; 4969#L362 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 5432#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5392#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5393#L930 assume !(0 != activate_threads_~tmp~1#1); 5170#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4962#L380 assume !(1 == ~t1_pc~0); 4963#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 5331#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4731#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4732#L938 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5351#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5332#L399 assume 1 == ~t2_pc~0; 5333#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4880#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5040#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5033#L946 assume !(0 != activate_threads_~tmp___1~0#1); 5034#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4717#L418 assume !(1 == ~t3_pc~0); 4696#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4697#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4707#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4708#L954 assume !(0 != activate_threads_~tmp___2~0#1); 5273#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5274#L437 assume 1 == ~t4_pc~0; 5465#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5388#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4791#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4792#L962 assume !(0 != activate_threads_~tmp___3~0#1); 5086#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5374#L456 assume !(1 == ~t5_pc~0); 4894#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4893#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5396#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5315#L970 assume !(0 != activate_threads_~tmp___4~0#1); 5316#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4784#L475 assume 1 == ~t6_pc~0; 4785#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4826#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4827#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5026#L978 assume !(0 != activate_threads_~tmp___5~0#1); 5266#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5267#L494 assume 1 == ~t7_pc~0; 5215#L495 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 5011#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5226#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5290#L986 assume !(0 != activate_threads_~tmp___6~0#1); 5291#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5461#L837 assume !(1 == ~M_E~0); 5435#L837-2 assume !(1 == ~T1_E~0); 5328#L842-1 assume !(1 == ~T2_E~0); 5093#L847-1 assume !(1 == ~T3_E~0); 5094#L852-1 assume !(1 == ~T4_E~0); 5160#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5046#L862-1 assume !(1 == ~T6_E~0); 5047#L867-1 assume !(1 == ~T7_E~0); 5053#L872-1 assume !(1 == ~E_1~0); 5126#L877-1 assume !(1 == ~E_2~0); 5304#L882-1 assume !(1 == ~E_3~0); 5440#L887-1 assume !(1 == ~E_4~0); 5347#L892-1 assume !(1 == ~E_5~0); 5348#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 5069#L902-1 assume !(1 == ~E_7~0); 5070#L907-1 assume { :end_inline_reset_delta_events } true; 4937#L1148-2
[2024-11-08 18:32:29,184 INFO L747 eck$LassoCheckResult]: Loop: 4937#L1148-2 assume !false; 4713#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4714#L729-1 assume !false; 5323#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 4910#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 4911#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 5064#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 4957#L626 assume !(0 != eval_~tmp~0#1); 4959#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5169#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4984#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4723#L754-5 assume !(0 == ~T1_E~0); 4724#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5106#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5107#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5275#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4883#L779-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4718#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4719#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4709#L794-3 assume !(0 == ~E_2~0); 4710#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4765#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4991#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4761#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4762#L819-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5379#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5123#L361-24 assume 1 == ~m_pc~0; 4867#L362-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 4868#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4813#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4814#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5424#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5258#L380-24 assume !(1 == ~t1_pc~0); 4795#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 4796#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5205#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4980#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4981#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5334#L399-24 assume 1 == ~t2_pc~0; 5399#L400-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4915#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4916#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5159#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4977#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4978#L418-24 assume !(1 == ~t3_pc~0); 4759#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 4760#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5050#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4886#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4887#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5317#L437-24 assume 1 == ~t4_pc~0; 5383#L438-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5384#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5158#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4870#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4871#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5265#L456-24 assume 1 == ~t5_pc~0; 5239#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5219#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5220#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5418#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5171#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5172#L475-24 assume 1 == ~t6_pc~0; 4720#L476-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4721#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4863#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4864#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 4702#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4703#L494-24 assume 1 == ~t7_pc~0; 5142#L495-8 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 5031#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5032#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4974#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4975#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5382#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5409#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5166#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5167#L847-3 assume !(1 == ~T3_E~0); 5313#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5223#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5224#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5466#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5137#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5138#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5218#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5269#L887-3 assume !(1 == ~E_4~0); 4902#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4903#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5408#L902-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5062#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 5063#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 4716#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 5000#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 5001#L1167 assume !(0 == start_simulation_~tmp~3#1); 5118#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 5119#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 4924#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 4729#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 4730#L1122 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 5100#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5101#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 4936#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 4937#L1148-2
[2024-11-08 18:32:29,185 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 18:32:29,186 INFO L85 PathProgramCache]: Analyzing trace with hash -1151321427, now seen corresponding path program 1 times
[2024-11-08 18:32:29,187 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 18:32:29,187 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1430396833]
[2024-11-08 18:32:29,187 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 18:32:29,188 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 18:32:29,207 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-11-08 18:32:29,252 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2024-11-08 18:32:29,252 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2024-11-08 18:32:29,253 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1430396833]
[2024-11-08 18:32:29,253 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1430396833] provided 1 perfect and 0 imperfect interpolant sequences
[2024-11-08 18:32:29,253 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2024-11-08 18:32:29,253 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2024-11-08 18:32:29,253 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [326615586]
[2024-11-08 18:32:29,254 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2024-11-08 18:32:29,254 INFO L750 eck$LassoCheckResult]: stem already infeasible
[2024-11-08 18:32:29,254 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 18:32:29,255 INFO L85 PathProgramCache]: Analyzing trace with hash 287623949, now seen corresponding path program 1 times
[2024-11-08 18:32:29,255 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 18:32:29,255 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [748271154]
[2024-11-08 18:32:29,255 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 18:32:29,256 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 18:32:29,270 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-11-08 18:32:29,310 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2024-11-08 18:32:29,311 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2024-11-08 18:32:29,311 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [748271154]
[2024-11-08 18:32:29,311 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [748271154] provided 1 perfect and 0 imperfect interpolant sequences
[2024-11-08 18:32:29,311 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2024-11-08 18:32:29,311 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2024-11-08 18:32:29,312 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [126556547]
[2024-11-08 18:32:29,312 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2024-11-08 18:32:29,312 INFO L762 eck$LassoCheckResult]: loop already infeasible
[2024-11-08 18:32:29,313 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2024-11-08 18:32:29,313 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2024-11-08 18:32:29,313 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2024-11-08 18:32:29,314 INFO L87 Difference]: Start difference. First operand 776 states and 1154 transitions. cyclomatic complexity: 379 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 18:32:29,335 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2024-11-08 18:32:29,335 INFO L93 Difference]: Finished difference Result 776 states and 1153 transitions.
[2024-11-08 18:32:29,335 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 776 states and 1153 transitions.
[2024-11-08 18:32:29,340 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 675
[2024-11-08 18:32:29,344 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 776 states to 776 states and 1153 transitions.
[2024-11-08 18:32:29,344 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 776
[2024-11-08 18:32:29,345 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 776
[2024-11-08 18:32:29,345 INFO L73 IsDeterministic]: Start isDeterministic. Operand 776 states and 1153 transitions.
[2024-11-08 18:32:29,346 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2024-11-08 18:32:29,347 INFO L218 hiAutomatonCegarLoop]: Abstraction has 776 states and 1153 transitions.
[2024-11-08 18:32:29,348 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 776 states and 1153 transitions.
[2024-11-08 18:32:29,392 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 776 to 776.
[2024-11-08 18:32:29,394 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 776 states, 776 states have (on average 1.4858247422680413) internal successors, (1153), 775 states have internal predecessors, (1153), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 18:32:29,397 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 776 states to 776 states and 1153 transitions.
[2024-11-08 18:32:29,397 INFO L240 hiAutomatonCegarLoop]: Abstraction has 776 states and 1153 transitions.
[2024-11-08 18:32:29,398 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states.
[2024-11-08 18:32:29,399 INFO L425 stractBuchiCegarLoop]: Abstraction has 776 states and 1153 transitions.
[2024-11-08 18:32:29,400 INFO L332 stractBuchiCegarLoop]: ======== Iteration 5 ============
[2024-11-08 18:32:29,400 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 776 states and 1153 transitions.
[2024-11-08 18:32:29,404 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 675
[2024-11-08 18:32:29,404 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2024-11-08 18:32:29,405 INFO L119 BuchiIsEmpty]: Starting construction of run
[2024-11-08 18:32:29,410 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 18:32:29,410 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 18:32:29,410 INFO L745 eck$LassoCheckResult]: Stem: 6467#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 6468#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 6995#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6996#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7015#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 7007#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7008#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6616#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6617#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 6686#L541-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 6530#L546-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 6531#L551-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 6497#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6498#L754 assume !(0 == ~M_E~0); 7023#L754-2 assume !(0 == ~T1_E~0); 6965#L759-1 assume !(0 == ~T2_E~0); 6847#L764-1 assume !(0 == ~T3_E~0); 6812#L769-1 assume !(0 == ~T4_E~0); 6813#L774-1 assume !(0 == ~T5_E~0); 6848#L779-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6970#L784-1 assume !(0 == ~T7_E~0); 6809#L789-1 assume !(0 == ~E_1~0); 6810#L794-1 assume !(0 == ~E_2~0); 6884#L799-1 assume !(0 == ~E_3~0); 6820#L804-1 assume !(0 == ~E_4~0); 6821#L809-1 assume !(0 == ~E_5~0); 6842#L814-1 assume !(0 == ~E_6~0); 6268#L819-1 assume 0 == ~E_7~0;~E_7~0 := 1; 6269#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6527#L361 assume 1 == ~m_pc~0; 6528#L362 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 6991#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6951#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 6952#L930 assume !(0 != activate_threads_~tmp~1#1); 6729#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6521#L380 assume !(1 == ~t1_pc~0); 6522#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 6890#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6290#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6291#L938 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6910#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6891#L399 assume 1 == ~t2_pc~0; 6892#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6439#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6599#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6592#L946 assume !(0 != activate_threads_~tmp___1~0#1); 6593#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6276#L418 assume !(1 == ~t3_pc~0); 6255#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 6256#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6266#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6267#L954 assume !(0 != activate_threads_~tmp___2~0#1); 6832#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6833#L437 assume 1 == ~t4_pc~0; 7024#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6946#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6349#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6350#L962 assume !(0 != activate_threads_~tmp___3~0#1); 6645#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6930#L456 assume !(1 == ~t5_pc~0); 6453#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 6452#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6955#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6874#L970 assume !(0 != activate_threads_~tmp___4~0#1); 6875#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6343#L475 assume 1 == ~t6_pc~0; 6344#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6385#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6386#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6585#L978 assume !(0 != activate_threads_~tmp___5~0#1); 6825#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6826#L494 assume 1 == ~t7_pc~0; 6774#L495 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 6570#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6785#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6849#L986 assume !(0 != activate_threads_~tmp___6~0#1); 6850#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7020#L837 assume !(1 == ~M_E~0); 6994#L837-2 assume !(1 == ~T1_E~0); 6887#L842-1 assume !(1 == ~T2_E~0); 6652#L847-1 assume !(1 == ~T3_E~0); 6653#L852-1 assume !(1 == ~T4_E~0); 6719#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6605#L862-1 assume !(1 == ~T6_E~0); 6606#L867-1 assume !(1 == ~T7_E~0); 6612#L872-1 assume !(1 == ~E_1~0); 6685#L877-1 assume !(1 == ~E_2~0); 6862#L882-1 assume !(1 == ~E_3~0); 6999#L887-1 assume !(1 == ~E_4~0); 6906#L892-1 assume !(1 == ~E_5~0); 6907#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 6628#L902-1 assume !(1 == ~E_7~0); 6629#L907-1 assume { :end_inline_reset_delta_events } true; 6496#L1148-2
[2024-11-08 18:32:29,411 INFO L747 eck$LassoCheckResult]: Loop: 6496#L1148-2 assume !false; 6270#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6271#L729-1 assume !false; 6882#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 6469#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 6470#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 6620#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 6514#L626 assume !(0 != eval_~tmp~0#1); 6516#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6728#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6543#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 6282#L754-5 assume !(0 == ~T1_E~0); 6283#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6664#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6665#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6834#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6442#L779-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6277#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 6278#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6272#L794-3 assume !(0 == ~E_2~0); 6273#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6324#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6550#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6320#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 6321#L819-3 assume 0 == ~E_7~0;~E_7~0 := 1; 6938#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6682#L361-24 assume 1 == ~m_pc~0; 6426#L362-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 6427#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6372#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 6373#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6983#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6817#L380-24 assume !(1 == ~t1_pc~0); 6354#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 6355#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6764#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6539#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6540#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6893#L399-24 assume 1 == ~t2_pc~0; 6958#L400-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6474#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6475#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6718#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6536#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6537#L418-24 assume 1 == ~t3_pc~0; 6982#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6319#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6609#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6445#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6446#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6876#L437-24 assume !(1 == ~t4_pc~0); 6944#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 6943#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6717#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6429#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6430#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6824#L456-24 assume 1 == ~t5_pc~0; 6798#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6778#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6779#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6977#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6730#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6731#L475-24 assume 1 == ~t6_pc~0; 6279#L476-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6280#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6422#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6423#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 6261#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6262#L494-24 assume !(1 == ~t7_pc~0); 6610#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 6590#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6591#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6533#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 6534#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6941#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 6968#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6725#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6726#L847-3 assume !(1 == ~T3_E~0); 6872#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6782#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6783#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 7025#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 6696#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6697#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6777#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6828#L887-3 assume !(1 == ~E_4~0); 6461#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6462#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 6967#L902-3 assume 1 == ~E_7~0;~E_7~0 := 2; 6618#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 6619#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 6275#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 6559#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 6560#L1167 assume !(0 == start_simulation_~tmp~3#1); 6677#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 6678#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 6480#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 6288#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 6289#L1122 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 6659#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6660#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 6495#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 6496#L1148-2
[2024-11-08 18:32:29,411 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 18:32:29,411 INFO L85 PathProgramCache]: Analyzing trace with hash 1267163051, now seen corresponding path program 1 times
[2024-11-08 18:32:29,411 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 18:32:29,412 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [350757294]
[2024-11-08 18:32:29,412 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 18:32:29,412 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 18:32:29,436 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-11-08 18:32:29,479 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2024-11-08 18:32:29,480 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2024-11-08 18:32:29,480 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [350757294]
[2024-11-08 18:32:29,480 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [350757294] provided 1 perfect and 0 imperfect interpolant sequences
[2024-11-08 18:32:29,480 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2024-11-08 18:32:29,480 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2024-11-08 18:32:29,481 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1537379092]
[2024-11-08 18:32:29,481 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2024-11-08 18:32:29,481 INFO L750 eck$LassoCheckResult]: stem already infeasible
[2024-11-08 18:32:29,481 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 18:32:29,483 INFO L85 PathProgramCache]: Analyzing trace with hash -900947156, now seen corresponding path program 1 times
[2024-11-08 18:32:29,483 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 18:32:29,483 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [655542399]
[2024-11-08 18:32:29,483 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 18:32:29,484 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 18:32:29,501 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-11-08 18:32:29,555 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2024-11-08 18:32:29,556 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2024-11-08 18:32:29,556 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [655542399]
[2024-11-08 18:32:29,557 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [655542399] provided 1 perfect and 0 imperfect interpolant sequences
[2024-11-08 18:32:29,557 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2024-11-08 18:32:29,557 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2024-11-08 18:32:29,557 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1330423113]
[2024-11-08 18:32:29,558 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2024-11-08 18:32:29,558 INFO L762 eck$LassoCheckResult]: loop already infeasible
[2024-11-08 18:32:29,558 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2024-11-08 18:32:29,559 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2024-11-08 18:32:29,559 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2024-11-08 18:32:29,559 INFO L87 Difference]: Start difference. First operand 776 states and 1153 transitions. cyclomatic complexity: 378 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 18:32:29,580 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2024-11-08 18:32:29,581 INFO L93 Difference]: Finished difference Result 776 states and 1152 transitions.
[2024-11-08 18:32:29,582 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 776 states and 1152 transitions.
[2024-11-08 18:32:29,587 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 675
[2024-11-08 18:32:29,590 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 776 states to 776 states and 1152 transitions.
[2024-11-08 18:32:29,591 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 776
[2024-11-08 18:32:29,591 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 776
[2024-11-08 18:32:29,592 INFO L73 IsDeterministic]: Start isDeterministic. Operand 776 states and 1152 transitions.
[2024-11-08 18:32:29,593 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2024-11-08 18:32:29,593 INFO L218 hiAutomatonCegarLoop]: Abstraction has 776 states and 1152 transitions.
[2024-11-08 18:32:29,594 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 776 states and 1152 transitions.
[2024-11-08 18:32:29,603 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 776 to 776.
[2024-11-08 18:32:29,605 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 776 states, 776 states have (on average 1.4845360824742269) internal successors, (1152), 775 states have internal predecessors, (1152), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 18:32:29,608 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 776 states to 776 states and 1152 transitions.
[2024-11-08 18:32:29,608 INFO L240 hiAutomatonCegarLoop]: Abstraction has 776 states and 1152 transitions.
[2024-11-08 18:32:29,608 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states.
[2024-11-08 18:32:29,610 INFO L425 stractBuchiCegarLoop]: Abstraction has 776 states and 1152 transitions.
[2024-11-08 18:32:29,611 INFO L332 stractBuchiCegarLoop]: ======== Iteration 6 ============
[2024-11-08 18:32:29,611 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 776 states and 1152 transitions.
[2024-11-08 18:32:29,615 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 675
[2024-11-08 18:32:29,615 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2024-11-08 18:32:29,615 INFO L119 BuchiIsEmpty]: Starting construction of run
[2024-11-08 18:32:29,617 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 18:32:29,617 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 18:32:29,617 INFO L745 eck$LassoCheckResult]: Stem: 8026#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 8027#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 8554#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8555#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8574#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 8566#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8567#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8175#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8176#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 8245#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 8089#L546-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8090#L551-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8056#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8057#L754 assume !(0 == ~M_E~0); 8582#L754-2 assume !(0 == ~T1_E~0); 8524#L759-1 assume !(0 == ~T2_E~0); 8406#L764-1 assume !(0 == ~T3_E~0); 8371#L769-1 assume !(0 == ~T4_E~0); 8372#L774-1 assume !(0 == ~T5_E~0); 8407#L779-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8529#L784-1 assume !(0 == ~T7_E~0); 8368#L789-1 assume !(0 == ~E_1~0); 8369#L794-1 assume !(0 == ~E_2~0); 8443#L799-1 assume !(0 == ~E_3~0); 8379#L804-1 assume !(0 == ~E_4~0); 8380#L809-1 assume !(0 == ~E_5~0); 8401#L814-1 assume !(0 == ~E_6~0); 7827#L819-1 assume 0 == ~E_7~0;~E_7~0 := 1; 7828#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8086#L361 assume 1 == ~m_pc~0; 8087#L362 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 8550#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8510#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 8511#L930 assume !(0 != activate_threads_~tmp~1#1); 8288#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8080#L380 assume !(1 == ~t1_pc~0); 8081#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 8449#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7849#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7850#L938 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8469#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8450#L399 assume 1 == ~t2_pc~0; 8451#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7998#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8158#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8151#L946 assume !(0 != activate_threads_~tmp___1~0#1); 8152#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7835#L418 assume !(1 == ~t3_pc~0); 7814#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 7815#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7825#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7826#L954 assume !(0 != activate_threads_~tmp___2~0#1); 8391#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8392#L437 assume 1 == ~t4_pc~0; 8583#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8505#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7908#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7909#L962 assume !(0 != activate_threads_~tmp___3~0#1); 8204#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8487#L456 assume !(1 == ~t5_pc~0); 8012#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 8011#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8514#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8432#L970 assume !(0 != activate_threads_~tmp___4~0#1); 8433#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7902#L475 assume 1 == ~t6_pc~0; 7903#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 7944#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7945#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8144#L978 assume !(0 != activate_threads_~tmp___5~0#1); 8384#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8385#L494 assume 1 == ~t7_pc~0; 8333#L495 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8129#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8344#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8408#L986 assume !(0 != activate_threads_~tmp___6~0#1); 8409#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8579#L837 assume !(1 == ~M_E~0); 8553#L837-2 assume !(1 == ~T1_E~0); 8446#L842-1 assume !(1 == ~T2_E~0); 8211#L847-1 assume !(1 == ~T3_E~0); 8212#L852-1 assume !(1 == ~T4_E~0); 8278#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8164#L862-1 assume !(1 == ~T6_E~0); 8165#L867-1 assume !(1 == ~T7_E~0); 8171#L872-1 assume !(1 == ~E_1~0); 8244#L877-1 assume !(1 == ~E_2~0); 8421#L882-1 assume !(1 == ~E_3~0); 8558#L887-1 assume !(1 == ~E_4~0); 8465#L892-1 assume !(1 == ~E_5~0); 8466#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 8187#L902-1 assume !(1 == ~E_7~0); 8188#L907-1 assume { :end_inline_reset_delta_events } true; 8055#L1148-2
[2024-11-08 18:32:29,617 INFO L747 eck$LassoCheckResult]: Loop: 8055#L1148-2 assume !false; 7829#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7830#L729-1 assume !false; 8441#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 8028#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 8029#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 8177#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 8073#L626 assume !(0 != eval_~tmp~0#1); 8075#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8287#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8102#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 7841#L754-5 assume !(0 == ~T1_E~0); 7842#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8223#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8224#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8393#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8001#L779-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7836#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 7837#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7831#L794-3 assume !(0 == ~E_2~0); 7832#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7883#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8109#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7879#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 7880#L819-3 assume 0 == ~E_7~0;~E_7~0 := 1; 8497#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8241#L361-24 assume 1 == ~m_pc~0; 7985#L362-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 7986#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7931#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7932#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8542#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8376#L380-24 assume !(1 == ~t1_pc~0); 7913#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 7914#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8323#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 8098#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8099#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8452#L399-24 assume 1 == ~t2_pc~0; 8517#L400-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8033#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8034#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8277#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8095#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8096#L418-24 assume !(1 == ~t3_pc~0); 7877#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 7878#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8168#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8004#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 8005#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8435#L437-24 assume 1 == ~t4_pc~0; 8501#L438-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8502#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8276#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7988#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7989#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8383#L456-24 assume 1 == ~t5_pc~0; 8357#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8337#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8338#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8536#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8289#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8290#L475-24 assume !(1 == ~t6_pc~0); 7840#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 7839#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7981#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7982#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 7820#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7821#L494-24 assume 1 == ~t7_pc~0; 8260#L495-8 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8149#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8150#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8092#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8093#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8500#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 8527#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8284#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8285#L847-3 assume !(1 == ~T3_E~0); 8431#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8341#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8342#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8584#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 8258#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8259#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8336#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8387#L887-3 assume !(1 == ~E_4~0); 8020#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8021#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8526#L902-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8181#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 8182#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 7834#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 8118#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 8119#L1167 assume !(0 == start_simulation_~tmp~3#1); 8236#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 8237#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 8042#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 7847#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 7848#L1122 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 8218#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8219#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 8054#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 8055#L1148-2
[2024-11-08 18:32:29,618 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 18:32:29,618 INFO L85 PathProgramCache]: Analyzing trace with hash -1148673299, now seen corresponding path program 1 times
[2024-11-08 18:32:29,618 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 18:32:29,620 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1303865358]
[2024-11-08 18:32:29,621 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 18:32:29,621 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 18:32:29,635 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-11-08 18:32:29,671 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2024-11-08 18:32:29,671 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2024-11-08 18:32:29,672 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1303865358]
[2024-11-08 18:32:29,672 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1303865358] provided 1 perfect and 0 imperfect interpolant sequences
[2024-11-08 18:32:29,673 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2024-11-08 18:32:29,673 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2024-11-08 18:32:29,674 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1934851390]
[2024-11-08 18:32:29,674 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2024-11-08 18:32:29,674 INFO L750 eck$LassoCheckResult]: stem already infeasible
[2024-11-08 18:32:29,674 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 18:32:29,675 INFO L85 PathProgramCache]: Analyzing trace with hash 687615148, now seen corresponding path program 1 times
[2024-11-08 18:32:29,675 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 18:32:29,675 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1131356315]
[2024-11-08 18:32:29,675 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 18:32:29,676 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 18:32:29,689 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-11-08 18:32:29,736 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2024-11-08 18:32:29,736 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2024-11-08 18:32:29,736 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1131356315]
[2024-11-08 18:32:29,737 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1131356315] provided 1 perfect and 0 imperfect interpolant sequences
[2024-11-08 18:32:29,737 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2024-11-08 18:32:29,737 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2024-11-08 18:32:29,738 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1394706611]
[2024-11-08 18:32:29,738 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2024-11-08 18:32:29,738 INFO L762 eck$LassoCheckResult]: loop already infeasible
[2024-11-08 18:32:29,739 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2024-11-08 18:32:29,739 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2024-11-08 18:32:29,740 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2024-11-08 18:32:29,740 INFO L87 Difference]: Start difference. First operand 776 states and 1152 transitions. cyclomatic complexity: 377 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 18:32:29,759 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2024-11-08 18:32:29,760 INFO L93 Difference]: Finished difference Result 776 states and 1151 transitions.
[2024-11-08 18:32:29,760 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 776 states and 1151 transitions.
[2024-11-08 18:32:29,765 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 675
[2024-11-08 18:32:29,768 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 776 states to 776 states and 1151 transitions.
[2024-11-08 18:32:29,769 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 776
[2024-11-08 18:32:29,769 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 776
[2024-11-08 18:32:29,770 INFO L73 IsDeterministic]: Start isDeterministic. Operand 776 states and 1151 transitions.
[2024-11-08 18:32:29,771 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2024-11-08 18:32:29,771 INFO L218 hiAutomatonCegarLoop]: Abstraction has 776 states and 1151 transitions.
[2024-11-08 18:32:29,772 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 776 states and 1151 transitions.
[2024-11-08 18:32:29,781 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 776 to 776.
[2024-11-08 18:32:29,782 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 776 states, 776 states have (on average 1.4832474226804124) internal successors, (1151), 775 states have internal predecessors, (1151), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 18:32:29,785 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 776 states to 776 states and 1151 transitions.
[2024-11-08 18:32:29,786 INFO L240 hiAutomatonCegarLoop]: Abstraction has 776 states and 1151 transitions.
[2024-11-08 18:32:29,786 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states.
[2024-11-08 18:32:29,787 INFO L425 stractBuchiCegarLoop]: Abstraction has 776 states and 1151 transitions.
[2024-11-08 18:32:29,787 INFO L332 stractBuchiCegarLoop]: ======== Iteration 7 ============
[2024-11-08 18:32:29,787 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 776 states and 1151 transitions.
[2024-11-08 18:32:29,792 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 675
[2024-11-08 18:32:29,792 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2024-11-08 18:32:29,792 INFO L119 BuchiIsEmpty]: Starting construction of run
[2024-11-08 18:32:29,793 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 18:32:29,794 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 18:32:29,794 INFO L745 eck$LassoCheckResult]: Stem: 9585#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 9586#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 10113#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10114#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10133#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 10125#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10126#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9734#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9735#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9804#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 9648#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 9649#L551-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 9615#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9616#L754 assume !(0 == ~M_E~0); 10141#L754-2 assume !(0 == ~T1_E~0); 10083#L759-1 assume !(0 == ~T2_E~0); 9965#L764-1 assume !(0 == ~T3_E~0); 9930#L769-1 assume !(0 == ~T4_E~0); 9931#L774-1 assume !(0 == ~T5_E~0); 9966#L779-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10088#L784-1 assume !(0 == ~T7_E~0); 9927#L789-1 assume !(0 == ~E_1~0); 9928#L794-1 assume !(0 == ~E_2~0); 10002#L799-1 assume !(0 == ~E_3~0); 9938#L804-1 assume !(0 == ~E_4~0); 9939#L809-1 assume !(0 == ~E_5~0); 9960#L814-1 assume !(0 == ~E_6~0); 9386#L819-1 assume 0 == ~E_7~0;~E_7~0 := 1; 9387#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9645#L361 assume 1 == ~m_pc~0; 9646#L362 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 10109#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10069#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 10070#L930 assume !(0 != activate_threads_~tmp~1#1); 9847#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9639#L380 assume !(1 == ~t1_pc~0); 9640#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 10008#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9408#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9409#L938 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10028#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10009#L399 assume 1 == ~t2_pc~0; 10010#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9557#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9717#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9710#L946 assume !(0 != activate_threads_~tmp___1~0#1); 9711#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9394#L418 assume !(1 == ~t3_pc~0); 9373#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 9374#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9384#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9385#L954 assume !(0 != activate_threads_~tmp___2~0#1); 9950#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9951#L437 assume 1 == ~t4_pc~0; 10142#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10064#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9467#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9468#L962 assume !(0 != activate_threads_~tmp___3~0#1); 9763#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10046#L456 assume !(1 == ~t5_pc~0); 9571#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 9570#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10073#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9991#L970 assume !(0 != activate_threads_~tmp___4~0#1); 9992#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9461#L475 assume 1 == ~t6_pc~0; 9462#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 9503#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9504#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9703#L978 assume !(0 != activate_threads_~tmp___5~0#1); 9943#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9944#L494 assume 1 == ~t7_pc~0; 9892#L495 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 9688#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9903#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9967#L986 assume !(0 != activate_threads_~tmp___6~0#1); 9968#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10138#L837 assume !(1 == ~M_E~0); 10112#L837-2 assume !(1 == ~T1_E~0); 10005#L842-1 assume !(1 == ~T2_E~0); 9770#L847-1 assume !(1 == ~T3_E~0); 9771#L852-1 assume !(1 == ~T4_E~0); 9837#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9723#L862-1 assume !(1 == ~T6_E~0); 9724#L867-1 assume !(1 == ~T7_E~0); 9730#L872-1 assume !(1 == ~E_1~0); 9803#L877-1 assume !(1 == ~E_2~0); 9980#L882-1 assume !(1 == ~E_3~0); 10117#L887-1 assume !(1 == ~E_4~0); 10024#L892-1 assume !(1 == ~E_5~0); 10025#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 9746#L902-1 assume !(1 == ~E_7~0); 9747#L907-1 assume { :end_inline_reset_delta_events } true; 9614#L1148-2
[2024-11-08 18:32:29,794 INFO L747 eck$LassoCheckResult]: Loop: 9614#L1148-2 assume !false; 9388#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9389#L729-1 assume !false; 10000#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 9587#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 9588#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 9736#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 9632#L626 assume !(0 != eval_~tmp~0#1); 9634#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9846#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9661#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9400#L754-5 assume !(0 == ~T1_E~0); 9401#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9782#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9783#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9952#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9560#L779-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9395#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 9396#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9390#L794-3 assume !(0 == ~E_2~0); 9391#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9442#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 9668#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9438#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9439#L819-3 assume 0 == ~E_7~0;~E_7~0 := 1; 10056#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9800#L361-24 assume 1 == ~m_pc~0; 9544#L362-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 9545#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9490#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 9491#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10101#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9935#L380-24 assume !(1 == ~t1_pc~0); 9472#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 9473#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9882#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9657#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 9658#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10011#L399-24 assume 1 == ~t2_pc~0; 10076#L400-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9592#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9593#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9836#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9654#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9655#L418-24 assume 1 == ~t3_pc~0; 10100#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9437#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9727#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9563#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9564#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9994#L437-24 assume 1 == ~t4_pc~0; 10060#L438-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10061#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9835#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9547#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9548#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9942#L456-24 assume 1 == ~t5_pc~0; 9916#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9896#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9897#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10095#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 9848#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9849#L475-24 assume 1 == ~t6_pc~0; 9397#L476-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 9398#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9540#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9541#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 9379#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9380#L494-24 assume !(1 == ~t7_pc~0); 9728#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 9708#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9709#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9651#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 9652#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10059#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 10086#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9843#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9844#L847-3 assume !(1 == ~T3_E~0); 9990#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9900#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9901#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10143#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 9817#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9818#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 9895#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9946#L887-3 assume !(1 == ~E_4~0); 9579#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9580#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 10085#L902-3 assume 1 == ~E_7~0;~E_7~0 := 2; 9740#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 9741#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 9393#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 9677#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 9678#L1167 assume !(0 == start_simulation_~tmp~3#1); 9795#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 9796#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 9601#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 9406#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 9407#L1122 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 9777#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9778#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 9613#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 9614#L1148-2
[2024-11-08 18:32:29,795 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 18:32:29,795 INFO L85 PathProgramCache]: Analyzing trace with hash 1821437803, now seen corresponding path program 1 times
[2024-11-08 18:32:29,796 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 18:32:29,796 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [542587578]
[2024-11-08 18:32:29,796 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 18:32:29,796 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 18:32:29,811 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-11-08 18:32:29,863 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2024-11-08 18:32:29,863 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2024-11-08 18:32:29,863 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [542587578]
[2024-11-08 18:32:29,864 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [542587578] provided 1 perfect and 0 imperfect interpolant sequences
[2024-11-08 18:32:29,864 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2024-11-08 18:32:29,865 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2024-11-08 18:32:29,865 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1150350766]
[2024-11-08 18:32:29,865 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2024-11-08 18:32:29,865 INFO L750 eck$LassoCheckResult]: stem already infeasible
[2024-11-08 18:32:29,866 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 18:32:29,866 INFO L85 PathProgramCache]: Analyzing trace with hash -199378931, now seen corresponding path program 1 times
[2024-11-08 18:32:29,866 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 18:32:29,866 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [899222580]
[2024-11-08 18:32:29,866 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 18:32:29,867 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 18:32:29,881 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-11-08 18:32:29,919 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2024-11-08 18:32:29,920 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2024-11-08 18:32:29,920 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [899222580]
[2024-11-08 18:32:29,920 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [899222580] provided 1 perfect and 0 imperfect interpolant sequences
[2024-11-08 18:32:29,921 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2024-11-08 18:32:29,921 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2024-11-08 18:32:29,921 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [448167436]
[2024-11-08 18:32:29,921 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2024-11-08 18:32:29,922 INFO L762 eck$LassoCheckResult]: loop already infeasible
[2024-11-08 18:32:29,922 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2024-11-08 18:32:29,922 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2024-11-08 18:32:29,922 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2024-11-08 18:32:29,922 INFO L87 Difference]: Start difference. First operand 776 states and 1151 transitions. cyclomatic complexity: 376 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 18:32:29,942 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2024-11-08 18:32:29,942 INFO L93 Difference]: Finished difference Result 776 states and 1150 transitions.
[2024-11-08 18:32:29,942 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 776 states and 1150 transitions.
[2024-11-08 18:32:29,947 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 675
[2024-11-08 18:32:29,951 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 776 states to 776 states and 1150 transitions.
[2024-11-08 18:32:29,951 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 776
[2024-11-08 18:32:29,951 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 776
[2024-11-08 18:32:29,952 INFO L73 IsDeterministic]: Start isDeterministic. Operand 776 states and 1150 transitions.
[2024-11-08 18:32:29,953 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2024-11-08 18:32:29,953 INFO L218 hiAutomatonCegarLoop]: Abstraction has 776 states and 1150 transitions.
[2024-11-08 18:32:29,954 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 776 states and 1150 transitions.
[2024-11-08 18:32:29,963 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 776 to 776.
[2024-11-08 18:32:29,964 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 776 states, 776 states have (on average 1.481958762886598) internal successors, (1150), 775 states have internal predecessors, (1150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 18:32:29,967 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 776 states to 776 states and 1150 transitions.
[2024-11-08 18:32:29,967 INFO L240 hiAutomatonCegarLoop]: Abstraction has 776 states and 1150 transitions.
[2024-11-08 18:32:29,968 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states.
[2024-11-08 18:32:29,969 INFO L425 stractBuchiCegarLoop]: Abstraction has 776 states and 1150 transitions.
[2024-11-08 18:32:29,970 INFO L332 stractBuchiCegarLoop]: ======== Iteration 8 ============
[2024-11-08 18:32:29,970 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 776 states and 1150 transitions.
[2024-11-08 18:32:29,974 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 675
[2024-11-08 18:32:29,974 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2024-11-08 18:32:29,974 INFO L119 BuchiIsEmpty]: Starting construction of run
[2024-11-08 18:32:29,975 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 18:32:29,975 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 18:32:29,976 INFO L745 eck$LassoCheckResult]: Stem: 11144#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 11145#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 11672#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11673#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11692#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 11684#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11685#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11293#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 11294#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 11363#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 11208#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 11209#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 11174#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11175#L754 assume !(0 == ~M_E~0); 11700#L754-2 assume !(0 == ~T1_E~0); 11642#L759-1 assume !(0 == ~T2_E~0); 11524#L764-1 assume !(0 == ~T3_E~0); 11490#L769-1 assume !(0 == ~T4_E~0); 11491#L774-1 assume !(0 == ~T5_E~0); 11525#L779-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11647#L784-1 assume !(0 == ~T7_E~0); 11487#L789-1 assume !(0 == ~E_1~0); 11488#L794-1 assume !(0 == ~E_2~0); 11561#L799-1 assume !(0 == ~E_3~0); 11497#L804-1 assume !(0 == ~E_4~0); 11498#L809-1 assume !(0 == ~E_5~0); 11519#L814-1 assume !(0 == ~E_6~0); 10949#L819-1 assume 0 == ~E_7~0;~E_7~0 := 1; 10950#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11204#L361 assume 1 == ~m_pc~0; 11205#L362 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 11668#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11628#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 11629#L930 assume !(0 != activate_threads_~tmp~1#1); 11406#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11198#L380 assume !(1 == ~t1_pc~0); 11199#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 11567#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10967#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 10968#L938 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11587#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11568#L399 assume 1 == ~t2_pc~0; 11569#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11116#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11276#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11269#L946 assume !(0 != activate_threads_~tmp___1~0#1); 11270#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10953#L418 assume !(1 == ~t3_pc~0); 10932#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 10933#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10943#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10944#L954 assume !(0 != activate_threads_~tmp___2~0#1); 11509#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11510#L437 assume 1 == ~t4_pc~0; 11701#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 11624#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11027#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 11028#L962 assume !(0 != activate_threads_~tmp___3~0#1); 11322#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11610#L456 assume !(1 == ~t5_pc~0); 11130#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 11129#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11632#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11551#L970 assume !(0 != activate_threads_~tmp___4~0#1); 11552#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11020#L475 assume 1 == ~t6_pc~0; 11021#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11062#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11063#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11262#L978 assume !(0 != activate_threads_~tmp___5~0#1); 11502#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11503#L494 assume 1 == ~t7_pc~0; 11451#L495 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11247#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11462#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11526#L986 assume !(0 != activate_threads_~tmp___6~0#1); 11527#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11697#L837 assume !(1 == ~M_E~0); 11671#L837-2 assume !(1 == ~T1_E~0); 11564#L842-1 assume !(1 == ~T2_E~0); 11329#L847-1 assume !(1 == ~T3_E~0); 11330#L852-1 assume !(1 == ~T4_E~0); 11396#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 11282#L862-1 assume !(1 == ~T6_E~0); 11283#L867-1 assume !(1 == ~T7_E~0); 11289#L872-1 assume !(1 == ~E_1~0); 11362#L877-1 assume !(1 == ~E_2~0); 11539#L882-1 assume !(1 == ~E_3~0); 11676#L887-1 assume !(1 == ~E_4~0); 11583#L892-1 assume !(1 == ~E_5~0); 11584#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 11305#L902-1 assume !(1 == ~E_7~0); 11306#L907-1 assume { :end_inline_reset_delta_events } true; 11173#L1148-2
[2024-11-08 18:32:29,976 INFO L747 eck$LassoCheckResult]: Loop: 11173#L1148-2 assume !false; 10945#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10946#L729-1 assume !false; 11559#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 11146#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 11147#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 11295#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 11191#L626 assume !(0 != eval_~tmp~0#1); 11193#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11405#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11220#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 10959#L754-5 assume !(0 == ~T1_E~0); 10960#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11341#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11342#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11511#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11119#L779-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10954#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 10955#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10947#L794-3 assume !(0 == ~E_2~0); 10948#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 11001#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 11227#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10997#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 10998#L819-3 assume 0 == ~E_7~0;~E_7~0 := 1; 11615#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11359#L361-24 assume !(1 == ~m_pc~0); 11105#L361-26 is_master_triggered_~__retres1~0#1 := 0; 11104#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11049#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 11050#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 11660#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11494#L380-24 assume !(1 == ~t1_pc~0); 11031#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 11032#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11441#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 11216#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11217#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11570#L399-24 assume 1 == ~t2_pc~0; 11635#L400-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11151#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11152#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11395#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11213#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11214#L418-24 assume !(1 == ~t3_pc~0); 10995#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 10996#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11286#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 11122#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 11123#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11553#L437-24 assume 1 == ~t4_pc~0; 11619#L438-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 11620#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11394#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 11106#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 11107#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11501#L456-24 assume 1 == ~t5_pc~0; 11475#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 11455#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11456#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11654#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 11407#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11408#L475-24 assume 1 == ~t6_pc~0; 10956#L476-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10957#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11099#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11100#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 10938#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10939#L494-24 assume 1 == ~t7_pc~0; 11378#L495-8 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11267#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11268#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11210#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 11211#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11618#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 11645#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11402#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11403#L847-3 assume !(1 == ~T3_E~0); 11549#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11459#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 11460#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 11702#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 11376#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 11377#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 11454#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 11505#L887-3 assume !(1 == ~E_4~0); 11138#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 11139#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 11644#L902-3 assume 1 == ~E_7~0;~E_7~0 := 2; 11299#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 11300#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 10952#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 11236#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 11237#L1167 assume !(0 == start_simulation_~tmp~3#1); 11354#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 11355#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 11160#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 10965#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 10966#L1122 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 11336#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11337#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 11172#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 11173#L1148-2
[2024-11-08 18:32:29,977 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 18:32:29,977 INFO L85 PathProgramCache]: Analyzing trace with hash 254679853, now seen corresponding path program 1 times
[2024-11-08 18:32:29,977 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 18:32:29,977 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2146250555]
[2024-11-08 18:32:29,978 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 18:32:29,979 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 18:32:29,993 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-11-08 18:32:30,066 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2024-11-08 18:32:30,067 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2024-11-08 18:32:30,069 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2146250555]
[2024-11-08 18:32:30,073 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2146250555] provided 1 perfect and 0 imperfect interpolant sequences
[2024-11-08 18:32:30,073 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2024-11-08 18:32:30,073 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2024-11-08 18:32:30,073 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1690554526]
[2024-11-08 18:32:30,073 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2024-11-08 18:32:30,074 INFO L750 eck$LassoCheckResult]: stem already infeasible
[2024-11-08 18:32:30,074 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 18:32:30,074 INFO L85 PathProgramCache]: Analyzing trace with hash 366741804, now seen corresponding path program 1 times
[2024-11-08 18:32:30,074 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 18:32:30,074 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1908631949]
[2024-11-08 18:32:30,075 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 18:32:30,075 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 18:32:30,093 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-11-08 18:32:30,142 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2024-11-08 18:32:30,142 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2024-11-08 18:32:30,142 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1908631949]
[2024-11-08 18:32:30,144 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1908631949] provided 1 perfect and 0 imperfect interpolant sequences
[2024-11-08 18:32:30,145 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2024-11-08 18:32:30,145 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2024-11-08 18:32:30,145 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [497244382]
[2024-11-08 18:32:30,145 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2024-11-08 18:32:30,145 INFO L762 eck$LassoCheckResult]: loop already infeasible
[2024-11-08 18:32:30,145 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2024-11-08 18:32:30,146 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants.
[2024-11-08 18:32:30,146 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12
[2024-11-08 18:32:30,146 INFO L87 Difference]: Start difference. First operand 776 states and 1150 transitions. cyclomatic complexity: 375 Second operand has 4 states, 4 states have (on average 23.25) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 18:32:30,312 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2024-11-08 18:32:30,312 INFO L93 Difference]: Finished difference Result 1464 states and 2164 transitions.
[2024-11-08 18:32:30,312 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1464 states and 2164 transitions.
[2024-11-08 18:32:30,322 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1350
[2024-11-08 18:32:30,329 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1464 states to 1464 states and 2164 transitions.
[2024-11-08 18:32:30,329 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1464
[2024-11-08 18:32:30,330 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1464
[2024-11-08 18:32:30,330 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1464 states and 2164 transitions.
[2024-11-08 18:32:30,333 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2024-11-08 18:32:30,333 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1464 states and 2164 transitions.
[2024-11-08 18:32:30,337 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1464 states and 2164 transitions.
[2024-11-08 18:32:30,389 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1464 to 1464.
[2024-11-08 18:32:30,392 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1464 states, 1464 states have (on average 1.4781420765027322) internal successors, (2164), 1463 states have internal predecessors, (2164), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 18:32:30,398 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1464 states to 1464 states and 2164 transitions.
[2024-11-08 18:32:30,398 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1464 states and 2164 transitions.
[2024-11-08 18:32:30,399 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states.
[2024-11-08 18:32:30,399 INFO L425 stractBuchiCegarLoop]: Abstraction has 1464 states and 2164 transitions.
[2024-11-08 18:32:30,400 INFO L332 stractBuchiCegarLoop]: ======== Iteration 9 ============
[2024-11-08 18:32:30,400 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1464 states and 2164 transitions.
[2024-11-08 18:32:30,410 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1350
[2024-11-08 18:32:30,410 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2024-11-08 18:32:30,410 INFO L119 BuchiIsEmpty]: Starting construction of run
[2024-11-08 18:32:30,413 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 18:32:30,413 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 18:32:30,414 INFO L745 eck$LassoCheckResult]: Stem: 13394#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 13395#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 13965#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13966#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 13997#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 13986#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13987#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 13545#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 13546#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 13617#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 13457#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 13458#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 13424#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13425#L754 assume !(0 == ~M_E~0); 14012#L754-2 assume !(0 == ~T1_E~0); 13926#L759-1 assume !(0 == ~T2_E~0); 13794#L764-1 assume !(0 == ~T3_E~0); 13755#L769-1 assume !(0 == ~T4_E~0); 13756#L774-1 assume !(0 == ~T5_E~0); 13795#L779-1 assume !(0 == ~T6_E~0); 13931#L784-1 assume !(0 == ~T7_E~0); 13752#L789-1 assume !(0 == ~E_1~0); 13753#L794-1 assume !(0 == ~E_2~0); 13833#L799-1 assume !(0 == ~E_3~0); 13763#L804-1 assume !(0 == ~E_4~0); 13764#L809-1 assume !(0 == ~E_5~0); 13789#L814-1 assume !(0 == ~E_6~0); 13195#L819-1 assume 0 == ~E_7~0;~E_7~0 := 1; 13196#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13454#L361 assume 1 == ~m_pc~0; 13455#L362 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 13959#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13912#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 13913#L930 assume !(0 != activate_threads_~tmp~1#1); 13661#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13448#L380 assume !(1 == ~t1_pc~0); 13449#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 13844#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13217#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 13218#L938 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 13869#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13845#L399 assume 1 == ~t2_pc~0; 13846#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13366#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13528#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 13521#L946 assume !(0 != activate_threads_~tmp___1~0#1); 13522#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13203#L418 assume !(1 == ~t3_pc~0); 13182#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 13183#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13193#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 13194#L954 assume !(0 != activate_threads_~tmp___2~0#1); 13777#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13778#L437 assume 1 == ~t4_pc~0; 14013#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13906#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13276#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 13277#L962 assume !(0 != activate_threads_~tmp___3~0#1); 13574#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13892#L456 assume !(1 == ~t5_pc~0); 13380#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 13379#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13916#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 13822#L970 assume !(0 != activate_threads_~tmp___4~0#1); 13823#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13270#L475 assume 1 == ~t6_pc~0; 13271#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13312#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13313#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13514#L978 assume !(0 != activate_threads_~tmp___5~0#1); 13769#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13770#L494 assume 1 == ~t7_pc~0; 13711#L495 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 13499#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13725#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13796#L986 assume !(0 != activate_threads_~tmp___6~0#1); 13797#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14003#L837 assume !(1 == ~M_E~0); 13964#L837-2 assume !(1 == ~T1_E~0); 13840#L842-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 13841#L847-1 assume !(1 == ~T3_E~0); 14372#L852-1 assume !(1 == ~T4_E~0); 14026#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 13534#L862-1 assume !(1 == ~T6_E~0); 13535#L867-1 assume !(1 == ~T7_E~0); 13541#L872-1 assume !(1 == ~E_1~0); 13616#L877-1 assume !(1 == ~E_2~0); 13811#L882-1 assume !(1 == ~E_3~0); 13970#L887-1 assume !(1 == ~E_4~0); 13862#L892-1 assume !(1 == ~E_5~0); 13863#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 14054#L902-1 assume !(1 == ~E_7~0); 14051#L907-1 assume { :end_inline_reset_delta_events } true; 14049#L1148-2
[2024-11-08 18:32:30,415 INFO L747 eck$LassoCheckResult]: Loop: 14049#L1148-2 assume !false; 14042#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 14041#L729-1 assume !false; 14040#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 14032#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 13938#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 13552#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 13443#L626 assume !(0 != eval_~tmp~0#1); 13445#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 13660#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 13472#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 13209#L754-5 assume !(0 == ~T1_E~0); 13210#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 14027#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14487#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13779#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13373#L779-3 assume !(0 == ~T6_E~0); 13204#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 13205#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 13199#L794-3 assume !(0 == ~E_2~0); 13200#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 13251#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 13479#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 13249#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 13250#L819-3 assume 0 == ~E_7~0;~E_7~0 := 1; 13897#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13612#L361-24 assume 1 == ~m_pc~0; 13613#L362-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 14406#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14405#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 14404#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14403#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14402#L380-24 assume !(1 == ~t1_pc~0); 13281#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 13282#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13701#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 13468#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 13469#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13847#L399-24 assume 1 == ~t2_pc~0; 13919#L400-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13401#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13402#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 13650#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 13465#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13466#L418-24 assume !(1 == ~t3_pc~0); 13245#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 13246#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13537#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 13371#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13372#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13824#L437-24 assume !(1 == ~t4_pc~0); 13904#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 13903#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13649#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 13356#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13357#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13768#L456-24 assume 1 == ~t5_pc~0; 13739#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 13740#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14373#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 13967#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 13662#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13663#L475-24 assume !(1 == ~t6_pc~0); 14023#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 13724#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13349#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13350#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 14329#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13717#L494-24 assume 1 == ~t7_pc~0; 13633#L495-8 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 13518#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13519#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13462#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 13463#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13901#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 13929#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13657#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 13658#L847-3 assume !(1 == ~T3_E~0); 13820#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 13720#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 13721#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 14016#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 13628#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13629#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 13714#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 13773#L887-3 assume !(1 == ~E_4~0); 13388#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 13389#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 13928#L902-3 assume 1 == ~E_7~0;~E_7~0 := 2; 13550#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 13551#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 13202#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 13488#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 13489#L1167 assume !(0 == start_simulation_~tmp~3#1); 13606#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 13607#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 13410#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 13215#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 13216#L1122 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 13588#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 13589#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 13675#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 14049#L1148-2
[2024-11-08 18:32:30,415 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 18:32:30,416 INFO L85 PathProgramCache]: Analyzing trace with hash -2141947347, now seen corresponding path program 1 times
[2024-11-08 18:32:30,416 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 18:32:30,416 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [374102842]
[2024-11-08 18:32:30,416 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 18:32:30,417 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 18:32:30,439 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-11-08 18:32:30,508 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2024-11-08 18:32:30,509 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2024-11-08 18:32:30,509 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [374102842]
[2024-11-08 18:32:30,509 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [374102842] provided 1 perfect and 0 imperfect interpolant sequences
[2024-11-08 18:32:30,509 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2024-11-08 18:32:30,509 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2
[2024-11-08 18:32:30,510 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1920458478]
[2024-11-08 18:32:30,510 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2024-11-08 18:32:30,510 INFO L750 eck$LassoCheckResult]: stem already infeasible
[2024-11-08 18:32:30,511 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 18:32:30,512 INFO L85 PathProgramCache]: Analyzing trace with hash -1972527863, now seen corresponding path program 1 times
[2024-11-08 18:32:30,512 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 18:32:30,512 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [543922300]
[2024-11-08 18:32:30,512 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 18:32:30,513 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 18:32:30,533 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-11-08 18:32:30,592 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2024-11-08 18:32:30,593 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2024-11-08 18:32:30,593 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [543922300]
[2024-11-08 18:32:30,593 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [543922300] provided 1 perfect and 0 imperfect interpolant sequences
[2024-11-08 18:32:30,593 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2024-11-08 18:32:30,593 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2024-11-08 18:32:30,594 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1267362361]
[2024-11-08 18:32:30,594 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2024-11-08 18:32:30,594 INFO L762 eck$LassoCheckResult]: loop already infeasible
[2024-11-08 18:32:30,595 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2024-11-08 18:32:30,595 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2024-11-08 18:32:30,595 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2024-11-08 18:32:30,596 INFO L87 Difference]: Start difference. First operand 1464 states and 2164 transitions. cyclomatic complexity: 702 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 2 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 18:32:30,665 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2024-11-08 18:32:30,665 INFO L93 Difference]: Finished difference Result 1464 states and 2138 transitions.
[2024-11-08 18:32:30,666 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1464 states and 2138 transitions.
[2024-11-08 18:32:30,675 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1350
[2024-11-08 18:32:30,682 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1464 states to 1464 states and 2138 transitions.
[2024-11-08 18:32:30,682 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1464
[2024-11-08 18:32:30,684 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1464
[2024-11-08 18:32:30,684 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1464 states and 2138 transitions.
[2024-11-08 18:32:30,686 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2024-11-08 18:32:30,686 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1464 states and 2138 transitions.
[2024-11-08 18:32:30,688 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1464 states and 2138 transitions.
[2024-11-08 18:32:30,709 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1464 to 1464.
[2024-11-08 18:32:30,712 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1464 states, 1464 states have (on average 1.460382513661202) internal successors, (2138), 1463 states have internal predecessors, (2138), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 18:32:30,717 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1464 states to 1464 states and 2138 transitions.
[2024-11-08 18:32:30,718 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1464 states and 2138 transitions.
[2024-11-08 18:32:30,718 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states.
[2024-11-08 18:32:30,719 INFO L425 stractBuchiCegarLoop]: Abstraction has 1464 states and 2138 transitions.
[2024-11-08 18:32:30,720 INFO L332 stractBuchiCegarLoop]: ======== Iteration 10 ============
[2024-11-08 18:32:30,720 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1464 states and 2138 transitions.
[2024-11-08 18:32:30,730 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1350
[2024-11-08 18:32:30,731 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2024-11-08 18:32:30,731 INFO L119 BuchiIsEmpty]: Starting construction of run
[2024-11-08 18:32:30,732 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 18:32:30,732 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 18:32:30,733 INFO L745 eck$LassoCheckResult]: Stem: 16327#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 16328#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 16892#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16893#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16925#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 16909#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16910#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 16478#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 16479#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 16550#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 16390#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 16391#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 16357#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16358#L754 assume !(0 == ~M_E~0); 16939#L754-2 assume !(0 == ~T1_E~0); 16856#L759-1 assume !(0 == ~T2_E~0); 16721#L764-1 assume !(0 == ~T3_E~0); 16680#L769-1 assume !(0 == ~T4_E~0); 16681#L774-1 assume !(0 == ~T5_E~0); 16722#L779-1 assume !(0 == ~T6_E~0); 16861#L784-1 assume !(0 == ~T7_E~0); 16677#L789-1 assume !(0 == ~E_1~0); 16678#L794-1 assume !(0 == ~E_2~0); 16763#L799-1 assume !(0 == ~E_3~0); 16688#L804-1 assume !(0 == ~E_4~0); 16689#L809-1 assume !(0 == ~E_5~0); 16715#L814-1 assume !(0 == ~E_6~0); 16130#L819-1 assume !(0 == ~E_7~0); 16131#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16387#L361 assume 1 == ~m_pc~0; 16388#L362 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 16885#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16842#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 16843#L930 assume !(0 != activate_threads_~tmp~1#1); 16593#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16381#L380 assume !(1 == ~t1_pc~0); 16382#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 16773#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16152#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 16153#L938 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 16797#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16774#L399 assume 1 == ~t2_pc~0; 16775#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 16299#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16461#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 16454#L946 assume !(0 != activate_threads_~tmp___1~0#1); 16455#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16138#L418 assume !(1 == ~t3_pc~0); 16117#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 16118#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16128#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 16129#L954 assume !(0 != activate_threads_~tmp___2~0#1); 16703#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16704#L437 assume 1 == ~t4_pc~0; 16940#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 16835#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16211#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 16212#L962 assume !(0 != activate_threads_~tmp___3~0#1); 16508#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16817#L456 assume !(1 == ~t5_pc~0); 16313#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 16312#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16846#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 16751#L970 assume !(0 != activate_threads_~tmp___4~0#1); 16752#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16205#L475 assume 1 == ~t6_pc~0; 16206#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 16247#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16248#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16447#L978 assume !(0 != activate_threads_~tmp___5~0#1); 16694#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16695#L494 assume !(1 == ~t7_pc~0); 16431#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 16432#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16653#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16723#L986 assume !(0 != activate_threads_~tmp___6~0#1); 16724#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16932#L837 assume !(1 == ~M_E~0); 16891#L837-2 assume !(1 == ~T1_E~0); 16768#L842-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 16515#L847-1 assume !(1 == ~T3_E~0); 16516#L852-1 assume !(1 == ~T4_E~0); 16583#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 16467#L862-1 assume !(1 == ~T6_E~0); 16468#L867-1 assume !(1 == ~T7_E~0); 16474#L872-1 assume !(1 == ~E_1~0); 16549#L877-1 assume !(1 == ~E_2~0); 16738#L882-1 assume !(1 == ~E_3~0); 16897#L887-1 assume !(1 == ~E_4~0); 16790#L892-1 assume !(1 == ~E_5~0); 16791#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 16491#L902-1 assume !(1 == ~E_7~0); 16492#L907-1 assume { :end_inline_reset_delta_events } true; 16536#L1148-2
[2024-11-08 18:32:30,733 INFO L747 eck$LassoCheckResult]: Loop: 16536#L1148-2 assume !false; 16537#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16760#L729-1 assume !false; 16761#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 16329#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 16330#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 16952#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 16374#L626 assume !(0 != eval_~tmp~0#1); 16376#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 16592#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 16403#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 16144#L754-5 assume !(0 == ~T1_E~0); 16145#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 16526#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 16527#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17436#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 17434#L779-3 assume !(0 == ~T6_E~0); 17431#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 17429#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 17428#L794-3 assume !(0 == ~E_2~0); 17427#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 17426#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 17425#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 17424#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 17423#L819-3 assume !(0 == ~E_7~0); 17422#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17421#L361-24 assume 1 == ~m_pc~0; 17419#L362-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 17418#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17417#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 17416#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 17415#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17414#L380-24 assume !(1 == ~t1_pc~0); 17412#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 17411#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17410#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 17409#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 17408#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17407#L399-24 assume 1 == ~t2_pc~0; 17405#L400-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 17404#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17403#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 17402#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 17401#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17400#L418-24 assume !(1 == ~t3_pc~0); 16180#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 16181#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16471#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 16305#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 16306#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16754#L437-24 assume !(1 == ~t4_pc~0); 16833#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 16832#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16581#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 16290#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 16291#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17382#L456-24 assume !(1 == ~t5_pc~0); 17379#L456-26 is_transmit5_triggered_~__retres1~5#1 := 0; 17376#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17374#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 17372#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 17370#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17369#L475-24 assume 1 == ~t6_pc~0; 16141#L476-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 16142#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16283#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16284#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 16123#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16124#L494-24 assume !(1 == ~t7_pc~0); 16472#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 16452#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16453#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16393#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 16394#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16830#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 16859#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 16589#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 16590#L847-3 assume !(1 == ~T3_E~0); 16750#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16650#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 16651#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 16942#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 16563#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 16564#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 16644#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 16698#L887-3 assume !(1 == ~E_4~0); 16321#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 16322#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 16858#L902-3 assume !(1 == ~E_7~0); 16485#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 16486#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 16137#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 16420#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 16421#L1167 assume !(0 == start_simulation_~tmp~3#1); 16541#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 16542#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 16343#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 16150#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 16151#L1122 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 16521#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16522#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 16965#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 16536#L1148-2
[2024-11-08 18:32:30,734 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 18:32:30,734 INFO L85 PathProgramCache]: Analyzing trace with hash 1307665866, now seen corresponding path program 1 times
[2024-11-08 18:32:30,734 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 18:32:30,735 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [820012766]
[2024-11-08 18:32:30,735 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 18:32:30,735 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 18:32:30,749 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-11-08 18:32:30,797 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2024-11-08 18:32:30,798 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2024-11-08 18:32:30,798 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [820012766]
[2024-11-08 18:32:30,801 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [820012766] provided 1 perfect and 0 imperfect interpolant sequences
[2024-11-08 18:32:30,801 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2024-11-08 18:32:30,801 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2
[2024-11-08 18:32:30,801 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1846575870]
[2024-11-08 18:32:30,801 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2024-11-08 18:32:30,802 INFO L750 eck$LassoCheckResult]: stem already infeasible
[2024-11-08 18:32:30,802 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 18:32:30,802 INFO L85 PathProgramCache]: Analyzing trace with hash -1186290396, now seen corresponding path program 1 times
[2024-11-08 18:32:30,802 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 18:32:30,802 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2139258846]
[2024-11-08 18:32:30,803 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 18:32:30,803 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 18:32:30,817 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-11-08 18:32:30,862 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2024-11-08 18:32:30,862 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2024-11-08 18:32:30,862 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2139258846]
[2024-11-08 18:32:30,862 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2139258846] provided 1 perfect and 0 imperfect interpolant sequences
[2024-11-08 18:32:30,865 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2024-11-08 18:32:30,865 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2024-11-08 18:32:30,866 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1816462673]
[2024-11-08 18:32:30,866 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2024-11-08 18:32:30,866 INFO L762 eck$LassoCheckResult]: loop already infeasible
[2024-11-08 18:32:30,866 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2024-11-08 18:32:30,867 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2024-11-08 18:32:30,867 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2024-11-08 18:32:30,867 INFO L87 Difference]: Start difference. First operand 1464 states and 2138 transitions. cyclomatic complexity: 676 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 2 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 18:32:30,997 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2024-11-08 18:32:30,998 INFO L93 Difference]: Finished difference Result 2793 states and 4040 transitions.
[2024-11-08 18:32:30,998 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2793 states and 4040 transitions.
[2024-11-08 18:32:31,014 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2676
[2024-11-08 18:32:31,027 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2793 states to 2793 states and 4040 transitions.
[2024-11-08 18:32:31,027 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2793
[2024-11-08 18:32:31,029 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2793
[2024-11-08 18:32:31,029 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2793 states and 4040 transitions.
[2024-11-08 18:32:31,033 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2024-11-08 18:32:31,033 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2793 states and 4040 transitions.
[2024-11-08 18:32:31,036 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2793 states and 4040 transitions.
[2024-11-08 18:32:31,074 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2793 to 2679.
[2024-11-08 18:32:31,079 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2679 states, 2679 states have (on average 1.4497946995147444) internal successors, (3884), 2678 states have internal predecessors, (3884), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 18:32:31,088 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2679 states to 2679 states and 3884 transitions.
[2024-11-08 18:32:31,088 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2679 states and 3884 transitions.
[2024-11-08 18:32:31,089 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states.
[2024-11-08 18:32:31,090 INFO L425 stractBuchiCegarLoop]: Abstraction has 2679 states and 3884 transitions.
[2024-11-08 18:32:31,090 INFO L332 stractBuchiCegarLoop]: ======== Iteration 11 ============
[2024-11-08 18:32:31,090 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2679 states and 3884 transitions.
[2024-11-08 18:32:31,105 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2562
[2024-11-08 18:32:31,105 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2024-11-08 18:32:31,105 INFO L119 BuchiIsEmpty]: Starting construction of run
[2024-11-08 18:32:31,107 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 18:32:31,107 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 18:32:31,107 INFO L745 eck$LassoCheckResult]: Stem: 20592#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 20593#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 21218#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 21219#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21278#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 21250#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21251#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 20747#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20748#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 20821#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 20654#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 20655#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 20622#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20623#L754 assume !(0 == ~M_E~0); 21300#L754-2 assume !(0 == ~T1_E~0); 21169#L759-1 assume !(0 == ~T2_E~0); 21018#L764-1 assume !(0 == ~T3_E~0); 20970#L769-1 assume !(0 == ~T4_E~0); 20971#L774-1 assume !(0 == ~T5_E~0); 21019#L779-1 assume !(0 == ~T6_E~0); 21177#L784-1 assume !(0 == ~T7_E~0); 20967#L789-1 assume !(0 == ~E_1~0); 20968#L794-1 assume !(0 == ~E_2~0); 21067#L799-1 assume !(0 == ~E_3~0); 20980#L804-1 assume !(0 == ~E_4~0); 20981#L809-1 assume !(0 == ~E_5~0); 21012#L814-1 assume !(0 == ~E_6~0); 20394#L819-1 assume !(0 == ~E_7~0); 20395#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20652#L361 assume !(1 == ~m_pc~0); 20653#L361-2 is_master_triggered_~__retres1~0#1 := 0; 21211#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21154#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 21155#L930 assume !(0 != activate_threads_~tmp~1#1); 20869#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20646#L380 assume !(1 == ~t1_pc~0); 20647#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 21075#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20416#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 20417#L938 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 21104#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21076#L399 assume 1 == ~t2_pc~0; 21077#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 20564#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20728#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 20721#L946 assume !(0 != activate_threads_~tmp___1~0#1); 20722#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20402#L418 assume !(1 == ~t3_pc~0); 20381#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 20382#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20392#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 20393#L954 assume !(0 != activate_threads_~tmp___2~0#1); 20998#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20999#L437 assume 1 == ~t4_pc~0; 21301#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21149#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20475#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 20476#L962 assume !(0 != activate_threads_~tmp___3~0#1); 20776#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 21125#L456 assume !(1 == ~t5_pc~0); 20578#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 20577#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21158#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 21053#L970 assume !(0 != activate_threads_~tmp___4~0#1); 21054#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 20469#L475 assume 1 == ~t6_pc~0; 20470#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 20510#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 20511#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20714#L978 assume !(0 != activate_threads_~tmp___5~0#1); 20987#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20988#L494 assume !(1 == ~t7_pc~0); 20698#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 20699#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20937#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 21020#L986 assume !(0 != activate_threads_~tmp___6~0#1); 21021#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21290#L837 assume !(1 == ~M_E~0); 21217#L837-2 assume !(1 == ~T1_E~0); 21071#L842-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 21072#L847-1 assume !(1 == ~T3_E~0); 23030#L852-1 assume !(1 == ~T4_E~0); 23029#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 23028#L862-1 assume !(1 == ~T6_E~0); 20735#L867-1 assume !(1 == ~T7_E~0); 23027#L872-1 assume !(1 == ~E_1~0); 23026#L877-1 assume !(1 == ~E_2~0); 23025#L882-1 assume !(1 == ~E_3~0); 21308#L887-1 assume !(1 == ~E_4~0); 21098#L892-1 assume !(1 == ~E_5~0); 21099#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 22601#L902-1 assume !(1 == ~E_7~0); 22598#L907-1 assume { :end_inline_reset_delta_events } true; 20804#L1148-2
[2024-11-08 18:32:31,108 INFO L747 eck$LassoCheckResult]: Loop: 20804#L1148-2 assume !false; 20396#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 20397#L729-1 assume !false; 22592#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 22584#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 21183#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 21184#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 22582#L626 assume !(0 != eval_~tmp~0#1); 21100#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 21101#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 20667#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 20408#L754-5 assume !(0 == ~T1_E~0); 20409#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 22580#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 22899#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 22898#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 22897#L779-3 assume !(0 == ~T6_E~0); 22896#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 22895#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 22894#L794-3 assume !(0 == ~E_2~0); 22893#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 22892#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 22891#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 22890#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 22889#L819-3 assume !(0 == ~E_7~0); 22888#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22887#L361-24 assume !(1 == ~m_pc~0); 22886#L361-26 is_master_triggered_~__retres1~0#1 := 0; 22885#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22884#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 22883#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 22882#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20977#L380-24 assume !(1 == ~t1_pc~0); 20480#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 20481#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20908#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 20909#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 21078#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21079#L399-24 assume !(1 == ~t2_pc~0); 20683#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 20684#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21024#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 21025#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 20660#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20661#L418-24 assume 1 == ~t3_pc~0; 21200#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 20445#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21231#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 20570#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 20571#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21056#L437-24 assume 1 == ~t4_pc~0; 22868#L438-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 22867#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22866#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 20556#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20557#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 21274#L456-24 assume 1 == ~t5_pc~0; 21275#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 20926#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20927#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 22861#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 22859#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22854#L475-24 assume 1 == ~t6_pc~0; 20405#L476-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 20406#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 20549#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20550#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 20982#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20928#L494-24 assume !(1 == ~t7_pc~0); 20741#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 20719#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20720#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20657#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 20658#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21144#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 21174#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 20864#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 20865#L847-3 assume !(1 == ~T3_E~0); 21051#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 20932#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 20933#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 21305#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 21306#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 20924#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 20925#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 21318#L887-3 assume !(1 == ~E_4~0); 20586#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 20587#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 21332#L902-3 assume !(1 == ~E_7~0); 21333#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 21228#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 20401#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 20685#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 20686#L1167 assume !(0 == start_simulation_~tmp~3#1); 20808#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 20809#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 22608#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 22607#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 22605#L1122 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 22603#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 22602#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 22599#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 20804#L1148-2
[2024-11-08 18:32:31,109 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 18:32:31,109 INFO L85 PathProgramCache]: Analyzing trace with hash 2012584553, now seen corresponding path program 1 times
[2024-11-08 18:32:31,109 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 18:32:31,109 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1575361639]
[2024-11-08 18:32:31,109 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 18:32:31,110 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 18:32:31,124 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-11-08 18:32:31,190 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2024-11-08 18:32:31,190 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2024-11-08 18:32:31,190 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1575361639]
[2024-11-08 18:32:31,190 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1575361639] provided 1 perfect and 0 imperfect interpolant sequences
[2024-11-08 18:32:31,191 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2024-11-08 18:32:31,191 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5
[2024-11-08 18:32:31,191 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [958939196]
[2024-11-08 18:32:31,191 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2024-11-08 18:32:31,191 INFO L750 eck$LassoCheckResult]: stem already infeasible
[2024-11-08 18:32:31,192 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 18:32:31,193 INFO L85 PathProgramCache]: Analyzing trace with hash -1546000763, now seen corresponding path program 1 times
[2024-11-08 18:32:31,193 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 18:32:31,193 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2089858085]
[2024-11-08 18:32:31,193 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 18:32:31,194 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 18:32:31,208 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-11-08 18:32:31,245 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2024-11-08 18:32:31,246 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2024-11-08 18:32:31,246 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2089858085]
[2024-11-08 18:32:31,246 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2089858085] provided 1 perfect and 0 imperfect interpolant sequences
[2024-11-08 18:32:31,246 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2024-11-08 18:32:31,246 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2024-11-08 18:32:31,246 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1644738318]
[2024-11-08 18:32:31,247 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2024-11-08 18:32:31,247 INFO L762 eck$LassoCheckResult]: loop already infeasible
[2024-11-08 18:32:31,247 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2024-11-08 18:32:31,247 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants.
[2024-11-08 18:32:31,248 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20
[2024-11-08 18:32:31,248 INFO L87 Difference]: Start difference. First operand 2679 states and 3884 transitions. cyclomatic complexity: 1209 Second operand has 5 states, 5 states have (on average 18.6) internal successors, (93), 5 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 18:32:31,504 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2024-11-08 18:32:31,504 INFO L93 Difference]: Finished difference Result 2784 states and 3989 transitions.
[2024-11-08 18:32:31,504 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2784 states and 3989 transitions.
[2024-11-08 18:32:31,520 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2664
[2024-11-08 18:32:31,533 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2784 states to 2784 states and 3989 transitions.
[2024-11-08 18:32:31,533 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2784
[2024-11-08 18:32:31,536 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2784
[2024-11-08 18:32:31,536 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2784 states and 3989 transitions.
[2024-11-08 18:32:31,539 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2024-11-08 18:32:31,539 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2784 states and 3989 transitions.
[2024-11-08 18:32:31,542 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2784 states and 3989 transitions.
[2024-11-08 18:32:31,577 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2784 to 2784.
[2024-11-08 18:32:31,582 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2784 states, 2784 states have (on average 1.432830459770115) internal successors, (3989), 2783 states have internal predecessors, (3989), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 18:32:31,591 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2784 states to 2784 states and 3989 transitions.
[2024-11-08 18:32:31,591 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2784 states and 3989 transitions.
[2024-11-08 18:32:31,591 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states.
[2024-11-08 18:32:31,592 INFO L425 stractBuchiCegarLoop]: Abstraction has 2784 states and 3989 transitions.
[2024-11-08 18:32:31,592 INFO L332 stractBuchiCegarLoop]: ======== Iteration 12 ============
[2024-11-08 18:32:31,592 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2784 states and 3989 transitions.
[2024-11-08 18:32:31,603 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2664
[2024-11-08 18:32:31,604 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2024-11-08 18:32:31,604 INFO L119 BuchiIsEmpty]: Starting construction of run
[2024-11-08 18:32:31,605 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 18:32:31,605 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 18:32:31,606 INFO L745 eck$LassoCheckResult]: Stem: 26064#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 26065#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 26625#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 26626#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 26660#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 26649#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 26650#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 26218#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 26219#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 26289#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 26129#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 26130#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 26095#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 26096#L754 assume !(0 == ~M_E~0); 26673#L754-2 assume !(0 == ~T1_E~0); 26591#L759-1 assume !(0 == ~T2_E~0); 26459#L764-1 assume !(0 == ~T3_E~0); 26420#L769-1 assume !(0 == ~T4_E~0); 26421#L774-1 assume !(0 == ~T5_E~0); 26460#L779-1 assume !(0 == ~T6_E~0); 26598#L784-1 assume !(0 == ~T7_E~0); 26417#L789-1 assume !(0 == ~E_1~0); 26418#L794-1 assume !(0 == ~E_2~0); 26503#L799-1 assume !(0 == ~E_3~0); 26427#L804-1 assume !(0 == ~E_4~0); 26428#L809-1 assume !(0 == ~E_5~0); 26454#L814-1 assume !(0 == ~E_6~0); 25870#L819-1 assume !(0 == ~E_7~0); 25871#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26125#L361 assume !(1 == ~m_pc~0); 26126#L361-2 is_master_triggered_~__retres1~0#1 := 0; 26621#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26578#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 26579#L930 assume !(0 != activate_threads_~tmp~1#1); 26333#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26119#L380 assume !(1 == ~t1_pc~0); 26120#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 26658#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25888#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 25889#L938 assume !(0 != activate_threads_~tmp___0~0#1); 26535#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26515#L399 assume 1 == ~t2_pc~0; 26516#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 26036#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26199#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 26192#L946 assume !(0 != activate_threads_~tmp___1~0#1); 26193#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25874#L418 assume !(1 == ~t3_pc~0); 25853#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 25854#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25864#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 25865#L954 assume !(0 != activate_threads_~tmp___2~0#1); 26441#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26442#L437 assume 1 == ~t4_pc~0; 26674#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 26573#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25947#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 25948#L962 assume !(0 != activate_threads_~tmp___3~0#1); 26247#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26559#L456 assume !(1 == ~t5_pc~0); 26050#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 26049#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26582#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 26492#L970 assume !(0 != activate_threads_~tmp___4~0#1); 26493#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25941#L475 assume 1 == ~t6_pc~0; 25942#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 25984#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25985#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 26185#L978 assume !(0 != activate_threads_~tmp___5~0#1); 26432#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 26433#L494 assume !(1 == ~t7_pc~0); 26169#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 26170#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 26389#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26461#L986 assume !(0 != activate_threads_~tmp___6~0#1); 26462#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26667#L837 assume !(1 == ~M_E~0); 26624#L837-2 assume !(1 == ~T1_E~0); 26510#L842-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 26511#L847-1 assume !(1 == ~T3_E~0); 28012#L852-1 assume !(1 == ~T4_E~0); 28008#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 28006#L862-1 assume !(1 == ~T6_E~0); 26206#L867-1 assume !(1 == ~T7_E~0); 28005#L872-1 assume !(1 == ~E_1~0); 28004#L877-1 assume !(1 == ~E_2~0); 28003#L882-1 assume !(1 == ~E_3~0); 28002#L887-1 assume !(1 == ~E_4~0); 28001#L892-1 assume !(1 == ~E_5~0); 28000#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 27991#L902-1 assume !(1 == ~E_7~0); 27981#L907-1 assume { :end_inline_reset_delta_events } true; 27980#L1148-2
[2024-11-08 18:32:31,606 INFO L747 eck$LassoCheckResult]: Loop: 27980#L1148-2 assume !false; 27567#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 27566#L729-1 assume !false; 27565#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 27557#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 27556#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 27555#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 27553#L626 assume !(0 != eval_~tmp~0#1); 27554#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 28188#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 28187#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 28186#L754-5 assume !(0 == ~T1_E~0); 28185#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 28184#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 28182#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 28181#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 28180#L779-3 assume !(0 == ~T6_E~0); 28179#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 28177#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 28176#L794-3 assume !(0 == ~E_2~0); 28175#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 28174#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 28173#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 28171#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 28169#L819-3 assume !(0 == ~E_7~0); 28167#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28165#L361-24 assume !(1 == ~m_pc~0); 28163#L361-26 is_master_triggered_~__retres1~0#1 := 0; 28161#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28157#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 28155#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 28153#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28151#L380-24 assume !(1 == ~t1_pc~0); 28146#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 28144#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28142#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 28139#L938-24 assume !(0 != activate_threads_~tmp___0~0#1); 28136#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28134#L399-24 assume 1 == ~t2_pc~0; 28131#L400-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 28129#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 28127#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 28124#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 28122#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28120#L418-24 assume !(1 == ~t3_pc~0); 28117#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 28115#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28113#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 28110#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 28108#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28106#L437-24 assume 1 == ~t4_pc~0; 28103#L438-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 28101#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28099#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 28096#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 28094#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 28092#L456-24 assume !(1 == ~t5_pc~0); 28089#L456-26 is_transmit5_triggered_~__retres1~5#1 := 0; 28087#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28085#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 28082#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 28080#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 28078#L475-24 assume 1 == ~t6_pc~0; 28075#L476-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 28073#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 28070#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 28068#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 28066#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 28064#L494-24 assume !(1 == ~t7_pc~0); 28061#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 28059#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 28057#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 28055#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 28053#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28052#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 28050#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 28048#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 28044#L847-3 assume !(1 == ~T3_E~0); 28043#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 28041#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 28039#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 28035#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 28033#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 28031#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 28029#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 28027#L887-3 assume !(1 == ~E_4~0); 28026#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 28025#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 28024#L902-3 assume !(1 == ~E_7~0); 28023#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 28021#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 28014#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 28013#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 28010#L1167 assume !(0 == start_simulation_~tmp~3#1); 28007#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 27996#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 27990#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 27989#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 27988#L1122 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 27986#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 27984#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 27982#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 27980#L1148-2
[2024-11-08 18:32:31,606 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 18:32:31,607 INFO L85 PathProgramCache]: Analyzing trace with hash -1406363737, now seen corresponding path program 1 times
[2024-11-08 18:32:31,607 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 18:32:31,607 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1855353069]
[2024-11-08 18:32:31,607 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 18:32:31,607 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 18:32:31,620 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-11-08 18:32:31,683 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2024-11-08 18:32:31,683 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2024-11-08 18:32:31,683 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1855353069]
[2024-11-08 18:32:31,683 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1855353069] provided 1 perfect and 0 imperfect interpolant sequences
[2024-11-08 18:32:31,683 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2024-11-08 18:32:31,684 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2
[2024-11-08 18:32:31,685 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [29311779]
[2024-11-08 18:32:31,685 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2024-11-08 18:32:31,685 INFO L750 eck$LassoCheckResult]: stem already infeasible
[2024-11-08 18:32:31,686 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 18:32:31,686 INFO L85 PathProgramCache]: Analyzing trace with hash -1137571742, now seen corresponding path program 1 times
[2024-11-08 18:32:31,686 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 18:32:31,686 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1849091711]
[2024-11-08 18:32:31,686 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 18:32:31,686 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 18:32:31,702 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-11-08 18:32:31,737 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2024-11-08 18:32:31,738 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2024-11-08 18:32:31,738 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1849091711]
[2024-11-08 18:32:31,738 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1849091711] provided 1 perfect and 0 imperfect interpolant sequences
[2024-11-08 18:32:31,738 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2024-11-08 18:32:31,738 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2024-11-08 18:32:31,738 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1206016924]
[2024-11-08 18:32:31,739 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2024-11-08 18:32:31,739 INFO L762 eck$LassoCheckResult]: loop already infeasible
[2024-11-08 18:32:31,739 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2024-11-08 18:32:31,739 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2024-11-08 18:32:31,740 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2024-11-08 18:32:31,740 INFO L87 Difference]: Start difference. First operand 2784 states and 3989 transitions. cyclomatic complexity: 1209 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 2 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 18:32:31,854 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2024-11-08 18:32:31,854 INFO L93 Difference]: Finished difference Result 5175 states and 7372 transitions.
[2024-11-08 18:32:31,854 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5175 states and 7372 transitions.
[2024-11-08 18:32:31,881 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5044
[2024-11-08 18:32:31,907 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5175 states to 5175 states and 7372 transitions.
[2024-11-08 18:32:31,908 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5175
[2024-11-08 18:32:31,913 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5175
[2024-11-08 18:32:31,913 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5175 states and 7372 transitions.
[2024-11-08 18:32:31,919 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2024-11-08 18:32:31,920 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5175 states and 7372 transitions.
[2024-11-08 18:32:31,925 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5175 states and 7372 transitions.
[2024-11-08 18:32:32,002 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5175 to 5167.
[2024-11-08 18:32:32,012 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5167 states, 5167 states have (on average 1.4251983742984324) internal successors, (7364), 5166 states have internal predecessors, (7364), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 18:32:32,025 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5167 states to 5167 states and 7364 transitions.
[2024-11-08 18:32:32,025 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5167 states and 7364 transitions.
[2024-11-08 18:32:32,026 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states.
[2024-11-08 18:32:32,027 INFO L425 stractBuchiCegarLoop]: Abstraction has 5167 states and 7364 transitions.
[2024-11-08 18:32:32,028 INFO L332 stractBuchiCegarLoop]: ======== Iteration 13 ============
[2024-11-08 18:32:32,028 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5167 states and 7364 transitions.
[2024-11-08 18:32:32,048 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5036
[2024-11-08 18:32:32,048 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2024-11-08 18:32:32,049 INFO L119 BuchiIsEmpty]: Starting construction of run
[2024-11-08 18:32:32,050 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 18:32:32,050 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 18:32:32,051 INFO L745 eck$LassoCheckResult]: Stem: 34031#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 34032#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 34633#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 34634#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 34671#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 34654#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 34655#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 34186#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 34187#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 34259#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 34096#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 34097#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 34062#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 34063#L754 assume !(0 == ~M_E~0); 34689#L754-2 assume !(0 == ~T1_E~0); 34591#L759-1 assume !(0 == ~T2_E~0); 34439#L764-1 assume !(0 == ~T3_E~0); 34398#L769-1 assume !(0 == ~T4_E~0); 34399#L774-1 assume !(0 == ~T5_E~0); 34440#L779-1 assume !(0 == ~T6_E~0); 34600#L784-1 assume !(0 == ~T7_E~0); 34396#L789-1 assume !(0 == ~E_1~0); 34397#L794-1 assume !(0 == ~E_2~0); 34487#L799-1 assume !(0 == ~E_3~0); 34408#L804-1 assume !(0 == ~E_4~0); 34409#L809-1 assume !(0 == ~E_5~0); 34434#L814-1 assume !(0 == ~E_6~0); 33834#L819-1 assume !(0 == ~E_7~0); 33835#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 34094#L361 assume !(1 == ~m_pc~0); 34095#L361-2 is_master_triggered_~__retres1~0#1 := 0; 34626#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 34577#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 34578#L930 assume !(0 != activate_threads_~tmp~1#1); 34303#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 34087#L380 assume !(1 == ~t1_pc~0); 34088#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 34711#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33854#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 33855#L938 assume !(0 != activate_threads_~tmp___0~0#1); 34529#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34505#L399 assume !(1 == ~t2_pc~0); 34001#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 34002#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 34167#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 34160#L946 assume !(0 != activate_threads_~tmp___1~0#1); 34161#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33840#L418 assume !(1 == ~t3_pc~0); 33819#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 33820#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33830#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 33831#L954 assume !(0 != activate_threads_~tmp___2~0#1); 34423#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 34424#L437 assume 1 == ~t4_pc~0; 34690#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 34572#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33913#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 33914#L962 assume !(0 != activate_threads_~tmp___3~0#1); 34217#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 34552#L456 assume !(1 == ~t5_pc~0); 34017#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 34016#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 34582#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 34476#L970 assume !(0 != activate_threads_~tmp___4~0#1); 34477#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 33907#L475 assume 1 == ~t6_pc~0; 33908#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 33951#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33952#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 34152#L978 assume !(0 != activate_threads_~tmp___5~0#1); 34414#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 34415#L494 assume !(1 == ~t7_pc~0); 34136#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 34137#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 34367#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 34441#L986 assume !(0 != activate_threads_~tmp___6~0#1); 34442#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 34681#L837 assume !(1 == ~M_E~0); 34632#L837-2 assume !(1 == ~T1_E~0); 34499#L842-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 34224#L847-1 assume !(1 == ~T3_E~0); 34225#L852-1 assume !(1 == ~T4_E~0); 34293#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 34173#L862-1 assume !(1 == ~T6_E~0); 34174#L867-1 assume !(1 == ~T7_E~0); 34181#L872-1 assume !(1 == ~E_1~0); 34258#L877-1 assume !(1 == ~E_2~0); 34456#L882-1 assume !(1 == ~E_3~0); 34637#L887-1 assume !(1 == ~E_4~0); 34523#L892-1 assume !(1 == ~E_5~0); 34524#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 34198#L902-1 assume !(1 == ~E_7~0); 34199#L907-1 assume { :end_inline_reset_delta_events } true; 34549#L1148-2
[2024-11-08 18:32:32,051 INFO L747 eck$LassoCheckResult]: Loop: 34549#L1148-2 assume !false; 35607#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 36523#L729-1 assume !false; 36522#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 36514#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 36513#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 36512#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 36510#L626 assume !(0 != eval_~tmp~0#1); 36511#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 37593#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 37592#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 37591#L754-5 assume !(0 == ~T1_E~0); 37590#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 37589#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 37588#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 37587#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 37586#L779-3 assume !(0 == ~T6_E~0); 37585#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 37584#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 37583#L794-3 assume !(0 == ~E_2~0); 37582#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 37581#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 37580#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 37579#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 37578#L819-3 assume !(0 == ~E_7~0); 37577#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37576#L361-24 assume !(1 == ~m_pc~0); 37575#L361-26 is_master_triggered_~__retres1~0#1 := 0; 37574#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 37573#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 37572#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 37571#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 37570#L380-24 assume 1 == ~t1_pc~0; 37568#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 37566#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 37564#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 37562#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 37561#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 37559#L399-24 assume !(1 == ~t2_pc~0); 37557#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 37555#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 37553#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 37551#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 37549#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 37547#L418-24 assume !(1 == ~t3_pc~0); 37543#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 37540#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 37537#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 37534#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 37532#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 37530#L437-24 assume 1 == ~t4_pc~0; 37527#L438-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 37525#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 37523#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 37521#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 37519#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 37517#L456-24 assume !(1 == ~t5_pc~0); 37513#L456-26 is_transmit5_triggered_~__retres1~5#1 := 0; 37511#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 37509#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 37507#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 37505#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 37503#L475-24 assume 1 == ~t6_pc~0; 37499#L476-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 37497#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 37495#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 37493#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 37491#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 37489#L494-24 assume !(1 == ~t7_pc~0); 37485#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 37483#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37479#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 37477#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 37474#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37472#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 37469#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 37467#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 36988#L847-3 assume !(1 == ~T3_E~0); 37459#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 37456#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 37453#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 36978#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 37447#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 37443#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 37439#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 37435#L887-3 assume !(1 == ~E_4~0); 37433#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 37430#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 37427#L902-3 assume !(1 == ~E_7~0); 37423#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 37419#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 37405#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 37402#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 37398#L1167 assume !(0 == start_simulation_~tmp~3#1); 37391#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 37337#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 36204#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 35877#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 35621#L1122 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 35616#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 35613#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 35610#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 34549#L1148-2
[2024-11-08 18:32:32,051 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 18:32:32,052 INFO L85 PathProgramCache]: Analyzing trace with hash -2107931962, now seen corresponding path program 1 times
[2024-11-08 18:32:32,052 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 18:32:32,052 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [71323965]
[2024-11-08 18:32:32,052 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 18:32:32,053 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 18:32:32,068 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-11-08 18:32:32,112 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2024-11-08 18:32:32,112 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2024-11-08 18:32:32,113 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [71323965]
[2024-11-08 18:32:32,113 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [71323965] provided 1 perfect and 0 imperfect interpolant sequences
[2024-11-08 18:32:32,113 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2024-11-08 18:32:32,113 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2
[2024-11-08 18:32:32,113 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [8406823]
[2024-11-08 18:32:32,113 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2024-11-08 18:32:32,114 INFO L750 eck$LassoCheckResult]: stem already infeasible
[2024-11-08 18:32:32,115 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 18:32:32,115 INFO L85 PathProgramCache]: Analyzing trace with hash -607442076, now seen corresponding path program 1 times
[2024-11-08 18:32:32,115 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 18:32:32,115 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1315932972]
[2024-11-08 18:32:32,116 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 18:32:32,116 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 18:32:32,131 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-11-08 18:32:32,167 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2024-11-08 18:32:32,168 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2024-11-08 18:32:32,168 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1315932972]
[2024-11-08 18:32:32,168 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1315932972] provided 1 perfect and 0 imperfect interpolant sequences
[2024-11-08 18:32:32,168 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2024-11-08 18:32:32,168 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2024-11-08 18:32:32,168 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [681317624]
[2024-11-08 18:32:32,169 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2024-11-08 18:32:32,169 INFO L762 eck$LassoCheckResult]: loop already infeasible
[2024-11-08 18:32:32,170 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2024-11-08 18:32:32,170 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2024-11-08 18:32:32,170 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2024-11-08 18:32:32,171 INFO L87 Difference]: Start difference. First operand 5167 states and 7364 transitions. cyclomatic complexity: 2205 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 2 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 18:32:32,327 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2024-11-08 18:32:32,327 INFO L93 Difference]: Finished difference Result 9674 states and 13721 transitions.
[2024-11-08 18:32:32,327 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9674 states and 13721 transitions.
[2024-11-08 18:32:32,377 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 9512
[2024-11-08 18:32:32,415 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9674 states to 9674 states and 13721 transitions.
[2024-11-08 18:32:32,415 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9674
[2024-11-08 18:32:32,424 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9674
[2024-11-08 18:32:32,424 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9674 states and 13721 transitions.
[2024-11-08 18:32:32,436 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2024-11-08 18:32:32,436 INFO L218 hiAutomatonCegarLoop]: Abstraction has 9674 states and 13721 transitions.
[2024-11-08 18:32:32,447 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9674 states and 13721 transitions.
[2024-11-08 18:32:32,597 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9674 to 9658.
[2024-11-08 18:32:32,617 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9658 states, 9658 states have (on average 1.419030855249534) internal successors, (13705), 9657 states have internal predecessors, (13705), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 18:32:32,646 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9658 states to 9658 states and 13705 transitions.
[2024-11-08 18:32:32,646 INFO L240 hiAutomatonCegarLoop]: Abstraction has 9658 states and 13705 transitions.
[2024-11-08 18:32:32,647 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states.
[2024-11-08 18:32:32,648 INFO L425 stractBuchiCegarLoop]: Abstraction has 9658 states and 13705 transitions.
[2024-11-08 18:32:32,648 INFO L332 stractBuchiCegarLoop]: ======== Iteration 14 ============
[2024-11-08 18:32:32,648 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9658 states and 13705 transitions.
[2024-11-08 18:32:32,725 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 9496
[2024-11-08 18:32:32,726 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2024-11-08 18:32:32,726 INFO L119 BuchiIsEmpty]: Starting construction of run
[2024-11-08 18:32:32,728 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 18:32:32,728 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 18:32:32,728 INFO L745 eck$LassoCheckResult]: Stem: 48881#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 48882#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 49454#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 49455#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 49488#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 49476#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 49477#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 49034#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 49035#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 49107#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 48946#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 48947#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 48913#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 48914#L754 assume !(0 == ~M_E~0); 49504#L754-2 assume !(0 == ~T1_E~0); 49413#L759-1 assume !(0 == ~T2_E~0); 49281#L764-1 assume !(0 == ~T3_E~0); 49241#L769-1 assume !(0 == ~T4_E~0); 49242#L774-1 assume !(0 == ~T5_E~0); 49282#L779-1 assume !(0 == ~T6_E~0); 49420#L784-1 assume !(0 == ~T7_E~0); 49238#L789-1 assume !(0 == ~E_1~0); 49239#L794-1 assume !(0 == ~E_2~0); 49324#L799-1 assume !(0 == ~E_3~0); 49249#L804-1 assume !(0 == ~E_4~0); 49250#L809-1 assume !(0 == ~E_5~0); 49276#L814-1 assume !(0 == ~E_6~0); 48679#L819-1 assume !(0 == ~E_7~0); 48680#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 48944#L361 assume !(1 == ~m_pc~0); 48945#L361-2 is_master_triggered_~__retres1~0#1 := 0; 49450#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 49398#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 49399#L930 assume !(0 != activate_threads_~tmp~1#1); 49150#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 48937#L380 assume !(1 == ~t1_pc~0); 48938#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 49521#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 48701#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 48702#L938 assume !(0 != activate_threads_~tmp___0~0#1); 49354#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 49334#L399 assume !(1 == ~t2_pc~0); 48850#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 48851#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 49015#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 49008#L946 assume !(0 != activate_threads_~tmp___1~0#1); 49009#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 48687#L418 assume !(1 == ~t3_pc~0); 48667#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 48668#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 48677#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 48678#L954 assume !(0 != activate_threads_~tmp___2~0#1); 49263#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 49264#L437 assume !(1 == ~t4_pc~0); 49478#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 49393#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 48760#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 48761#L962 assume !(0 != activate_threads_~tmp___3~0#1); 49063#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 49374#L456 assume !(1 == ~t5_pc~0); 48864#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 48863#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 49402#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 49311#L970 assume !(0 != activate_threads_~tmp___4~0#1); 49312#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 48754#L475 assume 1 == ~t6_pc~0; 48755#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 48798#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 48799#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 49001#L978 assume !(0 != activate_threads_~tmp___5~0#1); 49255#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 49256#L494 assume !(1 == ~t7_pc~0); 48985#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 48986#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 49211#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 49283#L986 assume !(0 != activate_threads_~tmp___6~0#1); 49284#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 49497#L837 assume !(1 == ~M_E~0); 49453#L837-2 assume !(1 == ~T1_E~0); 49329#L842-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 49072#L847-1 assume !(1 == ~T3_E~0); 49073#L852-1 assume !(1 == ~T4_E~0); 49140#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 49525#L862-1 assume !(1 == ~T6_E~0); 49023#L867-1 assume !(1 == ~T7_E~0); 49105#L872-1 assume !(1 == ~E_1~0); 49106#L877-1 assume !(1 == ~E_2~0); 49458#L882-1 assume !(1 == ~E_3~0); 49459#L887-1 assume !(1 == ~E_4~0); 49349#L892-1 assume !(1 == ~E_5~0); 49350#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 49045#L902-1 assume !(1 == ~E_7~0); 49046#L907-1 assume { :end_inline_reset_delta_events } true; 53125#L1148-2
[2024-11-08 18:32:32,729 INFO L747 eck$LassoCheckResult]: Loop: 53125#L1148-2 assume !false; 52981#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 52980#L729-1 assume !false; 52979#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 52969#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 52968#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 52967#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 52963#L626 assume !(0 != eval_~tmp~0#1); 52964#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 53528#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 53526#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 53524#L754-5 assume !(0 == ~T1_E~0); 53522#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 53520#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 53518#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 53515#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 53512#L779-3 assume !(0 == ~T6_E~0); 53509#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 53506#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 53504#L794-3 assume !(0 == ~E_2~0); 53502#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 53500#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 53498#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 53496#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 53494#L819-3 assume !(0 == ~E_7~0); 53492#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 53490#L361-24 assume !(1 == ~m_pc~0); 53487#L361-26 is_master_triggered_~__retres1~0#1 := 0; 53485#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 53483#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 53481#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 53479#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 53477#L380-24 assume 1 == ~t1_pc~0; 53474#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 53471#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 53468#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 53465#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 53462#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 53459#L399-24 assume !(1 == ~t2_pc~0); 53455#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 53452#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 53449#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 53446#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 53443#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 53440#L418-24 assume !(1 == ~t3_pc~0); 53438#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 53437#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 53434#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 53424#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 53421#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 53418#L437-24 assume !(1 == ~t4_pc~0); 53414#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 53410#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 53407#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 53403#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 53399#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 53396#L456-24 assume 1 == ~t5_pc~0; 53392#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 53387#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 53383#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 53379#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 53375#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 53371#L475-24 assume 1 == ~t6_pc~0; 53366#L476-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 53362#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 53358#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 53354#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 53349#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 53345#L494-24 assume !(1 == ~t7_pc~0); 53340#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 53336#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 53332#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 53327#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 53323#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 53319#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 53315#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 53310#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 53304#L847-3 assume !(1 == ~T3_E~0); 53300#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 53296#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 53292#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 53286#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 53282#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 53278#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 53273#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 53269#L887-3 assume !(1 == ~E_4~0); 53265#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 53261#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 53256#L902-3 assume !(1 == ~E_7~0); 53253#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 53193#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 53183#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 53180#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 53176#L1167 assume !(0 == start_simulation_~tmp~3#1); 53172#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 53154#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 53148#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 53145#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 53142#L1122 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 53138#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 53135#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 53129#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 53125#L1148-2
[2024-11-08 18:32:32,729 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 18:32:32,729 INFO L85 PathProgramCache]: Analyzing trace with hash -1707940763, now seen corresponding path program 1 times
[2024-11-08 18:32:32,730 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 18:32:32,730 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [946532344]
[2024-11-08 18:32:32,730 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 18:32:32,730 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 18:32:32,749 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-11-08 18:32:32,811 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2024-11-08 18:32:32,812 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2024-11-08 18:32:32,812 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [946532344]
[2024-11-08 18:32:32,812 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [946532344] provided 1 perfect and 0 imperfect interpolant sequences
[2024-11-08 18:32:32,812 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2024-11-08 18:32:32,812 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2
[2024-11-08 18:32:32,813 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [503916135]
[2024-11-08 18:32:32,813 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2024-11-08 18:32:32,813 INFO L750 eck$LassoCheckResult]: stem already infeasible
[2024-11-08 18:32:32,814 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 18:32:32,814 INFO L85 PathProgramCache]: Analyzing trace with hash -1005532, now seen corresponding path program 1 times
[2024-11-08 18:32:32,814 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 18:32:32,817 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [283242126]
[2024-11-08 18:32:32,817 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 18:32:32,817 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 18:32:32,836 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-11-08 18:32:32,883 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2024-11-08 18:32:32,883 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2024-11-08 18:32:32,883 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [283242126]
[2024-11-08 18:32:32,883 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [283242126] provided 1 perfect and 0 imperfect interpolant sequences
[2024-11-08 18:32:32,883 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2024-11-08 18:32:32,884 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2024-11-08 18:32:32,884 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [223565542]
[2024-11-08 18:32:32,884 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2024-11-08 18:32:32,885 INFO L762 eck$LassoCheckResult]: loop already infeasible
[2024-11-08 18:32:32,885 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2024-11-08 18:32:32,886 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2024-11-08 18:32:32,886 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2024-11-08 18:32:32,890 INFO L87 Difference]: Start difference. First operand 9658 states and 13705 transitions. cyclomatic complexity: 4063 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 2 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 18:32:33,084 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2024-11-08 18:32:33,085 INFO L93 Difference]: Finished difference Result 18129 states and 25606 transitions.
[2024-11-08 18:32:33,085 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 18129 states and 25606 transitions.
[2024-11-08 18:32:33,183 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 17888
[2024-11-08 18:32:33,258 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 18129 states to 18129 states and 25606 transitions.
[2024-11-08 18:32:33,258 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18129
[2024-11-08 18:32:33,275 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18129
[2024-11-08 18:32:33,275 INFO L73 IsDeterministic]: Start isDeterministic. Operand 18129 states and 25606 transitions.
[2024-11-08 18:32:33,296 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2024-11-08 18:32:33,296 INFO L218 hiAutomatonCegarLoop]: Abstraction has 18129 states and 25606 transitions.
[2024-11-08 18:32:33,316 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18129 states and 25606 transitions.
[2024-11-08 18:32:33,740 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18129 to 18097.
[2024-11-08 18:32:33,778 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 18097 states, 18097 states have (on average 1.413162402608167) internal successors, (25574), 18096 states have internal predecessors, (25574), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 18:32:33,828 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18097 states to 18097 states and 25574 transitions.
[2024-11-08 18:32:33,829 INFO L240 hiAutomatonCegarLoop]: Abstraction has 18097 states and 25574 transitions.
[2024-11-08 18:32:33,829 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states.
[2024-11-08 18:32:33,830 INFO L425 stractBuchiCegarLoop]: Abstraction has 18097 states and 25574 transitions.
[2024-11-08 18:32:33,830 INFO L332 stractBuchiCegarLoop]: ======== Iteration 15 ============
[2024-11-08 18:32:33,830 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 18097 states and 25574 transitions.
[2024-11-08 18:32:33,893 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 17856
[2024-11-08 18:32:33,893 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2024-11-08 18:32:33,893 INFO L119 BuchiIsEmpty]: Starting construction of run
[2024-11-08 18:32:33,894 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 18:32:33,895 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 18:32:33,895 INFO L745 eck$LassoCheckResult]: Stem: 76670#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 76671#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 77267#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 77268#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 77308#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 77294#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 77295#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 76829#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 76830#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 76901#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 76736#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 76737#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 76703#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 76704#L754 assume !(0 == ~M_E~0); 77323#L754-2 assume !(0 == ~T1_E~0); 77225#L759-1 assume !(0 == ~T2_E~0); 77082#L764-1 assume !(0 == ~T3_E~0); 77040#L769-1 assume !(0 == ~T4_E~0); 77041#L774-1 assume !(0 == ~T5_E~0); 77083#L779-1 assume !(0 == ~T6_E~0); 77236#L784-1 assume !(0 == ~T7_E~0); 77037#L789-1 assume !(0 == ~E_1~0); 77038#L794-1 assume !(0 == ~E_2~0); 77132#L799-1 assume !(0 == ~E_3~0); 77048#L804-1 assume !(0 == ~E_4~0); 77049#L809-1 assume !(0 == ~E_5~0); 77077#L814-1 assume !(0 == ~E_6~0); 76478#L819-1 assume !(0 == ~E_7~0); 76479#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 76733#L361 assume !(1 == ~m_pc~0); 76734#L361-2 is_master_triggered_~__retres1~0#1 := 0; 77263#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 77213#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 77214#L930 assume !(0 != activate_threads_~tmp~1#1); 76949#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 76727#L380 assume !(1 == ~t1_pc~0); 76728#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 77345#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 76496#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 76497#L938 assume !(0 != activate_threads_~tmp___0~0#1); 77166#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 77143#L399 assume !(1 == ~t2_pc~0); 76641#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 76642#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 76807#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 76800#L946 assume !(0 != activate_threads_~tmp___1~0#1); 76801#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 76482#L418 assume !(1 == ~t3_pc~0); 76461#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 76462#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 76472#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 76473#L954 assume !(0 != activate_threads_~tmp___2~0#1); 77062#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 77063#L437 assume !(1 == ~t4_pc~0); 77296#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 77209#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 76555#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 76556#L962 assume !(0 != activate_threads_~tmp___3~0#1); 76858#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 77192#L456 assume !(1 == ~t5_pc~0); 76656#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 76655#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 77217#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 77118#L970 assume !(0 != activate_threads_~tmp___4~0#1); 77119#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 76548#L475 assume !(1 == ~t6_pc~0); 76549#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 76589#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 76590#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 76792#L978 assume !(0 != activate_threads_~tmp___5~0#1); 77053#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 77054#L494 assume !(1 == ~t7_pc~0); 76776#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 76777#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 77007#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 77084#L986 assume !(0 != activate_threads_~tmp___6~0#1); 77085#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 77316#L837 assume !(1 == ~M_E~0); 77266#L837-2 assume !(1 == ~T1_E~0); 77138#L842-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 76865#L847-1 assume !(1 == ~T3_E~0); 76866#L852-1 assume !(1 == ~T4_E~0); 76939#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 76814#L862-1 assume !(1 == ~T6_E~0); 76815#L867-1 assume !(1 == ~T7_E~0); 76825#L872-1 assume !(1 == ~E_1~0); 76900#L877-1 assume !(1 == ~E_2~0); 77100#L882-1 assume !(1 == ~E_3~0); 77274#L887-1 assume !(1 == ~E_4~0); 77162#L892-1 assume !(1 == ~E_5~0); 77163#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 76842#L902-1 assume !(1 == ~E_7~0); 76843#L907-1 assume { :end_inline_reset_delta_events } true; 77186#L1148-2
[2024-11-08 18:32:33,895 INFO L747 eck$LassoCheckResult]: Loop: 77186#L1148-2 assume !false; 81709#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 81707#L729-1 assume !false; 81706#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 81640#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 81634#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 81630#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 81625#L626 assume !(0 != eval_~tmp~0#1); 81626#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 81996#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 81995#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 81994#L754-5 assume !(0 == ~T1_E~0); 81993#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 81992#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 81991#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 81990#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 81989#L779-3 assume !(0 == ~T6_E~0); 81988#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 81987#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 81986#L794-3 assume !(0 == ~E_2~0); 81985#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 81984#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 81983#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 81982#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 81981#L819-3 assume !(0 == ~E_7~0); 81980#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 81979#L361-24 assume !(1 == ~m_pc~0); 81978#L361-26 is_master_triggered_~__retres1~0#1 := 0; 81977#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 81976#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 81974#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 81972#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 81970#L380-24 assume !(1 == ~t1_pc~0); 81968#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 81965#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 81962#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 81959#L938-24 assume !(0 != activate_threads_~tmp___0~0#1); 81955#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 81952#L399-24 assume !(1 == ~t2_pc~0); 81949#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 81946#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 81944#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 81942#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 81940#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 81938#L418-24 assume 1 == ~t3_pc~0; 81936#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 81933#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 81931#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 81929#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 81926#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 81924#L437-24 assume !(1 == ~t4_pc~0); 81921#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 81918#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 81915#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 81912#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 81909#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 81906#L456-24 assume 1 == ~t5_pc~0; 81903#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 81898#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 81894#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 81890#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 81885#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 81882#L475-24 assume !(1 == ~t6_pc~0); 81879#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 81876#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 81873#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 81870#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 81867#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 81864#L494-24 assume !(1 == ~t7_pc~0); 81860#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 81856#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 81853#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 81849#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 81846#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 81842#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 81838#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 81834#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 79729#L847-3 assume !(1 == ~T3_E~0); 81827#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 81823#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 81819#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 79718#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 81810#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 81805#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 81800#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 81797#L887-3 assume !(1 == ~E_4~0); 81793#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 81789#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 81785#L902-3 assume !(1 == ~E_7~0); 81781#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 81769#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 81757#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 81755#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 81753#L1167 assume !(0 == start_simulation_~tmp~3#1); 81751#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 81746#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 81740#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 81738#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 81736#L1122 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 81734#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 81732#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 81730#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 77186#L1148-2
[2024-11-08 18:32:33,896 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 18:32:33,896 INFO L85 PathProgramCache]: Analyzing trace with hash -2016379772, now seen corresponding path program 1 times
[2024-11-08 18:32:33,896 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 18:32:33,896 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1988496073]
[2024-11-08 18:32:33,896 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 18:32:33,897 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 18:32:33,908 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-11-08 18:32:34,022 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2024-11-08 18:32:34,022 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2024-11-08 18:32:34,022 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1988496073]
[2024-11-08 18:32:34,023 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1988496073] provided 1 perfect and 0 imperfect interpolant sequences
[2024-11-08 18:32:34,023 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2024-11-08 18:32:34,023 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2
[2024-11-08 18:32:34,023 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [350612656]
[2024-11-08 18:32:34,023 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2024-11-08 18:32:34,024 INFO L750 eck$LassoCheckResult]: stem already infeasible
[2024-11-08 18:32:34,024 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 18:32:34,024 INFO L85 PathProgramCache]: Analyzing trace with hash 1715422081, now seen corresponding path program 1 times
[2024-11-08 18:32:34,024 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 18:32:34,024 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1425107781]
[2024-11-08 18:32:34,024 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 18:32:34,025 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 18:32:34,037 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-11-08 18:32:34,076 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2024-11-08 18:32:34,077 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2024-11-08 18:32:34,077 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1425107781]
[2024-11-08 18:32:34,077 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1425107781] provided 1 perfect and 0 imperfect interpolant sequences
[2024-11-08 18:32:34,077 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2024-11-08 18:32:34,077 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2024-11-08 18:32:34,077 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1054240584]
[2024-11-08 18:32:34,078 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2024-11-08 18:32:34,078 INFO L762 eck$LassoCheckResult]: loop already infeasible
[2024-11-08 18:32:34,078 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2024-11-08 18:32:34,078 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2024-11-08 18:32:34,078 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2024-11-08 18:32:34,079 INFO L87 Difference]: Start difference. First operand 18097 states and 25574 transitions. cyclomatic complexity: 7509 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 2 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 18:32:34,168 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2024-11-08 18:32:34,168 INFO L93 Difference]: Finished difference Result 18093 states and 25485 transitions.
[2024-11-08 18:32:34,169 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 18093 states and 25485 transitions.
[2024-11-08 18:32:34,383 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 17856
[2024-11-08 18:32:34,485 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 18093 states to 18093 states and 25485 transitions.
[2024-11-08 18:32:34,486 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18093
[2024-11-08 18:32:34,509 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18093
[2024-11-08 18:32:34,509 INFO L73 IsDeterministic]: Start isDeterministic. Operand 18093 states and 25485 transitions.
[2024-11-08 18:32:34,536 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2024-11-08 18:32:34,536 INFO L218 hiAutomatonCegarLoop]: Abstraction has 18093 states and 25485 transitions.
[2024-11-08 18:32:34,610 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18093 states and 25485 transitions.
[2024-11-08 18:32:34,837 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18093 to 9092.
[2024-11-08 18:32:34,853 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9092 states, 9092 states have (on average 1.4083809942806864) internal successors, (12805), 9091 states have internal predecessors, (12805), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 18:32:34,882 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9092 states to 9092 states and 12805 transitions.
[2024-11-08 18:32:34,882 INFO L240 hiAutomatonCegarLoop]: Abstraction has 9092 states and 12805 transitions.
[2024-11-08 18:32:34,883 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states.
[2024-11-08 18:32:34,884 INFO L425 stractBuchiCegarLoop]: Abstraction has 9092 states and 12805 transitions.
[2024-11-08 18:32:34,884 INFO L332 stractBuchiCegarLoop]: ======== Iteration 16 ============
[2024-11-08 18:32:34,884 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9092 states and 12805 transitions.
[2024-11-08 18:32:34,922 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 8928
[2024-11-08 18:32:34,922 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2024-11-08 18:32:34,922 INFO L119 BuchiIsEmpty]: Starting construction of run
[2024-11-08 18:32:34,924 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 18:32:34,924 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 18:32:34,924 INFO L745 eck$LassoCheckResult]: Stem: 112869#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 112870#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 113434#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 113435#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 113467#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 113453#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 113454#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 113021#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 113022#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 113094#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 112933#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 112934#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 112900#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 112901#L754 assume !(0 == ~M_E~0); 113477#L754-2 assume !(0 == ~T1_E~0); 113394#L759-1 assume !(0 == ~T2_E~0); 113264#L764-1 assume !(0 == ~T3_E~0); 113225#L769-1 assume !(0 == ~T4_E~0); 113226#L774-1 assume !(0 == ~T5_E~0); 113265#L779-1 assume !(0 == ~T6_E~0); 113404#L784-1 assume !(0 == ~T7_E~0); 113222#L789-1 assume !(0 == ~E_1~0); 113223#L794-1 assume !(0 == ~E_2~0); 113309#L799-1 assume !(0 == ~E_3~0); 113232#L804-1 assume !(0 == ~E_4~0); 113233#L809-1 assume !(0 == ~E_5~0); 113259#L814-1 assume !(0 == ~E_6~0); 112674#L819-1 assume !(0 == ~E_7~0); 112675#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 112930#L361 assume !(1 == ~m_pc~0); 112931#L361-2 is_master_triggered_~__retres1~0#1 := 0; 113428#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 113381#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 113382#L930 assume !(0 != activate_threads_~tmp~1#1); 113138#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 112924#L380 assume !(1 == ~t1_pc~0); 112925#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 113495#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 112692#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 112693#L938 assume !(0 != activate_threads_~tmp___0~0#1); 113337#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 113318#L399 assume !(1 == ~t2_pc~0); 112837#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 112838#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 113001#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 112994#L946 assume !(0 != activate_threads_~tmp___1~0#1); 112995#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 112678#L418 assume !(1 == ~t3_pc~0); 112658#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 112659#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 112668#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 112669#L954 assume !(0 != activate_threads_~tmp___2~0#1); 113247#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 113248#L437 assume !(1 == ~t4_pc~0); 113455#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 113376#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 112752#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 112753#L962 assume !(0 != activate_threads_~tmp___3~0#1); 113050#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 113360#L456 assume !(1 == ~t5_pc~0); 112852#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 112851#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 113385#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 113299#L970 assume !(0 != activate_threads_~tmp___4~0#1); 113300#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 112745#L475 assume !(1 == ~t6_pc~0); 112746#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 112787#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 112788#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 112987#L978 assume !(0 != activate_threads_~tmp___5~0#1); 113237#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 113238#L494 assume !(1 == ~t7_pc~0); 112971#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 112972#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 113194#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 113266#L986 assume !(0 != activate_threads_~tmp___6~0#1); 113267#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 113472#L837 assume !(1 == ~M_E~0); 113433#L837-2 assume !(1 == ~T1_E~0); 113314#L842-1 assume !(1 == ~T2_E~0); 113059#L847-1 assume !(1 == ~T3_E~0); 113060#L852-1 assume !(1 == ~T4_E~0); 113127#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 113007#L862-1 assume !(1 == ~T6_E~0); 113008#L867-1 assume !(1 == ~T7_E~0); 113017#L872-1 assume !(1 == ~E_1~0); 113093#L877-1 assume !(1 == ~E_2~0); 113282#L882-1 assume !(1 == ~E_3~0); 113438#L887-1 assume !(1 == ~E_4~0); 113332#L892-1 assume !(1 == ~E_5~0); 113333#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 113034#L902-1 assume !(1 == ~E_7~0); 113035#L907-1 assume { :end_inline_reset_delta_events } true; 113354#L1148-2
[2024-11-08 18:32:34,925 INFO L747 eck$LassoCheckResult]: Loop: 113354#L1148-2 assume !false; 116245#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 116244#L729-1 assume !false; 116242#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 116223#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 116220#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 116218#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 116215#L626 assume !(0 != eval_~tmp~0#1); 116216#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 116444#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 116440#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 116438#L754-5 assume !(0 == ~T1_E~0); 116436#L759-3 assume !(0 == ~T2_E~0); 116435#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 116432#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 116431#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 116430#L779-3 assume !(0 == ~T6_E~0); 116429#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 116428#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 116427#L794-3 assume !(0 == ~E_2~0); 116426#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 116425#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 116424#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 116423#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 116422#L819-3 assume !(0 == ~E_7~0); 116421#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 116420#L361-24 assume !(1 == ~m_pc~0); 116419#L361-26 is_master_triggered_~__retres1~0#1 := 0; 116418#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 116417#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 116415#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 116414#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 116413#L380-24 assume 1 == ~t1_pc~0; 116411#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 116409#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 116407#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 116403#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 116401#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 116399#L399-24 assume !(1 == ~t2_pc~0); 116395#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 116393#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 116391#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 116389#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 116386#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 116384#L418-24 assume !(1 == ~t3_pc~0); 116381#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 116379#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 116377#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 116375#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 116373#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 116371#L437-24 assume !(1 == ~t4_pc~0); 116369#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 116366#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 116364#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 116362#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 116360#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 116358#L456-24 assume !(1 == ~t5_pc~0); 116355#L456-26 is_transmit5_triggered_~__retres1~5#1 := 0; 116353#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 116351#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 116349#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 116347#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 116345#L475-24 assume !(1 == ~t6_pc~0); 116343#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 116340#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 116338#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 116336#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 116334#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 116332#L494-24 assume !(1 == ~t7_pc~0); 116329#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 116327#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 116325#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 116323#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 116321#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 116319#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 116316#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 116314#L842-3 assume !(1 == ~T2_E~0); 116312#L847-3 assume !(1 == ~T3_E~0); 116310#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 116308#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 116306#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 116304#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 116302#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 116300#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 116298#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 116296#L887-3 assume !(1 == ~E_4~0); 116294#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 116292#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 116290#L902-3 assume !(1 == ~E_7~0); 116288#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 116282#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 116274#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 116272#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 116270#L1167 assume !(0 == start_simulation_~tmp~3#1); 116268#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 116264#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 116259#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 116258#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 116256#L1122 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 116255#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 116254#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 116252#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 113354#L1148-2
[2024-11-08 18:32:34,925 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 18:32:34,925 INFO L85 PathProgramCache]: Analyzing trace with hash 1267470274, now seen corresponding path program 1 times
[2024-11-08 18:32:34,988 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 18:32:34,989 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1755341351]
[2024-11-08 18:32:34,989 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 18:32:34,989 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 18:32:35,008 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-11-08 18:32:35,056 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2024-11-08 18:32:35,056 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2024-11-08 18:32:35,057 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1755341351]
[2024-11-08 18:32:35,057 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1755341351] provided 1 perfect and 0 imperfect interpolant sequences
[2024-11-08 18:32:35,057 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2024-11-08 18:32:35,057 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2
[2024-11-08 18:32:35,057 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [269543392]
[2024-11-08 18:32:35,057 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2024-11-08 18:32:35,058 INFO L750 eck$LassoCheckResult]: stem already infeasible
[2024-11-08 18:32:35,058 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 18:32:35,058 INFO L85 PathProgramCache]: Analyzing trace with hash 1030083742, now seen corresponding path program 1 times
[2024-11-08 18:32:35,058 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 18:32:35,058 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [189076255]
[2024-11-08 18:32:35,058 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 18:32:35,059 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 18:32:35,076 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-11-08 18:32:35,123 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2024-11-08 18:32:35,123 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2024-11-08 18:32:35,123 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [189076255]
[2024-11-08 18:32:35,124 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [189076255] provided 1 perfect and 0 imperfect interpolant sequences
[2024-11-08 18:32:35,124 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2024-11-08 18:32:35,124 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2024-11-08 18:32:35,124 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [741832862]
[2024-11-08 18:32:35,124 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2024-11-08 18:32:35,124 INFO L762 eck$LassoCheckResult]: loop already infeasible
[2024-11-08 18:32:35,124 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2024-11-08 18:32:35,125 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2024-11-08 18:32:35,125 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2024-11-08 18:32:35,125 INFO L87 Difference]: Start difference. First operand 9092 states and 12805 transitions. cyclomatic complexity: 3729 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 2 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 18:32:35,187 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2024-11-08 18:32:35,187 INFO L93 Difference]: Finished difference Result 9092 states and 12755 transitions.
[2024-11-08 18:32:35,187 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9092 states and 12755 transitions.
[2024-11-08 18:32:35,227 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 8928
[2024-11-08 18:32:35,254 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9092 states to 9092 states and 12755 transitions.
[2024-11-08 18:32:35,254 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9092
[2024-11-08 18:32:35,262 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9092
[2024-11-08 18:32:35,262 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9092 states and 12755 transitions.
[2024-11-08 18:32:35,270 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2024-11-08 18:32:35,270 INFO L218 hiAutomatonCegarLoop]: Abstraction has 9092 states and 12755 transitions.
[2024-11-08 18:32:35,278 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9092 states and 12755 transitions.
[2024-11-08 18:32:35,368 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9092 to 9092.
[2024-11-08 18:32:35,381 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9092 states, 9092 states have (on average 1.402881654201496) internal successors, (12755), 9091 states have internal predecessors, (12755), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 18:32:35,409 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9092 states to 9092 states and 12755 transitions.
[2024-11-08 18:32:35,409 INFO L240 hiAutomatonCegarLoop]: Abstraction has 9092 states and 12755 transitions.
[2024-11-08 18:32:35,409 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states.
[2024-11-08 18:32:35,410 INFO L425 stractBuchiCegarLoop]: Abstraction has 9092 states and 12755 transitions.
[2024-11-08 18:32:35,410 INFO L332 stractBuchiCegarLoop]: ======== Iteration 17 ============
[2024-11-08 18:32:35,410 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9092 states and 12755 transitions.
[2024-11-08 18:32:35,447 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 8928
[2024-11-08 18:32:35,448 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2024-11-08 18:32:35,448 INFO L119 BuchiIsEmpty]: Starting construction of run
[2024-11-08 18:32:35,450 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 18:32:35,450 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 18:32:35,450 INFO L745 eck$LassoCheckResult]: Stem: 131060#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 131061#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 131652#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 131653#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 131684#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 131669#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 131670#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 131211#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 131212#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 131285#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 131122#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 131123#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 131090#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 131091#L754 assume !(0 == ~M_E~0); 131701#L754-2 assume !(0 == ~T1_E~0); 131603#L759-1 assume !(0 == ~T2_E~0); 131467#L764-1 assume !(0 == ~T3_E~0); 131421#L769-1 assume !(0 == ~T4_E~0); 131422#L774-1 assume !(0 == ~T5_E~0); 131468#L779-1 assume !(0 == ~T6_E~0); 131615#L784-1 assume !(0 == ~T7_E~0); 131417#L789-1 assume !(0 == ~E_1~0); 131418#L794-1 assume !(0 == ~E_2~0); 131512#L799-1 assume !(0 == ~E_3~0); 131430#L804-1 assume !(0 == ~E_4~0); 131431#L809-1 assume !(0 == ~E_5~0); 131462#L814-1 assume !(0 == ~E_6~0); 130861#L819-1 assume !(0 == ~E_7~0); 130862#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 131120#L361 assume !(1 == ~m_pc~0); 131121#L361-2 is_master_triggered_~__retres1~0#1 := 0; 131647#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 131590#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 131591#L930 assume !(0 != activate_threads_~tmp~1#1); 131331#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 131114#L380 assume !(1 == ~t1_pc~0); 131115#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 131681#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 131682#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 131724#L938 assume !(0 != activate_threads_~tmp___0~0#1); 131546#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 131524#L399 assume !(1 == ~t2_pc~0); 131029#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 131030#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 131192#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 131185#L946 assume !(0 != activate_threads_~tmp___1~0#1); 131186#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 130869#L418 assume !(1 == ~t3_pc~0); 130849#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 130850#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 130859#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 130860#L954 assume !(0 != activate_threads_~tmp___2~0#1); 131447#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 131448#L437 assume !(1 == ~t4_pc~0); 131671#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 131585#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 130940#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 130941#L962 assume !(0 != activate_threads_~tmp___3~0#1); 131239#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 131565#L456 assume !(1 == ~t5_pc~0); 131044#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 131043#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 131594#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 131497#L970 assume !(0 != activate_threads_~tmp___4~0#1); 131498#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 130935#L475 assume !(1 == ~t6_pc~0); 130936#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 130977#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 130978#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 131178#L978 assume !(0 != activate_threads_~tmp___5~0#1); 131435#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 131436#L494 assume !(1 == ~t7_pc~0); 131162#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 131163#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 131390#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 131469#L986 assume !(0 != activate_threads_~tmp___6~0#1); 131470#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 131692#L837 assume !(1 == ~M_E~0); 131651#L837-2 assume !(1 == ~T1_E~0); 131520#L842-1 assume !(1 == ~T2_E~0); 131249#L847-1 assume !(1 == ~T3_E~0); 131250#L852-1 assume !(1 == ~T4_E~0); 131321#L857-1 assume !(1 == ~T5_E~0); 131198#L862-1 assume !(1 == ~T6_E~0); 131199#L867-1 assume !(1 == ~T7_E~0); 131207#L872-1 assume !(1 == ~E_1~0); 131284#L877-1 assume !(1 == ~E_2~0); 131484#L882-1 assume !(1 == ~E_3~0); 131657#L887-1 assume !(1 == ~E_4~0); 131540#L892-1 assume !(1 == ~E_5~0); 131541#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 131222#L902-1 assume !(1 == ~E_7~0); 131223#L907-1 assume { :end_inline_reset_delta_events } true; 131089#L1148-2
[2024-11-08 18:32:35,451 INFO L747 eck$LassoCheckResult]: Loop: 131089#L1148-2 assume !false; 130863#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 130864#L729-1 assume !false; 131510#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 131062#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 131063#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 131213#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 131107#L626 assume !(0 != eval_~tmp~0#1); 131109#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 131542#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 139731#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 139730#L754-5 assume !(0 == ~T1_E~0); 139729#L759-3 assume !(0 == ~T2_E~0); 139728#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 139727#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 139726#L774-3 assume !(0 == ~T5_E~0); 131033#L779-3 assume !(0 == ~T6_E~0); 131034#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 139725#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 139724#L794-3 assume !(0 == ~E_2~0); 139723#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 139722#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 139721#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 139720#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 131624#L819-3 assume !(0 == ~E_7~0); 131625#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 139517#L361-24 assume !(1 == ~m_pc~0); 139516#L361-26 is_master_triggered_~__retres1~0#1 := 0; 139515#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 139514#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 139513#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 139511#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 139510#L380-24 assume !(1 == ~t1_pc~0); 139508#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 139506#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 139504#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 139503#L938-24 assume !(0 != activate_threads_~tmp___0~0#1); 139501#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 139500#L399-24 assume !(1 == ~t2_pc~0); 139499#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 139498#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 139497#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 139496#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 139495#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 139494#L418-24 assume !(1 == ~t3_pc~0); 139492#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 139490#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 139489#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 139488#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 139487#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 139486#L437-24 assume !(1 == ~t4_pc~0); 139485#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 139484#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 139482#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 139480#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 139478#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 139476#L456-24 assume 1 == ~t5_pc~0; 139474#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 139471#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 139469#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 139467#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 139465#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 139463#L475-24 assume !(1 == ~t6_pc~0); 139461#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 139459#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 139457#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 139455#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 139453#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 139451#L494-24 assume !(1 == ~t7_pc~0); 139448#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 139446#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 139443#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 139441#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 139439#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 139437#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 139435#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 139431#L842-3 assume !(1 == ~T2_E~0); 139429#L847-3 assume !(1 == ~T3_E~0); 139427#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 139425#L857-3 assume !(1 == ~T5_E~0); 139422#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 139420#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 139418#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 139416#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 139414#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 139412#L887-3 assume !(1 == ~E_4~0); 139410#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 139408#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 139406#L902-3 assume !(1 == ~E_7~0); 139403#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 139397#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 139389#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 139387#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 139385#L1167 assume !(0 == start_simulation_~tmp~3#1); 131274#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 131275#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 131076#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 130881#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 130882#L1122 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 131254#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 131255#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 131088#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 131089#L1148-2
[2024-11-08 18:32:35,451 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 18:32:35,452 INFO L85 PathProgramCache]: Analyzing trace with hash 1968534852, now seen corresponding path program 1 times
[2024-11-08 18:32:35,452 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 18:32:35,452 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1400360386]
[2024-11-08 18:32:35,452 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 18:32:35,453 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 18:32:35,473 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-11-08 18:32:35,598 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2024-11-08 18:32:35,599 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2024-11-08 18:32:35,599 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1400360386]
[2024-11-08 18:32:35,599 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1400360386] provided 1 perfect and 0 imperfect interpolant sequences
[2024-11-08 18:32:35,599 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2024-11-08 18:32:35,599 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2024-11-08 18:32:35,600 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [449407120]
[2024-11-08 18:32:35,600 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2024-11-08 18:32:35,600 INFO L750 eck$LassoCheckResult]: stem already infeasible
[2024-11-08 18:32:35,600 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 18:32:35,601 INFO L85 PathProgramCache]: Analyzing trace with hash 121162976, now seen corresponding path program 1 times
[2024-11-08 18:32:35,601 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 18:32:35,601 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1043258633]
[2024-11-08 18:32:35,601 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 18:32:35,601 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 18:32:35,615 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-11-08 18:32:35,645 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2024-11-08 18:32:35,645 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2024-11-08 18:32:35,645 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1043258633]
[2024-11-08 18:32:35,645 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1043258633] provided 1 perfect and 0 imperfect interpolant sequences
[2024-11-08 18:32:35,645 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2024-11-08 18:32:35,645 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2024-11-08 18:32:35,646 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1354354355]
[2024-11-08 18:32:35,646 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2024-11-08 18:32:35,646 INFO L762 eck$LassoCheckResult]: loop already infeasible
[2024-11-08 18:32:35,646 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2024-11-08 18:32:35,647 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants.
[2024-11-08 18:32:35,647 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12
[2024-11-08 18:32:35,647 INFO L87 Difference]: Start difference. First operand 9092 states and 12755 transitions. cyclomatic complexity: 3679 Second operand has 4 states, 4 states have (on average 23.25) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 18:32:35,849 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2024-11-08 18:32:35,849 INFO L93 Difference]: Finished difference Result 18501 states and 25862 transitions.
[2024-11-08 18:32:35,849 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 18501 states and 25862 transitions.
[2024-11-08 18:32:35,922 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 18184
[2024-11-08 18:32:35,978 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 18501 states to 18501 states and 25862 transitions.
[2024-11-08 18:32:35,978 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18501
[2024-11-08 18:32:35,993 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18501
[2024-11-08 18:32:35,993 INFO L73 IsDeterministic]: Start isDeterministic. Operand 18501 states and 25862 transitions.
[2024-11-08 18:32:36,011 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2024-11-08 18:32:36,011 INFO L218 hiAutomatonCegarLoop]: Abstraction has 18501 states and 25862 transitions.
[2024-11-08 18:32:36,029 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18501 states and 25862 transitions.
[2024-11-08 18:32:36,325 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18501 to 10331.
[2024-11-08 18:32:36,338 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10331 states, 10331 states have (on average 1.3969606040073566) internal successors, (14432), 10330 states have internal predecessors, (14432), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 18:32:36,361 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10331 states to 10331 states and 14432 transitions.
[2024-11-08 18:32:36,362 INFO L240 hiAutomatonCegarLoop]: Abstraction has 10331 states and 14432 transitions.
[2024-11-08 18:32:36,363 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states.
[2024-11-08 18:32:36,364 INFO L425 stractBuchiCegarLoop]: Abstraction has 10331 states and 14432 transitions.
[2024-11-08 18:32:36,364 INFO L332 stractBuchiCegarLoop]: ======== Iteration 18 ============
[2024-11-08 18:32:36,364 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10331 states and 14432 transitions.
[2024-11-08 18:32:36,395 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 10096
[2024-11-08 18:32:36,396 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2024-11-08 18:32:36,396 INFO L119 BuchiIsEmpty]: Starting construction of run
[2024-11-08 18:32:36,397 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 18:32:36,398 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 18:32:36,398 INFO L745 eck$LassoCheckResult]: Stem: 158666#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 158667#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 159278#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 159279#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 159321#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 159303#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 159304#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 158825#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 158826#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 158895#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 158731#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 158732#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 158699#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 158700#L754 assume !(0 == ~M_E~0); 159339#L754-2 assume !(0 == ~T1_E~0); 159229#L759-1 assume !(0 == ~T2_E~0); 159076#L764-1 assume !(0 == ~T3_E~0); 159034#L769-1 assume !(0 == ~T4_E~0); 159035#L774-1 assume !(0 == ~T5_E~0); 159077#L779-1 assume !(0 == ~T6_E~0); 159237#L784-1 assume !(0 == ~T7_E~0); 159031#L789-1 assume !(0 == ~E_1~0); 159032#L794-1 assume !(0 == ~E_2~0); 159133#L799-1 assume !(0 == ~E_3~0); 159042#L804-1 assume !(0 == ~E_4~0); 159043#L809-1 assume !(0 == ~E_5~0); 159071#L814-1 assume 0 == ~E_6~0;~E_6~0 := 1; 158464#L819-1 assume !(0 == ~E_7~0); 158465#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 158729#L361 assume !(1 == ~m_pc~0); 158730#L361-2 is_master_triggered_~__retres1~0#1 := 0; 159346#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 159347#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 159312#L930 assume !(0 != activate_threads_~tmp~1#1); 159313#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 158723#L380 assume !(1 == ~t1_pc~0); 158724#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 159394#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 159392#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 159372#L938 assume !(0 != activate_threads_~tmp___0~0#1); 159164#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 159143#L399 assume !(1 == ~t2_pc~0); 159144#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 159322#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 159323#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 158797#L946 assume !(0 != activate_threads_~tmp___1~0#1); 158798#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 159387#L418 assume !(1 == ~t3_pc~0); 158452#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 158453#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 159386#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 159373#L954 assume !(0 != activate_threads_~tmp___2~0#1); 159374#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 159340#L437 assume !(1 == ~t4_pc~0); 159341#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 159385#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 158544#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 158545#L962 assume !(0 != activate_threads_~tmp___3~0#1); 159290#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 159185#L456 assume !(1 == ~t5_pc~0); 159186#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 159335#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 159221#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 159116#L970 assume !(0 != activate_threads_~tmp___4~0#1); 159117#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 158539#L475 assume !(1 == ~t6_pc~0); 158540#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 158581#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 158582#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 159105#L978 assume !(0 != activate_threads_~tmp___5~0#1); 159106#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 159258#L494 assume !(1 == ~t7_pc~0); 158987#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 159002#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 159003#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 159078#L986 assume !(0 != activate_threads_~tmp___6~0#1); 159079#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 159331#L837 assume !(1 == ~M_E~0); 159332#L837-2 assume !(1 == ~T1_E~0); 159380#L842-1 assume !(1 == ~T2_E~0); 159379#L847-1 assume !(1 == ~T3_E~0); 158930#L852-1 assume !(1 == ~T4_E~0); 158931#L857-1 assume !(1 == ~T5_E~0); 158811#L862-1 assume !(1 == ~T6_E~0); 158812#L867-1 assume !(1 == ~T7_E~0); 159378#L872-1 assume !(1 == ~E_1~0); 159093#L877-1 assume !(1 == ~E_2~0); 159094#L882-1 assume !(1 == ~E_3~0); 159345#L887-1 assume !(1 == ~E_4~0); 159158#L892-1 assume !(1 == ~E_5~0); 159159#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 158836#L902-1 assume !(1 == ~E_7~0); 158837#L907-1 assume { :end_inline_reset_delta_events } true; 159184#L1148-2
[2024-11-08 18:32:36,398 INFO L747 eck$LassoCheckResult]: Loop: 159184#L1148-2 assume !false; 164606#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 164604#L729-1 assume !false; 164602#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 164578#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 164576#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 164574#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 164571#L626 assume !(0 != eval_~tmp~0#1); 164572#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 164982#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 164979#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 164977#L754-5 assume !(0 == ~T1_E~0); 164975#L759-3 assume !(0 == ~T2_E~0); 164973#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 164971#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 164968#L774-3 assume !(0 == ~T5_E~0); 164966#L779-3 assume !(0 == ~T6_E~0); 164964#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 164962#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 164960#L794-3 assume !(0 == ~E_2~0); 164958#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 164956#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 164953#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 164950#L814-3 assume !(0 == ~E_6~0); 164951#L819-3 assume !(0 == ~E_7~0); 167567#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 167565#L361-24 assume !(1 == ~m_pc~0); 167563#L361-26 is_master_triggered_~__retres1~0#1 := 0; 167561#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 167558#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 167556#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 167554#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 167552#L380-24 assume 1 == ~t1_pc~0; 167550#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 167551#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 167573#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 167541#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 167539#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 167537#L399-24 assume !(1 == ~t2_pc~0); 167535#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 167533#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 167530#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 167528#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 167526#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 167524#L418-24 assume 1 == ~t3_pc~0; 167522#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 167519#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 167517#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 167515#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 167513#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 167511#L437-24 assume !(1 == ~t4_pc~0); 167509#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 167506#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 167504#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 167502#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 167500#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 167498#L456-24 assume !(1 == ~t5_pc~0); 167495#L456-26 is_transmit5_triggered_~__retres1~5#1 := 0; 167493#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 167491#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 167489#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 167487#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 167485#L475-24 assume !(1 == ~t6_pc~0); 167483#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 167481#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 167243#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 167136#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 167134#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 167132#L494-24 assume !(1 == ~t7_pc~0); 167130#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 167129#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 167128#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 167119#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 167117#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 167115#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 167111#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 167109#L842-3 assume !(1 == ~T2_E~0); 167108#L847-3 assume !(1 == ~T3_E~0); 167107#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 167106#L857-3 assume !(1 == ~T5_E~0); 167105#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 167104#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 167095#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 167093#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 167091#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 167089#L887-3 assume !(1 == ~E_4~0); 167087#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 164879#L897-3 assume !(1 == ~E_6~0); 164876#L902-3 assume !(1 == ~E_7~0); 164874#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 164868#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 164860#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 164858#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 164856#L1167 assume !(0 == start_simulation_~tmp~3#1); 164854#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 164850#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 164845#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 164844#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 164842#L1122 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 164841#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 164840#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 164839#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 159184#L1148-2
[2024-11-08 18:32:36,399 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 18:32:36,399 INFO L85 PathProgramCache]: Analyzing trace with hash -1110278718, now seen corresponding path program 1 times
[2024-11-08 18:32:36,399 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 18:32:36,400 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1142882683]
[2024-11-08 18:32:36,400 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 18:32:36,400 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 18:32:36,411 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-11-08 18:32:36,457 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2024-11-08 18:32:36,458 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2024-11-08 18:32:36,458 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1142882683]
[2024-11-08 18:32:36,458 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1142882683] provided 1 perfect and 0 imperfect interpolant sequences
[2024-11-08 18:32:36,458 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2024-11-08 18:32:36,458 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2024-11-08 18:32:36,459 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1978957013]
[2024-11-08 18:32:36,459 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2024-11-08 18:32:36,459 INFO L750 eck$LassoCheckResult]: stem already infeasible
[2024-11-08 18:32:36,459 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 18:32:36,460 INFO L85 PathProgramCache]: Analyzing trace with hash -1259607353, now seen corresponding path program 1 times
[2024-11-08 18:32:36,460 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 18:32:36,460 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1460091120]
[2024-11-08 18:32:36,460 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 18:32:36,460 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 18:32:36,472 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-11-08 18:32:36,502 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2024-11-08 18:32:36,502 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2024-11-08 18:32:36,502 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1460091120]
[2024-11-08 18:32:36,502 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1460091120] provided 1 perfect and 0 imperfect interpolant sequences
[2024-11-08 18:32:36,503 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2024-11-08 18:32:36,503 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2024-11-08 18:32:36,503 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1129901430]
[2024-11-08 18:32:36,503 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2024-11-08 18:32:36,503 INFO L762 eck$LassoCheckResult]: loop already infeasible
[2024-11-08 18:32:36,504 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2024-11-08 18:32:36,504 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants.
[2024-11-08 18:32:36,504 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12
[2024-11-08 18:32:36,504 INFO L87 Difference]: Start difference. First operand 10331 states and 14432 transitions. cyclomatic complexity: 4117 Second operand has 4 states, 4 states have (on average 23.25) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 18:32:36,791 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2024-11-08 18:32:36,791 INFO L93 Difference]: Finished difference Result 17156 states and 23937 transitions.
[2024-11-08 18:32:36,791 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17156 states and 23937 transitions.
[2024-11-08 18:32:36,884 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 16912
[2024-11-08 18:32:36,956 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17156 states to 17156 states and 23937 transitions.
[2024-11-08 18:32:36,956 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17156
[2024-11-08 18:32:36,972 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17156
[2024-11-08 18:32:36,972 INFO L73 IsDeterministic]: Start isDeterministic. Operand 17156 states and 23937 transitions.
[2024-11-08 18:32:36,991 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2024-11-08 18:32:36,992 INFO L218 hiAutomatonCegarLoop]: Abstraction has 17156 states and 23937 transitions.
[2024-11-08 18:32:37,012 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17156 states and 23937 transitions.
[2024-11-08 18:32:37,162 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17156 to 9092.
[2024-11-08 18:32:37,176 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9092 states, 9092 states have (on average 1.3916630004399473) internal successors, (12653), 9091 states have internal predecessors, (12653), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 18:32:37,317 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9092 states to 9092 states and 12653 transitions.
[2024-11-08 18:32:37,317 INFO L240 hiAutomatonCegarLoop]: Abstraction has 9092 states and 12653 transitions.
[2024-11-08 18:32:37,318 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states.
[2024-11-08 18:32:37,318 INFO L425 stractBuchiCegarLoop]: Abstraction has 9092 states and 12653 transitions.
[2024-11-08 18:32:37,318 INFO L332 stractBuchiCegarLoop]: ======== Iteration 19 ============
[2024-11-08 18:32:37,318 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9092 states and 12653 transitions.
[2024-11-08 18:32:37,343 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 8928
[2024-11-08 18:32:37,343 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2024-11-08 18:32:37,343 INFO L119 BuchiIsEmpty]: Starting construction of run
[2024-11-08 18:32:37,344 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 18:32:37,345 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 18:32:37,345 INFO L745 eck$LassoCheckResult]: Stem: 186158#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 186159#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 186748#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 186749#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 186786#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 186773#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 186774#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 186312#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 186313#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 186384#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 186220#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 186221#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 186188#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 186189#L754 assume !(0 == ~M_E~0); 186805#L754-2 assume !(0 == ~T1_E~0); 186697#L759-1 assume !(0 == ~T2_E~0); 186568#L764-1 assume !(0 == ~T3_E~0); 186519#L769-1 assume !(0 == ~T4_E~0); 186520#L774-1 assume !(0 == ~T5_E~0); 186569#L779-1 assume !(0 == ~T6_E~0); 186710#L784-1 assume !(0 == ~T7_E~0); 186516#L789-1 assume !(0 == ~E_1~0); 186517#L794-1 assume !(0 == ~E_2~0); 186611#L799-1 assume !(0 == ~E_3~0); 186528#L804-1 assume !(0 == ~E_4~0); 186529#L809-1 assume !(0 == ~E_5~0); 186562#L814-1 assume !(0 == ~E_6~0); 185962#L819-1 assume !(0 == ~E_7~0); 185963#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 186218#L361 assume !(1 == ~m_pc~0); 186219#L361-2 is_master_triggered_~__retres1~0#1 := 0; 186743#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 186684#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 186685#L930 assume !(0 != activate_threads_~tmp~1#1); 186431#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 186212#L380 assume !(1 == ~t1_pc~0); 186213#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 186782#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 186783#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 186817#L938 assume !(0 != activate_threads_~tmp___0~0#1); 186640#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 186621#L399 assume !(1 == ~t2_pc~0); 186128#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 186129#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 186293#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 186286#L946 assume !(0 != activate_threads_~tmp___1~0#1); 186287#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 185970#L418 assume !(1 == ~t3_pc~0); 185949#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 185950#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 185960#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 185961#L954 assume !(0 != activate_threads_~tmp___2~0#1); 186546#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 186547#L437 assume !(1 == ~t4_pc~0); 186775#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 186678#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 186039#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 186040#L962 assume !(0 != activate_threads_~tmp___3~0#1); 186341#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 186660#L456 assume !(1 == ~t5_pc~0); 186142#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 186141#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 186688#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 186599#L970 assume !(0 != activate_threads_~tmp___4~0#1); 186600#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 186034#L475 assume !(1 == ~t6_pc~0); 186035#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 186076#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 186077#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 186278#L978 assume !(0 != activate_threads_~tmp___5~0#1); 186533#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 186534#L494 assume !(1 == ~t7_pc~0); 186262#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 186263#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 186489#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 186570#L986 assume !(0 != activate_threads_~tmp___6~0#1); 186571#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 186796#L837 assume !(1 == ~M_E~0); 186747#L837-2 assume !(1 == ~T1_E~0); 186616#L842-1 assume !(1 == ~T2_E~0); 186350#L847-1 assume !(1 == ~T3_E~0); 186351#L852-1 assume !(1 == ~T4_E~0); 186420#L857-1 assume !(1 == ~T5_E~0); 186299#L862-1 assume !(1 == ~T6_E~0); 186300#L867-1 assume !(1 == ~T7_E~0); 186308#L872-1 assume !(1 == ~E_1~0); 186383#L877-1 assume !(1 == ~E_2~0); 186585#L882-1 assume !(1 == ~E_3~0); 186754#L887-1 assume !(1 == ~E_4~0); 186635#L892-1 assume !(1 == ~E_5~0); 186636#L897-1 assume !(1 == ~E_6~0); 186323#L902-1 assume !(1 == ~E_7~0); 186324#L907-1 assume { :end_inline_reset_delta_events } true; 186659#L1148-2
[2024-11-08 18:32:37,345 INFO L747 eck$LassoCheckResult]: Loop: 186659#L1148-2 assume !false; 192513#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 192512#L729-1 assume !false; 192511#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 192503#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 192501#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 192500#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 192498#L626 assume !(0 != eval_~tmp~0#1); 192499#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 194735#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 194734#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 194732#L754-5 assume !(0 == ~T1_E~0); 194730#L759-3 assume !(0 == ~T2_E~0); 194728#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 194725#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 194722#L774-3 assume !(0 == ~T5_E~0); 194720#L779-3 assume !(0 == ~T6_E~0); 194718#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 194715#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 194712#L794-3 assume !(0 == ~E_2~0); 194708#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 194706#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 192978#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 192975#L814-3 assume !(0 == ~E_6~0); 192973#L819-3 assume !(0 == ~E_7~0); 192971#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 192969#L361-24 assume !(1 == ~m_pc~0); 192966#L361-26 is_master_triggered_~__retres1~0#1 := 0; 192964#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 192962#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 192959#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 192957#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 192955#L380-24 assume !(1 == ~t1_pc~0); 192951#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 192949#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 192947#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 192944#L938-24 assume !(0 != activate_threads_~tmp___0~0#1); 192941#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 192939#L399-24 assume !(1 == ~t2_pc~0); 192937#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 192935#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 192933#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 192930#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 192928#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 192926#L418-24 assume !(1 == ~t3_pc~0); 192923#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 192921#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 192919#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 192916#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 192914#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 192912#L437-24 assume !(1 == ~t4_pc~0); 192910#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 192908#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 192906#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 192904#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 192902#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 192900#L456-24 assume 1 == ~t5_pc~0; 192898#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 192895#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 192892#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 192890#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 192888#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 192886#L475-24 assume !(1 == ~t6_pc~0); 192884#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 192882#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 192881#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 192880#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 192877#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 192875#L494-24 assume !(1 == ~t7_pc~0); 192872#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 192871#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 192868#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 192865#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 192861#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 192857#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 192853#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 192849#L842-3 assume !(1 == ~T2_E~0); 192845#L847-3 assume !(1 == ~T3_E~0); 192840#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 192838#L857-3 assume !(1 == ~T5_E~0); 192836#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 192835#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 192834#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 192833#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 192832#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 192831#L887-3 assume !(1 == ~E_4~0); 192830#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 192829#L897-3 assume !(1 == ~E_6~0); 192828#L902-3 assume !(1 == ~E_7~0); 192827#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 192825#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 192818#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 192809#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 192806#L1167 assume !(0 == start_simulation_~tmp~3#1); 192803#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 192736#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 192731#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 192730#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 192729#L1122 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 192728#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 192727#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 192726#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 186659#L1148-2
[2024-11-08 18:32:37,346 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 18:32:37,346 INFO L85 PathProgramCache]: Analyzing trace with hash 1968536774, now seen corresponding path program 1 times
[2024-11-08 18:32:37,346 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 18:32:37,346 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1885012750]
[2024-11-08 18:32:37,346 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 18:32:37,346 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 18:32:37,359 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-11-08 18:32:37,359 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2024-11-08 18:32:37,367 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-11-08 18:32:37,414 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2024-11-08 18:32:37,415 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 18:32:37,415 INFO L85 PathProgramCache]: Analyzing trace with hash -918460956, now seen corresponding path program 1 times
[2024-11-08 18:32:37,415 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 18:32:37,415 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [369499016]
[2024-11-08 18:32:37,415 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 18:32:37,415 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 18:32:37,428 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-11-08 18:32:37,460 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2024-11-08 18:32:37,461 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2024-11-08 18:32:37,461 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [369499016]
[2024-11-08 18:32:37,461 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [369499016] provided 1 perfect and 0 imperfect interpolant sequences
[2024-11-08 18:32:37,461 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2024-11-08 18:32:37,461 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2024-11-08 18:32:37,461 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1585725503]
[2024-11-08 18:32:37,461 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2024-11-08 18:32:37,462 INFO L762 eck$LassoCheckResult]: loop already infeasible
[2024-11-08 18:32:37,462 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2024-11-08 18:32:37,462 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2024-11-08 18:32:37,462 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2024-11-08 18:32:37,462 INFO L87 Difference]: Start difference. First operand 9092 states and 12653 transitions. cyclomatic complexity: 3577 Second operand has 3 states, 3 states have (on average 34.0) internal successors, (102), 3 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 18:32:37,536 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2024-11-08 18:32:37,536 INFO L93 Difference]: Finished difference Result 10331 states and 14356 transitions.
[2024-11-08 18:32:37,536 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10331 states and 14356 transitions.
[2024-11-08 18:32:37,577 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 10096
[2024-11-08 18:32:37,609 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10331 states to 10331 states and 14356 transitions.
[2024-11-08 18:32:37,610 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10331
[2024-11-08 18:32:37,706 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10331
[2024-11-08 18:32:37,710 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10331 states and 14356 transitions.
[2024-11-08 18:32:37,719 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2024-11-08 18:32:37,719 INFO L218 hiAutomatonCegarLoop]: Abstraction has 10331 states and 14356 transitions.
[2024-11-08 18:32:37,728 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10331 states and 14356 transitions.
[2024-11-08 18:32:37,819 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10331 to 10331.
[2024-11-08 18:32:37,833 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10331 states, 10331 states have (on average 1.3896041041525506) internal successors, (14356), 10330 states have internal predecessors, (14356), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 18:32:37,857 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10331 states to 10331 states and 14356 transitions.
[2024-11-08 18:32:37,857 INFO L240 hiAutomatonCegarLoop]: Abstraction has 10331 states and 14356 transitions.
[2024-11-08 18:32:37,858 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states.
[2024-11-08 18:32:37,858 INFO L425 stractBuchiCegarLoop]: Abstraction has 10331 states and 14356 transitions.
[2024-11-08 18:32:37,858 INFO L332 stractBuchiCegarLoop]: ======== Iteration 20 ============
[2024-11-08 18:32:37,859 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10331 states and 14356 transitions.
[2024-11-08 18:32:37,890 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 10096
[2024-11-08 18:32:37,890 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2024-11-08 18:32:37,890 INFO L119 BuchiIsEmpty]: Starting construction of run
[2024-11-08 18:32:37,891 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 18:32:37,892 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 18:32:37,892 INFO L745 eck$LassoCheckResult]: Stem: 205588#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 205589#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 206188#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 206189#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 206226#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 206207#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 206208#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 205744#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 205745#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 205815#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 205651#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 205652#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 205618#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 205619#L754 assume !(0 == ~M_E~0); 206242#L754-2 assume !(0 == ~T1_E~0); 206136#L759-1 assume !(0 == ~T2_E~0); 205993#L764-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 205948#L769-1 assume !(0 == ~T4_E~0); 205949#L774-1 assume !(0 == ~T5_E~0); 206218#L779-1 assume !(0 == ~T6_E~0); 206219#L784-1 assume !(0 == ~T7_E~0); 205945#L789-1 assume !(0 == ~E_1~0); 205946#L794-1 assume !(0 == ~E_2~0); 206040#L799-1 assume !(0 == ~E_3~0); 205956#L804-1 assume !(0 == ~E_4~0); 205957#L809-1 assume !(0 == ~E_5~0); 206170#L814-1 assume !(0 == ~E_6~0); 206171#L819-1 assume !(0 == ~E_7~0); 205709#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 205710#L361 assume !(1 == ~m_pc~0); 206183#L361-2 is_master_triggered_~__retres1~0#1 := 0; 206184#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 206300#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 206216#L930 assume !(0 != activate_threads_~tmp~1#1); 206217#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 205642#L380 assume !(1 == ~t1_pc~0); 205643#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 206298#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 206296#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 206294#L938 assume !(0 != activate_threads_~tmp___0~0#1); 206293#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 206292#L399 assume !(1 == ~t2_pc~0); 205557#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 205558#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 205722#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 205723#L946 assume !(0 != activate_threads_~tmp___1~0#1); 206291#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 206290#L418 assume !(1 == ~t3_pc~0); 205378#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 205379#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 206289#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 206269#L954 assume !(0 != activate_threads_~tmp___2~0#1); 206270#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 206245#L437 assume !(1 == ~t4_pc~0); 206246#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 206288#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 205472#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 205473#L962 assume !(0 != activate_threads_~tmp___3~0#1); 205773#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 206286#L456 assume !(1 == ~t5_pc~0); 205571#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 205570#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 206285#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 206284#L970 assume !(0 != activate_threads_~tmp___4~0#1); 206257#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 205465#L475 assume !(1 == ~t6_pc~0); 205466#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 206282#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 205705#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 205706#L978 assume !(0 != activate_threads_~tmp___5~0#1); 206023#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 206167#L494 assume !(1 == ~t7_pc~0); 205689#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 205690#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 205918#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 205997#L986 assume !(0 != activate_threads_~tmp___6~0#1); 205998#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 206235#L837 assume !(1 == ~M_E~0); 206187#L837-2 assume !(1 == ~T1_E~0); 206048#L842-1 assume !(1 == ~T2_E~0); 205780#L847-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 205781#L852-1 assume !(1 == ~T4_E~0); 205849#L857-1 assume !(1 == ~T5_E~0); 205730#L862-1 assume !(1 == ~T6_E~0); 205731#L867-1 assume !(1 == ~T7_E~0); 205740#L872-1 assume !(1 == ~E_1~0); 205814#L877-1 assume !(1 == ~E_2~0); 206013#L882-1 assume !(1 == ~E_3~0); 206192#L887-1 assume !(1 == ~E_4~0); 206069#L892-1 assume !(1 == ~E_5~0); 206070#L897-1 assume !(1 == ~E_6~0); 205756#L902-1 assume !(1 == ~E_7~0); 205757#L907-1 assume { :end_inline_reset_delta_events } true; 206094#L1148-2
[2024-11-08 18:32:37,892 INFO L747 eck$LassoCheckResult]: Loop: 206094#L1148-2 assume !false; 209447#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 209445#L729-1 assume !false; 209443#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 209424#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 209422#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 209421#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 209418#L626 assume !(0 != eval_~tmp~0#1); 209419#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 209688#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 209686#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 209685#L754-5 assume !(0 == ~T1_E~0); 209684#L759-3 assume !(0 == ~T2_E~0); 209682#L764-3 assume !(0 == ~T3_E~0); 209683#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 209816#L774-3 assume !(0 == ~T5_E~0); 209815#L779-3 assume !(0 == ~T6_E~0); 209814#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 209812#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 209811#L794-3 assume !(0 == ~E_2~0); 209810#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 209808#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 209806#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 209804#L814-3 assume !(0 == ~E_6~0); 209802#L819-3 assume !(0 == ~E_7~0); 209800#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 209798#L361-24 assume !(1 == ~m_pc~0); 209797#L361-26 is_master_triggered_~__retres1~0#1 := 0; 209793#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 209791#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 209789#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 209787#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 209784#L380-24 assume 1 == ~t1_pc~0; 209782#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 209783#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 209817#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 209773#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 209771#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 209769#L399-24 assume !(1 == ~t2_pc~0); 209767#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 209765#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 209762#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 209760#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 209758#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 209756#L418-24 assume 1 == ~t3_pc~0; 209754#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 209751#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 209749#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 209747#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 209745#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 209743#L437-24 assume !(1 == ~t4_pc~0); 209741#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 209739#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 209736#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 209734#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 209732#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 209730#L456-24 assume 1 == ~t5_pc~0; 209728#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 209725#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 209723#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 209721#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 209719#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 209717#L475-24 assume !(1 == ~t6_pc~0); 209715#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 209712#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 209710#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 209708#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 209706#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 209704#L494-24 assume !(1 == ~t7_pc~0); 209701#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 209700#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 209696#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 209694#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 209692#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 209691#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 209690#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 209689#L842-3 assume !(1 == ~T2_E~0); 209544#L847-3 assume !(1 == ~T3_E~0); 209542#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 209540#L857-3 assume !(1 == ~T5_E~0); 209538#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 209537#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 209536#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 209535#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 209534#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 209533#L887-3 assume !(1 == ~E_4~0); 209532#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 209530#L897-3 assume !(1 == ~E_6~0); 209528#L902-3 assume !(1 == ~E_7~0); 209526#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 209512#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 209504#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 209502#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 209499#L1167 assume !(0 == start_simulation_~tmp~3#1); 209496#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 209484#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 209478#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 209476#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 209474#L1122 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 209472#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 209470#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 209468#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 206094#L1148-2
[2024-11-08 18:32:37,895 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 18:32:37,896 INFO L85 PathProgramCache]: Analyzing trace with hash -1766690110, now seen corresponding path program 1 times
[2024-11-08 18:32:37,896 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 18:32:37,897 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [215699870]
[2024-11-08 18:32:37,897 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 18:32:37,897 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 18:32:37,908 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-11-08 18:32:37,959 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2024-11-08 18:32:37,960 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2024-11-08 18:32:37,960 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [215699870]
[2024-11-08 18:32:37,960 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [215699870] provided 1 perfect and 0 imperfect interpolant sequences
[2024-11-08 18:32:37,960 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2024-11-08 18:32:37,960 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2024-11-08 18:32:37,961 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [910445164]
[2024-11-08 18:32:37,961 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2024-11-08 18:32:37,961 INFO L750 eck$LassoCheckResult]: stem already infeasible
[2024-11-08 18:32:37,961 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 18:32:37,962 INFO L85 PathProgramCache]: Analyzing trace with hash -722336150, now seen corresponding path program 1 times
[2024-11-08 18:32:37,962 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 18:32:37,962 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [613176574]
[2024-11-08 18:32:37,962 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 18:32:37,962 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 18:32:37,974 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-11-08 18:32:38,010 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2024-11-08 18:32:38,011 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2024-11-08 18:32:38,011 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [613176574]
[2024-11-08 18:32:38,011 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [613176574] provided 1 perfect and 0 imperfect interpolant sequences
[2024-11-08 18:32:38,011 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2024-11-08 18:32:38,011 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2024-11-08 18:32:38,012 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [147774511]
[2024-11-08 18:32:38,012 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2024-11-08 18:32:38,012 INFO L762 eck$LassoCheckResult]: loop already infeasible
[2024-11-08 18:32:38,012 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2024-11-08 18:32:38,013 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants.
[2024-11-08 18:32:38,013 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12
[2024-11-08 18:32:38,013 INFO L87 Difference]: Start difference. First operand 10331 states and 14356 transitions. cyclomatic complexity: 4041 Second operand has 4 states, 4 states have (on average 23.25) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 18:32:38,171 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2024-11-08 18:32:38,171 INFO L93 Difference]: Finished difference Result 18096 states and 25156 transitions.
[2024-11-08 18:32:38,171 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 18096 states and 25156 transitions.
[2024-11-08 18:32:38,351 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 17856
[2024-11-08 18:32:38,409 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 18096 states to 18096 states and 25156 transitions.
[2024-11-08 18:32:38,409 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18096
[2024-11-08 18:32:38,421 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18096
[2024-11-08 18:32:38,421 INFO L73 IsDeterministic]: Start isDeterministic. Operand 18096 states and 25156 transitions.
[2024-11-08 18:32:38,437 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2024-11-08 18:32:38,437 INFO L218 hiAutomatonCegarLoop]: Abstraction has 18096 states and 25156 transitions.
[2024-11-08 18:32:38,454 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18096 states and 25156 transitions.
[2024-11-08 18:32:38,564 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18096 to 9092.
[2024-11-08 18:32:38,577 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9092 states, 9092 states have (on average 1.3897932248130225) internal successors, (12636), 9091 states have internal predecessors, (12636), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 18:32:38,598 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9092 states to 9092 states and 12636 transitions.
[2024-11-08 18:32:38,598 INFO L240 hiAutomatonCegarLoop]: Abstraction has 9092 states and 12636 transitions.
[2024-11-08 18:32:38,599 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states.
[2024-11-08 18:32:38,599 INFO L425 stractBuchiCegarLoop]: Abstraction has 9092 states and 12636 transitions.
[2024-11-08 18:32:38,599 INFO L332 stractBuchiCegarLoop]: ======== Iteration 21 ============
[2024-11-08 18:32:38,600 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9092 states and 12636 transitions.
[2024-11-08 18:32:38,628 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 8928
[2024-11-08 18:32:38,628 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2024-11-08 18:32:38,628 INFO L119 BuchiIsEmpty]: Starting construction of run
[2024-11-08 18:32:38,629 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 18:32:38,630 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 18:32:38,630 INFO L745 eck$LassoCheckResult]: Stem: 234025#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 234026#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 234606#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 234607#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 234641#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 234629#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 234630#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 234178#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 234179#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 234253#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 234088#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 234089#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 234056#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 234057#L754 assume !(0 == ~M_E~0); 234658#L754-2 assume !(0 == ~T1_E~0); 234562#L759-1 assume !(0 == ~T2_E~0); 234431#L764-1 assume !(0 == ~T3_E~0); 234388#L769-1 assume !(0 == ~T4_E~0); 234389#L774-1 assume !(0 == ~T5_E~0); 234432#L779-1 assume !(0 == ~T6_E~0); 234576#L784-1 assume !(0 == ~T7_E~0); 234385#L789-1 assume !(0 == ~E_1~0); 234386#L794-1 assume !(0 == ~E_2~0); 234477#L799-1 assume !(0 == ~E_3~0); 234396#L804-1 assume !(0 == ~E_4~0); 234397#L809-1 assume !(0 == ~E_5~0); 234426#L814-1 assume !(0 == ~E_6~0); 233830#L819-1 assume !(0 == ~E_7~0); 233831#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 234086#L361 assume !(1 == ~m_pc~0); 234087#L361-2 is_master_triggered_~__retres1~0#1 := 0; 234601#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 234550#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 234551#L930 assume !(0 != activate_threads_~tmp~1#1); 234299#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 234080#L380 assume !(1 == ~t1_pc~0); 234081#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 234677#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 233849#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 233850#L938 assume !(0 != activate_threads_~tmp___0~0#1); 234507#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 234487#L399 assume !(1 == ~t2_pc~0); 233994#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 233995#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 234159#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 234152#L946 assume !(0 != activate_threads_~tmp___1~0#1); 234153#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 233836#L418 assume !(1 == ~t3_pc~0); 233815#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 233816#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 233826#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 233827#L954 assume !(0 != activate_threads_~tmp___2~0#1); 234412#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 234413#L437 assume !(1 == ~t4_pc~0); 234631#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 234545#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 233906#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 233907#L962 assume !(0 != activate_threads_~tmp___3~0#1); 234208#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 234530#L456 assume !(1 == ~t5_pc~0); 234008#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 234007#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 234554#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 234466#L970 assume !(0 != activate_threads_~tmp___4~0#1); 234467#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 233901#L475 assume !(1 == ~t6_pc~0); 233902#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 233942#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 233943#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 234145#L978 assume !(0 != activate_threads_~tmp___5~0#1); 234403#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 234404#L494 assume !(1 == ~t7_pc~0); 234129#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 234130#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 234357#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 234433#L986 assume !(0 != activate_threads_~tmp___6~0#1); 234434#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 234650#L837 assume !(1 == ~M_E~0); 234605#L837-2 assume !(1 == ~T1_E~0); 234483#L842-1 assume !(1 == ~T2_E~0); 234217#L847-1 assume !(1 == ~T3_E~0); 234218#L852-1 assume !(1 == ~T4_E~0); 234289#L857-1 assume !(1 == ~T5_E~0); 234165#L862-1 assume !(1 == ~T6_E~0); 234166#L867-1 assume !(1 == ~T7_E~0); 234174#L872-1 assume !(1 == ~E_1~0); 234252#L877-1 assume !(1 == ~E_2~0); 234447#L882-1 assume !(1 == ~E_3~0); 234610#L887-1 assume !(1 == ~E_4~0); 234502#L892-1 assume !(1 == ~E_5~0); 234503#L897-1 assume !(1 == ~E_6~0); 234190#L902-1 assume !(1 == ~E_7~0); 234191#L907-1 assume { :end_inline_reset_delta_events } true; 234524#L1148-2
[2024-11-08 18:32:38,630 INFO L747 eck$LassoCheckResult]: Loop: 234524#L1148-2 assume !false; 236548#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 236546#L729-1 assume !false; 236544#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 236486#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 236479#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 236473#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 236466#L626 assume !(0 != eval_~tmp~0#1); 236467#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 242720#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 242719#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 242718#L754-5 assume !(0 == ~T1_E~0); 242717#L759-3 assume !(0 == ~T2_E~0); 242716#L764-3 assume !(0 == ~T3_E~0); 242715#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 242714#L774-3 assume !(0 == ~T5_E~0); 242713#L779-3 assume !(0 == ~T6_E~0); 242712#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 242711#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 242710#L794-3 assume !(0 == ~E_2~0); 242709#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 242708#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 242707#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 242706#L814-3 assume !(0 == ~E_6~0); 242705#L819-3 assume !(0 == ~E_7~0); 242642#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 242641#L361-24 assume !(1 == ~m_pc~0); 242640#L361-26 is_master_triggered_~__retres1~0#1 := 0; 234340#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 233929#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 233930#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 234593#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 234392#L380-24 assume 1 == ~t1_pc~0; 234394#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 234615#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 242464#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 241970#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 238257#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 238253#L399-24 assume !(1 == ~t2_pc~0); 238252#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 238250#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 238248#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 238247#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 238244#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 238242#L418-24 assume 1 == ~t3_pc~0; 238238#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 238234#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 238231#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 238230#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 238229#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 238228#L437-24 assume !(1 == ~t4_pc~0); 238222#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 238221#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 238220#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 238219#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 238218#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 238217#L456-24 assume !(1 == ~t5_pc~0); 238215#L456-26 is_transmit5_triggered_~__retres1~5#1 := 0; 238214#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 238212#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 238211#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 238210#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 238209#L475-24 assume !(1 == ~t6_pc~0); 238208#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 238207#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 238205#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 238202#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 238200#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 238198#L494-24 assume !(1 == ~t7_pc~0); 238195#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 238193#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 238189#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 238187#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 238185#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 238183#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 238180#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 238178#L842-3 assume !(1 == ~T2_E~0); 238176#L847-3 assume !(1 == ~T3_E~0); 238173#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 238171#L857-3 assume !(1 == ~T5_E~0); 238169#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 238167#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 238165#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 238163#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 238160#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 238158#L887-3 assume !(1 == ~E_4~0); 238156#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 238154#L897-3 assume !(1 == ~E_6~0); 238152#L902-3 assume !(1 == ~E_7~0); 238150#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 237172#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 237165#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 237161#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 237158#L1167 assume !(0 == start_simulation_~tmp~3#1); 237155#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 236584#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 236578#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 236575#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 236573#L1122 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 236571#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 236569#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 236567#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 234524#L1148-2
[2024-11-08 18:32:38,632 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 18:32:38,632 INFO L85 PathProgramCache]: Analyzing trace with hash 1968536774, now seen corresponding path program 2 times
[2024-11-08 18:32:38,632 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 18:32:38,632 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1749123276]
[2024-11-08 18:32:38,632 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 18:32:38,632 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 18:32:38,647 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-11-08 18:32:38,649 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2024-11-08 18:32:38,657 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-11-08 18:32:38,687 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2024-11-08 18:32:38,688 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 18:32:38,688 INFO L85 PathProgramCache]: Analyzing trace with hash -2030340919, now seen corresponding path program 1 times
[2024-11-08 18:32:38,688 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 18:32:38,688 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1327797199]
[2024-11-08 18:32:38,688 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 18:32:38,689 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 18:32:38,703 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-11-08 18:32:38,734 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2024-11-08 18:32:38,734 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2024-11-08 18:32:38,734 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1327797199]
[2024-11-08 18:32:38,735 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1327797199] provided 1 perfect and 0 imperfect interpolant sequences
[2024-11-08 18:32:38,735 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2024-11-08 18:32:38,735 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2024-11-08 18:32:38,735 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [43185409]
[2024-11-08 18:32:38,735 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2024-11-08 18:32:38,735 INFO L762 eck$LassoCheckResult]: loop already infeasible
[2024-11-08 18:32:38,735 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2024-11-08 18:32:38,736 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2024-11-08 18:32:38,736 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2024-11-08 18:32:38,736 INFO L87 Difference]: Start difference. First operand 9092 states and 12636 transitions. cyclomatic complexity: 3560 Second operand has 3 states, 3 states have (on average 34.0) internal successors, (102), 3 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 18:32:39,036 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2024-11-08 18:32:39,036 INFO L93 Difference]: Finished difference Result 13487 states and 18676 transitions.
[2024-11-08 18:32:39,037 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 13487 states and 18676 transitions.
[2024-11-08 18:32:39,113 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 13228
[2024-11-08 18:32:39,171 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 13487 states to 13487 states and 18676 transitions.
[2024-11-08 18:32:39,171 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13487
[2024-11-08 18:32:39,181 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13487
[2024-11-08 18:32:39,181 INFO L73 IsDeterministic]: Start isDeterministic. Operand 13487 states and 18676 transitions.
[2024-11-08 18:32:39,197 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2024-11-08 18:32:39,197 INFO L218 hiAutomatonCegarLoop]: Abstraction has 13487 states and 18676 transitions.
[2024-11-08 18:32:39,207 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13487 states and 18676 transitions.
[2024-11-08 18:32:39,378 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13487 to 13479.
[2024-11-08 18:32:39,400 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13479 states, 13479 states have (on average 1.3849692113658283) internal successors, (18668), 13478 states have internal predecessors, (18668), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 18:32:39,443 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13479 states to 13479 states and 18668 transitions.
[2024-11-08 18:32:39,444 INFO L240 hiAutomatonCegarLoop]: Abstraction has 13479 states and 18668 transitions.
[2024-11-08 18:32:39,444 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states.
[2024-11-08 18:32:39,445 INFO L425 stractBuchiCegarLoop]: Abstraction has 13479 states and 18668 transitions.
[2024-11-08 18:32:39,445 INFO L332 stractBuchiCegarLoop]: ======== Iteration 22 ============
[2024-11-08 18:32:39,445 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 13479 states and 18668 transitions.
[2024-11-08 18:32:39,498 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 13220
[2024-11-08 18:32:39,499 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2024-11-08 18:32:39,499 INFO L119 BuchiIsEmpty]: Starting construction of run
[2024-11-08 18:32:39,501 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 18:32:39,501 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 18:32:39,502 INFO L745 eck$LassoCheckResult]: Stem: 256609#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 256610#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 257209#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 257210#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 257252#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 257233#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 257234#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 256764#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 256765#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 256835#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 256671#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 256672#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 256639#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 256640#L754 assume !(0 == ~M_E~0); 257272#L754-2 assume !(0 == ~T1_E~0); 257162#L759-1 assume !(0 == ~T2_E~0); 257022#L764-1 assume !(0 == ~T3_E~0); 256977#L769-1 assume !(0 == ~T4_E~0); 256978#L774-1 assume !(0 == ~T5_E~0); 257023#L779-1 assume !(0 == ~T6_E~0); 257171#L784-1 assume !(0 == ~T7_E~0); 256974#L789-1 assume !(0 == ~E_1~0); 256975#L794-1 assume !(0 == ~E_2~0); 257068#L799-1 assume !(0 == ~E_3~0); 256986#L804-1 assume 0 == ~E_4~0;~E_4~0 := 1; 256987#L809-1 assume !(0 == ~E_5~0); 257189#L814-1 assume !(0 == ~E_6~0); 257190#L819-1 assume !(0 == ~E_7~0); 256731#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 256732#L361 assume !(1 == ~m_pc~0); 257203#L361-2 is_master_triggered_~__retres1~0#1 := 0; 257204#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 257149#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 257150#L930 assume !(0 != activate_threads_~tmp~1#1); 256881#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 256882#L380 assume !(1 == ~t1_pc~0); 257309#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 257310#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 257344#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 257341#L938 assume !(0 != activate_threads_~tmp___0~0#1); 257340#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 257339#L399 assume !(1 == ~t2_pc~0); 256579#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 256580#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 256745#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 256746#L946 assume !(0 != activate_threads_~tmp___1~0#1); 257338#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 257337#L418 assume !(1 == ~t3_pc~0); 256400#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 256401#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 257336#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 257316#L954 assume !(0 != activate_threads_~tmp___2~0#1); 257317#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 257273#L437 assume !(1 == ~t4_pc~0); 257274#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 257335#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 256493#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 256494#L962 assume !(0 != activate_threads_~tmp___3~0#1); 256793#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 257333#L456 assume !(1 == ~t5_pc~0); 256594#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 256593#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 257332#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 257331#L970 assume !(0 != activate_threads_~tmp___4~0#1); 257295#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 257296#L475 assume !(1 == ~t6_pc~0); 256937#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 256938#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 256727#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 256728#L978 assume !(0 != activate_threads_~tmp___5~0#1); 257049#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 257187#L494 assume !(1 == ~t7_pc~0); 256931#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 256946#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 256947#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 257024#L986 assume !(0 != activate_threads_~tmp___6~0#1); 257025#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 257263#L837 assume !(1 == ~M_E~0); 257264#L837-2 assume !(1 == ~T1_E~0); 257328#L842-1 assume !(1 == ~T2_E~0); 257327#L847-1 assume !(1 == ~T3_E~0); 256869#L852-1 assume !(1 == ~T4_E~0); 256870#L857-1 assume !(1 == ~T5_E~0); 256752#L862-1 assume !(1 == ~T6_E~0); 256753#L867-1 assume !(1 == ~T7_E~0); 256760#L872-1 assume !(1 == ~E_1~0); 256834#L877-1 assume !(1 == ~E_2~0); 257039#L882-1 assume !(1 == ~E_3~0); 257215#L887-1 assume 1 == ~E_4~0;~E_4~0 := 2; 257099#L892-1 assume !(1 == ~E_5~0); 257100#L897-1 assume !(1 == ~E_6~0); 256775#L902-1 assume !(1 == ~E_7~0); 256776#L907-1 assume { :end_inline_reset_delta_events } true; 257122#L1148-2
[2024-11-08 18:32:39,503 INFO L747 eck$LassoCheckResult]: Loop: 257122#L1148-2 assume !false; 259559#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 259557#L729-1 assume !false; 259556#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 259542#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 259538#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 259536#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 259533#L626 assume !(0 != eval_~tmp~0#1); 259534#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 259763#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 259761#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 259759#L754-5 assume !(0 == ~T1_E~0); 259757#L759-3 assume !(0 == ~T2_E~0); 259755#L764-3 assume !(0 == ~T3_E~0); 259753#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 259751#L774-3 assume !(0 == ~T5_E~0); 259749#L779-3 assume !(0 == ~T6_E~0); 259748#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 259747#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 259746#L794-3 assume !(0 == ~E_2~0); 259745#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 259743#L804-3 assume !(0 == ~E_4~0); 259744#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 259879#L814-3 assume !(0 == ~E_6~0); 259875#L819-3 assume !(0 == ~E_7~0); 259873#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 259871#L361-24 assume !(1 == ~m_pc~0); 259869#L361-26 is_master_triggered_~__retres1~0#1 := 0; 259866#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 259864#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 259862#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 259860#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 259858#L380-24 assume 1 == ~t1_pc~0; 259856#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 259857#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 259887#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 259847#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 259844#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 259842#L399-24 assume !(1 == ~t2_pc~0); 259840#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 259838#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 259836#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 259834#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 259832#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 259830#L418-24 assume !(1 == ~t3_pc~0); 259827#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 259825#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 259823#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 259821#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 259818#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 259816#L437-24 assume !(1 == ~t4_pc~0); 259814#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 259812#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 259810#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 259808#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 259806#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 259804#L456-24 assume 1 == ~t5_pc~0; 259802#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 259799#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 259797#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 259794#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 259792#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 259790#L475-24 assume !(1 == ~t6_pc~0); 259788#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 259786#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 259784#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 259783#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 259779#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 259777#L494-24 assume !(1 == ~t7_pc~0); 259774#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 259773#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 259770#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 259769#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 259768#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 259767#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 259766#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 259765#L842-3 assume !(1 == ~T2_E~0); 259764#L847-3 assume !(1 == ~T3_E~0); 259762#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 259760#L857-3 assume !(1 == ~T5_E~0); 259758#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 259756#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 259754#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 259752#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 259750#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 259611#L887-3 assume !(1 == ~E_4~0); 259609#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 259607#L897-3 assume !(1 == ~E_6~0); 259605#L902-3 assume !(1 == ~E_7~0); 259603#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 259597#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 259589#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 259587#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 259585#L1167 assume !(0 == start_simulation_~tmp~3#1); 259583#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 259578#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 259573#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 259572#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 259570#L1122 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 259569#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 259568#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 259566#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 257122#L1148-2
[2024-11-08 18:32:39,503 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 18:32:39,503 INFO L85 PathProgramCache]: Analyzing trace with hash -1835651390, now seen corresponding path program 1 times
[2024-11-08 18:32:39,504 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 18:32:39,504 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [672321095]
[2024-11-08 18:32:39,504 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 18:32:39,505 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 18:32:39,612 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-11-08 18:32:39,662 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2024-11-08 18:32:39,662 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2024-11-08 18:32:39,662 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [672321095]
[2024-11-08 18:32:39,662 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [672321095] provided 1 perfect and 0 imperfect interpolant sequences
[2024-11-08 18:32:39,663 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2024-11-08 18:32:39,663 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2024-11-08 18:32:39,663 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1021429269]
[2024-11-08 18:32:39,663 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2024-11-08 18:32:39,664 INFO L750 eck$LassoCheckResult]: stem already infeasible
[2024-11-08 18:32:39,664 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 18:32:39,664 INFO L85 PathProgramCache]: Analyzing trace with hash 1373145675, now seen corresponding path program 1 times
[2024-11-08 18:32:39,664 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 18:32:39,665 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1907629397]
[2024-11-08 18:32:39,665 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 18:32:39,665 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 18:32:39,680 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-11-08 18:32:39,735 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2024-11-08 18:32:39,735 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2024-11-08 18:32:39,736 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1907629397]
[2024-11-08 18:32:39,736 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1907629397] provided 1 perfect and 0 imperfect interpolant sequences
[2024-11-08 18:32:39,737 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2024-11-08 18:32:39,737 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5
[2024-11-08 18:32:39,737 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [974941471]
[2024-11-08 18:32:39,737 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2024-11-08 18:32:39,738 INFO L762 eck$LassoCheckResult]: loop already infeasible
[2024-11-08 18:32:39,738 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2024-11-08 18:32:39,738 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants.
[2024-11-08 18:32:39,738 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12
[2024-11-08 18:32:39,739 INFO L87 Difference]: Start difference. First operand 13479 states and 18668 transitions. cyclomatic complexity: 5205 Second operand has 4 states, 4 states have (on average 23.25) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 18:32:39,992 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2024-11-08 18:32:39,992 INFO L93 Difference]: Finished difference Result 24632 states and 34164 transitions.
[2024-11-08 18:32:39,992 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 24632 states and 34164 transitions.
[2024-11-08 18:32:40,096 INFO L131 ngComponentsAnalysis]: Automaton has 40 accepting balls. 23344
[2024-11-08 18:32:40,304 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 24632 states to 24632 states and 34164 transitions.
[2024-11-08 18:32:40,305 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 24632
[2024-11-08 18:32:40,329 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 24632
[2024-11-08 18:32:40,329 INFO L73 IsDeterministic]: Start isDeterministic. Operand 24632 states and 34164 transitions.
[2024-11-08 18:32:40,344 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2024-11-08 18:32:40,344 INFO L218 hiAutomatonCegarLoop]: Abstraction has 24632 states and 34164 transitions.
[2024-11-08 18:32:40,357 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24632 states and 34164 transitions.
[2024-11-08 18:32:40,500 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24632 to 12828.
[2024-11-08 18:32:40,514 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12828 states, 12828 states have (on average 1.384081696289367) internal successors, (17755), 12827 states have internal predecessors, (17755), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 18:32:40,537 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12828 states to 12828 states and 17755 transitions.
[2024-11-08 18:32:40,538 INFO L240 hiAutomatonCegarLoop]: Abstraction has 12828 states and 17755 transitions.
[2024-11-08 18:32:40,538 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states.
[2024-11-08 18:32:40,539 INFO L425 stractBuchiCegarLoop]: Abstraction has 12828 states and 17755 transitions.
[2024-11-08 18:32:40,539 INFO L332 stractBuchiCegarLoop]: ======== Iteration 23 ============
[2024-11-08 18:32:40,539 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12828 states and 17755 transitions.
[2024-11-08 18:32:40,576 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 12640
[2024-11-08 18:32:40,576 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2024-11-08 18:32:40,578 INFO L119 BuchiIsEmpty]: Starting construction of run
[2024-11-08 18:32:40,580 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 18:32:40,580 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 18:32:40,580 INFO L745 eck$LassoCheckResult]: Stem: 294735#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 294736#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 295313#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 295314#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 295360#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 295341#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 295342#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 294888#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 294889#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 294957#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 294798#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 294799#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 294765#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 294766#L754 assume !(0 == ~M_E~0); 295378#L754-2 assume !(0 == ~T1_E~0); 295272#L759-1 assume !(0 == ~T2_E~0); 295139#L764-1 assume !(0 == ~T3_E~0); 295094#L769-1 assume !(0 == ~T4_E~0); 295095#L774-1 assume !(0 == ~T5_E~0); 295140#L779-1 assume !(0 == ~T6_E~0); 295279#L784-1 assume !(0 == ~T7_E~0); 295091#L789-1 assume !(0 == ~E_1~0); 295092#L794-1 assume !(0 == ~E_2~0); 295183#L799-1 assume !(0 == ~E_3~0); 295102#L804-1 assume !(0 == ~E_4~0); 295103#L809-1 assume !(0 == ~E_5~0); 295134#L814-1 assume !(0 == ~E_6~0); 294536#L819-1 assume !(0 == ~E_7~0); 294537#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 294796#L361 assume !(1 == ~m_pc~0); 294797#L361-2 is_master_triggered_~__retres1~0#1 := 0; 295306#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 295258#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 295259#L930 assume !(0 != activate_threads_~tmp~1#1); 295004#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 294790#L380 assume !(1 == ~t1_pc~0); 294791#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 295403#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 294557#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 294558#L938 assume !(0 != activate_threads_~tmp___0~0#1); 295217#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 295194#L399 assume !(1 == ~t2_pc~0); 294704#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 294705#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 294867#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 294860#L946 assume !(0 != activate_threads_~tmp___1~0#1); 294861#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 294544#L418 assume !(1 == ~t3_pc~0); 294523#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 294524#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 294534#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 294535#L954 assume !(0 != activate_threads_~tmp___2~0#1); 295121#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 295122#L437 assume !(1 == ~t4_pc~0); 295343#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 295253#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 294614#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 294615#L962 assume !(0 != activate_threads_~tmp___3~0#1); 294917#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 295237#L456 assume !(1 == ~t5_pc~0); 294719#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 294718#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 295263#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 295170#L970 assume !(0 != activate_threads_~tmp___4~0#1); 295171#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 294609#L475 assume !(1 == ~t6_pc~0); 294610#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 294651#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 294652#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 294853#L978 assume !(0 != activate_threads_~tmp___5~0#1); 295110#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 295111#L494 assume !(1 == ~t7_pc~0); 294837#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 294838#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 295066#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 295141#L986 assume !(0 != activate_threads_~tmp___6~0#1); 295142#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 295371#L837 assume !(1 == ~M_E~0); 295312#L837-2 assume !(1 == ~T1_E~0); 295190#L842-1 assume !(1 == ~T2_E~0); 294926#L847-1 assume !(1 == ~T3_E~0); 294927#L852-1 assume !(1 == ~T4_E~0); 294993#L857-1 assume !(1 == ~T5_E~0); 294873#L862-1 assume !(1 == ~T6_E~0); 294874#L867-1 assume !(1 == ~T7_E~0); 294882#L872-1 assume !(1 == ~E_1~0); 294956#L877-1 assume !(1 == ~E_2~0); 295155#L882-1 assume !(1 == ~E_3~0); 295320#L887-1 assume !(1 == ~E_4~0); 295211#L892-1 assume !(1 == ~E_5~0); 295212#L897-1 assume !(1 == ~E_6~0); 294900#L902-1 assume !(1 == ~E_7~0); 294901#L907-1 assume { :end_inline_reset_delta_events } true; 295236#L1148-2
[2024-11-08 18:32:40,580 INFO L747 eck$LassoCheckResult]: Loop: 295236#L1148-2 assume !false; 297201#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 297199#L729-1 assume !false; 297198#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 297166#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 297159#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 297154#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 297148#L626 assume !(0 != eval_~tmp~0#1); 297149#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 297581#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 297580#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 297579#L754-5 assume !(0 == ~T1_E~0); 297578#L759-3 assume !(0 == ~T2_E~0); 297577#L764-3 assume !(0 == ~T3_E~0); 297576#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 297575#L774-3 assume !(0 == ~T5_E~0); 297574#L779-3 assume !(0 == ~T6_E~0); 297573#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 297572#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 297571#L794-3 assume !(0 == ~E_2~0); 297570#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 297569#L804-3 assume !(0 == ~E_4~0); 297568#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 297567#L814-3 assume !(0 == ~E_6~0); 297566#L819-3 assume !(0 == ~E_7~0); 297565#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 297564#L361-24 assume !(1 == ~m_pc~0); 297563#L361-26 is_master_triggered_~__retres1~0#1 := 0; 297562#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 297561#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 297560#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 297559#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 297558#L380-24 assume 1 == ~t1_pc~0; 297556#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 297554#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 297552#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 297550#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 297549#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 297548#L399-24 assume !(1 == ~t2_pc~0); 297547#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 297546#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 297545#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 297544#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 297543#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 297542#L418-24 assume !(1 == ~t3_pc~0); 297540#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 297539#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 297538#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 297537#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 297536#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 297535#L437-24 assume !(1 == ~t4_pc~0); 297534#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 297533#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 297532#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 297531#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 297530#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 297529#L456-24 assume !(1 == ~t5_pc~0); 297527#L456-26 is_transmit5_triggered_~__retres1~5#1 := 0; 297526#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 297525#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 297524#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 297523#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 297522#L475-24 assume !(1 == ~t6_pc~0); 297521#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 297520#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 297519#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 297518#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 297517#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 297516#L494-24 assume !(1 == ~t7_pc~0); 297514#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 297513#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 297511#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 297509#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 297507#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 297505#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 297503#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 297501#L842-3 assume !(1 == ~T2_E~0); 297499#L847-3 assume !(1 == ~T3_E~0); 297497#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 297495#L857-3 assume !(1 == ~T5_E~0); 297493#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 297491#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 297489#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 297487#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 297485#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 297482#L887-3 assume !(1 == ~E_4~0); 297479#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 297475#L897-3 assume !(1 == ~E_6~0); 297471#L902-3 assume !(1 == ~E_7~0); 297468#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 297369#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 297356#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 297352#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 297245#L1167 assume !(0 == start_simulation_~tmp~3#1); 297242#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 297236#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 297230#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 297228#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 297226#L1122 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 297224#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 297222#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 297220#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 295236#L1148-2
[2024-11-08 18:32:40,581 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 18:32:40,581 INFO L85 PathProgramCache]: Analyzing trace with hash 1968536774, now seen corresponding path program 3 times
[2024-11-08 18:32:40,581 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 18:32:40,581 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [926947312]
[2024-11-08 18:32:40,581 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 18:32:40,582 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 18:32:40,596 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-11-08 18:32:40,596 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2024-11-08 18:32:40,606 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-11-08 18:32:40,642 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2024-11-08 18:32:40,642 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 18:32:40,642 INFO L85 PathProgramCache]: Analyzing trace with hash 65140906, now seen corresponding path program 1 times
[2024-11-08 18:32:40,643 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 18:32:40,643 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [169785849]
[2024-11-08 18:32:40,643 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 18:32:40,643 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 18:32:40,659 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-11-08 18:32:40,716 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2024-11-08 18:32:40,716 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2024-11-08 18:32:40,716 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [169785849]
[2024-11-08 18:32:40,716 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [169785849] provided 1 perfect and 0 imperfect interpolant sequences
[2024-11-08 18:32:40,716 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2024-11-08 18:32:40,716 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5
[2024-11-08 18:32:40,716 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [156788255]
[2024-11-08 18:32:40,717 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2024-11-08 18:32:40,717 INFO L762 eck$LassoCheckResult]: loop already infeasible
[2024-11-08 18:32:40,717 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2024-11-08 18:32:40,717 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants.
[2024-11-08 18:32:40,717 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20
[2024-11-08 18:32:40,718 INFO L87 Difference]: Start difference. First operand 12828 states and 17755 transitions. cyclomatic complexity: 4943 Second operand has 5 states, 5 states have (on average 20.4) internal successors, (102), 5 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 18:32:40,967 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2024-11-08 18:32:40,968 INFO L93 Difference]: Finished difference Result 12964 states and 17891 transitions.
[2024-11-08 18:32:40,968 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 12964 states and 17891 transitions.
[2024-11-08 18:32:41,019 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 12776
[2024-11-08 18:32:41,061 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 12964 states to 12964 states and 17891 transitions.
[2024-11-08 18:32:41,061 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12964
[2024-11-08 18:32:41,070 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12964
[2024-11-08 18:32:41,070 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12964 states and 17891 transitions.
[2024-11-08 18:32:41,081 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2024-11-08 18:32:41,081 INFO L218 hiAutomatonCegarLoop]: Abstraction has 12964 states and 17891 transitions.
[2024-11-08 18:32:41,090 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12964 states and 17891 transitions.
[2024-11-08 18:32:41,201 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12964 to 12900.
[2024-11-08 18:32:41,216 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12900 states, 12900 states have (on average 1.381937984496124) internal successors, (17827), 12899 states have internal predecessors, (17827), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 18:32:41,238 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12900 states to 12900 states and 17827 transitions.
[2024-11-08 18:32:41,239 INFO L240 hiAutomatonCegarLoop]: Abstraction has 12900 states and 17827 transitions.
[2024-11-08 18:32:41,239 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states.
[2024-11-08 18:32:41,240 INFO L425 stractBuchiCegarLoop]: Abstraction has 12900 states and 17827 transitions.
[2024-11-08 18:32:41,240 INFO L332 stractBuchiCegarLoop]: ======== Iteration 24 ============
[2024-11-08 18:32:41,241 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12900 states and 17827 transitions.
[2024-11-08 18:32:41,280 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 12712
[2024-11-08 18:32:41,280 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2024-11-08 18:32:41,280 INFO L119 BuchiIsEmpty]: Starting construction of run
[2024-11-08 18:32:41,281 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 18:32:41,281 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 18:32:41,282 INFO L745 eck$LassoCheckResult]: Stem: 320534#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 320535#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 321130#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 321131#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 321171#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 321154#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 321155#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 320686#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 320687#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 320756#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 320598#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 320599#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 320567#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 320568#L754 assume !(0 == ~M_E~0); 321182#L754-2 assume !(0 == ~T1_E~0); 321084#L759-1 assume !(0 == ~T2_E~0); 320941#L764-1 assume !(0 == ~T3_E~0); 320894#L769-1 assume !(0 == ~T4_E~0); 320895#L774-1 assume !(0 == ~T5_E~0); 320942#L779-1 assume !(0 == ~T6_E~0); 321093#L784-1 assume !(0 == ~T7_E~0); 320891#L789-1 assume !(0 == ~E_1~0); 320892#L794-1 assume !(0 == ~E_2~0); 320992#L799-1 assume !(0 == ~E_3~0); 320902#L804-1 assume !(0 == ~E_4~0); 320903#L809-1 assume !(0 == ~E_5~0); 320936#L814-1 assume !(0 == ~E_6~0); 320336#L819-1 assume !(0 == ~E_7~0); 320337#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 320596#L361 assume !(1 == ~m_pc~0); 320597#L361-2 is_master_triggered_~__retres1~0#1 := 0; 321125#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 321070#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 321071#L930 assume !(0 != activate_threads_~tmp~1#1); 320799#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 320590#L380 assume !(1 == ~t1_pc~0); 320591#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 321167#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 321168#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 321209#L938 assume !(0 != activate_threads_~tmp___0~0#1); 321027#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 321003#L399 assume !(1 == ~t2_pc~0); 320504#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 320505#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 320667#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 320660#L946 assume !(0 != activate_threads_~tmp___1~0#1); 320661#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 320344#L418 assume !(1 == ~t3_pc~0); 320323#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 320324#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 320334#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 320335#L954 assume !(0 != activate_threads_~tmp___2~0#1); 320918#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 320919#L437 assume !(1 == ~t4_pc~0); 321156#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 321064#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 320413#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 320414#L962 assume !(0 != activate_threads_~tmp___3~0#1); 320715#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 321047#L456 assume !(1 == ~t5_pc~0); 320518#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 320517#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 321074#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 320976#L970 assume !(0 != activate_threads_~tmp___4~0#1); 320977#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 320408#L475 assume !(1 == ~t6_pc~0); 320409#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 320450#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 320451#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 320653#L978 assume !(0 != activate_threads_~tmp___5~0#1); 320907#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 320908#L494 assume !(1 == ~t7_pc~0); 320637#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 320638#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 320865#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 320943#L986 assume !(0 != activate_threads_~tmp___6~0#1); 320944#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 321179#L837 assume !(1 == ~M_E~0); 321129#L837-2 assume !(1 == ~T1_E~0); 320999#L842-1 assume !(1 == ~T2_E~0); 320723#L847-1 assume !(1 == ~T3_E~0); 320724#L852-1 assume !(1 == ~T4_E~0); 320789#L857-1 assume !(1 == ~T5_E~0); 320673#L862-1 assume !(1 == ~T6_E~0); 320674#L867-1 assume !(1 == ~T7_E~0); 320682#L872-1 assume !(1 == ~E_1~0); 320755#L877-1 assume !(1 == ~E_2~0); 320959#L882-1 assume !(1 == ~E_3~0); 321138#L887-1 assume !(1 == ~E_4~0); 321020#L892-1 assume !(1 == ~E_5~0); 321021#L897-1 assume !(1 == ~E_6~0); 320698#L902-1 assume !(1 == ~E_7~0); 320699#L907-1 assume { :end_inline_reset_delta_events } true; 321046#L1148-2
[2024-11-08 18:32:41,283 INFO L747 eck$LassoCheckResult]: Loop: 321046#L1148-2 assume !false; 323231#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 323230#L729-1 assume !false; 323229#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 323220#L569 assume !(0 == ~m_st~0); 323221#L573 assume !(0 == ~t1_st~0); 323226#L577 assume !(0 == ~t2_st~0); 323228#L581 assume !(0 == ~t3_st~0); 323224#L585 assume !(0 == ~t4_st~0); 323225#L589 assume !(0 == ~t5_st~0); 323227#L593 assume !(0 == ~t6_st~0); 323222#L597 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8#1 := 0; 323223#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 323081#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 323082#L626 assume !(0 != eval_~tmp~0#1); 323904#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 323903#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 323902#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 323901#L754-5 assume !(0 == ~T1_E~0); 323900#L759-3 assume !(0 == ~T2_E~0); 323899#L764-3 assume !(0 == ~T3_E~0); 323898#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 323897#L774-3 assume !(0 == ~T5_E~0); 323896#L779-3 assume !(0 == ~T6_E~0); 323895#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 323894#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 323893#L794-3 assume !(0 == ~E_2~0); 323892#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 323891#L804-3 assume !(0 == ~E_4~0); 323890#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 323889#L814-3 assume !(0 == ~E_6~0); 323888#L819-3 assume !(0 == ~E_7~0); 323887#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 323886#L361-24 assume !(1 == ~m_pc~0); 323885#L361-26 is_master_triggered_~__retres1~0#1 := 0; 323884#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 323883#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 323882#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 323881#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 323880#L380-24 assume 1 == ~t1_pc~0; 323878#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 323876#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 323874#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 323872#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 323871#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 323870#L399-24 assume !(1 == ~t2_pc~0); 323869#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 323868#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 323867#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 323866#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 323865#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 323864#L418-24 assume !(1 == ~t3_pc~0); 323862#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 323861#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 323860#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 323859#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 323858#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 323857#L437-24 assume !(1 == ~t4_pc~0); 323856#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 323855#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 323854#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 323853#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 323852#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 323851#L456-24 assume !(1 == ~t5_pc~0); 323849#L456-26 is_transmit5_triggered_~__retres1~5#1 := 0; 323848#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 323847#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 323846#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 323845#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 323844#L475-24 assume !(1 == ~t6_pc~0); 323843#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 323842#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 323841#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 323840#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 323839#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 323838#L494-24 assume !(1 == ~t7_pc~0); 323836#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 323835#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 323834#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 323833#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 323832#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 323831#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 323830#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 323829#L842-3 assume !(1 == ~T2_E~0); 323828#L847-3 assume !(1 == ~T3_E~0); 323827#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 323826#L857-3 assume !(1 == ~T5_E~0); 323825#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 323824#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 323823#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 323822#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 323821#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 323820#L887-3 assume !(1 == ~E_4~0); 323819#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 323818#L897-3 assume !(1 == ~E_6~0); 323817#L902-3 assume !(1 == ~E_7~0); 323816#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 323814#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 323563#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 323546#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 323541#L1167 assume !(0 == start_simulation_~tmp~3#1); 323536#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 323530#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 323359#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 323254#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 323252#L1122 assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1; 323249#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 323245#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 323240#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 321046#L1148-2
[2024-11-08 18:32:41,283 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 18:32:41,284 INFO L85 PathProgramCache]: Analyzing trace with hash 1968536774, now seen corresponding path program 4 times
[2024-11-08 18:32:41,284 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 18:32:41,284 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1574946042]
[2024-11-08 18:32:41,284 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 18:32:41,284 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 18:32:41,433 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-11-08 18:32:41,433 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2024-11-08 18:32:41,449 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-11-08 18:32:41,481 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2024-11-08 18:32:41,481 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 18:32:41,482 INFO L85 PathProgramCache]: Analyzing trace with hash 693935532, now seen corresponding path program 1 times
[2024-11-08 18:32:41,482 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 18:32:41,482 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [456880598]
[2024-11-08 18:32:41,482 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 18:32:41,482 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 18:32:41,501 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-11-08 18:32:41,578 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2024-11-08 18:32:41,578 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2024-11-08 18:32:41,578 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [456880598]
[2024-11-08 18:32:41,578 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [456880598] provided 1 perfect and 0 imperfect interpolant sequences
[2024-11-08 18:32:41,578 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2024-11-08 18:32:41,579 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5
[2024-11-08 18:32:41,579 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1163248321]
[2024-11-08 18:32:41,579 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2024-11-08 18:32:41,579 INFO L762 eck$LassoCheckResult]: loop already infeasible
[2024-11-08 18:32:41,580 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2024-11-08 18:32:41,580 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants.
[2024-11-08 18:32:41,581 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20
[2024-11-08 18:32:41,581 INFO L87 Difference]: Start difference. First operand 12900 states and 17827 transitions. cyclomatic complexity: 4943 Second operand has 5 states, 5 states have (on average 21.8) internal successors, (109), 5 states have internal predecessors, (109), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 18:32:41,759 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2024-11-08 18:32:41,760 INFO L93 Difference]: Finished difference Result 12980 states and 17907 transitions.
[2024-11-08 18:32:41,760 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 12980 states and 17907 transitions.
[2024-11-08 18:32:41,826 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 12792
[2024-11-08 18:32:41,879 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 12980 states to 12980 states and 17907 transitions.
[2024-11-08 18:32:41,880 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12980
[2024-11-08 18:32:41,889 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12980
[2024-11-08 18:32:41,889 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12980 states and 17907 transitions.
[2024-11-08 18:32:41,903 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2024-11-08 18:32:41,904 INFO L218 hiAutomatonCegarLoop]: Abstraction has 12980 states and 17907 transitions.
[2024-11-08 18:32:41,913 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12980 states and 17907 transitions.
[2024-11-08 18:32:42,061 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12980 to 12948.
[2024-11-08 18:32:42,076 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12948 states, 12948 states have (on average 1.3805220883534137) internal successors, (17875), 12947 states have internal predecessors, (17875), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 18:32:42,110 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12948 states to 12948 states and 17875 transitions.
[2024-11-08 18:32:42,110 INFO L240 hiAutomatonCegarLoop]: Abstraction has 12948 states and 17875 transitions.
[2024-11-08 18:32:42,111 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states.
[2024-11-08 18:32:42,111 INFO L425 stractBuchiCegarLoop]: Abstraction has 12948 states and 17875 transitions.
[2024-11-08 18:32:42,111 INFO L332 stractBuchiCegarLoop]: ======== Iteration 25 ============
[2024-11-08 18:32:42,112 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12948 states and 17875 transitions.
[2024-11-08 18:32:42,163 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 12760
[2024-11-08 18:32:42,164 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2024-11-08 18:32:42,164 INFO L119 BuchiIsEmpty]: Starting construction of run
[2024-11-08 18:32:42,166 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 18:32:42,166 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 18:32:42,166 INFO L745 eck$LassoCheckResult]: Stem: 346420#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 346421#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 347042#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 347043#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 347093#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 347070#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 347071#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 346576#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 346577#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 346649#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 346482#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 346483#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 346451#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 346452#L754 assume !(0 == ~M_E~0); 347107#L754-2 assume !(0 == ~T1_E~0); 346990#L759-1 assume !(0 == ~T2_E~0); 346849#L764-1 assume !(0 == ~T3_E~0); 346800#L769-1 assume !(0 == ~T4_E~0); 346801#L774-1 assume !(0 == ~T5_E~0); 346850#L779-1 assume !(0 == ~T6_E~0); 346999#L784-1 assume !(0 == ~T7_E~0); 346796#L789-1 assume !(0 == ~E_1~0); 346797#L794-1 assume !(0 == ~E_2~0); 346901#L799-1 assume !(0 == ~E_3~0); 346809#L804-1 assume !(0 == ~E_4~0); 346810#L809-1 assume !(0 == ~E_5~0); 346843#L814-1 assume !(0 == ~E_6~0); 346223#L819-1 assume !(0 == ~E_7~0); 346224#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 346480#L361 assume !(1 == ~m_pc~0); 346481#L361-2 is_master_triggered_~__retres1~0#1 := 0; 347036#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 346976#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 346977#L930 assume !(0 != activate_threads_~tmp~1#1); 346696#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 346474#L380 assume !(1 == ~t1_pc~0); 346475#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 347087#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 347088#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 347144#L938 assume !(0 != activate_threads_~tmp___0~0#1); 346932#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 346910#L399 assume !(1 == ~t2_pc~0); 346390#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 346391#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 346554#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 346547#L946 assume !(0 != activate_threads_~tmp___1~0#1); 346548#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 346231#L418 assume !(1 == ~t3_pc~0); 346211#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 346212#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 346221#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 346222#L954 assume !(0 != activate_threads_~tmp___2~0#1); 346826#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 346827#L437 assume !(1 == ~t4_pc~0); 347072#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 346970#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 346300#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 346301#L962 assume !(0 != activate_threads_~tmp___3~0#1); 346606#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 346950#L456 assume !(1 == ~t5_pc~0); 346404#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 346403#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 346980#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 346887#L970 assume !(0 != activate_threads_~tmp___4~0#1); 346888#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 346295#L475 assume !(1 == ~t6_pc~0); 346296#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 346337#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 346338#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 346539#L978 assume !(0 != activate_threads_~tmp___5~0#1); 346816#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 346817#L494 assume !(1 == ~t7_pc~0); 346523#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 346524#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 346768#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 346851#L986 assume !(0 != activate_threads_~tmp___6~0#1); 346852#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 347099#L837 assume !(1 == ~M_E~0); 347041#L837-2 assume !(1 == ~T1_E~0); 346906#L842-1 assume !(1 == ~T2_E~0); 346615#L847-1 assume !(1 == ~T3_E~0); 346616#L852-1 assume !(1 == ~T4_E~0); 346685#L857-1 assume !(1 == ~T5_E~0); 346560#L862-1 assume !(1 == ~T6_E~0); 346561#L867-1 assume !(1 == ~T7_E~0); 346572#L872-1 assume !(1 == ~E_1~0); 346648#L877-1 assume !(1 == ~E_2~0); 346870#L882-1 assume !(1 == ~E_3~0); 347048#L887-1 assume !(1 == ~E_4~0); 346925#L892-1 assume !(1 == ~E_5~0); 346926#L897-1 assume !(1 == ~E_6~0); 346588#L902-1 assume !(1 == ~E_7~0); 346589#L907-1 assume { :end_inline_reset_delta_events } true; 346949#L1148-2
[2024-11-08 18:32:42,167 INFO L747 eck$LassoCheckResult]: Loop: 346949#L1148-2 assume !false; 349321#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 349320#L729-1 assume !false; 349319#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 349310#L569 assume !(0 == ~m_st~0); 349311#L573 assume !(0 == ~t1_st~0); 349316#L577 assume !(0 == ~t2_st~0); 349318#L581 assume !(0 == ~t3_st~0); 349314#L585 assume !(0 == ~t4_st~0); 349315#L589 assume !(0 == ~t5_st~0); 349317#L593 assume !(0 == ~t6_st~0); 349312#L597 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8#1 := 0; 349313#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 349130#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 349131#L626 assume !(0 != eval_~tmp~0#1); 350019#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 350018#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 350017#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 350016#L754-5 assume !(0 == ~T1_E~0); 350015#L759-3 assume !(0 == ~T2_E~0); 350014#L764-3 assume !(0 == ~T3_E~0); 350013#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 350012#L774-3 assume !(0 == ~T5_E~0); 350011#L779-3 assume !(0 == ~T6_E~0); 350010#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 350009#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 350008#L794-3 assume !(0 == ~E_2~0); 350007#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 350006#L804-3 assume !(0 == ~E_4~0); 350005#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 350004#L814-3 assume !(0 == ~E_6~0); 350003#L819-3 assume !(0 == ~E_7~0); 350002#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 350001#L361-24 assume !(1 == ~m_pc~0); 350000#L361-26 is_master_triggered_~__retres1~0#1 := 0; 349999#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 349998#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 349997#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 349996#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 349995#L380-24 assume 1 == ~t1_pc~0; 349993#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 349991#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 349989#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 349987#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 349986#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 349985#L399-24 assume !(1 == ~t2_pc~0); 349984#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 349983#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 349982#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 349981#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 349980#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 349979#L418-24 assume !(1 == ~t3_pc~0); 349977#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 349976#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 349975#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 349974#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 349973#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 349972#L437-24 assume !(1 == ~t4_pc~0); 349971#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 349970#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 349969#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 349968#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 349967#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 349966#L456-24 assume 1 == ~t5_pc~0; 349965#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 349963#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 349962#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 349961#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 349960#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 349959#L475-24 assume !(1 == ~t6_pc~0); 349958#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 349957#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 349956#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 349955#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 349954#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 349953#L494-24 assume !(1 == ~t7_pc~0); 349951#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 349950#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 349949#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 349948#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 349947#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 349945#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 349943#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 349941#L842-3 assume !(1 == ~T2_E~0); 349939#L847-3 assume !(1 == ~T3_E~0); 349937#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 349935#L857-3 assume !(1 == ~T5_E~0); 349933#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 349930#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 349927#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 349924#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 349921#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 349919#L887-3 assume !(1 == ~E_4~0); 349917#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 349915#L897-3 assume !(1 == ~E_6~0); 349913#L902-3 assume !(1 == ~E_7~0); 349911#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 349908#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 349582#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 349369#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 349365#L1167 assume !(0 == start_simulation_~tmp~3#1); 349362#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 349357#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 349351#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 349346#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 349343#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 349339#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 349335#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 349330#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 346949#L1148-2
[2024-11-08 18:32:42,167 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 18:32:42,168 INFO L85 PathProgramCache]: Analyzing trace with hash 1968536774, now seen corresponding path program 5 times
[2024-11-08 18:32:42,168 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 18:32:42,168 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1396723011]
[2024-11-08 18:32:42,168 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 18:32:42,168 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 18:32:42,187 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-11-08 18:32:42,188 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2024-11-08 18:32:42,198 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-11-08 18:32:42,221 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2024-11-08 18:32:42,222 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 18:32:42,222 INFO L85 PathProgramCache]: Analyzing trace with hash 2001880719, now seen corresponding path program 1 times
[2024-11-08 18:32:42,222 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 18:32:42,223 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1495563954]
[2024-11-08 18:32:42,223 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 18:32:42,223 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 18:32:42,246 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-11-08 18:32:42,346 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2024-11-08 18:32:42,346 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2024-11-08 18:32:42,346 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1495563954]
[2024-11-08 18:32:42,346 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1495563954] provided 1 perfect and 0 imperfect interpolant sequences
[2024-11-08 18:32:42,347 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2024-11-08 18:32:42,347 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5
[2024-11-08 18:32:42,347 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2134772246]
[2024-11-08 18:32:42,347 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2024-11-08 18:32:42,347 INFO L762 eck$LassoCheckResult]: loop already infeasible
[2024-11-08 18:32:42,348 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2024-11-08 18:32:42,348 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants.
[2024-11-08 18:32:42,349 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20
[2024-11-08 18:32:42,349 INFO L87 Difference]: Start difference. First operand 12948 states and 17875 transitions. cyclomatic complexity: 4943 Second operand has 5 states, 5 states have (on average 21.8) internal successors, (109), 5 states have internal predecessors, (109), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 18:32:42,638 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2024-11-08 18:32:42,639 INFO L93 Difference]: Finished difference Result 13200 states and 18054 transitions.
[2024-11-08 18:32:42,639 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 13200 states and 18054 transitions.
[2024-11-08 18:32:42,710 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 13012
[2024-11-08 18:32:42,766 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 13200 states to 13200 states and 18054 transitions.
[2024-11-08 18:32:42,766 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13200
[2024-11-08 18:32:42,776 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13200
[2024-11-08 18:32:42,777 INFO L73 IsDeterministic]: Start isDeterministic. Operand 13200 states and 18054 transitions.
[2024-11-08 18:32:42,794 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2024-11-08 18:32:42,794 INFO L218 hiAutomatonCegarLoop]: Abstraction has 13200 states and 18054 transitions.
[2024-11-08 18:32:42,804 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13200 states and 18054 transitions.
[2024-11-08 18:32:43,069 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13200 to 13200.
[2024-11-08 18:32:43,083 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13200 states, 13200 states have (on average 1.3677272727272727) internal successors, (18054), 13199 states have internal predecessors, (18054), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 18:32:43,108 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13200 states to 13200 states and 18054 transitions.
[2024-11-08 18:32:43,108 INFO L240 hiAutomatonCegarLoop]: Abstraction has 13200 states and 18054 transitions.
[2024-11-08 18:32:43,108 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states.
[2024-11-08 18:32:43,109 INFO L425 stractBuchiCegarLoop]: Abstraction has 13200 states and 18054 transitions.
[2024-11-08 18:32:43,109 INFO L332 stractBuchiCegarLoop]: ======== Iteration 26 ============
[2024-11-08 18:32:43,109 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 13200 states and 18054 transitions.
[2024-11-08 18:32:43,150 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 13012
[2024-11-08 18:32:43,150 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2024-11-08 18:32:43,150 INFO L119 BuchiIsEmpty]: Starting construction of run
[2024-11-08 18:32:43,151 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 18:32:43,152 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 18:32:43,152 INFO L745 eck$LassoCheckResult]: Stem: 372574#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 372575#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 373150#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 373151#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 373188#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 373171#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 373172#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 372725#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 372726#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 372793#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 372636#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 372637#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 372604#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 372605#L754 assume !(0 == ~M_E~0); 373204#L754-2 assume !(0 == ~T1_E~0); 373108#L759-1 assume !(0 == ~T2_E~0); 372973#L764-1 assume !(0 == ~T3_E~0); 372927#L769-1 assume !(0 == ~T4_E~0); 372928#L774-1 assume !(0 == ~T5_E~0); 372974#L779-1 assume !(0 == ~T6_E~0); 373118#L784-1 assume !(0 == ~T7_E~0); 372924#L789-1 assume !(0 == ~E_1~0); 372925#L794-1 assume !(0 == ~E_2~0); 373024#L799-1 assume !(0 == ~E_3~0); 372935#L804-1 assume !(0 == ~E_4~0); 372936#L809-1 assume !(0 == ~E_5~0); 372968#L814-1 assume !(0 == ~E_6~0); 372384#L819-1 assume !(0 == ~E_7~0); 372385#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 372633#L361 assume !(1 == ~m_pc~0); 372634#L361-2 is_master_triggered_~__retres1~0#1 := 0; 373146#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 373096#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 373097#L930 assume !(0 != activate_threads_~tmp~1#1); 372836#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 372627#L380 assume !(1 == ~t1_pc~0); 372628#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 373184#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 373185#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 373222#L938 assume !(0 != activate_threads_~tmp___0~0#1); 373055#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 373034#L399 assume !(1 == ~t2_pc~0); 372545#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 372546#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 372706#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 372699#L946 assume !(0 != activate_threads_~tmp___1~0#1); 372700#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 372388#L418 assume !(1 == ~t3_pc~0); 372367#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 372368#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 372378#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 372379#L954 assume !(0 != activate_threads_~tmp___2~0#1); 372953#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 372954#L437 assume !(1 == ~t4_pc~0); 373173#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 373091#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 372460#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 372461#L962 assume !(0 != activate_threads_~tmp___3~0#1); 372753#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 373078#L456 assume !(1 == ~t5_pc~0); 372560#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 372559#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 373100#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 373011#L970 assume !(0 != activate_threads_~tmp___4~0#1); 373012#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 372452#L475 assume !(1 == ~t6_pc~0); 372453#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 372495#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 372496#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 372692#L978 assume !(0 != activate_threads_~tmp___5~0#1); 372940#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 372941#L494 assume !(1 == ~t7_pc~0); 372676#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 372677#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 372895#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 372975#L986 assume !(0 != activate_threads_~tmp___6~0#1); 372976#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 373198#L837 assume !(1 == ~M_E~0); 373149#L837-2 assume !(1 == ~T1_E~0); 373030#L842-1 assume !(1 == ~T2_E~0); 372760#L847-1 assume !(1 == ~T3_E~0); 372761#L852-1 assume !(1 == ~T4_E~0); 372826#L857-1 assume !(1 == ~T5_E~0); 372712#L862-1 assume !(1 == ~T6_E~0); 372713#L867-1 assume !(1 == ~T7_E~0); 372721#L872-1 assume !(1 == ~E_1~0); 372792#L877-1 assume !(1 == ~E_2~0); 372994#L882-1 assume !(1 == ~E_3~0); 373156#L887-1 assume !(1 == ~E_4~0); 373049#L892-1 assume !(1 == ~E_5~0); 373050#L897-1 assume !(1 == ~E_6~0); 372737#L902-1 assume !(1 == ~E_7~0); 372738#L907-1 assume { :end_inline_reset_delta_events } true; 373073#L1148-2
[2024-11-08 18:32:43,152 INFO L747 eck$LassoCheckResult]: Loop: 373073#L1148-2 assume !false; 376383#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 376381#L729-1 assume !false; 376380#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 376140#L569 assume !(0 == ~m_st~0); 376141#L573 assume !(0 == ~t1_st~0); 376146#L577 assume !(0 == ~t2_st~0); 376148#L581 assume !(0 == ~t3_st~0); 376144#L585 assume !(0 == ~t4_st~0); 376145#L589 assume !(0 == ~t5_st~0); 376147#L593 assume !(0 == ~t6_st~0); 376142#L597 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8#1 := 0; 376143#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 376125#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 376126#L626 assume !(0 != eval_~tmp~0#1); 377019#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 377015#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 377012#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 377011#L754-5 assume !(0 == ~T1_E~0); 377010#L759-3 assume !(0 == ~T2_E~0); 377007#L764-3 assume !(0 == ~T3_E~0); 377006#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 377005#L774-3 assume !(0 == ~T5_E~0); 377003#L779-3 assume !(0 == ~T6_E~0); 376977#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 376619#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 376615#L794-3 assume !(0 == ~E_2~0); 376613#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 376611#L804-3 assume !(0 == ~E_4~0); 376609#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 376606#L814-3 assume !(0 == ~E_6~0); 376604#L819-3 assume !(0 == ~E_7~0); 376602#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 376600#L361-24 assume !(1 == ~m_pc~0); 376598#L361-26 is_master_triggered_~__retres1~0#1 := 0; 376596#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 376594#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 376592#L930-24 assume !(0 != activate_threads_~tmp~1#1); 376590#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 376587#L380-24 assume !(1 == ~t1_pc~0); 376585#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 376850#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 376846#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 376577#L938-24 assume !(0 != activate_threads_~tmp___0~0#1); 376573#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 376571#L399-24 assume !(1 == ~t2_pc~0); 376569#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 376567#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 376565#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 376563#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 376560#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 376558#L418-24 assume 1 == ~t3_pc~0; 376553#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 376550#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 376548#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 376546#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 376544#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 376542#L437-24 assume !(1 == ~t4_pc~0); 376540#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 376537#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 376535#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 376533#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 376531#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 376529#L456-24 assume 1 == ~t5_pc~0; 376527#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 376524#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 376522#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 376520#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 376518#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 376516#L475-24 assume !(1 == ~t6_pc~0); 376514#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 376511#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 376509#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 376507#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 376505#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 376503#L494-24 assume !(1 == ~t7_pc~0); 376500#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 376498#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 376496#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 376494#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 376492#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 376490#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 376487#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 376485#L842-3 assume !(1 == ~T2_E~0); 376483#L847-3 assume !(1 == ~T3_E~0); 376481#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 376479#L857-3 assume !(1 == ~T5_E~0); 376477#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 376475#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 376473#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 376471#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 376469#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 376467#L887-3 assume !(1 == ~E_4~0); 376465#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 376463#L897-3 assume !(1 == ~E_6~0); 376461#L902-3 assume !(1 == ~E_7~0); 376459#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 376453#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 376445#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 376443#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 376441#L1167 assume !(0 == start_simulation_~tmp~3#1); 376439#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 376435#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 376429#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 376427#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 376426#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 376424#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 376423#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 376422#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 373073#L1148-2
[2024-11-08 18:32:43,152 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 18:32:43,153 INFO L85 PathProgramCache]: Analyzing trace with hash 1968536774, now seen corresponding path program 6 times
[2024-11-08 18:32:43,153 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 18:32:43,153 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1801476243]
[2024-11-08 18:32:43,153 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 18:32:43,153 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 18:32:43,168 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-11-08 18:32:43,168 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2024-11-08 18:32:43,175 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-11-08 18:32:43,192 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2024-11-08 18:32:43,193 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 18:32:43,193 INFO L85 PathProgramCache]: Analyzing trace with hash -899749365, now seen corresponding path program 1 times
[2024-11-08 18:32:43,193 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 18:32:43,193 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [560075884]
[2024-11-08 18:32:43,194 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 18:32:43,194 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 18:32:43,208 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-11-08 18:32:43,246 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2024-11-08 18:32:43,246 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2024-11-08 18:32:43,246 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [560075884]
[2024-11-08 18:32:43,247 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [560075884] provided 1 perfect and 0 imperfect interpolant sequences
[2024-11-08 18:32:43,247 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2024-11-08 18:32:43,247 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2024-11-08 18:32:43,247 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1517410533]
[2024-11-08 18:32:43,248 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2024-11-08 18:32:43,248 INFO L762 eck$LassoCheckResult]: loop already infeasible
[2024-11-08 18:32:43,248 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2024-11-08 18:32:43,249 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2024-11-08 18:32:43,249 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2024-11-08 18:32:43,249 INFO L87 Difference]: Start difference. First operand 13200 states and 18054 transitions. cyclomatic complexity: 4870 Second operand has 3 states, 3 states have (on average 36.333333333333336) internal successors, (109), 3 states have internal predecessors, (109), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 18:32:43,376 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2024-11-08 18:32:43,376 INFO L93 Difference]: Finished difference Result 23284 states and 31490 transitions.
[2024-11-08 18:32:43,376 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 23284 states and 31490 transitions.
[2024-11-08 18:32:43,469 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 23030
[2024-11-08 18:32:43,538 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 23284 states to 23284 states and 31490 transitions.
[2024-11-08 18:32:43,539 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 23284
[2024-11-08 18:32:43,554 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 23284
[2024-11-08 18:32:43,554 INFO L73 IsDeterministic]: Start isDeterministic. Operand 23284 states and 31490 transitions.
[2024-11-08 18:32:43,574 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2024-11-08 18:32:43,574 INFO L218 hiAutomatonCegarLoop]: Abstraction has 23284 states and 31490 transitions.
[2024-11-08 18:32:43,589 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23284 states and 31490 transitions.
[2024-11-08 18:32:43,949 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23284 to 22628.
[2024-11-08 18:32:43,967 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 22628 states, 22628 states have (on average 1.3538978257026693) internal successors, (30636), 22627 states have internal predecessors, (30636), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 18:32:44,006 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22628 states to 22628 states and 30636 transitions.
[2024-11-08 18:32:44,006 INFO L240 hiAutomatonCegarLoop]: Abstraction has 22628 states and 30636 transitions.
[2024-11-08 18:32:44,007 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states.
[2024-11-08 18:32:44,007 INFO L425 stractBuchiCegarLoop]: Abstraction has 22628 states and 30636 transitions.
[2024-11-08 18:32:44,007 INFO L332 stractBuchiCegarLoop]: ======== Iteration 27 ============
[2024-11-08 18:32:44,007 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 22628 states and 30636 transitions.
[2024-11-08 18:32:44,069 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 22374
[2024-11-08 18:32:44,070 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2024-11-08 18:32:44,070 INFO L119 BuchiIsEmpty]: Starting construction of run
[2024-11-08 18:32:44,071 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 18:32:44,071 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 18:32:44,072 INFO L745 eck$LassoCheckResult]: Stem: 409062#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 409063#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 409646#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 409647#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 409686#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 409671#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 409672#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 409216#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 409217#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 409286#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 409127#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 409128#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 409094#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 409095#L754 assume !(0 == ~M_E~0); 409702#L754-2 assume !(0 == ~T1_E~0); 409598#L759-1 assume !(0 == ~T2_E~0); 409464#L764-1 assume !(0 == ~T3_E~0); 409423#L769-1 assume !(0 == ~T4_E~0); 409424#L774-1 assume !(0 == ~T5_E~0); 409465#L779-1 assume !(0 == ~T6_E~0); 409609#L784-1 assume !(0 == ~T7_E~0); 409420#L789-1 assume !(0 == ~E_1~0); 409421#L794-1 assume !(0 == ~E_2~0); 409514#L799-1 assume !(0 == ~E_3~0); 409431#L804-1 assume !(0 == ~E_4~0); 409432#L809-1 assume !(0 == ~E_5~0); 409459#L814-1 assume !(0 == ~E_6~0); 408874#L819-1 assume !(0 == ~E_7~0); 408875#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 409124#L361 assume !(1 == ~m_pc~0); 409125#L361-2 is_master_triggered_~__retres1~0#1 := 0; 409641#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 409585#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 409586#L930 assume !(0 != activate_threads_~tmp~1#1); 409330#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 409118#L380 assume !(1 == ~t1_pc~0); 409119#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 409682#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 409683#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 409728#L938 assume !(0 != activate_threads_~tmp___0~0#1); 409544#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 409524#L399 assume !(1 == ~t2_pc~0); 409033#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 409034#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 409197#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 409190#L946 assume !(0 != activate_threads_~tmp___1~0#1); 409191#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 408878#L418 assume !(1 == ~t3_pc~0); 408857#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 408858#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 408868#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 408869#L954 assume !(0 != activate_threads_~tmp___2~0#1); 409445#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 409446#L437 assume !(1 == ~t4_pc~0); 409673#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 409580#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 408949#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 408950#L962 assume !(0 != activate_threads_~tmp___3~0#1); 409246#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 409565#L456 assume !(1 == ~t5_pc~0); 409048#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 409047#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 409589#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 409501#L970 assume !(0 != activate_threads_~tmp___4~0#1); 409502#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 408942#L475 assume !(1 == ~t6_pc~0); 408943#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 408983#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 408984#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 409183#L978 assume !(0 != activate_threads_~tmp___5~0#1); 409436#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 409437#L494 assume !(1 == ~t7_pc~0); 409167#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 409168#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 409391#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 409466#L986 assume !(0 != activate_threads_~tmp___6~0#1); 409467#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 409697#L837 assume !(1 == ~M_E~0); 409645#L837-2 assume !(1 == ~T1_E~0); 409520#L842-1 assume !(1 == ~T2_E~0); 409253#L847-1 assume !(1 == ~T3_E~0); 409254#L852-1 assume !(1 == ~T4_E~0); 409320#L857-1 assume !(1 == ~T5_E~0); 409203#L862-1 assume !(1 == ~T6_E~0); 409204#L867-1 assume !(1 == ~T7_E~0); 409212#L872-1 assume !(1 == ~E_1~0); 409285#L877-1 assume !(1 == ~E_2~0); 409483#L882-1 assume !(1 == ~E_3~0); 409652#L887-1 assume !(1 == ~E_4~0); 409538#L892-1 assume !(1 == ~E_5~0); 409539#L897-1 assume !(1 == ~E_6~0); 409230#L902-1 assume !(1 == ~E_7~0); 409231#L907-1 assume { :end_inline_reset_delta_events } true; 409560#L1148-2 assume !false; 423074#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 423072#L729-1
[2024-11-08 18:32:44,072 INFO L747 eck$LassoCheckResult]: Loop: 423072#L729-1 assume !false; 423070#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 423067#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 423064#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 423062#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 423058#L626 assume 0 != eval_~tmp~0#1; 423055#L626-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 423052#L634 assume !(0 != eval_~tmp_ndt_1~0#1); 423051#L634-2 havoc eval_~tmp_ndt_1~0#1; 423046#L631-1 assume !(0 == ~t1_st~0); 423044#L645-1 assume !(0 == ~t2_st~0); 423045#L659-1 assume !(0 == ~t3_st~0); 423315#L673-1 assume !(0 == ~t4_st~0); 423304#L687-1 assume !(0 == ~t5_st~0); 423296#L701-1 assume !(0 == ~t6_st~0); 423076#L715-1 assume !(0 == ~t7_st~0); 423072#L729-1
[2024-11-08 18:32:44,073 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 18:32:44,073 INFO L85 PathProgramCache]: Analyzing trace with hash 1978243432, now seen corresponding path program 1 times
[2024-11-08 18:32:44,073 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 18:32:44,073 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [174096199]
[2024-11-08 18:32:44,074 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 18:32:44,074 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 18:32:44,089 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-11-08 18:32:44,090 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2024-11-08 18:32:44,097 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-11-08 18:32:44,117 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2024-11-08 18:32:44,117 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 18:32:44,118 INFO L85 PathProgramCache]: Analyzing trace with hash 1530346669, now seen corresponding path program 1 times
[2024-11-08 18:32:44,118 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 18:32:44,118 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1760417813]
[2024-11-08 18:32:44,118 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 18:32:44,118 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 18:32:44,123 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-11-08 18:32:44,123 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2024-11-08 18:32:44,125 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-11-08 18:32:44,126 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2024-11-08 18:32:44,127 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 18:32:44,128 INFO L85 PathProgramCache]: Analyzing trace with hash -651745260, now seen corresponding path program 1 times
[2024-11-08 18:32:44,128 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 18:32:44,128 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1479890739]
[2024-11-08 18:32:44,128 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 18:32:44,128 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 18:32:44,142 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-11-08 18:32:44,181 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2024-11-08 18:32:44,181 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2024-11-08 18:32:44,181 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1479890739]
[2024-11-08 18:32:44,181 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1479890739] provided 1 perfect and 0 imperfect interpolant sequences
[2024-11-08 18:32:44,181 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2024-11-08 18:32:44,182 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2024-11-08 18:32:44,182 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1205007186]
[2024-11-08 18:32:44,182 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2024-11-08 18:32:44,318 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2024-11-08 18:32:44,319 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2024-11-08 18:32:44,319 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2024-11-08 18:32:44,319 INFO L87 Difference]: Start difference. First operand 22628 states and 30636 transitions. cyclomatic complexity: 8032 Second operand has 3 states, 3 states have (on average 37.0) internal successors, (111), 3 states have internal predecessors, (111), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 18:32:44,489 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2024-11-08 18:32:44,489 INFO L93 Difference]: Finished difference Result 42778 states and 57617 transitions.
[2024-11-08 18:32:44,490 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 42778 states and 57617 transitions.
[2024-11-08 18:32:44,648 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 42276
[2024-11-08 18:32:44,756 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 42778 states to 42778 states and 57617 transitions.
[2024-11-08 18:32:44,757 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 42778
[2024-11-08 18:32:44,784 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 42778
[2024-11-08 18:32:44,784 INFO L73 IsDeterministic]: Start isDeterministic. Operand 42778 states and 57617 transitions.
[2024-11-08 18:32:45,085 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2024-11-08 18:32:45,089 INFO L218 hiAutomatonCegarLoop]: Abstraction has 42778 states and 57617 transitions.
[2024-11-08 18:32:45,141 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 42778 states and 57617 transitions.
[2024-11-08 18:32:45,455 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 42778 to 40634.
[2024-11-08 18:32:45,497 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 40634 states, 40634 states have (on average 1.3492395530836245) internal successors, (54825), 40633 states have internal predecessors, (54825), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 18:32:45,566 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40634 states to 40634 states and 54825 transitions.
[2024-11-08 18:32:45,566 INFO L240 hiAutomatonCegarLoop]: Abstraction has 40634 states and 54825 transitions.
[2024-11-08 18:32:45,567 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states.
[2024-11-08 18:32:45,567 INFO L425 stractBuchiCegarLoop]: Abstraction has 40634 states and 54825 transitions.
[2024-11-08 18:32:45,567 INFO L332 stractBuchiCegarLoop]: ======== Iteration 28 ============
[2024-11-08 18:32:45,567 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 40634 states and 54825 transitions.
[2024-11-08 18:32:45,685 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 40132
[2024-11-08 18:32:45,685 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2024-11-08 18:32:45,685 INFO L119 BuchiIsEmpty]: Starting construction of run
[2024-11-08 18:32:45,686 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 18:32:45,687 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 18:32:45,687 INFO L745 eck$LassoCheckResult]: Stem: 474480#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 474481#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 475102#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 475103#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 475153#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 475133#L521-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 475134#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 474639#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 474640#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 474711#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 474548#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 474549#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 474512#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 474513#L754 assume !(0 == ~M_E~0); 475169#L754-2 assume !(0 == ~T1_E~0); 475047#L759-1 assume !(0 == ~T2_E~0); 474899#L764-1 assume !(0 == ~T3_E~0); 474855#L769-1 assume !(0 == ~T4_E~0); 474856#L774-1 assume !(0 == ~T5_E~0); 474900#L779-1 assume !(0 == ~T6_E~0); 475060#L784-1 assume !(0 == ~T7_E~0); 474852#L789-1 assume !(0 == ~E_1~0); 474853#L794-1 assume !(0 == ~E_2~0); 474952#L799-1 assume !(0 == ~E_3~0); 474864#L804-1 assume !(0 == ~E_4~0); 474865#L809-1 assume !(0 == ~E_5~0); 474893#L814-1 assume !(0 == ~E_6~0); 474288#L819-1 assume !(0 == ~E_7~0); 474289#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 474543#L361 assume !(1 == ~m_pc~0); 474544#L361-2 is_master_triggered_~__retres1~0#1 := 0; 475095#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 475034#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 475035#L930 assume !(0 != activate_threads_~tmp~1#1); 474756#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 474536#L380 assume !(1 == ~t1_pc~0); 474537#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 475148#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 475149#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 486832#L938 assume !(0 != activate_threads_~tmp___0~0#1); 486831#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 486830#L399 assume !(1 == ~t2_pc~0); 486829#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 486828#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 486827#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 486826#L946 assume !(0 != activate_threads_~tmp___1~0#1); 486825#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 486824#L418 assume !(1 == ~t3_pc~0); 486822#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 486821#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 486820#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 486819#L954 assume !(0 != activate_threads_~tmp___2~0#1); 486818#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 486817#L437 assume !(1 == ~t4_pc~0); 486816#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 486815#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 486814#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 486813#L962 assume !(0 != activate_threads_~tmp___3~0#1); 486812#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 486811#L456 assume !(1 == ~t5_pc~0); 486809#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 486808#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 486807#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 486806#L970 assume !(0 != activate_threads_~tmp___4~0#1); 486805#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 486804#L475 assume !(1 == ~t6_pc~0); 486803#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 486802#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 486801#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 486800#L978 assume !(0 != activate_threads_~tmp___5~0#1); 486799#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 486798#L494 assume !(1 == ~t7_pc~0); 486796#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 486795#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 486794#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 486793#L986 assume !(0 != activate_threads_~tmp___6~0#1); 486792#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 486791#L837 assume !(1 == ~M_E~0); 486790#L837-2 assume !(1 == ~T1_E~0); 486789#L842-1 assume !(1 == ~T2_E~0); 486788#L847-1 assume !(1 == ~T3_E~0); 486787#L852-1 assume !(1 == ~T4_E~0); 486786#L857-1 assume !(1 == ~T5_E~0); 486785#L862-1 assume !(1 == ~T6_E~0); 486784#L867-1 assume !(1 == ~T7_E~0); 486783#L872-1 assume !(1 == ~E_1~0); 486782#L877-1 assume !(1 == ~E_2~0); 486781#L882-1 assume !(1 == ~E_3~0); 486780#L887-1 assume !(1 == ~E_4~0); 486779#L892-1 assume !(1 == ~E_5~0); 486778#L897-1 assume !(1 == ~E_6~0); 486777#L902-1 assume !(1 == ~E_7~0); 486776#L907-1 assume { :end_inline_reset_delta_events } true; 486774#L1148-2 assume !false; 486679#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 486677#L729-1
[2024-11-08 18:32:45,687 INFO L747 eck$LassoCheckResult]: Loop: 486677#L729-1 assume !false; 486675#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 486673#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 486671#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 486669#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 486668#L626 assume 0 != eval_~tmp~0#1; 486665#L626-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 486663#L634 assume !(0 != eval_~tmp_ndt_1~0#1); 486661#L634-2 havoc eval_~tmp_ndt_1~0#1; 486658#L631-1 assume !(0 == ~t1_st~0); 486656#L645-1 assume !(0 == ~t2_st~0); 486652#L659-1 assume !(0 == ~t3_st~0); 486647#L673-1 assume !(0 == ~t4_st~0); 486643#L687-1 assume !(0 == ~t5_st~0); 486644#L701-1 assume !(0 == ~t6_st~0); 486681#L715-1 assume !(0 == ~t7_st~0); 486677#L729-1
[2024-11-08 18:32:45,688 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 18:32:45,688 INFO L85 PathProgramCache]: Analyzing trace with hash -439660634, now seen corresponding path program 1 times
[2024-11-08 18:32:45,688 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 18:32:45,688 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2074484633]
[2024-11-08 18:32:45,688 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 18:32:45,689 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 18:32:45,699 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-11-08 18:32:45,718 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2024-11-08 18:32:45,718 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2024-11-08 18:32:45,719 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2074484633]
[2024-11-08 18:32:45,719 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2074484633] provided 1 perfect and 0 imperfect interpolant sequences
[2024-11-08 18:32:45,719 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2024-11-08 18:32:45,719 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2024-11-08 18:32:45,719 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [28858882]
[2024-11-08 18:32:45,719 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2024-11-08 18:32:45,720 INFO L750 eck$LassoCheckResult]: stem already infeasible
[2024-11-08 18:32:45,720 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 18:32:45,720 INFO L85 PathProgramCache]: Analyzing trace with hash 1530346669, now seen corresponding path program 2 times
[2024-11-08 18:32:45,720 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 18:32:45,721 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2058629790]
[2024-11-08 18:32:45,721 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 18:32:45,721 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 18:32:45,724 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-11-08 18:32:45,724 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2024-11-08 18:32:45,726 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-11-08 18:32:45,728 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2024-11-08 18:32:45,832 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2024-11-08 18:32:45,833 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2024-11-08 18:32:45,833 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2024-11-08 18:32:45,833 INFO L87 Difference]: Start difference. First operand 40634 states and 54825 transitions. cyclomatic complexity: 14215 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 18:32:46,305 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2024-11-08 18:32:46,306 INFO L93 Difference]: Finished difference Result 40538 states and 54695 transitions.
[2024-11-08 18:32:46,306 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 40538 states and 54695 transitions.
[2024-11-08 18:32:46,493 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 40132
[2024-11-08 18:32:46,626 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 40538 states to 40538 states and 54695 transitions.
[2024-11-08 18:32:46,626 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 40538
[2024-11-08 18:32:46,653 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 40538
[2024-11-08 18:32:46,654 INFO L73 IsDeterministic]: Start isDeterministic. Operand 40538 states and 54695 transitions.
[2024-11-08 18:32:46,719 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2024-11-08 18:32:46,719 INFO L218 hiAutomatonCegarLoop]: Abstraction has 40538 states and 54695 transitions.
[2024-11-08 18:32:46,749 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40538 states and 54695 transitions.
[2024-11-08 18:32:47,199 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40538 to 40538.
[2024-11-08 18:32:47,238 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 40538 states, 40538 states have (on average 1.3492278849474566) internal successors, (54695), 40537 states have internal predecessors, (54695), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 18:32:47,338 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40538 states to 40538 states and 54695 transitions.
[2024-11-08 18:32:47,338 INFO L240 hiAutomatonCegarLoop]: Abstraction has 40538 states and 54695 transitions.
[2024-11-08 18:32:47,339 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states.
[2024-11-08 18:32:47,343 INFO L425 stractBuchiCegarLoop]: Abstraction has 40538 states and 54695 transitions.
[2024-11-08 18:32:47,343 INFO L332 stractBuchiCegarLoop]: ======== Iteration 29 ============
[2024-11-08 18:32:47,344 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 40538 states and 54695 transitions.
[2024-11-08 18:32:47,490 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 40132
[2024-11-08 18:32:47,490 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2024-11-08 18:32:47,490 INFO L119 BuchiIsEmpty]: Starting construction of run
[2024-11-08 18:32:47,491 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 18:32:47,492 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 18:32:47,492 INFO L745 eck$LassoCheckResult]: Stem: 555660#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 555661#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 556261#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 556262#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 556311#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 556289#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 556290#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 555815#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 555816#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 555888#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 555723#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 555724#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 555690#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 555691#L754 assume !(0 == ~M_E~0); 556326#L754-2 assume !(0 == ~T1_E~0); 556211#L759-1 assume !(0 == ~T2_E~0); 556077#L764-1 assume !(0 == ~T3_E~0); 556032#L769-1 assume !(0 == ~T4_E~0); 556033#L774-1 assume !(0 == ~T5_E~0); 556078#L779-1 assume !(0 == ~T6_E~0); 556222#L784-1 assume !(0 == ~T7_E~0); 556029#L789-1 assume !(0 == ~E_1~0); 556030#L794-1 assume !(0 == ~E_2~0); 556126#L799-1 assume !(0 == ~E_3~0); 556040#L804-1 assume !(0 == ~E_4~0); 556041#L809-1 assume !(0 == ~E_5~0); 556072#L814-1 assume !(0 == ~E_6~0); 555466#L819-1 assume !(0 == ~E_7~0); 555467#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 555720#L361 assume !(1 == ~m_pc~0); 555721#L361-2 is_master_triggered_~__retres1~0#1 := 0; 556254#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 556199#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 556200#L930 assume !(0 != activate_threads_~tmp~1#1); 555936#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 555714#L380 assume !(1 == ~t1_pc~0); 555715#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 556308#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 556309#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 556355#L938 assume !(0 != activate_threads_~tmp___0~0#1); 556158#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 556136#L399 assume !(1 == ~t2_pc~0); 555628#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 555629#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 555795#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 555788#L946 assume !(0 != activate_threads_~tmp___1~0#1); 555789#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 555470#L418 assume !(1 == ~t3_pc~0); 555449#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 555450#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 555460#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 555461#L954 assume !(0 != activate_threads_~tmp___2~0#1); 556055#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 556056#L437 assume !(1 == ~t4_pc~0); 556291#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 556195#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 555543#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 555544#L962 assume !(0 != activate_threads_~tmp___3~0#1); 555845#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 556181#L456 assume !(1 == ~t5_pc~0); 555644#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 555643#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 556203#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 556112#L970 assume !(0 != activate_threads_~tmp___4~0#1); 556113#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 555536#L475 assume !(1 == ~t6_pc~0); 555537#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 555577#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 555578#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 555781#L978 assume !(0 != activate_threads_~tmp___5~0#1); 556046#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 556047#L494 assume !(1 == ~t7_pc~0); 555765#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 555766#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 555999#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 556079#L986 assume !(0 != activate_threads_~tmp___6~0#1); 556080#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 556321#L837 assume !(1 == ~M_E~0); 556260#L837-2 assume !(1 == ~T1_E~0); 556132#L842-1 assume !(1 == ~T2_E~0); 555854#L847-1 assume !(1 == ~T3_E~0); 555855#L852-1 assume !(1 == ~T4_E~0); 555924#L857-1 assume !(1 == ~T5_E~0); 555801#L862-1 assume !(1 == ~T6_E~0); 555802#L867-1 assume !(1 == ~T7_E~0); 555811#L872-1 assume !(1 == ~E_1~0); 555887#L877-1 assume !(1 == ~E_2~0); 556095#L882-1 assume !(1 == ~E_3~0); 556267#L887-1 assume !(1 == ~E_4~0); 556151#L892-1 assume !(1 == ~E_5~0); 556152#L897-1 assume !(1 == ~E_6~0); 555829#L902-1 assume !(1 == ~E_7~0); 555830#L907-1 assume { :end_inline_reset_delta_events } true; 556176#L1148-2 assume !false; 561349#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 561347#L729-1
[2024-11-08 18:32:47,492 INFO L747 eck$LassoCheckResult]: Loop: 561347#L729-1 assume !false; 561345#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 561342#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 561340#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 561337#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 561335#L626 assume 0 != eval_~tmp~0#1; 561332#L626-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 561327#L634 assume !(0 != eval_~tmp_ndt_1~0#1); 561328#L634-2 havoc eval_~tmp_ndt_1~0#1; 562206#L631-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 561282#L648 assume !(0 != eval_~tmp_ndt_2~0#1); 562198#L648-2 havoc eval_~tmp_ndt_2~0#1; 562861#L645-1 assume !(0 == ~t2_st~0); 562857#L659-1 assume !(0 == ~t3_st~0); 557372#L673-1 assume !(0 == ~t4_st~0); 557368#L687-1 assume !(0 == ~t5_st~0); 557365#L701-1 assume !(0 == ~t6_st~0); 557366#L715-1 assume !(0 == ~t7_st~0); 561347#L729-1
[2024-11-08 18:32:47,493 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 18:32:47,493 INFO L85 PathProgramCache]: Analyzing trace with hash 1978243432, now seen corresponding path program 2 times
[2024-11-08 18:32:47,493 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 18:32:47,493 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [234282571]
[2024-11-08 18:32:47,494 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 18:32:47,494 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 18:32:47,778 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-11-08 18:32:47,778 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2024-11-08 18:32:47,785 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-11-08 18:32:47,802 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2024-11-08 18:32:47,803 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 18:32:47,803 INFO L85 PathProgramCache]: Analyzing trace with hash 737007248, now seen corresponding path program 1 times
[2024-11-08 18:32:47,803 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 18:32:47,803 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1650936492]
[2024-11-08 18:32:47,803 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 18:32:47,803 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 18:32:47,807 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-11-08 18:32:47,808 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2024-11-08 18:32:47,810 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-11-08 18:32:47,813 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2024-11-08 18:32:47,813 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 18:32:47,813 INFO L85 PathProgramCache]: Analyzing trace with hash -309296073, now seen corresponding path program 1 times
[2024-11-08 18:32:47,813 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 18:32:47,814 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [931525821]
[2024-11-08 18:32:47,814 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 18:32:47,814 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 18:32:47,826 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-11-08 18:32:47,861 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2024-11-08 18:32:47,862 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2024-11-08 18:32:47,862 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [931525821]
[2024-11-08 18:32:47,862 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [931525821] provided 1 perfect and 0 imperfect interpolant sequences
[2024-11-08 18:32:47,863 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2024-11-08 18:32:47,863 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2024-11-08 18:32:47,863 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1484993827]
[2024-11-08 18:32:47,863 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2024-11-08 18:32:47,985 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2024-11-08 18:32:47,986 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2024-11-08 18:32:47,986 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2024-11-08 18:32:47,987 INFO L87 Difference]: Start difference. First operand 40538 states and 54695 transitions. cyclomatic complexity: 14181 Second operand has 3 states, 3 states have (on average 37.666666666666664) internal successors, (113), 3 states have internal predecessors, (113), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 18:32:48,221 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2024-11-08 18:32:48,221 INFO L93 Difference]: Finished difference Result 54760 states and 73511 transitions.
[2024-11-08 18:32:48,221 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 54760 states and 73511 transitions.
[2024-11-08 18:32:48,442 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 54250
[2024-11-08 18:32:48,547 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 54760 states to 54760 states and 73511 transitions.
[2024-11-08 18:32:48,547 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 54760
[2024-11-08 18:32:48,574 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 54760
[2024-11-08 18:32:48,575 INFO L73 IsDeterministic]: Start isDeterministic. Operand 54760 states and 73511 transitions.
[2024-11-08 18:32:48,599 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2024-11-08 18:32:48,599 INFO L218 hiAutomatonCegarLoop]: Abstraction has 54760 states and 73511 transitions.
[2024-11-08 18:32:48,634 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54760 states and 73511 transitions.
[2024-11-08 18:32:49,433 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54760 to 52928.
[2024-11-08 18:32:49,467 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 52928 states, 52928 states have (on average 1.3438444679564692) internal successors, (71127), 52927 states have internal predecessors, (71127), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 18:32:49,544 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 52928 states to 52928 states and 71127 transitions.
[2024-11-08 18:32:49,544 INFO L240 hiAutomatonCegarLoop]: Abstraction has 52928 states and 71127 transitions.
[2024-11-08 18:32:49,545 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states.
[2024-11-08 18:32:49,545 INFO L425 stractBuchiCegarLoop]: Abstraction has 52928 states and 71127 transitions.
[2024-11-08 18:32:49,546 INFO L332 stractBuchiCegarLoop]: ======== Iteration 30 ============
[2024-11-08 18:32:49,546 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 52928 states and 71127 transitions.
[2024-11-08 18:32:49,698 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 52418
[2024-11-08 18:32:49,698 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2024-11-08 18:32:49,698 INFO L119 BuchiIsEmpty]: Starting construction of run
[2024-11-08 18:32:49,699 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 18:32:49,699 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 18:32:49,699 INFO L745 eck$LassoCheckResult]: Stem: 650964#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 650965#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 651581#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 651582#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 651632#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 651611#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 651612#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 651122#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 651123#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 651190#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 651027#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 651028#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 650996#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 650997#L754 assume !(0 == ~M_E~0); 651649#L754-2 assume !(0 == ~T1_E~0); 651529#L759-1 assume !(0 == ~T2_E~0); 651380#L764-1 assume !(0 == ~T3_E~0); 651335#L769-1 assume !(0 == ~T4_E~0); 651336#L774-1 assume !(0 == ~T5_E~0); 651381#L779-1 assume !(0 == ~T6_E~0); 651538#L784-1 assume !(0 == ~T7_E~0); 651332#L789-1 assume !(0 == ~E_1~0); 651333#L794-1 assume !(0 == ~E_2~0); 651435#L799-1 assume !(0 == ~E_3~0); 651346#L804-1 assume !(0 == ~E_4~0); 651347#L809-1 assume !(0 == ~E_5~0); 651375#L814-1 assume !(0 == ~E_6~0); 650767#L819-1 assume !(0 == ~E_7~0); 650768#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 651025#L361 assume !(1 == ~m_pc~0); 651026#L361-2 is_master_triggered_~__retres1~0#1 := 0; 651576#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 651512#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 651513#L930 assume !(0 != activate_threads_~tmp~1#1); 651235#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 651019#L380 assume !(1 == ~t1_pc~0); 651020#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 651628#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 651629#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 651683#L938 assume !(0 != activate_threads_~tmp___0~0#1); 651466#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 651444#L399 assume !(1 == ~t2_pc~0); 650934#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 650935#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 651102#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 651094#L946 assume !(0 != activate_threads_~tmp___1~0#1); 651095#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 650775#L418 assume !(1 == ~t3_pc~0); 650755#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 650756#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 650765#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 650766#L954 assume !(0 != activate_threads_~tmp___2~0#1); 651362#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 651363#L437 assume !(1 == ~t4_pc~0); 651613#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 651506#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 650847#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 650848#L962 assume !(0 != activate_threads_~tmp___3~0#1); 651151#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 651489#L456 assume !(1 == ~t5_pc~0); 650948#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 650947#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 651518#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 651417#L970 assume !(0 != activate_threads_~tmp___4~0#1); 651418#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 650842#L475 assume !(1 == ~t6_pc~0); 650843#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 650884#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 650885#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 651087#L978 assume !(0 != activate_threads_~tmp___5~0#1); 651351#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 651352#L494 assume !(1 == ~t7_pc~0); 651070#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 651071#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 651302#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 651382#L986 assume !(0 != activate_threads_~tmp___6~0#1); 651383#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 651643#L837 assume !(1 == ~M_E~0); 651580#L837-2 assume !(1 == ~T1_E~0); 651440#L842-1 assume !(1 == ~T2_E~0); 651158#L847-1 assume !(1 == ~T3_E~0); 651159#L852-1 assume !(1 == ~T4_E~0); 651225#L857-1 assume !(1 == ~T5_E~0); 651108#L862-1 assume !(1 == ~T6_E~0); 651109#L867-1 assume !(1 == ~T7_E~0); 651117#L872-1 assume !(1 == ~E_1~0); 651189#L877-1 assume !(1 == ~E_2~0); 651398#L882-1 assume !(1 == ~E_3~0); 651589#L887-1 assume !(1 == ~E_4~0); 651460#L892-1 assume !(1 == ~E_5~0); 651461#L897-1 assume !(1 == ~E_6~0); 651133#L902-1 assume !(1 == ~E_7~0); 651134#L907-1 assume { :end_inline_reset_delta_events } true; 651488#L1148-2 assume !false; 662821#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 662822#L729-1
[2024-11-08 18:32:49,700 INFO L747 eck$LassoCheckResult]: Loop: 662822#L729-1 assume !false; 664368#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 664366#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 664365#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 664361#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 664359#L626 assume 0 != eval_~tmp~0#1; 664357#L626-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 664354#L634 assume !(0 != eval_~tmp_ndt_1~0#1); 664352#L634-2 havoc eval_~tmp_ndt_1~0#1; 662796#L631-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 662794#L648 assume !(0 != eval_~tmp_ndt_2~0#1); 662792#L648-2 havoc eval_~tmp_ndt_2~0#1; 662790#L645-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 662787#L662 assume !(0 != eval_~tmp_ndt_3~0#1); 662786#L662-2 havoc eval_~tmp_ndt_3~0#1; 662783#L659-1 assume !(0 == ~t3_st~0); 662779#L673-1 assume !(0 == ~t4_st~0); 662780#L687-1 assume !(0 == ~t5_st~0); 664373#L701-1 assume !(0 == ~t6_st~0); 664370#L715-1 assume !(0 == ~t7_st~0); 662822#L729-1
[2024-11-08 18:32:49,700 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 18:32:49,700 INFO L85 PathProgramCache]: Analyzing trace with hash 1978243432, now seen corresponding path program 3 times
[2024-11-08 18:32:49,700 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 18:32:49,700 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [571198234]
[2024-11-08 18:32:49,701 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 18:32:49,701 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 18:32:49,715 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-11-08 18:32:49,715 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2024-11-08 18:32:49,722 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-11-08 18:32:49,738 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2024-11-08 18:32:49,738 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 18:32:49,739 INFO L85 PathProgramCache]: Analyzing trace with hash -1963196563, now seen corresponding path program 1 times
[2024-11-08 18:32:49,739 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 18:32:49,739 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2115585351]
[2024-11-08 18:32:49,739 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 18:32:49,739 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 18:32:49,742 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-11-08 18:32:49,743 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2024-11-08 18:32:49,744 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-11-08 18:32:49,746 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2024-11-08 18:32:49,747 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 18:32:49,747 INFO L85 PathProgramCache]: Analyzing trace with hash 1856626516, now seen corresponding path program 1 times
[2024-11-08 18:32:49,747 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 18:32:49,747 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [562065927]
[2024-11-08 18:32:49,747 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 18:32:49,748 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 18:32:49,759 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-11-08 18:32:49,795 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2024-11-08 18:32:49,795 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2024-11-08 18:32:49,795 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [562065927]
[2024-11-08 18:32:49,795 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [562065927] provided 1 perfect and 0 imperfect interpolant sequences
[2024-11-08 18:32:49,796 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2024-11-08 18:32:49,796 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2024-11-08 18:32:49,796 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1880869581]
[2024-11-08 18:32:49,796 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2024-11-08 18:32:49,903 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2024-11-08 18:32:49,903 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2024-11-08 18:32:49,903 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2024-11-08 18:32:49,903 INFO L87 Difference]: Start difference. First operand 52928 states and 71127 transitions. cyclomatic complexity: 18223 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 18:32:50,215 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2024-11-08 18:32:50,216 INFO L93 Difference]: Finished difference Result 100634 states and 134827 transitions.
[2024-11-08 18:32:50,216 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 100634 states and 134827 transitions.
[2024-11-08 18:32:51,046 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 99716
[2024-11-08 18:32:51,221 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 100634 states to 100634 states and 134827 transitions.
[2024-11-08 18:32:51,221 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 100634
[2024-11-08 18:32:51,261 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 100634
[2024-11-08 18:32:51,262 INFO L73 IsDeterministic]: Start isDeterministic. Operand 100634 states and 134827 transitions.
[2024-11-08 18:32:51,297 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2024-11-08 18:32:51,297 INFO L218 hiAutomatonCegarLoop]: Abstraction has 100634 states and 134827 transitions.
[2024-11-08 18:32:51,337 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 100634 states and 134827 transitions.
[2024-11-08 18:32:52,333 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 100634 to 97658.
[2024-11-08 18:32:52,395 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 97658 states, 97658 states have (on average 1.3422658665956706) internal successors, (131083), 97657 states have internal predecessors, (131083), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 18:32:52,618 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 97658 states to 97658 states and 131083 transitions.
[2024-11-08 18:32:52,618 INFO L240 hiAutomatonCegarLoop]: Abstraction has 97658 states and 131083 transitions.
[2024-11-08 18:32:52,619 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states.
[2024-11-08 18:32:52,619 INFO L425 stractBuchiCegarLoop]: Abstraction has 97658 states and 131083 transitions.
[2024-11-08 18:32:52,620 INFO L332 stractBuchiCegarLoop]: ======== Iteration 31 ============
[2024-11-08 18:32:52,620 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 97658 states and 131083 transitions.
[2024-11-08 18:32:52,944 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 96740
[2024-11-08 18:32:52,944 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2024-11-08 18:32:52,944 INFO L119 BuchiIsEmpty]: Starting construction of run
[2024-11-08 18:32:52,945 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 18:32:52,946 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 18:32:52,946 INFO L745 eck$LassoCheckResult]: Stem: 804537#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 804538#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 805180#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 805181#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 805236#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 805211#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 805212#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 804695#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 804696#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 804770#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 804603#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 804604#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 804570#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 804571#L754 assume !(0 == ~M_E~0); 805261#L754-2 assume !(0 == ~T1_E~0); 805120#L759-1 assume !(0 == ~T2_E~0); 804970#L764-1 assume !(0 == ~T3_E~0); 804922#L769-1 assume !(0 == ~T4_E~0); 804923#L774-1 assume !(0 == ~T5_E~0); 804971#L779-1 assume !(0 == ~T6_E~0); 805133#L784-1 assume !(0 == ~T7_E~0); 804920#L789-1 assume !(0 == ~E_1~0); 804921#L794-1 assume !(0 == ~E_2~0); 805026#L799-1 assume !(0 == ~E_3~0); 804932#L804-1 assume !(0 == ~E_4~0); 804933#L809-1 assume !(0 == ~E_5~0); 804965#L814-1 assume !(0 == ~E_6~0); 804340#L819-1 assume !(0 == ~E_7~0); 804341#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 804600#L361 assume !(1 == ~m_pc~0); 804601#L361-2 is_master_triggered_~__retres1~0#1 := 0; 805171#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 805105#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 805106#L930 assume !(0 != activate_threads_~tmp~1#1); 804816#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 804594#L380 assume !(1 == ~t1_pc~0); 804595#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 805233#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 805234#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 805300#L938 assume !(0 != activate_threads_~tmp___0~0#1); 805058#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 805036#L399 assume !(1 == ~t2_pc~0); 804506#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 804507#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 804676#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 804667#L946 assume !(0 != activate_threads_~tmp___1~0#1); 804668#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 804346#L418 assume !(1 == ~t3_pc~0); 804325#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 804326#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 804336#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 804337#L954 assume !(0 != activate_threads_~tmp___2~0#1); 804948#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 804949#L437 assume !(1 == ~t4_pc~0); 805213#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 805099#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 804416#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 804417#L962 assume !(0 != activate_threads_~tmp___3~0#1); 804725#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 805080#L456 assume !(1 == ~t5_pc~0); 804522#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 804521#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 805110#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 805010#L970 assume !(0 != activate_threads_~tmp___4~0#1); 805011#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 804411#L475 assume !(1 == ~t6_pc~0); 804412#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 804454#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 804455#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 804660#L978 assume !(0 != activate_threads_~tmp___5~0#1); 804937#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 804938#L494 assume !(1 == ~t7_pc~0); 804644#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 804645#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 804886#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 804972#L986 assume !(0 != activate_threads_~tmp___6~0#1); 804973#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 805248#L837 assume !(1 == ~M_E~0); 805179#L837-2 assume !(1 == ~T1_E~0); 805032#L842-1 assume !(1 == ~T2_E~0); 804732#L847-1 assume !(1 == ~T3_E~0); 804733#L852-1 assume !(1 == ~T4_E~0); 804806#L857-1 assume !(1 == ~T5_E~0); 804682#L862-1 assume !(1 == ~T6_E~0); 804683#L867-1 assume !(1 == ~T7_E~0); 804690#L872-1 assume !(1 == ~E_1~0); 804769#L877-1 assume !(1 == ~E_2~0); 804988#L882-1 assume !(1 == ~E_3~0); 805187#L887-1 assume !(1 == ~E_4~0); 805052#L892-1 assume !(1 == ~E_5~0); 805053#L897-1 assume !(1 == ~E_6~0); 804708#L902-1 assume !(1 == ~E_7~0); 804709#L907-1 assume { :end_inline_reset_delta_events } true; 805077#L1148-2 assume !false; 816886#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 816884#L729-1
[2024-11-08 18:32:52,947 INFO L747 eck$LassoCheckResult]: Loop: 816884#L729-1 assume !false; 816882#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 816879#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 816877#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 816874#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 816872#L626 assume 0 != eval_~tmp~0#1; 816869#L626-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 816860#L634 assume !(0 != eval_~tmp_ndt_1~0#1); 816855#L634-2 havoc eval_~tmp_ndt_1~0#1; 816847#L631-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 816407#L648 assume !(0 != eval_~tmp_ndt_2~0#1); 816404#L648-2 havoc eval_~tmp_ndt_2~0#1; 816402#L645-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 816399#L662 assume !(0 != eval_~tmp_ndt_3~0#1); 816400#L662-2 havoc eval_~tmp_ndt_3~0#1; 816935#L659-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 816932#L676 assume !(0 != eval_~tmp_ndt_4~0#1); 816926#L676-2 havoc eval_~tmp_ndt_4~0#1; 816919#L673-1 assume !(0 == ~t4_st~0); 816902#L687-1 assume !(0 == ~t5_st~0); 816892#L701-1 assume !(0 == ~t6_st~0); 816888#L715-1 assume !(0 == ~t7_st~0); 816884#L729-1
[2024-11-08 18:32:52,947 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 18:32:52,948 INFO L85 PathProgramCache]: Analyzing trace with hash 1978243432, now seen corresponding path program 4 times
[2024-11-08 18:32:52,948 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 18:32:52,948 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [160225096]
[2024-11-08 18:32:52,948 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 18:32:52,949 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 18:32:52,968 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-11-08 18:32:52,969 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2024-11-08 18:32:52,980 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-11-08 18:32:52,999 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2024-11-08 18:32:53,000 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 18:32:53,000 INFO L85 PathProgramCache]: Analyzing trace with hash 55675408, now seen corresponding path program 1 times
[2024-11-08 18:32:53,001 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 18:32:53,002 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2036154758]
[2024-11-08 18:32:53,002 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 18:32:53,002 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 18:32:53,007 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-11-08 18:32:53,008 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2024-11-08 18:32:53,011 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-11-08 18:32:53,014 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2024-11-08 18:32:53,014 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 18:32:53,015 INFO L85 PathProgramCache]: Analyzing trace with hash -1291383753, now seen corresponding path program 1 times
[2024-11-08 18:32:53,015 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 18:32:53,015 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [535993036]
[2024-11-08 18:32:53,015 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 18:32:53,016 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 18:32:53,035 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-11-08 18:32:53,086 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2024-11-08 18:32:53,086 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2024-11-08 18:32:53,087 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [535993036]
[2024-11-08 18:32:53,087 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [535993036] provided 1 perfect and 0 imperfect interpolant sequences
[2024-11-08 18:32:53,087 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2024-11-08 18:32:53,087 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2024-11-08 18:32:53,087 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [929634841]
[2024-11-08 18:32:53,088 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2024-11-08 18:32:53,228 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2024-11-08 18:32:53,229 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2024-11-08 18:32:53,229 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2024-11-08 18:32:53,230 INFO L87 Difference]: Start difference. First operand 97658 states and 131083 transitions. cyclomatic complexity: 33449 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 18:32:54,290 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2024-11-08 18:32:54,291 INFO L93 Difference]: Finished difference Result 148314 states and 198503 transitions.
[2024-11-08 18:32:54,291 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 148314 states and 198503 transitions.
[2024-11-08 18:32:54,757 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 146980
[2024-11-08 18:32:55,032 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 148314 states to 148314 states and 198503 transitions.
[2024-11-08 18:32:55,032 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 148314
[2024-11-08 18:32:55,100 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 148314
[2024-11-08 18:32:55,100 INFO L73 IsDeterministic]: Start isDeterministic. Operand 148314 states and 198503 transitions.
[2024-11-08 18:32:55,818 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2024-11-08 18:32:55,818 INFO L218 hiAutomatonCegarLoop]: Abstraction has 148314 states and 198503 transitions.
[2024-11-08 18:32:55,888 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 148314 states and 198503 transitions.
[2024-11-08 18:32:57,245 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 148314 to 143610.
[2024-11-08 18:32:57,356 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 143610 states, 143610 states have (on average 1.3407910312652322) internal successors, (192551), 143609 states have internal predecessors, (192551), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 18:32:57,630 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 143610 states to 143610 states and 192551 transitions.
[2024-11-08 18:32:57,630 INFO L240 hiAutomatonCegarLoop]: Abstraction has 143610 states and 192551 transitions.
[2024-11-08 18:32:57,631 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states.
[2024-11-08 18:32:57,631 INFO L425 stractBuchiCegarLoop]: Abstraction has 143610 states and 192551 transitions.
[2024-11-08 18:32:57,631 INFO L332 stractBuchiCegarLoop]: ======== Iteration 32 ============
[2024-11-08 18:32:57,631 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 143610 states and 192551 transitions.
[2024-11-08 18:32:57,989 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 142276
[2024-11-08 18:32:57,989 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2024-11-08 18:32:57,989 INFO L119 BuchiIsEmpty]: Starting construction of run
[2024-11-08 18:32:57,990 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 18:32:57,990 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 18:32:57,990 INFO L745 eck$LassoCheckResult]: Stem: 1050516#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 1050517#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1051176#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1051177#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1051247#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 1051216#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1051217#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1050676#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1050677#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1050750#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1050583#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1050584#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1050550#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1050551#L754 assume !(0 == ~M_E~0); 1051276#L754-2 assume !(0 == ~T1_E~0); 1051120#L759-1 assume !(0 == ~T2_E~0); 1050960#L764-1 assume !(0 == ~T3_E~0); 1050911#L769-1 assume !(0 == ~T4_E~0); 1050912#L774-1 assume !(0 == ~T5_E~0); 1050961#L779-1 assume !(0 == ~T6_E~0); 1051132#L784-1 assume !(0 == ~T7_E~0); 1050908#L789-1 assume !(0 == ~E_1~0); 1050909#L794-1 assume !(0 == ~E_2~0); 1051017#L799-1 assume !(0 == ~E_3~0); 1050923#L804-1 assume !(0 == ~E_4~0); 1050924#L809-1 assume !(0 == ~E_5~0); 1050955#L814-1 assume !(0 == ~E_6~0); 1050317#L819-1 assume !(0 == ~E_7~0); 1050318#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1050581#L361 assume !(1 == ~m_pc~0); 1050582#L361-2 is_master_triggered_~__retres1~0#1 := 0; 1051169#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1051106#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1051107#L930 assume !(0 != activate_threads_~tmp~1#1); 1050804#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1050575#L380 assume !(1 == ~t1_pc~0); 1050576#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1051241#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1051242#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1051326#L938 assume !(0 != activate_threads_~tmp___0~0#1); 1051057#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1051028#L399 assume !(1 == ~t2_pc~0); 1050486#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1050487#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1050654#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1050648#L946 assume !(0 != activate_threads_~tmp___1~0#1); 1050649#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1050325#L418 assume !(1 == ~t3_pc~0); 1050305#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1050306#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1050315#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1050316#L954 assume !(0 != activate_threads_~tmp___2~0#1); 1050942#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1050943#L437 assume !(1 == ~t4_pc~0); 1051218#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1051101#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1050396#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1050397#L962 assume !(0 != activate_threads_~tmp___3~0#1); 1050707#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1051079#L456 assume !(1 == ~t5_pc~0); 1050502#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1050501#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1051111#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1050998#L970 assume !(0 != activate_threads_~tmp___4~0#1); 1050999#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1050391#L475 assume !(1 == ~t6_pc~0); 1050392#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1050434#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1050435#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1050640#L978 assume !(0 != activate_threads_~tmp___5~0#1); 1050930#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1050931#L494 assume !(1 == ~t7_pc~0); 1050624#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1050625#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1050877#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1050962#L986 assume !(0 != activate_threads_~tmp___6~0#1); 1050963#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1051263#L837 assume !(1 == ~M_E~0); 1051175#L837-2 assume !(1 == ~T1_E~0); 1051024#L842-1 assume !(1 == ~T2_E~0); 1050715#L847-1 assume !(1 == ~T3_E~0); 1050716#L852-1 assume !(1 == ~T4_E~0); 1050792#L857-1 assume !(1 == ~T5_E~0); 1050661#L862-1 assume !(1 == ~T6_E~0); 1050662#L867-1 assume !(1 == ~T7_E~0); 1050672#L872-1 assume !(1 == ~E_1~0); 1050749#L877-1 assume !(1 == ~E_2~0); 1050977#L882-1 assume !(1 == ~E_3~0); 1051188#L887-1 assume !(1 == ~E_4~0); 1051048#L892-1 assume !(1 == ~E_5~0); 1051049#L897-1 assume !(1 == ~E_6~0); 1050688#L902-1 assume !(1 == ~E_7~0); 1050689#L907-1 assume { :end_inline_reset_delta_events } true; 1051078#L1148-2 assume !false; 1108042#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1108040#L729-1
[2024-11-08 18:32:57,990 INFO L747 eck$LassoCheckResult]: Loop: 1108040#L729-1 assume !false; 1108039#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1108035#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1108034#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1108033#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1108030#L626 assume 0 != eval_~tmp~0#1; 1108027#L626-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 1108024#L634 assume !(0 != eval_~tmp_ndt_1~0#1); 1108025#L634-2 havoc eval_~tmp_ndt_1~0#1; 1090492#L631-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 1090490#L648 assume !(0 != eval_~tmp_ndt_2~0#1); 1090489#L648-2 havoc eval_~tmp_ndt_2~0#1; 1090488#L645-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 1090483#L662 assume !(0 != eval_~tmp_ndt_3~0#1); 1090481#L662-2 havoc eval_~tmp_ndt_3~0#1; 1090479#L659-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 1067661#L676 assume !(0 != eval_~tmp_ndt_4~0#1); 1069638#L676-2 havoc eval_~tmp_ndt_4~0#1; 1108059#L673-1 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 1108057#L690 assume !(0 != eval_~tmp_ndt_5~0#1); 1108054#L690-2 havoc eval_~tmp_ndt_5~0#1; 1108052#L687-1 assume !(0 == ~t5_st~0); 1108048#L701-1 assume !(0 == ~t6_st~0); 1108044#L715-1 assume !(0 == ~t7_st~0); 1108040#L729-1
[2024-11-08 18:32:57,991 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 18:32:57,991 INFO L85 PathProgramCache]: Analyzing trace with hash 1978243432, now seen corresponding path program 5 times
[2024-11-08 18:32:57,991 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 18:32:57,991 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2135536798]
[2024-11-08 18:32:57,991 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 18:32:57,992 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 18:32:58,005 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-11-08 18:32:58,006 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2024-11-08 18:32:58,013 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-11-08 18:32:58,029 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2024-11-08 18:32:58,029 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 18:32:58,029 INFO L85 PathProgramCache]: Analyzing trace with hash -351987155, now seen corresponding path program 1 times
[2024-11-08 18:32:58,030 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 18:32:58,030 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1688221080]
[2024-11-08 18:32:58,030 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 18:32:58,030 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 18:32:58,034 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-11-08 18:32:58,034 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2024-11-08 18:32:58,036 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-11-08 18:32:58,038 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2024-11-08 18:32:58,039 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 18:32:58,039 INFO L85 PathProgramCache]: Analyzing trace with hash -2090684780, now seen corresponding path program 1 times
[2024-11-08 18:32:58,039 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 18:32:58,039 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [531982371]
[2024-11-08 18:32:58,040 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 18:32:58,040 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 18:32:58,052 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-11-08 18:32:58,085 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2024-11-08 18:32:58,085 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2024-11-08 18:32:58,085 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [531982371]
[2024-11-08 18:32:58,086 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [531982371] provided 1 perfect and 0 imperfect interpolant sequences
[2024-11-08 18:32:58,086 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2024-11-08 18:32:58,086 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2024-11-08 18:32:58,086 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1638343404]
[2024-11-08 18:32:58,086 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2024-11-08 18:32:58,205 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2024-11-08 18:32:58,205 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2024-11-08 18:32:58,205 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2024-11-08 18:32:58,205 INFO L87 Difference]: Start difference. First operand 143610 states and 192551 transitions. cyclomatic complexity: 48965 Second operand has 3 states, 3 states have (on average 39.666666666666664) internal successors, (119), 3 states have internal predecessors, (119), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 18:32:59,748 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2024-11-08 18:32:59,748 INFO L93 Difference]: Finished difference Result 260466 states and 347975 transitions.
[2024-11-08 18:32:59,748 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 260466 states and 347975 transitions.
[2024-11-08 18:33:00,829 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 257900
[2024-11-08 18:33:02,171 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 260466 states to 260466 states and 347975 transitions.
[2024-11-08 18:33:02,172 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 260466
[2024-11-08 18:33:02,280 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 260466
[2024-11-08 18:33:02,280 INFO L73 IsDeterministic]: Start isDeterministic. Operand 260466 states and 347975 transitions.
[2024-11-08 18:33:02,372 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2024-11-08 18:33:02,372 INFO L218 hiAutomatonCegarLoop]: Abstraction has 260466 states and 347975 transitions.
[2024-11-08 18:33:02,478 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 260466 states and 347975 transitions.
[2024-11-08 18:33:05,183 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 260466 to 252066.
[2024-11-08 18:33:05,390 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 252066 states, 252066 states have (on average 1.3395499591376863) internal successors, (337655), 252065 states have internal predecessors, (337655), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 18:33:05,919 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 252066 states to 252066 states and 337655 transitions.
[2024-11-08 18:33:05,919 INFO L240 hiAutomatonCegarLoop]: Abstraction has 252066 states and 337655 transitions.
[2024-11-08 18:33:05,919 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states.
[2024-11-08 18:33:05,920 INFO L425 stractBuchiCegarLoop]: Abstraction has 252066 states and 337655 transitions.
[2024-11-08 18:33:05,920 INFO L332 stractBuchiCegarLoop]: ======== Iteration 33 ============
[2024-11-08 18:33:05,920 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 252066 states and 337655 transitions.
[2024-11-08 18:33:07,309 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 249500
[2024-11-08 18:33:07,309 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2024-11-08 18:33:07,309 INFO L119 BuchiIsEmpty]: Starting construction of run
[2024-11-08 18:33:07,310 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 18:33:07,310 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-11-08 18:33:07,311 INFO L745 eck$LassoCheckResult]: Stem: 1454604#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 1454605#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1455270#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1455271#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1455338#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 1455308#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1455309#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1454767#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1454768#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1454837#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1454670#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1454671#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1454637#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1454638#L754 assume !(0 == ~M_E~0); 1455366#L754-2 assume !(0 == ~T1_E~0); 1455206#L759-1 assume !(0 == ~T2_E~0); 1455042#L764-1 assume !(0 == ~T3_E~0); 1454992#L769-1 assume !(0 == ~T4_E~0); 1454993#L774-1 assume !(0 == ~T5_E~0); 1455043#L779-1 assume !(0 == ~T6_E~0); 1455221#L784-1 assume !(0 == ~T7_E~0); 1454989#L789-1 assume !(0 == ~E_1~0); 1454990#L794-1 assume !(0 == ~E_2~0); 1455104#L799-1 assume !(0 == ~E_3~0); 1455003#L804-1 assume !(0 == ~E_4~0); 1455004#L809-1 assume !(0 == ~E_5~0); 1455035#L814-1 assume !(0 == ~E_6~0); 1454401#L819-1 assume !(0 == ~E_7~0); 1454402#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1454668#L361 assume !(1 == ~m_pc~0); 1454669#L361-2 is_master_triggered_~__retres1~0#1 := 0; 1455265#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1455193#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1455194#L930 assume !(0 != activate_threads_~tmp~1#1); 1454888#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1454662#L380 assume !(1 == ~t1_pc~0); 1454663#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1455334#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1455335#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1455424#L938 assume !(0 != activate_threads_~tmp___0~0#1); 1455146#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1455119#L399 assume !(1 == ~t2_pc~0); 1454572#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1454573#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1454744#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1454737#L946 assume !(0 != activate_threads_~tmp___1~0#1); 1454738#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1454409#L418 assume !(1 == ~t3_pc~0); 1454389#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1454390#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1454399#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1454400#L954 assume !(0 != activate_threads_~tmp___2~0#1); 1455022#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1455023#L437 assume !(1 == ~t4_pc~0); 1455310#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1455187#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1454481#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1454482#L962 assume !(0 != activate_threads_~tmp___3~0#1); 1454797#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1455167#L456 assume !(1 == ~t5_pc~0); 1454588#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1454587#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1455197#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1455082#L970 assume !(0 != activate_threads_~tmp___4~0#1); 1455083#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1454476#L475 assume !(1 == ~t6_pc~0); 1454477#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1454518#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1454519#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1454729#L978 assume !(0 != activate_threads_~tmp___5~0#1); 1455009#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1455010#L494 assume !(1 == ~t7_pc~0); 1454713#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1454714#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1454958#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1455044#L986 assume !(0 != activate_threads_~tmp___6~0#1); 1455045#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1455353#L837 assume !(1 == ~M_E~0); 1455269#L837-2 assume !(1 == ~T1_E~0); 1455112#L842-1 assume !(1 == ~T2_E~0); 1454804#L847-1 assume !(1 == ~T3_E~0); 1454805#L852-1 assume !(1 == ~T4_E~0); 1454875#L857-1 assume !(1 == ~T5_E~0); 1454751#L862-1 assume !(1 == ~T6_E~0); 1454752#L867-1 assume !(1 == ~T7_E~0); 1454762#L872-1 assume !(1 == ~E_1~0); 1454836#L877-1 assume !(1 == ~E_2~0); 1455061#L882-1 assume !(1 == ~E_3~0); 1455280#L887-1 assume !(1 == ~E_4~0); 1455139#L892-1 assume !(1 == ~E_5~0); 1455140#L897-1 assume !(1 == ~E_6~0); 1454779#L902-1 assume !(1 == ~E_7~0); 1454780#L907-1 assume { :end_inline_reset_delta_events } true; 1455166#L1148-2 assume !false; 1494113#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1494114#L729-1
[2024-11-08 18:33:07,311 INFO L747 eck$LassoCheckResult]: Loop: 1494114#L729-1 assume !false; 1517925#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1517922#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1517920#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1517919#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1517917#L626 assume 0 != eval_~tmp~0#1; 1494018#L626-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 1494015#L634 assume !(0 != eval_~tmp_ndt_1~0#1); 1494017#L634-2 havoc eval_~tmp_ndt_1~0#1; 1489224#L631-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 1489222#L648 assume !(0 != eval_~tmp_ndt_2~0#1); 1489221#L648-2 havoc eval_~tmp_ndt_2~0#1; 1489219#L645-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 1489216#L662 assume !(0 != eval_~tmp_ndt_3~0#1); 1489214#L662-2 havoc eval_~tmp_ndt_3~0#1; 1489213#L659-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 1489190#L676 assume !(0 != eval_~tmp_ndt_4~0#1); 1489211#L676-2 havoc eval_~tmp_ndt_4~0#1; 1500365#L673-1 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 1500363#L690 assume !(0 != eval_~tmp_ndt_5~0#1); 1500362#L690-2 havoc eval_~tmp_ndt_5~0#1; 1500360#L687-1 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0#1;havoc eval_#t~nondet10#1;eval_~tmp_ndt_6~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 1481020#L704 assume !(0 != eval_~tmp_ndt_6~0#1); 1494138#L704-2 havoc eval_~tmp_ndt_6~0#1; 1517934#L701-1 assume !(0 == ~t6_st~0); 1517930#L715-1 assume !(0 == ~t7_st~0); 1494114#L729-1
[2024-11-08 18:33:07,311 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 18:33:07,312 INFO L85 PathProgramCache]: Analyzing trace with hash 1978243432, now seen corresponding path program 6 times
[2024-11-08 18:33:07,312 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 18:33:07,312 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [127127305]
[2024-11-08 18:33:07,312 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 18:33:07,312 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 18:33:07,351 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-11-08 18:33:07,357 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2024-11-08 18:33:07,381 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-11-08 18:33:07,420 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2024-11-08 18:33:07,424 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 18:33:07,425 INFO L85 PathProgramCache]: Analyzing trace with hash 829736336, now seen corresponding path program 1 times
[2024-11-08 18:33:07,425 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 18:33:07,425 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [939680333]
[2024-11-08 18:33:07,425 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 18:33:07,425 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 18:33:07,434 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-11-08 18:33:07,434 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2024-11-08 18:33:07,436 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-11-08 18:33:07,439 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2024-11-08 18:33:07,440 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-11-08 18:33:07,440 INFO L85 PathProgramCache]: Analyzing trace with hash 683596855, now seen corresponding path program 1 times
[2024-11-08 18:33:07,440 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL
[2024-11-08 18:33:07,440 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [411097497]
[2024-11-08 18:33:07,441 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-11-08 18:33:07,441 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-11-08 18:33:07,456 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-11-08 18:33:07,501 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2024-11-08 18:33:07,501 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2024-11-08 18:33:07,501 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [411097497]
[2024-11-08 18:33:07,502 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [411097497] provided 1 perfect and 0 imperfect interpolant sequences
[2024-11-08 18:33:07,502 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2024-11-08 18:33:07,502 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2024-11-08 18:33:07,502 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [928874429]
[2024-11-08 18:33:07,502 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2024-11-08 18:33:07,639 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2024-11-08 18:33:07,640 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2024-11-08 18:33:07,640 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2024-11-08 18:33:07,640 INFO L87 Difference]: Start difference. First operand 252066 states and 337655 transitions. cyclomatic complexity: 85613 Second operand has 3 states, 3 states have (on average 40.333333333333336) internal successors, (121), 3 states have internal predecessors, (121), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-11-08 18:33:08,896 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2024-11-08 18:33:08,896 INFO L93 Difference]: Finished difference Result 345132 states and 459967 transitions.
[2024-11-08 18:33:08,896 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 345132 states and 459967 transitions.
[2024-11-08 18:33:11,081 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 341814
[2024-11-08 18:33:12,384 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 345132 states to 345132 states and 459967 transitions.
[2024-11-08 18:33:12,385 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 345132
[2024-11-08 18:33:12,459 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 345132
[2024-11-08 18:33:12,460 INFO L73 IsDeterministic]: Start isDeterministic. Operand 345132 states and 459967 transitions.
[2024-11-08 18:33:12,568 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2024-11-08 18:33:12,568 INFO L218 hiAutomatonCegarLoop]: Abstraction has 345132 states and 459967 transitions.
[2024-11-08 18:33:12,713 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 345132 states and 459967 transitions.