./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.12.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version a0165632 Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_715d87bb-b70b-4c27-8539-3080c61e267a/bin/uautomizer-verify-jihMAELWvX/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_715d87bb-b70b-4c27-8539-3080c61e267a/bin/uautomizer-verify-jihMAELWvX/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_715d87bb-b70b-4c27-8539-3080c61e267a/bin/uautomizer-verify-jihMAELWvX/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_715d87bb-b70b-4c27-8539-3080c61e267a/bin/uautomizer-verify-jihMAELWvX/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.12.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_715d87bb-b70b-4c27-8539-3080c61e267a/bin/uautomizer-verify-jihMAELWvX/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_715d87bb-b70b-4c27-8539-3080c61e267a/bin/uautomizer-verify-jihMAELWvX --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 062c7418109a213aa13d25a99437d8241cca4f6492c123259890838dc94aff90 --- Real Ultimate output --- This is Ultimate 0.2.5-dev-a016563 [2024-11-08 17:07:10,513 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-08 17:07:10,629 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_715d87bb-b70b-4c27-8539-3080c61e267a/bin/uautomizer-verify-jihMAELWvX/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-11-08 17:07:10,635 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-08 17:07:10,639 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-08 17:07:10,676 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-08 17:07:10,677 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-08 17:07:10,678 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-08 17:07:10,679 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-08 17:07:10,680 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-08 17:07:10,681 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-08 17:07:10,681 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-08 17:07:10,682 INFO L153 SettingsManager]: * Use SBE=true [2024-11-08 17:07:10,683 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-11-08 17:07:10,685 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-11-08 17:07:10,685 INFO L153 SettingsManager]: * Use old map elimination=false [2024-11-08 17:07:10,686 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-11-08 17:07:10,686 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-11-08 17:07:10,686 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-11-08 17:07:10,687 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-08 17:07:10,687 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-11-08 17:07:10,690 INFO L153 SettingsManager]: * sizeof long=4 [2024-11-08 17:07:10,690 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-08 17:07:10,690 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-11-08 17:07:10,692 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-08 17:07:10,693 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-11-08 17:07:10,693 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-11-08 17:07:10,693 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-11-08 17:07:10,696 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-11-08 17:07:10,697 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-11-08 17:07:10,697 INFO L153 SettingsManager]: * sizeof long double=12 [2024-11-08 17:07:10,697 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-08 17:07:10,698 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-11-08 17:07:10,698 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-08 17:07:10,698 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-11-08 17:07:10,698 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-08 17:07:10,699 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-08 17:07:10,699 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-11-08 17:07:10,699 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-11-08 17:07:10,700 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_715d87bb-b70b-4c27-8539-3080c61e267a/bin/uautomizer-verify-jihMAELWvX/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_715d87bb-b70b-4c27-8539-3080c61e267a/bin/uautomizer-verify-jihMAELWvX Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 062c7418109a213aa13d25a99437d8241cca4f6492c123259890838dc94aff90 [2024-11-08 17:07:11,030 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-08 17:07:11,061 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-08 17:07:11,064 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-08 17:07:11,065 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-08 17:07:11,066 INFO L274 PluginConnector]: CDTParser initialized [2024-11-08 17:07:11,068 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_715d87bb-b70b-4c27-8539-3080c61e267a/bin/uautomizer-verify-jihMAELWvX/../../sv-benchmarks/c/systemc/transmitter.12.cil.c Unable to find full path for "g++" [2024-11-08 17:07:13,089 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-11-08 17:07:13,325 INFO L384 CDTParser]: Found 1 translation units. [2024-11-08 17:07:13,329 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_715d87bb-b70b-4c27-8539-3080c61e267a/sv-benchmarks/c/systemc/transmitter.12.cil.c [2024-11-08 17:07:13,353 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_715d87bb-b70b-4c27-8539-3080c61e267a/bin/uautomizer-verify-jihMAELWvX/data/5004b5d76/58356a78bd0d400ca37a9f6ec6556e3c/FLAGcbdb072a1 [2024-11-08 17:07:13,374 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_715d87bb-b70b-4c27-8539-3080c61e267a/bin/uautomizer-verify-jihMAELWvX/data/5004b5d76/58356a78bd0d400ca37a9f6ec6556e3c [2024-11-08 17:07:13,378 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-08 17:07:13,379 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-08 17:07:13,381 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-08 17:07:13,382 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-08 17:07:13,389 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-08 17:07:13,390 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 08.11 05:07:13" (1/1) ... [2024-11-08 17:07:13,392 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@7e25ba0b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 05:07:13, skipping insertion in model container [2024-11-08 17:07:13,392 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 08.11 05:07:13" (1/1) ... [2024-11-08 17:07:13,450 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-08 17:07:13,872 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-08 17:07:13,905 INFO L200 MainTranslator]: Completed pre-run [2024-11-08 17:07:14,003 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-08 17:07:14,029 INFO L204 MainTranslator]: Completed translation [2024-11-08 17:07:14,029 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 05:07:14 WrapperNode [2024-11-08 17:07:14,029 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-08 17:07:14,030 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-08 17:07:14,031 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-08 17:07:14,031 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-08 17:07:14,039 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 05:07:14" (1/1) ... [2024-11-08 17:07:14,051 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 05:07:14" (1/1) ... [2024-11-08 17:07:14,174 INFO L138 Inliner]: procedures = 52, calls = 67, calls flagged for inlining = 62, calls inlined = 255, statements flattened = 3920 [2024-11-08 17:07:14,174 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-08 17:07:14,175 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-08 17:07:14,175 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-08 17:07:14,175 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-08 17:07:14,188 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 05:07:14" (1/1) ... [2024-11-08 17:07:14,189 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 05:07:14" (1/1) ... [2024-11-08 17:07:14,200 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 05:07:14" (1/1) ... [2024-11-08 17:07:14,247 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-11-08 17:07:14,248 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 05:07:14" (1/1) ... [2024-11-08 17:07:14,248 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 05:07:14" (1/1) ... [2024-11-08 17:07:14,304 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 05:07:14" (1/1) ... [2024-11-08 17:07:14,354 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 05:07:14" (1/1) ... [2024-11-08 17:07:14,366 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 05:07:14" (1/1) ... [2024-11-08 17:07:14,379 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 05:07:14" (1/1) ... [2024-11-08 17:07:14,395 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-08 17:07:14,396 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-11-08 17:07:14,398 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-11-08 17:07:14,398 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-11-08 17:07:14,399 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 05:07:14" (1/1) ... [2024-11-08 17:07:14,406 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 17:07:14,420 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_715d87bb-b70b-4c27-8539-3080c61e267a/bin/uautomizer-verify-jihMAELWvX/z3 [2024-11-08 17:07:14,440 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_715d87bb-b70b-4c27-8539-3080c61e267a/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 17:07:14,443 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_715d87bb-b70b-4c27-8539-3080c61e267a/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-11-08 17:07:14,481 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-08 17:07:14,481 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-11-08 17:07:14,481 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-08 17:07:14,482 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-08 17:07:14,607 INFO L238 CfgBuilder]: Building ICFG [2024-11-08 17:07:14,610 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-08 17:07:17,896 INFO L? ?]: Removed 830 outVars from TransFormulas that were not future-live. [2024-11-08 17:07:17,897 INFO L287 CfgBuilder]: Performing block encoding [2024-11-08 17:07:17,942 INFO L311 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-08 17:07:17,942 INFO L316 CfgBuilder]: Removed 16 assume(true) statements. [2024-11-08 17:07:17,943 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 08.11 05:07:17 BoogieIcfgContainer [2024-11-08 17:07:17,943 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-11-08 17:07:17,944 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-11-08 17:07:17,944 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-11-08 17:07:17,949 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-11-08 17:07:17,950 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-08 17:07:17,950 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 08.11 05:07:13" (1/3) ... [2024-11-08 17:07:17,951 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@668e0674 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 08.11 05:07:17, skipping insertion in model container [2024-11-08 17:07:17,951 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-08 17:07:17,951 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 05:07:14" (2/3) ... [2024-11-08 17:07:17,952 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@668e0674 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 08.11 05:07:17, skipping insertion in model container [2024-11-08 17:07:17,952 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-08 17:07:17,952 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 08.11 05:07:17" (3/3) ... [2024-11-08 17:07:17,954 INFO L332 chiAutomizerObserver]: Analyzing ICFG transmitter.12.cil.c [2024-11-08 17:07:18,061 INFO L300 stractBuchiCegarLoop]: Interprodecural is true [2024-11-08 17:07:18,061 INFO L301 stractBuchiCegarLoop]: Hoare is None [2024-11-08 17:07:18,061 INFO L302 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-11-08 17:07:18,061 INFO L303 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-11-08 17:07:18,061 INFO L304 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-11-08 17:07:18,062 INFO L305 stractBuchiCegarLoop]: Difference is false [2024-11-08 17:07:18,062 INFO L306 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-11-08 17:07:18,062 INFO L310 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-11-08 17:07:18,076 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1709 states, 1708 states have (on average 1.4976580796252927) internal successors, (2558), 1708 states have internal predecessors, (2558), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 17:07:18,187 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1544 [2024-11-08 17:07:18,187 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 17:07:18,188 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 17:07:18,204 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 17:07:18,205 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 17:07:18,205 INFO L332 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-11-08 17:07:18,209 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1709 states, 1708 states have (on average 1.4976580796252927) internal successors, (2558), 1708 states have internal predecessors, (2558), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 17:07:18,230 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1544 [2024-11-08 17:07:18,230 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 17:07:18,230 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 17:07:18,235 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 17:07:18,235 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 17:07:18,248 INFO L745 eck$LassoCheckResult]: Stem: 130#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 1621#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 630#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1617#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 524#L821true assume !(1 == ~m_i~0);~m_st~0 := 2; 599#L821-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 871#L826-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1186#L831-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1028#L836-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1334#L841-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 119#L846-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1636#L851-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 941#L856-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 450#L861-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 477#L866-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 392#L871-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 706#L876-1true assume !(1 == ~t12_i~0);~t12_st~0 := 2; 701#L881-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 240#L1174true assume !(0 == ~M_E~0); 1357#L1174-2true assume 0 == ~T1_E~0;~T1_E~0 := 1; 163#L1179-1true assume !(0 == ~T2_E~0); 117#L1184-1true assume !(0 == ~T3_E~0); 138#L1189-1true assume !(0 == ~T4_E~0); 184#L1194-1true assume !(0 == ~T5_E~0); 811#L1199-1true assume !(0 == ~T6_E~0); 977#L1204-1true assume !(0 == ~T7_E~0); 740#L1209-1true assume !(0 == ~T8_E~0); 1248#L1214-1true assume 0 == ~T9_E~0;~T9_E~0 := 1; 1651#L1219-1true assume !(0 == ~T10_E~0); 1571#L1224-1true assume !(0 == ~T11_E~0); 306#L1229-1true assume !(0 == ~T12_E~0); 84#L1234-1true assume !(0 == ~E_1~0); 489#L1239-1true assume !(0 == ~E_2~0); 98#L1244-1true assume !(0 == ~E_3~0); 1340#L1249-1true assume !(0 == ~E_4~0); 465#L1254-1true assume 0 == ~E_5~0;~E_5~0 := 1; 50#L1259-1true assume !(0 == ~E_6~0); 30#L1264-1true assume !(0 == ~E_7~0); 1702#L1269-1true assume !(0 == ~E_8~0); 1624#L1274-1true assume !(0 == ~E_9~0); 1328#L1279-1true assume !(0 == ~E_10~0); 140#L1284-1true assume !(0 == ~E_11~0); 1473#L1289-1true assume !(0 == ~E_12~0); 503#L1294-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1344#L566true assume 1 == ~m_pc~0; 37#L567true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 970#L577true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 538#is_master_triggered_returnLabel#1true activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1193#L1455true assume !(0 != activate_threads_~tmp~1#1); 252#L1455-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 783#L585true assume 1 == ~t1_pc~0; 83#L586true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1627#L596true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 861#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1546#L1463true assume !(0 != activate_threads_~tmp___0~0#1); 1414#L1463-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1405#L604true assume !(1 == ~t2_pc~0); 776#L604-2true is_transmit2_triggered_~__retres1~2#1 := 0; 1366#L615true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 223#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1202#L1471true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 984#L1471-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1471#L623true assume 1 == ~t3_pc~0; 356#L624true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1676#L634true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 836#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1021#L1479true assume !(0 != activate_threads_~tmp___2~0#1); 1246#L1479-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36#L642true assume !(1 == ~t4_pc~0); 670#L642-2true is_transmit4_triggered_~__retres1~4#1 := 0; 259#L653true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 61#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 72#L1487true assume !(0 != activate_threads_~tmp___3~0#1); 787#L1487-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1126#L661true assume 1 == ~t5_pc~0; 147#L662true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 714#L672true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1372#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1103#L1495true assume !(0 != activate_threads_~tmp___4~0#1); 818#L1495-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1703#L680true assume !(1 == ~t6_pc~0); 1705#L680-2true is_transmit6_triggered_~__retres1~6#1 := 0; 1500#L691true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 218#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1118#L1503true assume !(0 != activate_threads_~tmp___5~0#1); 1410#L1503-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1401#L699true assume 1 == ~t7_pc~0; 682#L700true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 890#L710true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1637#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 588#L1511true assume !(0 != activate_threads_~tmp___6~0#1); 795#L1511-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 504#L718true assume !(1 == ~t8_pc~0); 1254#L718-2true is_transmit8_triggered_~__retres1~8#1 := 0; 137#L729true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1322#is_transmit8_triggered_returnLabel#1true activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 155#L1519true assume !(0 != activate_threads_~tmp___7~0#1); 221#L1519-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 849#L737true assume 1 == ~t9_pc~0; 1512#L738true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1291#L748true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 244#is_transmit9_triggered_returnLabel#1true activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1652#L1527true assume !(0 != activate_threads_~tmp___8~0#1); 405#L1527-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1097#L756true assume 1 == ~t10_pc~0; 882#L757true assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 806#L767true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1119#is_transmit10_triggered_returnLabel#1true activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 531#L1535true assume !(0 != activate_threads_~tmp___9~0#1); 284#L1535-2true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 751#L775true assume !(1 == ~t11_pc~0); 446#L775-2true is_transmit11_triggered_~__retres1~11#1 := 0; 1269#L786true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1234#is_transmit11_triggered_returnLabel#1true activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 104#L1543true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 842#L1543-2true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 195#L794true assume 1 == ~t12_pc~0; 115#L795true assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 1104#L805true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 38#is_transmit12_triggered_returnLabel#1true activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 177#L1551true assume !(0 != activate_threads_~tmp___11~0#1); 698#L1551-2true havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 454#L1307true assume !(1 == ~M_E~0); 535#L1307-2true assume !(1 == ~T1_E~0); 1452#L1312-1true assume !(1 == ~T2_E~0); 474#L1317-1true assume 1 == ~T3_E~0;~T3_E~0 := 2; 643#L1322-1true assume !(1 == ~T4_E~0); 291#L1327-1true assume !(1 == ~T5_E~0); 686#L1332-1true assume !(1 == ~T6_E~0); 1427#L1337-1true assume !(1 == ~T7_E~0); 638#L1342-1true assume !(1 == ~T8_E~0); 1326#L1347-1true assume !(1 == ~T9_E~0); 1065#L1352-1true assume !(1 == ~T10_E~0); 891#L1357-1true assume 1 == ~T11_E~0;~T11_E~0 := 2; 391#L1362-1true assume !(1 == ~T12_E~0); 1137#L1367-1true assume !(1 == ~E_1~0); 185#L1372-1true assume !(1 == ~E_2~0); 484#L1377-1true assume !(1 == ~E_3~0); 349#L1382-1true assume !(1 == ~E_4~0); 777#L1387-1true assume !(1 == ~E_5~0); 1264#L1392-1true assume !(1 == ~E_6~0); 360#L1397-1true assume 1 == ~E_7~0;~E_7~0 := 2; 1394#L1402-1true assume !(1 == ~E_8~0); 193#L1407-1true assume !(1 == ~E_9~0); 1529#L1412-1true assume !(1 == ~E_10~0); 973#L1417-1true assume !(1 == ~E_11~0); 1709#L1422-1true assume !(1 == ~E_12~0); 1390#L1427-1true assume { :end_inline_reset_delta_events } true; 96#L1768-2true [2024-11-08 17:07:18,254 INFO L747 eck$LassoCheckResult]: Loop: 96#L1768-2true assume !false; 520#L1769true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 799#L1149-1true assume false; 498#eval_returnLabel#1true havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 318#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 997#L1174-3true assume 0 == ~M_E~0;~M_E~0 := 1; 989#L1174-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 722#L1179-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 1406#L1184-3true assume !(0 == ~T3_E~0); 892#L1189-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 576#L1194-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 173#L1199-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 815#L1204-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 302#L1209-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 11#L1214-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 628#L1219-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 414#L1224-3true assume !(0 == ~T11_E~0); 1707#L1229-3true assume 0 == ~T12_E~0;~T12_E~0 := 1; 425#L1234-3true assume 0 == ~E_1~0;~E_1~0 := 1; 101#L1239-3true assume 0 == ~E_2~0;~E_2~0 := 1; 336#L1244-3true assume 0 == ~E_3~0;~E_3~0 := 1; 668#L1249-3true assume 0 == ~E_4~0;~E_4~0 := 1; 1453#L1254-3true assume 0 == ~E_5~0;~E_5~0 := 1; 1241#L1259-3true assume 0 == ~E_6~0;~E_6~0 := 1; 763#L1264-3true assume !(0 == ~E_7~0); 103#L1269-3true assume 0 == ~E_8~0;~E_8~0 := 1; 1513#L1274-3true assume 0 == ~E_9~0;~E_9~0 := 1; 1325#L1279-3true assume 0 == ~E_10~0;~E_10~0 := 1; 412#L1284-3true assume 0 == ~E_11~0;~E_11~0 := 1; 1382#L1289-3true assume 0 == ~E_12~0;~E_12~0 := 1; 403#L1294-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 213#L566-39true assume 1 == ~m_pc~0; 747#L567-13true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 607#L577-13true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 650#is_master_triggered_returnLabel#14true activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1255#L1455-39true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 829#L1455-41true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1301#L585-39true assume !(1 == ~t1_pc~0); 217#L585-41true is_transmit1_triggered_~__retres1~1#1 := 0; 332#L596-13true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1487#is_transmit1_triggered_returnLabel#14true activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1229#L1463-39true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 864#L1463-41true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 592#L604-39true assume !(1 == ~t2_pc~0); 1224#L604-41true is_transmit2_triggered_~__retres1~2#1 := 0; 338#L615-13true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 453#is_transmit2_triggered_returnLabel#14true activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 632#L1471-39true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1005#L1471-41true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 324#L623-39true assume !(1 == ~t3_pc~0); 657#L623-41true is_transmit3_triggered_~__retres1~3#1 := 0; 845#L634-13true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1682#is_transmit3_triggered_returnLabel#14true activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 241#L1479-39true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 794#L1479-41true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1307#L642-39true assume !(1 == ~t4_pc~0); 598#L642-41true is_transmit4_triggered_~__retres1~4#1 := 0; 750#L653-13true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 573#is_transmit4_triggered_returnLabel#14true activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1040#L1487-39true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1183#L1487-41true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 199#L661-39true assume 1 == ~t5_pc~0; 1050#L662-13true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1641#L672-13true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 596#is_transmit5_triggered_returnLabel#14true activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1153#L1495-39true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 847#L1495-41true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1176#L680-39true assume !(1 == ~t6_pc~0); 975#L680-41true is_transmit6_triggered_~__retres1~6#1 := 0; 1146#L691-13true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1576#is_transmit6_triggered_returnLabel#14true activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 283#L1503-39true assume !(0 != activate_threads_~tmp___5~0#1); 1501#L1503-41true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1252#L699-39true assume 1 == ~t7_pc~0; 578#L700-13true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 380#L710-13true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 850#is_transmit7_triggered_returnLabel#14true activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1275#L1511-39true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1143#L1511-41true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1141#L718-39true assume 1 == ~t8_pc~0; 507#L719-13true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1393#L729-13true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 952#is_transmit8_triggered_returnLabel#14true activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1155#L1519-39true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 713#L1519-41true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 692#L737-39true assume 1 == ~t9_pc~0; 270#L738-13true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 451#L748-13true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 66#is_transmit9_triggered_returnLabel#14true activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1455#L1527-39true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1102#L1527-41true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1023#L756-39true assume 1 == ~t10_pc~0; 1379#L757-13true assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1524#L767-13true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1228#is_transmit10_triggered_returnLabel#14true activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 436#L1535-39true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 562#L1535-41true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 77#L775-39true assume !(1 == ~t11_pc~0); 458#L775-41true is_transmit11_triggered_~__retres1~11#1 := 0; 432#L786-13true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 616#is_transmit11_triggered_returnLabel#14true activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1556#L1543-39true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 757#L1543-41true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 464#L794-39true assume 1 == ~t12_pc~0; 271#L795-13true assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 913#L805-13true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 322#is_transmit12_triggered_returnLabel#14true activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 801#L1551-39true assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 48#L1551-41true havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1309#L1307-3true assume 1 == ~M_E~0;~M_E~0 := 2; 1203#L1307-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 1622#L1312-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 1614#L1317-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 819#L1322-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 1687#L1327-3true assume !(1 == ~T5_E~0); 110#L1332-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 99#L1337-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 528#L1342-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 954#L1347-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 634#L1352-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 1114#L1357-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 1697#L1362-3true assume 1 == ~T12_E~0;~T12_E~0 := 2; 1551#L1367-3true assume !(1 == ~E_1~0); 1518#L1372-3true assume 1 == ~E_2~0;~E_2~0 := 2; 17#L1377-3true assume 1 == ~E_3~0;~E_3~0 := 2; 428#L1382-3true assume 1 == ~E_4~0;~E_4~0 := 2; 340#L1387-3true assume 1 == ~E_5~0;~E_5~0 := 2; 926#L1392-3true assume 1 == ~E_6~0;~E_6~0 := 2; 1605#L1397-3true assume 1 == ~E_7~0;~E_7~0 := 2; 1376#L1402-3true assume 1 == ~E_8~0;~E_8~0 := 2; 606#L1407-3true assume !(1 == ~E_9~0); 153#L1412-3true assume 1 == ~E_10~0;~E_10~0 := 2; 1151#L1417-3true assume 1 == ~E_11~0;~E_11~0 := 2; 542#L1422-3true assume 1 == ~E_12~0;~E_12~0 := 2; 1107#L1427-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 157#L894-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1665#L961-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 191#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 609#L1787true assume !(0 == start_simulation_~tmp~3#1); 1441#L1787-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1218#L894-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1008#L961-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 25#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 1320#L1742true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 328#L1749true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1148#stop_simulation_returnLabel#1true start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 1601#L1800true assume !(0 != start_simulation_~tmp___0~1#1); 96#L1768-2true [2024-11-08 17:07:18,271 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 17:07:18,272 INFO L85 PathProgramCache]: Analyzing trace with hash -1422298547, now seen corresponding path program 1 times [2024-11-08 17:07:18,291 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 17:07:18,292 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [981850565] [2024-11-08 17:07:18,292 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 17:07:18,296 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 17:07:18,472 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:07:18,781 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 17:07:18,781 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 17:07:18,782 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [981850565] [2024-11-08 17:07:18,783 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [981850565] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 17:07:18,783 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 17:07:18,784 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 17:07:18,786 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [562525016] [2024-11-08 17:07:18,786 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 17:07:18,792 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 17:07:18,794 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 17:07:18,794 INFO L85 PathProgramCache]: Analyzing trace with hash -188107858, now seen corresponding path program 1 times [2024-11-08 17:07:18,794 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 17:07:18,795 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2089974290] [2024-11-08 17:07:18,795 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 17:07:18,795 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 17:07:18,849 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:07:18,948 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 17:07:18,952 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 17:07:18,952 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2089974290] [2024-11-08 17:07:18,952 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2089974290] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 17:07:18,953 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 17:07:18,953 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-08 17:07:18,953 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [295292701] [2024-11-08 17:07:18,954 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 17:07:18,955 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 17:07:18,958 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 17:07:18,999 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2024-11-08 17:07:19,000 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2024-11-08 17:07:19,006 INFO L87 Difference]: Start difference. First operand has 1709 states, 1708 states have (on average 1.4976580796252927) internal successors, (2558), 1708 states have internal predecessors, (2558), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 73.5) internal successors, (147), 2 states have internal predecessors, (147), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 17:07:19,103 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 17:07:19,103 INFO L93 Difference]: Finished difference Result 1707 states and 2523 transitions. [2024-11-08 17:07:19,105 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1707 states and 2523 transitions. [2024-11-08 17:07:19,125 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1540 [2024-11-08 17:07:19,145 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1707 states to 1701 states and 2517 transitions. [2024-11-08 17:07:19,146 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1701 [2024-11-08 17:07:19,150 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1701 [2024-11-08 17:07:19,151 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1701 states and 2517 transitions. [2024-11-08 17:07:19,164 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 17:07:19,167 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1701 states and 2517 transitions. [2024-11-08 17:07:19,199 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1701 states and 2517 transitions. [2024-11-08 17:07:19,267 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1701 to 1701. [2024-11-08 17:07:19,272 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1701 states, 1701 states have (on average 1.4797178130511464) internal successors, (2517), 1700 states have internal predecessors, (2517), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 17:07:19,280 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1701 states to 1701 states and 2517 transitions. [2024-11-08 17:07:19,281 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1701 states and 2517 transitions. [2024-11-08 17:07:19,282 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-11-08 17:07:19,289 INFO L425 stractBuchiCegarLoop]: Abstraction has 1701 states and 2517 transitions. [2024-11-08 17:07:19,289 INFO L332 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-11-08 17:07:19,289 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1701 states and 2517 transitions. [2024-11-08 17:07:19,302 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1540 [2024-11-08 17:07:19,302 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 17:07:19,302 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 17:07:19,306 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 17:07:19,307 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 17:07:19,307 INFO L745 eck$LassoCheckResult]: Stem: 3702#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 3703#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 4495#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4496#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4363#L821 assume !(1 == ~m_i~0);~m_st~0 := 2; 4364#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4457#L826-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 4756#L831-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4891#L836-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4892#L841-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3678#L846-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3679#L851-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4823#L856-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4261#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4262#L866-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 4172#L871-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 4173#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 4566#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3917#L1174 assume !(0 == ~M_E~0); 3918#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3769#L1179-1 assume !(0 == ~T2_E~0); 3675#L1184-1 assume !(0 == ~T3_E~0); 3676#L1189-1 assume !(0 == ~T4_E~0); 3718#L1194-1 assume !(0 == ~T5_E~0); 3811#L1199-1 assume !(0 == ~T6_E~0); 4690#L1204-1 assume !(0 == ~T7_E~0); 4611#L1209-1 assume !(0 == ~T8_E~0); 4612#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 5035#L1219-1 assume !(0 == ~T10_E~0); 5120#L1224-1 assume !(0 == ~T11_E~0); 4034#L1229-1 assume !(0 == ~T12_E~0); 3605#L1234-1 assume !(0 == ~E_1~0); 3606#L1239-1 assume !(0 == ~E_2~0); 3638#L1244-1 assume !(0 == ~E_3~0); 3639#L1249-1 assume !(0 == ~E_4~0); 4281#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 3535#L1259-1 assume !(0 == ~E_6~0); 3488#L1264-1 assume !(0 == ~E_7~0); 3489#L1269-1 assume !(0 == ~E_8~0); 5123#L1274-1 assume !(0 == ~E_9~0); 5062#L1279-1 assume !(0 == ~E_10~0); 3722#L1284-1 assume !(0 == ~E_11~0); 3723#L1289-1 assume !(0 == ~E_12~0); 4333#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4334#L566 assume 1 == ~m_pc~0; 3505#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3506#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4377#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4378#L1455 assume !(0 != activate_threads_~tmp~1#1); 3944#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3945#L585 assume 1 == ~t1_pc~0; 3602#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3603#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4746#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4747#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 5091#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5087#L604 assume !(1 == ~t2_pc~0); 4652#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4653#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3887#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3888#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4851#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4852#L623 assume 1 == ~t3_pc~0; 4118#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3464#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4721#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4722#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 4885#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3502#L642 assume !(1 == ~t4_pc~0); 3503#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3955#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3557#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3558#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 3579#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4665#L661 assume 1 == ~t5_pc~0; 3735#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3736#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4583#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4950#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 4697#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4698#L680 assume !(1 == ~t6_pc~0); 4151#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4152#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3878#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3879#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 4960#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5084#L699 assume 1 == ~t7_pc~0; 4546#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 4547#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4779#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4439#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 4440#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4335#L718 assume !(1 == ~t8_pc~0); 4336#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3716#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3717#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3751#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 3752#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3884#L737 assume 1 == ~t9_pc~0; 4735#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4015#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3924#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3925#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 4192#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4193#L756 assume 1 == ~t10_pc~0; 4769#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 4430#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4685#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 4370#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 3994#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 3995#L775 assume !(1 == ~t11_pc~0); 4253#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 4254#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 5028#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 3650#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 3651#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 3832#L794 assume 1 == ~t12_pc~0; 3673#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 3653#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 3508#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 3509#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 3797#L1551-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4265#L1307 assume !(1 == ~M_E~0); 4266#L1307-2 assume !(1 == ~T1_E~0); 4374#L1312-1 assume !(1 == ~T2_E~0); 4294#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4295#L1322-1 assume !(1 == ~T4_E~0); 4005#L1327-1 assume !(1 == ~T5_E~0); 4006#L1332-1 assume !(1 == ~T6_E~0); 4551#L1337-1 assume !(1 == ~T7_E~0); 4508#L1342-1 assume !(1 == ~T8_E~0); 4509#L1347-1 assume !(1 == ~T9_E~0); 4921#L1352-1 assume !(1 == ~T10_E~0); 4780#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 4170#L1362-1 assume !(1 == ~T12_E~0); 4171#L1367-1 assume !(1 == ~E_1~0); 3812#L1372-1 assume !(1 == ~E_2~0); 3813#L1377-1 assume !(1 == ~E_3~0); 4103#L1382-1 assume !(1 == ~E_4~0); 4104#L1387-1 assume !(1 == ~E_5~0); 4654#L1392-1 assume !(1 == ~E_6~0); 4121#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 4122#L1402-1 assume !(1 == ~E_8~0); 3827#L1407-1 assume !(1 == ~E_9~0); 3828#L1412-1 assume !(1 == ~E_10~0); 4846#L1417-1 assume !(1 == ~E_11~0); 4847#L1422-1 assume !(1 == ~E_12~0); 5081#L1427-1 assume { :end_inline_reset_delta_events } true; 3634#L1768-2 [2024-11-08 17:07:19,309 INFO L747 eck$LassoCheckResult]: Loop: 3634#L1768-2 assume !false; 3635#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4298#L1149-1 assume !false; 4676#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 4903#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 4012#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 4828#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 4898#L976 assume !(0 != eval_~tmp~0#1); 4326#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4055#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4056#L1174-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4856#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4594#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4595#L1184-3 assume !(0 == ~T3_E~0); 4781#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4425#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3788#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3789#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4025#L1209-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 3448#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3449#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 4205#L1224-3 assume !(0 == ~T11_E~0); 4206#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 4220#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3644#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3645#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4080#L1249-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4538#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5031#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4637#L1264-3 assume !(0 == ~E_7~0); 3648#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3649#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 5061#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 4201#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 4202#L1289-3 assume 0 == ~E_12~0;~E_12~0 := 1; 4189#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3868#L566-39 assume 1 == ~m_pc~0; 3869#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 4468#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4469#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4521#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4712#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4713#L585-39 assume !(1 == ~t1_pc~0); 3876#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 3877#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4077#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5025#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4750#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4445#L604-39 assume 1 == ~t2_pc~0; 4446#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4084#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4085#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4264#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4498#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4066#L623-39 assume 1 == ~t3_pc~0; 3465#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3466#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4730#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3919#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3920#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4672#L642-39 assume !(1 == ~t4_pc~0); 4257#L642-41 is_transmit4_triggered_~__retres1~4#1 := 0; 4256#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4420#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4421#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4902#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3838#L661-39 assume !(1 == ~t5_pc~0); 3473#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 3474#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4452#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4453#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4732#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4733#L680-39 assume 1 == ~t6_pc~0; 3540#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3541#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4981#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3992#L1503-39 assume !(0 != activate_threads_~tmp___5~0#1); 3993#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5037#L699-39 assume 1 == ~t7_pc~0; 4427#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 4154#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4155#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4737#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4977#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4974#L718-39 assume 1 == ~t8_pc~0; 4339#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4340#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4833#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4834#L1519-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4582#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4559#L737-39 assume 1 == ~t9_pc~0; 3973#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3974#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3568#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3569#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 4949#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4886#L756-39 assume !(1 == ~t10_pc~0); 4353#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 4354#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5024#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 4238#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 4239#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 3589#L775-39 assume 1 == ~t11_pc~0; 3590#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 4229#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4230#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 4479#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 4630#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4280#L794-39 assume !(1 == ~t12_pc~0); 3969#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 3970#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4063#is_transmit12_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4064#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 3531#L1551-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3532#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5008#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5009#L1312-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5122#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4699#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4700#L1327-3 assume !(1 == ~T5_E~0); 3665#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3640#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3641#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4368#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 4501#L1352-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 4502#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 4957#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 5117#L1367-3 assume !(1 == ~E_1~0); 5108#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3461#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3462#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4087#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4088#L1392-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4807#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5075#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4467#L1407-3 assume !(1 == ~E_9~0); 3747#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 3748#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 4382#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 4383#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 3755#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 3756#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 3823#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 3824#L1787 assume !(0 == start_simulation_~tmp~3#1); 4471#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 5017#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 3732#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 3480#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 3481#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4073#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4074#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 4984#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 3634#L1768-2 [2024-11-08 17:07:19,310 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 17:07:19,310 INFO L85 PathProgramCache]: Analyzing trace with hash -1422298547, now seen corresponding path program 2 times [2024-11-08 17:07:19,311 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 17:07:19,311 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1479063019] [2024-11-08 17:07:19,311 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 17:07:19,311 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 17:07:19,353 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:07:19,430 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 17:07:19,434 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 17:07:19,434 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1479063019] [2024-11-08 17:07:19,434 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1479063019] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 17:07:19,434 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 17:07:19,435 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 17:07:19,435 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1524777062] [2024-11-08 17:07:19,435 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 17:07:19,436 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 17:07:19,436 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 17:07:19,437 INFO L85 PathProgramCache]: Analyzing trace with hash 423913914, now seen corresponding path program 1 times [2024-11-08 17:07:19,437 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 17:07:19,437 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1568356404] [2024-11-08 17:07:19,438 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 17:07:19,438 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 17:07:19,467 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:07:19,586 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 17:07:19,589 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 17:07:19,589 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1568356404] [2024-11-08 17:07:19,590 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1568356404] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 17:07:19,590 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 17:07:19,590 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 17:07:19,590 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1592255805] [2024-11-08 17:07:19,590 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 17:07:19,591 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 17:07:19,591 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 17:07:19,593 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 17:07:19,594 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 17:07:19,594 INFO L87 Difference]: Start difference. First operand 1701 states and 2517 transitions. cyclomatic complexity: 817 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 17:07:19,646 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 17:07:19,646 INFO L93 Difference]: Finished difference Result 1701 states and 2516 transitions. [2024-11-08 17:07:19,647 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1701 states and 2516 transitions. [2024-11-08 17:07:19,659 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1540 [2024-11-08 17:07:19,669 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1701 states to 1701 states and 2516 transitions. [2024-11-08 17:07:19,669 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1701 [2024-11-08 17:07:19,672 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1701 [2024-11-08 17:07:19,673 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1701 states and 2516 transitions. [2024-11-08 17:07:19,679 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 17:07:19,679 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1701 states and 2516 transitions. [2024-11-08 17:07:19,683 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1701 states and 2516 transitions. [2024-11-08 17:07:19,705 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1701 to 1701. [2024-11-08 17:07:19,711 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1701 states, 1701 states have (on average 1.479129923574368) internal successors, (2516), 1700 states have internal predecessors, (2516), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 17:07:19,718 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1701 states to 1701 states and 2516 transitions. [2024-11-08 17:07:19,718 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1701 states and 2516 transitions. [2024-11-08 17:07:19,719 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 17:07:19,720 INFO L425 stractBuchiCegarLoop]: Abstraction has 1701 states and 2516 transitions. [2024-11-08 17:07:19,720 INFO L332 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-11-08 17:07:19,720 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1701 states and 2516 transitions. [2024-11-08 17:07:19,730 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1540 [2024-11-08 17:07:19,731 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 17:07:19,731 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 17:07:19,735 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 17:07:19,735 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 17:07:19,738 INFO L745 eck$LassoCheckResult]: Stem: 7111#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 7112#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 7904#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7905#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7772#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 7773#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7866#L826-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 8165#L831-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 8300#L836-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 8301#L841-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 7087#L846-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 7088#L851-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8232#L856-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 7670#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 7671#L866-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 7581#L871-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 7582#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 7975#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7326#L1174 assume !(0 == ~M_E~0); 7327#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7178#L1179-1 assume !(0 == ~T2_E~0); 7084#L1184-1 assume !(0 == ~T3_E~0); 7085#L1189-1 assume !(0 == ~T4_E~0); 7127#L1194-1 assume !(0 == ~T5_E~0); 7220#L1199-1 assume !(0 == ~T6_E~0); 8099#L1204-1 assume !(0 == ~T7_E~0); 8020#L1209-1 assume !(0 == ~T8_E~0); 8021#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 8444#L1219-1 assume !(0 == ~T10_E~0); 8529#L1224-1 assume !(0 == ~T11_E~0); 7443#L1229-1 assume !(0 == ~T12_E~0); 7014#L1234-1 assume !(0 == ~E_1~0); 7015#L1239-1 assume !(0 == ~E_2~0); 7047#L1244-1 assume !(0 == ~E_3~0); 7048#L1249-1 assume !(0 == ~E_4~0); 7690#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 6944#L1259-1 assume !(0 == ~E_6~0); 6897#L1264-1 assume !(0 == ~E_7~0); 6898#L1269-1 assume !(0 == ~E_8~0); 8532#L1274-1 assume !(0 == ~E_9~0); 8471#L1279-1 assume !(0 == ~E_10~0); 7131#L1284-1 assume !(0 == ~E_11~0); 7132#L1289-1 assume !(0 == ~E_12~0); 7742#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7743#L566 assume 1 == ~m_pc~0; 6914#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 6915#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7786#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7787#L1455 assume !(0 != activate_threads_~tmp~1#1); 7353#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7354#L585 assume 1 == ~t1_pc~0; 7011#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7012#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8155#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8156#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 8500#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8496#L604 assume !(1 == ~t2_pc~0); 8061#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 8062#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7296#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7297#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8260#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8261#L623 assume 1 == ~t3_pc~0; 7527#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6873#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8130#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8131#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 8294#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6911#L642 assume !(1 == ~t4_pc~0); 6912#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 7364#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6966#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6967#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 6988#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8074#L661 assume 1 == ~t5_pc~0; 7144#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7145#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7992#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8359#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 8106#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8107#L680 assume !(1 == ~t6_pc~0); 7560#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 7561#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7287#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7288#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 8369#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8493#L699 assume 1 == ~t7_pc~0; 7955#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 7956#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8188#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 7848#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 7849#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7744#L718 assume !(1 == ~t8_pc~0); 7745#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 7125#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7126#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 7160#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 7161#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7293#L737 assume 1 == ~t9_pc~0; 8144#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 7424#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 7333#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 7334#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 7601#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 7602#L756 assume 1 == ~t10_pc~0; 8178#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 7839#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8094#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 7779#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 7403#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 7404#L775 assume !(1 == ~t11_pc~0); 7662#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 7663#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 8437#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 7059#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 7060#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 7241#L794 assume 1 == ~t12_pc~0; 7082#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 7062#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 6917#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 6918#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 7206#L1551-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7674#L1307 assume !(1 == ~M_E~0); 7675#L1307-2 assume !(1 == ~T1_E~0); 7783#L1312-1 assume !(1 == ~T2_E~0); 7703#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7704#L1322-1 assume !(1 == ~T4_E~0); 7414#L1327-1 assume !(1 == ~T5_E~0); 7415#L1332-1 assume !(1 == ~T6_E~0); 7960#L1337-1 assume !(1 == ~T7_E~0); 7917#L1342-1 assume !(1 == ~T8_E~0); 7918#L1347-1 assume !(1 == ~T9_E~0); 8330#L1352-1 assume !(1 == ~T10_E~0); 8189#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 7579#L1362-1 assume !(1 == ~T12_E~0); 7580#L1367-1 assume !(1 == ~E_1~0); 7221#L1372-1 assume !(1 == ~E_2~0); 7222#L1377-1 assume !(1 == ~E_3~0); 7512#L1382-1 assume !(1 == ~E_4~0); 7513#L1387-1 assume !(1 == ~E_5~0); 8063#L1392-1 assume !(1 == ~E_6~0); 7530#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 7531#L1402-1 assume !(1 == ~E_8~0); 7236#L1407-1 assume !(1 == ~E_9~0); 7237#L1412-1 assume !(1 == ~E_10~0); 8255#L1417-1 assume !(1 == ~E_11~0); 8256#L1422-1 assume !(1 == ~E_12~0); 8490#L1427-1 assume { :end_inline_reset_delta_events } true; 7043#L1768-2 [2024-11-08 17:07:19,738 INFO L747 eck$LassoCheckResult]: Loop: 7043#L1768-2 assume !false; 7044#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7707#L1149-1 assume !false; 8085#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 8312#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 7421#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 8237#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 8307#L976 assume !(0 != eval_~tmp~0#1); 7735#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7464#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7465#L1174-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8265#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8003#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8004#L1184-3 assume !(0 == ~T3_E~0); 8190#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7834#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7197#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7198#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 7434#L1209-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 6857#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 6858#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 7614#L1224-3 assume !(0 == ~T11_E~0); 7615#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 7629#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7053#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7054#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7489#L1249-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7947#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8440#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 8046#L1264-3 assume !(0 == ~E_7~0); 7057#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 7058#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 8470#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 7610#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 7611#L1289-3 assume 0 == ~E_12~0;~E_12~0 := 1; 7598#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7277#L566-39 assume 1 == ~m_pc~0; 7278#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 7877#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7878#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7930#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8121#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8122#L585-39 assume !(1 == ~t1_pc~0); 7285#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 7286#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7486#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8434#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8159#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7854#L604-39 assume !(1 == ~t2_pc~0); 7856#L604-41 is_transmit2_triggered_~__retres1~2#1 := 0; 7493#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7494#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7673#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7907#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7475#L623-39 assume 1 == ~t3_pc~0; 6874#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6875#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8139#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7328#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7329#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8081#L642-39 assume 1 == ~t4_pc~0; 7664#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7665#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7829#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7830#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8311#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7247#L661-39 assume 1 == ~t5_pc~0; 7248#L662-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6883#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7861#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7862#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8141#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8142#L680-39 assume 1 == ~t6_pc~0; 6949#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6950#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8390#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7401#L1503-39 assume !(0 != activate_threads_~tmp___5~0#1); 7402#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8446#L699-39 assume 1 == ~t7_pc~0; 7836#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 7563#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7564#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8146#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8386#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8383#L718-39 assume 1 == ~t8_pc~0; 7748#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 7749#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8242#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8243#L1519-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 7991#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7968#L737-39 assume 1 == ~t9_pc~0; 7382#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 7383#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6977#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 6978#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 8358#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8295#L756-39 assume !(1 == ~t10_pc~0); 7762#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 7763#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8433#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 7647#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 7648#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 6998#L775-39 assume 1 == ~t11_pc~0; 6999#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 7638#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 7639#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 7888#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 8039#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 7689#L794-39 assume !(1 == ~t12_pc~0); 7378#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 7379#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 7472#is_transmit12_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 7473#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 6940#L1551-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6941#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 8417#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8418#L1312-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8531#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8108#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8109#L1327-3 assume !(1 == ~T5_E~0); 7074#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 7049#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 7050#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 7777#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 7910#L1352-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 7911#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 8366#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 8526#L1367-3 assume !(1 == ~E_1~0); 8517#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6870#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6871#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7496#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7497#L1392-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8216#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8484#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 7876#L1407-3 assume !(1 == ~E_9~0); 7156#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 7157#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 7791#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 7792#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 7164#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 7165#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 7232#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 7233#L1787 assume !(0 == start_simulation_~tmp~3#1); 7880#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 8426#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 7141#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 6889#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 6890#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7482#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7483#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 8393#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 7043#L1768-2 [2024-11-08 17:07:19,739 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 17:07:19,739 INFO L85 PathProgramCache]: Analyzing trace with hash -1760586097, now seen corresponding path program 1 times [2024-11-08 17:07:19,743 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 17:07:19,743 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [299266705] [2024-11-08 17:07:19,744 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 17:07:19,744 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 17:07:19,772 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:07:19,879 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 17:07:19,879 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 17:07:19,879 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [299266705] [2024-11-08 17:07:19,880 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [299266705] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 17:07:19,880 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 17:07:19,880 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 17:07:19,880 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1149756505] [2024-11-08 17:07:19,880 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 17:07:19,881 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 17:07:19,881 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 17:07:19,881 INFO L85 PathProgramCache]: Analyzing trace with hash -109129765, now seen corresponding path program 1 times [2024-11-08 17:07:19,882 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 17:07:19,882 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [982501824] [2024-11-08 17:07:19,882 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 17:07:19,882 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 17:07:19,909 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:07:19,994 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 17:07:19,994 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 17:07:19,994 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [982501824] [2024-11-08 17:07:19,994 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [982501824] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 17:07:19,995 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 17:07:19,995 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 17:07:19,995 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [193724004] [2024-11-08 17:07:19,995 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 17:07:19,996 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 17:07:19,996 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 17:07:19,998 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 17:07:19,998 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 17:07:19,998 INFO L87 Difference]: Start difference. First operand 1701 states and 2516 transitions. cyclomatic complexity: 816 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 17:07:20,036 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 17:07:20,037 INFO L93 Difference]: Finished difference Result 1701 states and 2515 transitions. [2024-11-08 17:07:20,037 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1701 states and 2515 transitions. [2024-11-08 17:07:20,050 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1540 [2024-11-08 17:07:20,059 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1701 states to 1701 states and 2515 transitions. [2024-11-08 17:07:20,060 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1701 [2024-11-08 17:07:20,062 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1701 [2024-11-08 17:07:20,062 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1701 states and 2515 transitions. [2024-11-08 17:07:20,065 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 17:07:20,065 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1701 states and 2515 transitions. [2024-11-08 17:07:20,068 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1701 states and 2515 transitions. [2024-11-08 17:07:20,087 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1701 to 1701. [2024-11-08 17:07:20,091 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1701 states, 1701 states have (on average 1.4785420340975897) internal successors, (2515), 1700 states have internal predecessors, (2515), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 17:07:20,097 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1701 states to 1701 states and 2515 transitions. [2024-11-08 17:07:20,098 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1701 states and 2515 transitions. [2024-11-08 17:07:20,098 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 17:07:20,099 INFO L425 stractBuchiCegarLoop]: Abstraction has 1701 states and 2515 transitions. [2024-11-08 17:07:20,099 INFO L332 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-11-08 17:07:20,099 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1701 states and 2515 transitions. [2024-11-08 17:07:20,109 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1540 [2024-11-08 17:07:20,110 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 17:07:20,110 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 17:07:20,119 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 17:07:20,120 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 17:07:20,120 INFO L745 eck$LassoCheckResult]: Stem: 10520#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 10521#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 11313#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11314#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11181#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 11182#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11275#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11574#L831-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 11709#L836-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 11710#L841-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 10496#L846-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 10497#L851-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 11641#L856-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 11079#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 11080#L866-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 10990#L871-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 10991#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 11384#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10735#L1174 assume !(0 == ~M_E~0); 10736#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10587#L1179-1 assume !(0 == ~T2_E~0); 10493#L1184-1 assume !(0 == ~T3_E~0); 10494#L1189-1 assume !(0 == ~T4_E~0); 10536#L1194-1 assume !(0 == ~T5_E~0); 10629#L1199-1 assume !(0 == ~T6_E~0); 11508#L1204-1 assume !(0 == ~T7_E~0); 11429#L1209-1 assume !(0 == ~T8_E~0); 11430#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 11853#L1219-1 assume !(0 == ~T10_E~0); 11938#L1224-1 assume !(0 == ~T11_E~0); 10852#L1229-1 assume !(0 == ~T12_E~0); 10423#L1234-1 assume !(0 == ~E_1~0); 10424#L1239-1 assume !(0 == ~E_2~0); 10456#L1244-1 assume !(0 == ~E_3~0); 10457#L1249-1 assume !(0 == ~E_4~0); 11099#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 10353#L1259-1 assume !(0 == ~E_6~0); 10306#L1264-1 assume !(0 == ~E_7~0); 10307#L1269-1 assume !(0 == ~E_8~0); 11941#L1274-1 assume !(0 == ~E_9~0); 11880#L1279-1 assume !(0 == ~E_10~0); 10540#L1284-1 assume !(0 == ~E_11~0); 10541#L1289-1 assume !(0 == ~E_12~0); 11151#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11152#L566 assume 1 == ~m_pc~0; 10323#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 10324#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11195#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11196#L1455 assume !(0 != activate_threads_~tmp~1#1); 10762#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10763#L585 assume 1 == ~t1_pc~0; 10420#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10421#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11564#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11565#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 11909#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11905#L604 assume !(1 == ~t2_pc~0); 11470#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 11471#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10705#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10706#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11669#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11670#L623 assume 1 == ~t3_pc~0; 10936#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10282#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11539#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11540#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 11703#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10320#L642 assume !(1 == ~t4_pc~0); 10321#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 10773#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10375#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10376#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 10397#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11483#L661 assume 1 == ~t5_pc~0; 10553#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10554#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11401#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 11768#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 11515#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11516#L680 assume !(1 == ~t6_pc~0); 10969#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 10970#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10696#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10697#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 11778#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11902#L699 assume 1 == ~t7_pc~0; 11364#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11365#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11597#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 11257#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 11258#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11153#L718 assume !(1 == ~t8_pc~0); 11154#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 10534#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10535#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 10569#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 10570#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 10702#L737 assume 1 == ~t9_pc~0; 11553#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 10833#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 10742#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 10743#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 11010#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 11011#L756 assume 1 == ~t10_pc~0; 11587#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 11248#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 11503#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 11188#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 10812#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 10813#L775 assume !(1 == ~t11_pc~0); 11071#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 11072#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 11846#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 10468#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 10469#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 10650#L794 assume 1 == ~t12_pc~0; 10491#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 10471#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 10326#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 10327#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 10615#L1551-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11083#L1307 assume !(1 == ~M_E~0); 11084#L1307-2 assume !(1 == ~T1_E~0); 11192#L1312-1 assume !(1 == ~T2_E~0); 11112#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11113#L1322-1 assume !(1 == ~T4_E~0); 10823#L1327-1 assume !(1 == ~T5_E~0); 10824#L1332-1 assume !(1 == ~T6_E~0); 11369#L1337-1 assume !(1 == ~T7_E~0); 11326#L1342-1 assume !(1 == ~T8_E~0); 11327#L1347-1 assume !(1 == ~T9_E~0); 11739#L1352-1 assume !(1 == ~T10_E~0); 11598#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 10988#L1362-1 assume !(1 == ~T12_E~0); 10989#L1367-1 assume !(1 == ~E_1~0); 10630#L1372-1 assume !(1 == ~E_2~0); 10631#L1377-1 assume !(1 == ~E_3~0); 10921#L1382-1 assume !(1 == ~E_4~0); 10922#L1387-1 assume !(1 == ~E_5~0); 11472#L1392-1 assume !(1 == ~E_6~0); 10939#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 10940#L1402-1 assume !(1 == ~E_8~0); 10645#L1407-1 assume !(1 == ~E_9~0); 10646#L1412-1 assume !(1 == ~E_10~0); 11664#L1417-1 assume !(1 == ~E_11~0); 11665#L1422-1 assume !(1 == ~E_12~0); 11899#L1427-1 assume { :end_inline_reset_delta_events } true; 10452#L1768-2 [2024-11-08 17:07:20,121 INFO L747 eck$LassoCheckResult]: Loop: 10452#L1768-2 assume !false; 10453#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 11116#L1149-1 assume !false; 11494#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 11721#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 10830#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 11646#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 11716#L976 assume !(0 != eval_~tmp~0#1); 11144#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10873#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10874#L1174-3 assume 0 == ~M_E~0;~M_E~0 := 1; 11674#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11412#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11413#L1184-3 assume !(0 == ~T3_E~0); 11599#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11243#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10606#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10607#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 10843#L1209-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 10266#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 10267#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 11023#L1224-3 assume !(0 == ~T11_E~0); 11024#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 11038#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10462#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10463#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10898#L1249-3 assume 0 == ~E_4~0;~E_4~0 := 1; 11356#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 11849#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 11455#L1264-3 assume !(0 == ~E_7~0); 10466#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 10467#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 11879#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 11019#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 11020#L1289-3 assume 0 == ~E_12~0;~E_12~0 := 1; 11007#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10686#L566-39 assume !(1 == ~m_pc~0); 10688#L566-41 is_master_triggered_~__retres1~0#1 := 0; 11286#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11287#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11339#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 11530#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11531#L585-39 assume !(1 == ~t1_pc~0); 10694#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 10695#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10895#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11843#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11568#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11263#L604-39 assume 1 == ~t2_pc~0; 11264#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10902#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10903#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11082#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11316#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10884#L623-39 assume 1 == ~t3_pc~0; 10283#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10284#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11548#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10737#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 10738#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11490#L642-39 assume 1 == ~t4_pc~0; 11073#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 11074#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11238#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11239#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 11720#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10656#L661-39 assume 1 == ~t5_pc~0; 10657#L662-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10292#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11270#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 11271#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 11550#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11551#L680-39 assume 1 == ~t6_pc~0; 10358#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10359#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11799#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10810#L1503-39 assume !(0 != activate_threads_~tmp___5~0#1); 10811#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11855#L699-39 assume 1 == ~t7_pc~0; 11245#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 10972#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10973#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 11555#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 11795#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11792#L718-39 assume 1 == ~t8_pc~0; 11157#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 11158#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 11651#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 11652#L1519-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 11400#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11377#L737-39 assume 1 == ~t9_pc~0; 10791#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 10792#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 10386#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 10387#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 11767#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 11704#L756-39 assume !(1 == ~t10_pc~0); 11171#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 11172#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 11842#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 11056#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 11057#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 10407#L775-39 assume 1 == ~t11_pc~0; 10408#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 11047#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 11048#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 11297#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 11448#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 11098#L794-39 assume !(1 == ~t12_pc~0); 10787#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 10788#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 10881#is_transmit12_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 10882#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 10349#L1551-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10350#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 11826#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11827#L1312-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11940#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11517#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11518#L1327-3 assume !(1 == ~T5_E~0); 10483#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10458#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 10459#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 11186#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 11319#L1352-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 11320#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 11775#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 11935#L1367-3 assume !(1 == ~E_1~0); 11926#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10279#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10280#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10905#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 10906#L1392-3 assume 1 == ~E_6~0;~E_6~0 := 2; 11625#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 11893#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 11285#L1407-3 assume !(1 == ~E_9~0); 10565#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 10566#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 11200#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 11201#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 10573#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 10574#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 10641#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 10642#L1787 assume !(0 == start_simulation_~tmp~3#1); 11289#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 11835#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 10550#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 10298#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 10299#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10891#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10892#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 11802#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 10452#L1768-2 [2024-11-08 17:07:20,122 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 17:07:20,122 INFO L85 PathProgramCache]: Analyzing trace with hash -1220156591, now seen corresponding path program 1 times [2024-11-08 17:07:20,122 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 17:07:20,123 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [613119657] [2024-11-08 17:07:20,123 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 17:07:20,123 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 17:07:20,145 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:07:20,209 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 17:07:20,209 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 17:07:20,209 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [613119657] [2024-11-08 17:07:20,210 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [613119657] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 17:07:20,210 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 17:07:20,210 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 17:07:20,211 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1892081909] [2024-11-08 17:07:20,211 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 17:07:20,212 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 17:07:20,213 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 17:07:20,214 INFO L85 PathProgramCache]: Analyzing trace with hash -691381925, now seen corresponding path program 1 times [2024-11-08 17:07:20,214 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 17:07:20,214 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1382988921] [2024-11-08 17:07:20,215 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 17:07:20,215 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 17:07:20,240 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:07:20,325 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 17:07:20,327 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 17:07:20,327 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1382988921] [2024-11-08 17:07:20,327 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1382988921] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 17:07:20,327 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 17:07:20,328 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 17:07:20,328 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [428555686] [2024-11-08 17:07:20,329 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 17:07:20,329 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 17:07:20,329 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 17:07:20,330 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 17:07:20,330 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 17:07:20,330 INFO L87 Difference]: Start difference. First operand 1701 states and 2515 transitions. cyclomatic complexity: 815 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 17:07:20,381 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 17:07:20,381 INFO L93 Difference]: Finished difference Result 1701 states and 2514 transitions. [2024-11-08 17:07:20,381 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1701 states and 2514 transitions. [2024-11-08 17:07:20,392 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1540 [2024-11-08 17:07:20,400 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1701 states to 1701 states and 2514 transitions. [2024-11-08 17:07:20,401 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1701 [2024-11-08 17:07:20,402 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1701 [2024-11-08 17:07:20,402 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1701 states and 2514 transitions. [2024-11-08 17:07:20,405 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 17:07:20,405 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1701 states and 2514 transitions. [2024-11-08 17:07:20,407 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1701 states and 2514 transitions. [2024-11-08 17:07:20,427 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1701 to 1701. [2024-11-08 17:07:20,432 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1701 states, 1701 states have (on average 1.4779541446208113) internal successors, (2514), 1700 states have internal predecessors, (2514), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 17:07:20,438 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1701 states to 1701 states and 2514 transitions. [2024-11-08 17:07:20,438 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1701 states and 2514 transitions. [2024-11-08 17:07:20,438 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 17:07:20,440 INFO L425 stractBuchiCegarLoop]: Abstraction has 1701 states and 2514 transitions. [2024-11-08 17:07:20,440 INFO L332 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-11-08 17:07:20,440 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1701 states and 2514 transitions. [2024-11-08 17:07:20,448 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1540 [2024-11-08 17:07:20,449 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 17:07:20,449 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 17:07:20,455 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 17:07:20,455 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 17:07:20,455 INFO L745 eck$LassoCheckResult]: Stem: 13929#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 13930#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 14723#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14724#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14590#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 14591#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14684#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14988#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15118#L836-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 15119#L841-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 13905#L846-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 13906#L851-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 15050#L856-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 14488#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 14489#L866-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 14401#L871-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 14402#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 14793#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14144#L1174 assume !(0 == ~M_E~0); 14145#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13998#L1179-1 assume !(0 == ~T2_E~0); 13902#L1184-1 assume !(0 == ~T3_E~0); 13903#L1189-1 assume !(0 == ~T4_E~0); 13945#L1194-1 assume !(0 == ~T5_E~0); 14040#L1199-1 assume !(0 == ~T6_E~0); 14917#L1204-1 assume !(0 == ~T7_E~0); 14838#L1209-1 assume !(0 == ~T8_E~0); 14839#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 15262#L1219-1 assume !(0 == ~T10_E~0); 15347#L1224-1 assume !(0 == ~T11_E~0); 14263#L1229-1 assume !(0 == ~T12_E~0); 13832#L1234-1 assume !(0 == ~E_1~0); 13833#L1239-1 assume !(0 == ~E_2~0); 13867#L1244-1 assume !(0 == ~E_3~0); 13868#L1249-1 assume !(0 == ~E_4~0); 14508#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 13762#L1259-1 assume !(0 == ~E_6~0); 13715#L1264-1 assume !(0 == ~E_7~0); 13716#L1269-1 assume !(0 == ~E_8~0); 15350#L1274-1 assume !(0 == ~E_9~0); 15290#L1279-1 assume !(0 == ~E_10~0); 13949#L1284-1 assume !(0 == ~E_11~0); 13950#L1289-1 assume !(0 == ~E_12~0); 14560#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14561#L566 assume 1 == ~m_pc~0; 13732#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 13733#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14604#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14605#L1455 assume !(0 != activate_threads_~tmp~1#1); 14171#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14172#L585 assume 1 == ~t1_pc~0; 13829#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 13830#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14973#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14974#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 15318#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15314#L604 assume !(1 == ~t2_pc~0); 14879#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 14880#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14119#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14120#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 15080#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15081#L623 assume 1 == ~t3_pc~0; 14345#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 13691#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14951#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14952#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 15112#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13729#L642 assume !(1 == ~t4_pc~0); 13730#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 14182#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13790#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13791#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 13806#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14892#L661 assume 1 == ~t5_pc~0; 13962#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 13963#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14810#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 15177#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 14926#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14927#L680 assume !(1 == ~t6_pc~0); 14378#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 14379#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14108#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14109#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 15187#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15312#L699 assume 1 == ~t7_pc~0; 14773#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14774#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15006#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 14666#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 14667#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14562#L718 assume !(1 == ~t8_pc~0); 14563#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 13943#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 13944#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 13980#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 13981#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 14111#L737 assume 1 == ~t9_pc~0; 14964#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 14244#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14151#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 14152#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 14419#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 14420#L756 assume 1 == ~t10_pc~0; 14996#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 14658#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 14912#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 14597#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 14221#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 14222#L775 assume !(1 == ~t11_pc~0); 14480#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 14481#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 15255#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 13877#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 13878#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 14059#L794 assume 1 == ~t12_pc~0; 13901#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 13880#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 13737#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 13738#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 14026#L1551-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14492#L1307 assume !(1 == ~M_E~0); 14493#L1307-2 assume !(1 == ~T1_E~0); 14601#L1312-1 assume !(1 == ~T2_E~0); 14521#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14522#L1322-1 assume !(1 == ~T4_E~0); 14232#L1327-1 assume !(1 == ~T5_E~0); 14233#L1332-1 assume !(1 == ~T6_E~0); 14778#L1337-1 assume !(1 == ~T7_E~0); 14736#L1342-1 assume !(1 == ~T8_E~0); 14737#L1347-1 assume !(1 == ~T9_E~0); 15148#L1352-1 assume !(1 == ~T10_E~0); 15007#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 14397#L1362-1 assume !(1 == ~T12_E~0); 14398#L1367-1 assume !(1 == ~E_1~0); 14041#L1372-1 assume !(1 == ~E_2~0); 14042#L1377-1 assume !(1 == ~E_3~0); 14330#L1382-1 assume !(1 == ~E_4~0); 14331#L1387-1 assume !(1 == ~E_5~0); 14881#L1392-1 assume !(1 == ~E_6~0); 14350#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 14351#L1402-1 assume !(1 == ~E_8~0); 14057#L1407-1 assume !(1 == ~E_9~0); 14058#L1412-1 assume !(1 == ~E_10~0); 15073#L1417-1 assume !(1 == ~E_11~0); 15074#L1422-1 assume !(1 == ~E_12~0); 15308#L1427-1 assume { :end_inline_reset_delta_events } true; 13861#L1768-2 [2024-11-08 17:07:20,456 INFO L747 eck$LassoCheckResult]: Loop: 13861#L1768-2 assume !false; 13862#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 14525#L1149-1 assume !false; 14905#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 15130#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 14239#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 15055#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 15125#L976 assume !(0 != eval_~tmp~0#1); 14553#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14282#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14283#L1174-3 assume 0 == ~M_E~0;~M_E~0 := 1; 15083#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14821#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 14822#L1184-3 assume !(0 == ~T3_E~0); 15009#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14652#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14018#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 14019#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 14252#L1209-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 13675#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 13676#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 14432#L1224-3 assume !(0 == ~T11_E~0); 14433#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 14447#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 13869#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13870#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14307#L1249-3 assume 0 == ~E_4~0;~E_4~0 := 1; 14765#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 15258#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 14864#L1264-3 assume !(0 == ~E_7~0); 13875#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 13876#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 15288#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 14428#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 14429#L1289-3 assume 0 == ~E_12~0;~E_12~0 := 1; 14416#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14095#L566-39 assume 1 == ~m_pc~0; 14096#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 14695#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14696#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14748#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14939#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14940#L585-39 assume !(1 == ~t1_pc~0); 14103#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 14104#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14304#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15252#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14977#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14672#L604-39 assume 1 == ~t2_pc~0; 14673#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14311#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14312#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14491#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14725#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14293#L623-39 assume 1 == ~t3_pc~0; 13692#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 13693#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14957#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14146#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 14147#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14899#L642-39 assume 1 == ~t4_pc~0; 14482#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 14483#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14647#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14648#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 15129#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14065#L661-39 assume 1 == ~t5_pc~0; 14066#L662-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 13701#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14679#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14680#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 14959#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14960#L680-39 assume 1 == ~t6_pc~0; 13767#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13768#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15208#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14219#L1503-39 assume !(0 != activate_threads_~tmp___5~0#1); 14220#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15264#L699-39 assume 1 == ~t7_pc~0; 14654#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14381#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14382#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 14963#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 15204#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15201#L718-39 assume 1 == ~t8_pc~0; 14566#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 14567#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15060#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 15061#L1519-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 14809#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 14786#L737-39 assume 1 == ~t9_pc~0; 14200#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 14201#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 13795#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 13796#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 15176#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 15113#L756-39 assume !(1 == ~t10_pc~0); 14580#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 14581#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 15251#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 14465#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 14466#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 13816#L775-39 assume 1 == ~t11_pc~0; 13817#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 14456#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 14457#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 14706#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 14857#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 14507#L794-39 assume !(1 == ~t12_pc~0); 14196#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 14197#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 14290#is_transmit12_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 14291#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 13758#L1551-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13759#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 15235#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15236#L1312-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15349#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14924#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14925#L1327-3 assume !(1 == ~T5_E~0); 13892#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 13865#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 13866#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 14595#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 14728#L1352-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 14729#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 15184#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 15344#L1367-3 assume !(1 == ~E_1~0); 15335#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 13685#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 13686#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14314#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14315#L1392-3 assume 1 == ~E_6~0;~E_6~0 := 2; 15034#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 15302#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 14694#L1407-3 assume !(1 == ~E_9~0); 13974#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 13975#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 14609#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 14610#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 13982#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 13983#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 14050#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 14051#L1787 assume !(0 == start_simulation_~tmp~3#1); 14698#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 15244#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 13959#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 13704#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 13705#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 14300#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14301#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 15211#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 13861#L1768-2 [2024-11-08 17:07:20,456 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 17:07:20,457 INFO L85 PathProgramCache]: Analyzing trace with hash -1064176049, now seen corresponding path program 1 times [2024-11-08 17:07:20,457 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 17:07:20,457 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1512643429] [2024-11-08 17:07:20,457 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 17:07:20,457 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 17:07:20,494 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:07:20,541 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 17:07:20,542 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 17:07:20,542 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1512643429] [2024-11-08 17:07:20,542 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1512643429] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 17:07:20,542 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 17:07:20,542 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 17:07:20,543 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [792593870] [2024-11-08 17:07:20,543 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 17:07:20,543 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 17:07:20,543 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 17:07:20,543 INFO L85 PathProgramCache]: Analyzing trace with hash 1128523324, now seen corresponding path program 1 times [2024-11-08 17:07:20,544 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 17:07:20,544 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [385259967] [2024-11-08 17:07:20,544 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 17:07:20,544 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 17:07:20,566 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:07:20,622 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 17:07:20,622 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 17:07:20,622 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [385259967] [2024-11-08 17:07:20,622 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [385259967] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 17:07:20,623 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 17:07:20,623 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 17:07:20,623 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1882471025] [2024-11-08 17:07:20,624 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 17:07:20,624 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 17:07:20,624 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 17:07:20,625 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 17:07:20,625 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 17:07:20,625 INFO L87 Difference]: Start difference. First operand 1701 states and 2514 transitions. cyclomatic complexity: 814 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 17:07:20,660 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 17:07:20,660 INFO L93 Difference]: Finished difference Result 1701 states and 2513 transitions. [2024-11-08 17:07:20,660 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1701 states and 2513 transitions. [2024-11-08 17:07:20,673 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1540 [2024-11-08 17:07:20,682 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1701 states to 1701 states and 2513 transitions. [2024-11-08 17:07:20,682 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1701 [2024-11-08 17:07:20,684 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1701 [2024-11-08 17:07:20,685 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1701 states and 2513 transitions. [2024-11-08 17:07:20,687 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 17:07:20,688 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1701 states and 2513 transitions. [2024-11-08 17:07:20,690 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1701 states and 2513 transitions. [2024-11-08 17:07:20,708 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1701 to 1701. [2024-11-08 17:07:20,711 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1701 states, 1701 states have (on average 1.477366255144033) internal successors, (2513), 1700 states have internal predecessors, (2513), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 17:07:20,717 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1701 states to 1701 states and 2513 transitions. [2024-11-08 17:07:20,717 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1701 states and 2513 transitions. [2024-11-08 17:07:20,717 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 17:07:20,718 INFO L425 stractBuchiCegarLoop]: Abstraction has 1701 states and 2513 transitions. [2024-11-08 17:07:20,718 INFO L332 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-11-08 17:07:20,718 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1701 states and 2513 transitions. [2024-11-08 17:07:20,726 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1540 [2024-11-08 17:07:20,726 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 17:07:20,726 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 17:07:20,729 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 17:07:20,730 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 17:07:20,731 INFO L745 eck$LassoCheckResult]: Stem: 17338#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 17339#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 18131#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 18132#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 17999#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 18000#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 18093#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 18394#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 18527#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 18528#L841-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 17314#L846-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 17315#L851-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 18459#L856-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 17897#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 17898#L866-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 17808#L871-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 17809#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 18202#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 17553#L1174 assume !(0 == ~M_E~0); 17554#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 17407#L1179-1 assume !(0 == ~T2_E~0); 17311#L1184-1 assume !(0 == ~T3_E~0); 17312#L1189-1 assume !(0 == ~T4_E~0); 17354#L1194-1 assume !(0 == ~T5_E~0); 17449#L1199-1 assume !(0 == ~T6_E~0); 18326#L1204-1 assume !(0 == ~T7_E~0); 18247#L1209-1 assume !(0 == ~T8_E~0); 18248#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 18671#L1219-1 assume !(0 == ~T10_E~0); 18756#L1224-1 assume !(0 == ~T11_E~0); 17670#L1229-1 assume !(0 == ~T12_E~0); 17241#L1234-1 assume !(0 == ~E_1~0); 17242#L1239-1 assume !(0 == ~E_2~0); 17276#L1244-1 assume !(0 == ~E_3~0); 17277#L1249-1 assume !(0 == ~E_4~0); 17917#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 17171#L1259-1 assume !(0 == ~E_6~0); 17124#L1264-1 assume !(0 == ~E_7~0); 17125#L1269-1 assume !(0 == ~E_8~0); 18759#L1274-1 assume !(0 == ~E_9~0); 18699#L1279-1 assume !(0 == ~E_10~0); 17358#L1284-1 assume !(0 == ~E_11~0); 17359#L1289-1 assume !(0 == ~E_12~0); 17969#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17970#L566 assume 1 == ~m_pc~0; 17141#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 17142#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18013#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 18014#L1455 assume !(0 != activate_threads_~tmp~1#1); 17580#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17581#L585 assume 1 == ~t1_pc~0; 17238#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 17239#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18382#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 18383#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 18727#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18723#L604 assume !(1 == ~t2_pc~0); 18288#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 18289#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17528#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17529#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 18489#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18490#L623 assume 1 == ~t3_pc~0; 17754#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 17100#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18360#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18361#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 18521#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17138#L642 assume !(1 == ~t4_pc~0); 17139#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 17591#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17196#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17197#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 17215#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18301#L661 assume 1 == ~t5_pc~0; 17371#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 17372#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18219#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 18586#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 18335#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18336#L680 assume !(1 == ~t6_pc~0); 17787#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 17788#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17514#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17515#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 18596#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18721#L699 assume 1 == ~t7_pc~0; 18182#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 18183#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 18415#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 18075#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 18076#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17971#L718 assume !(1 == ~t8_pc~0); 17972#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 17352#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17353#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 17387#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 17388#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 17520#L737 assume 1 == ~t9_pc~0; 18373#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 17651#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17560#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 17561#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 17828#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 17829#L756 assume 1 == ~t10_pc~0; 18405#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 18066#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 18321#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 18006#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 17630#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 17631#L775 assume !(1 == ~t11_pc~0); 17889#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 17890#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 18664#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 17286#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 17287#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 17468#L794 assume 1 == ~t12_pc~0; 17310#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 17289#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 17146#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 17147#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 17435#L1551-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17901#L1307 assume !(1 == ~M_E~0); 17902#L1307-2 assume !(1 == ~T1_E~0); 18010#L1312-1 assume !(1 == ~T2_E~0); 17930#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17931#L1322-1 assume !(1 == ~T4_E~0); 17641#L1327-1 assume !(1 == ~T5_E~0); 17642#L1332-1 assume !(1 == ~T6_E~0); 18187#L1337-1 assume !(1 == ~T7_E~0); 18144#L1342-1 assume !(1 == ~T8_E~0); 18145#L1347-1 assume !(1 == ~T9_E~0); 18557#L1352-1 assume !(1 == ~T10_E~0); 18416#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 17806#L1362-1 assume !(1 == ~T12_E~0); 17807#L1367-1 assume !(1 == ~E_1~0); 17450#L1372-1 assume !(1 == ~E_2~0); 17451#L1377-1 assume !(1 == ~E_3~0); 17739#L1382-1 assume !(1 == ~E_4~0); 17740#L1387-1 assume !(1 == ~E_5~0); 18290#L1392-1 assume !(1 == ~E_6~0); 17759#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 17760#L1402-1 assume !(1 == ~E_8~0); 17463#L1407-1 assume !(1 == ~E_9~0); 17464#L1412-1 assume !(1 == ~E_10~0); 18482#L1417-1 assume !(1 == ~E_11~0); 18483#L1422-1 assume !(1 == ~E_12~0); 18717#L1427-1 assume { :end_inline_reset_delta_events } true; 17270#L1768-2 [2024-11-08 17:07:20,731 INFO L747 eck$LassoCheckResult]: Loop: 17270#L1768-2 assume !false; 17271#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 17934#L1149-1 assume !false; 18314#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 18539#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 17648#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 18464#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 18534#L976 assume !(0 != eval_~tmp~0#1); 17962#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 17691#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 17692#L1174-3 assume 0 == ~M_E~0;~M_E~0 := 1; 18492#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 18230#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 18231#L1184-3 assume !(0 == ~T3_E~0); 18417#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 18061#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 17427#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 17428#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 17661#L1209-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 17084#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 17085#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 17841#L1224-3 assume !(0 == ~T11_E~0); 17842#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 17856#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 17280#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 17281#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 17716#L1249-3 assume 0 == ~E_4~0;~E_4~0 := 1; 18174#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 18667#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 18273#L1264-3 assume !(0 == ~E_7~0); 17284#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 17285#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 18697#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 17837#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 17838#L1289-3 assume 0 == ~E_12~0;~E_12~0 := 1; 17825#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17504#L566-39 assume 1 == ~m_pc~0; 17505#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 18104#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18105#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 18157#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 18348#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18349#L585-39 assume !(1 == ~t1_pc~0); 17512#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 17513#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17713#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 18661#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 18386#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18081#L604-39 assume 1 == ~t2_pc~0; 18082#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 17720#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17721#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17900#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 18138#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17702#L623-39 assume !(1 == ~t3_pc~0); 17105#L623-41 is_transmit3_triggered_~__retres1~3#1 := 0; 17104#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18366#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17555#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17556#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 18308#L642-39 assume 1 == ~t4_pc~0; 17893#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 17894#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18056#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18057#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 18538#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17473#L661-39 assume 1 == ~t5_pc~0; 17474#L662-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 17107#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18088#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 18089#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 18368#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18369#L680-39 assume 1 == ~t6_pc~0; 17176#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 17177#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18617#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17628#L1503-39 assume !(0 != activate_threads_~tmp___5~0#1); 17629#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18673#L699-39 assume !(1 == ~t7_pc~0); 18064#L699-41 is_transmit7_triggered_~__retres1~7#1 := 0; 17790#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17791#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 18372#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 18611#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18610#L718-39 assume 1 == ~t8_pc~0; 17975#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 17976#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 18468#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 18469#L1519-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 18218#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 18195#L737-39 assume 1 == ~t9_pc~0; 17609#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 17610#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17203#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 17204#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 18585#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 18522#L756-39 assume !(1 == ~t10_pc~0); 17989#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 17990#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 18660#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 17874#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 17875#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 17225#L775-39 assume 1 == ~t11_pc~0; 17226#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 17865#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 17866#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 18115#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 18266#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 17916#L794-39 assume !(1 == ~t12_pc~0); 17605#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 17606#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 17697#is_transmit12_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 17698#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 17167#L1551-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17168#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 18644#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 18645#L1312-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 18758#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 18333#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 18334#L1327-3 assume !(1 == ~T5_E~0); 17299#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 17274#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 17275#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 18004#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 18136#L1352-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 18137#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 18593#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 18753#L1367-3 assume !(1 == ~E_1~0); 18744#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 17094#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 17095#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 17723#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 17724#L1392-3 assume 1 == ~E_6~0;~E_6~0 := 2; 18443#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 18711#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 18103#L1407-3 assume !(1 == ~E_9~0); 17383#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 17384#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 18017#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 18018#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 17391#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 17392#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 17459#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 17460#L1787 assume !(0 == start_simulation_~tmp~3#1); 18106#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 18653#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 17368#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 17113#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 17114#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 17709#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 17710#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 18620#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 17270#L1768-2 [2024-11-08 17:07:20,732 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 17:07:20,732 INFO L85 PathProgramCache]: Analyzing trace with hash -1474786415, now seen corresponding path program 1 times [2024-11-08 17:07:20,732 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 17:07:20,732 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1612718849] [2024-11-08 17:07:20,733 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 17:07:20,733 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 17:07:20,748 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:07:20,794 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 17:07:20,794 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 17:07:20,794 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1612718849] [2024-11-08 17:07:20,795 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1612718849] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 17:07:20,795 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 17:07:20,796 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 17:07:20,796 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1242278215] [2024-11-08 17:07:20,796 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 17:07:20,796 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 17:07:20,796 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 17:07:20,797 INFO L85 PathProgramCache]: Analyzing trace with hash 926444794, now seen corresponding path program 1 times [2024-11-08 17:07:20,797 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 17:07:20,797 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [238442220] [2024-11-08 17:07:20,797 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 17:07:20,797 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 17:07:20,822 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:07:20,892 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 17:07:20,893 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 17:07:20,893 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [238442220] [2024-11-08 17:07:20,893 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [238442220] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 17:07:20,893 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 17:07:20,894 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 17:07:20,894 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1879369813] [2024-11-08 17:07:20,894 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 17:07:20,894 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 17:07:20,895 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 17:07:20,895 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 17:07:20,895 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 17:07:20,896 INFO L87 Difference]: Start difference. First operand 1701 states and 2513 transitions. cyclomatic complexity: 813 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 17:07:20,929 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 17:07:20,929 INFO L93 Difference]: Finished difference Result 1701 states and 2512 transitions. [2024-11-08 17:07:20,929 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1701 states and 2512 transitions. [2024-11-08 17:07:20,939 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1540 [2024-11-08 17:07:20,947 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1701 states to 1701 states and 2512 transitions. [2024-11-08 17:07:20,947 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1701 [2024-11-08 17:07:20,949 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1701 [2024-11-08 17:07:20,949 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1701 states and 2512 transitions. [2024-11-08 17:07:20,951 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 17:07:20,952 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1701 states and 2512 transitions. [2024-11-08 17:07:20,954 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1701 states and 2512 transitions. [2024-11-08 17:07:20,971 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1701 to 1701. [2024-11-08 17:07:20,975 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1701 states, 1701 states have (on average 1.4767783656672546) internal successors, (2512), 1700 states have internal predecessors, (2512), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 17:07:20,980 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1701 states to 1701 states and 2512 transitions. [2024-11-08 17:07:20,981 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1701 states and 2512 transitions. [2024-11-08 17:07:20,983 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 17:07:20,984 INFO L425 stractBuchiCegarLoop]: Abstraction has 1701 states and 2512 transitions. [2024-11-08 17:07:20,984 INFO L332 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-11-08 17:07:20,984 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1701 states and 2512 transitions. [2024-11-08 17:07:21,027 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1540 [2024-11-08 17:07:21,029 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 17:07:21,029 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 17:07:21,031 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 17:07:21,032 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 17:07:21,032 INFO L745 eck$LassoCheckResult]: Stem: 20747#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 20748#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 21540#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 21541#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21408#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 21409#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21502#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21801#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21936#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 21937#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 20723#L846-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 20724#L851-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 21868#L856-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 21306#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 21307#L866-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 21217#L871-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 21218#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 21611#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20962#L1174 assume !(0 == ~M_E~0); 20963#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 20814#L1179-1 assume !(0 == ~T2_E~0); 20720#L1184-1 assume !(0 == ~T3_E~0); 20721#L1189-1 assume !(0 == ~T4_E~0); 20763#L1194-1 assume !(0 == ~T5_E~0); 20856#L1199-1 assume !(0 == ~T6_E~0); 21735#L1204-1 assume !(0 == ~T7_E~0); 21656#L1209-1 assume !(0 == ~T8_E~0); 21657#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 22080#L1219-1 assume !(0 == ~T10_E~0); 22165#L1224-1 assume !(0 == ~T11_E~0); 21079#L1229-1 assume !(0 == ~T12_E~0); 20650#L1234-1 assume !(0 == ~E_1~0); 20651#L1239-1 assume !(0 == ~E_2~0); 20683#L1244-1 assume !(0 == ~E_3~0); 20684#L1249-1 assume !(0 == ~E_4~0); 21326#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 20580#L1259-1 assume !(0 == ~E_6~0); 20533#L1264-1 assume !(0 == ~E_7~0); 20534#L1269-1 assume !(0 == ~E_8~0); 22168#L1274-1 assume !(0 == ~E_9~0); 22107#L1279-1 assume !(0 == ~E_10~0); 20767#L1284-1 assume !(0 == ~E_11~0); 20768#L1289-1 assume !(0 == ~E_12~0); 21378#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21379#L566 assume 1 == ~m_pc~0; 20550#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 20551#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21422#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 21423#L1455 assume !(0 != activate_threads_~tmp~1#1); 20989#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20990#L585 assume 1 == ~t1_pc~0; 20647#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 20648#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21791#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 21792#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 22136#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22132#L604 assume !(1 == ~t2_pc~0); 21697#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 21698#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20932#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20933#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 21896#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21897#L623 assume 1 == ~t3_pc~0; 21163#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 20509#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21766#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21767#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 21930#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20547#L642 assume !(1 == ~t4_pc~0); 20548#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 21000#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20602#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20603#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 20624#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 21710#L661 assume 1 == ~t5_pc~0; 20780#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 20781#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21628#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 21995#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 21742#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 21743#L680 assume !(1 == ~t6_pc~0); 21196#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 21197#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 20923#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20924#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 22005#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 22129#L699 assume 1 == ~t7_pc~0; 21591#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 21592#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 21824#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21484#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 21485#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21380#L718 assume !(1 == ~t8_pc~0); 21381#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 20761#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20762#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 20796#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 20797#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 20929#L737 assume 1 == ~t9_pc~0; 21780#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 21060#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 20969#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 20970#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 21237#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21238#L756 assume 1 == ~t10_pc~0; 21814#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 21475#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 21730#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 21415#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 21039#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 21040#L775 assume !(1 == ~t11_pc~0); 21298#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 21299#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 22073#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 20695#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 20696#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 20877#L794 assume 1 == ~t12_pc~0; 20718#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 20698#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 20553#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 20554#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 20842#L1551-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21310#L1307 assume !(1 == ~M_E~0); 21311#L1307-2 assume !(1 == ~T1_E~0); 21419#L1312-1 assume !(1 == ~T2_E~0); 21339#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 21340#L1322-1 assume !(1 == ~T4_E~0); 21050#L1327-1 assume !(1 == ~T5_E~0); 21051#L1332-1 assume !(1 == ~T6_E~0); 21596#L1337-1 assume !(1 == ~T7_E~0); 21553#L1342-1 assume !(1 == ~T8_E~0); 21554#L1347-1 assume !(1 == ~T9_E~0); 21966#L1352-1 assume !(1 == ~T10_E~0); 21825#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 21215#L1362-1 assume !(1 == ~T12_E~0); 21216#L1367-1 assume !(1 == ~E_1~0); 20857#L1372-1 assume !(1 == ~E_2~0); 20858#L1377-1 assume !(1 == ~E_3~0); 21148#L1382-1 assume !(1 == ~E_4~0); 21149#L1387-1 assume !(1 == ~E_5~0); 21699#L1392-1 assume !(1 == ~E_6~0); 21166#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 21167#L1402-1 assume !(1 == ~E_8~0); 20872#L1407-1 assume !(1 == ~E_9~0); 20873#L1412-1 assume !(1 == ~E_10~0); 21891#L1417-1 assume !(1 == ~E_11~0); 21892#L1422-1 assume !(1 == ~E_12~0); 22126#L1427-1 assume { :end_inline_reset_delta_events } true; 20679#L1768-2 [2024-11-08 17:07:21,034 INFO L747 eck$LassoCheckResult]: Loop: 20679#L1768-2 assume !false; 20680#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 21343#L1149-1 assume !false; 21721#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 21948#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 21057#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 21873#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 21943#L976 assume !(0 != eval_~tmp~0#1); 21371#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 21100#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 21101#L1174-3 assume 0 == ~M_E~0;~M_E~0 := 1; 21901#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 21639#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 21640#L1184-3 assume !(0 == ~T3_E~0); 21826#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 21470#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 20833#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 20834#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 21070#L1209-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 20493#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 20494#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 21250#L1224-3 assume !(0 == ~T11_E~0); 21251#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 21265#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 20689#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 20690#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 21125#L1249-3 assume 0 == ~E_4~0;~E_4~0 := 1; 21583#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 22076#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 21682#L1264-3 assume !(0 == ~E_7~0); 20693#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 20694#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 22106#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 21246#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 21247#L1289-3 assume 0 == ~E_12~0;~E_12~0 := 1; 21234#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20913#L566-39 assume 1 == ~m_pc~0; 20914#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 21513#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21514#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 21566#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 21757#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21758#L585-39 assume !(1 == ~t1_pc~0); 20921#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 20922#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21122#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 22070#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 21795#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21490#L604-39 assume 1 == ~t2_pc~0; 21491#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 21129#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21130#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 21309#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 21543#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21111#L623-39 assume !(1 == ~t3_pc~0); 20512#L623-41 is_transmit3_triggered_~__retres1~3#1 := 0; 20511#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21775#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 20964#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 20965#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21717#L642-39 assume 1 == ~t4_pc~0; 21300#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21301#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21465#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 21466#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 21947#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20883#L661-39 assume 1 == ~t5_pc~0; 20884#L662-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 20519#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21497#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 21498#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 21777#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 21778#L680-39 assume 1 == ~t6_pc~0; 20585#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 20586#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22026#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 21037#L1503-39 assume !(0 != activate_threads_~tmp___5~0#1); 21038#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 22082#L699-39 assume 1 == ~t7_pc~0; 21472#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 21199#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 21200#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21782#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 22022#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 22019#L718-39 assume 1 == ~t8_pc~0; 21384#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 21385#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 21878#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 21879#L1519-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 21627#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 21604#L737-39 assume 1 == ~t9_pc~0; 21018#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 21019#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 20613#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 20614#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 21994#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21931#L756-39 assume !(1 == ~t10_pc~0); 21398#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 21399#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 22069#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 21283#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 21284#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 20634#L775-39 assume 1 == ~t11_pc~0; 20635#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 21274#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 21275#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 21524#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 21675#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 21325#L794-39 assume !(1 == ~t12_pc~0); 21014#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 21015#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 21108#is_transmit12_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 21109#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 20576#L1551-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20577#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 22053#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 22054#L1312-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 22167#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 21744#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 21745#L1327-3 assume !(1 == ~T5_E~0); 20710#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 20685#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 20686#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 21413#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 21546#L1352-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 21547#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 22002#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 22162#L1367-3 assume !(1 == ~E_1~0); 22153#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 20506#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 20507#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 21132#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 21133#L1392-3 assume 1 == ~E_6~0;~E_6~0 := 2; 21852#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 22120#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 21512#L1407-3 assume !(1 == ~E_9~0); 20792#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 20793#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 21427#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 21428#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 20800#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 20801#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 20868#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 20869#L1787 assume !(0 == start_simulation_~tmp~3#1); 21516#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 22062#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 20777#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 20525#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 20526#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 21118#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 21119#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 22029#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 20679#L1768-2 [2024-11-08 17:07:21,035 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 17:07:21,036 INFO L85 PathProgramCache]: Analyzing trace with hash 313083407, now seen corresponding path program 1 times [2024-11-08 17:07:21,036 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 17:07:21,036 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [632058772] [2024-11-08 17:07:21,036 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 17:07:21,036 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 17:07:21,052 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:07:21,098 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 17:07:21,099 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 17:07:21,099 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [632058772] [2024-11-08 17:07:21,099 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [632058772] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 17:07:21,099 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 17:07:21,099 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 17:07:21,100 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1585660494] [2024-11-08 17:07:21,100 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 17:07:21,100 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 17:07:21,100 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 17:07:21,101 INFO L85 PathProgramCache]: Analyzing trace with hash -740674789, now seen corresponding path program 1 times [2024-11-08 17:07:21,101 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 17:07:21,101 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1441550049] [2024-11-08 17:07:21,101 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 17:07:21,102 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 17:07:21,120 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:07:21,191 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 17:07:21,191 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 17:07:21,191 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1441550049] [2024-11-08 17:07:21,191 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1441550049] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 17:07:21,192 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 17:07:21,192 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 17:07:21,192 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [921776817] [2024-11-08 17:07:21,192 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 17:07:21,192 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 17:07:21,192 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 17:07:21,193 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 17:07:21,193 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 17:07:21,193 INFO L87 Difference]: Start difference. First operand 1701 states and 2512 transitions. cyclomatic complexity: 812 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 17:07:21,227 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 17:07:21,227 INFO L93 Difference]: Finished difference Result 1701 states and 2511 transitions. [2024-11-08 17:07:21,227 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1701 states and 2511 transitions. [2024-11-08 17:07:21,236 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1540 [2024-11-08 17:07:21,244 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1701 states to 1701 states and 2511 transitions. [2024-11-08 17:07:21,245 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1701 [2024-11-08 17:07:21,247 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1701 [2024-11-08 17:07:21,249 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1701 states and 2511 transitions. [2024-11-08 17:07:21,251 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 17:07:21,251 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1701 states and 2511 transitions. [2024-11-08 17:07:21,254 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1701 states and 2511 transitions. [2024-11-08 17:07:21,279 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1701 to 1701. [2024-11-08 17:07:21,282 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1701 states, 1701 states have (on average 1.4761904761904763) internal successors, (2511), 1700 states have internal predecessors, (2511), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 17:07:21,288 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1701 states to 1701 states and 2511 transitions. [2024-11-08 17:07:21,288 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1701 states and 2511 transitions. [2024-11-08 17:07:21,289 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 17:07:21,289 INFO L425 stractBuchiCegarLoop]: Abstraction has 1701 states and 2511 transitions. [2024-11-08 17:07:21,289 INFO L332 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-11-08 17:07:21,289 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1701 states and 2511 transitions. [2024-11-08 17:07:21,298 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1540 [2024-11-08 17:07:21,298 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 17:07:21,298 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 17:07:21,300 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 17:07:21,301 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 17:07:21,301 INFO L745 eck$LassoCheckResult]: Stem: 24156#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 24157#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 24949#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 24950#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 24817#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 24818#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 24911#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25210#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 25345#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 25346#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 24132#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 24133#L851-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 25277#L856-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 24715#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 24716#L866-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 24626#L871-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 24627#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 25020#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 24371#L1174 assume !(0 == ~M_E~0); 24372#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 24223#L1179-1 assume !(0 == ~T2_E~0); 24129#L1184-1 assume !(0 == ~T3_E~0); 24130#L1189-1 assume !(0 == ~T4_E~0); 24172#L1194-1 assume !(0 == ~T5_E~0); 24265#L1199-1 assume !(0 == ~T6_E~0); 25144#L1204-1 assume !(0 == ~T7_E~0); 25065#L1209-1 assume !(0 == ~T8_E~0); 25066#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 25489#L1219-1 assume !(0 == ~T10_E~0); 25574#L1224-1 assume !(0 == ~T11_E~0); 24488#L1229-1 assume !(0 == ~T12_E~0); 24059#L1234-1 assume !(0 == ~E_1~0); 24060#L1239-1 assume !(0 == ~E_2~0); 24092#L1244-1 assume !(0 == ~E_3~0); 24093#L1249-1 assume !(0 == ~E_4~0); 24735#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 23989#L1259-1 assume !(0 == ~E_6~0); 23942#L1264-1 assume !(0 == ~E_7~0); 23943#L1269-1 assume !(0 == ~E_8~0); 25577#L1274-1 assume !(0 == ~E_9~0); 25516#L1279-1 assume !(0 == ~E_10~0); 24176#L1284-1 assume !(0 == ~E_11~0); 24177#L1289-1 assume !(0 == ~E_12~0); 24787#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24788#L566 assume 1 == ~m_pc~0; 23959#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 23960#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24831#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 24832#L1455 assume !(0 != activate_threads_~tmp~1#1); 24398#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24399#L585 assume 1 == ~t1_pc~0; 24056#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 24057#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25200#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 25201#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 25545#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25541#L604 assume !(1 == ~t2_pc~0); 25106#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 25107#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24341#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24342#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 25305#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25306#L623 assume 1 == ~t3_pc~0; 24572#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 23918#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25175#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25176#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 25339#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23956#L642 assume !(1 == ~t4_pc~0); 23957#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 24409#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24011#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 24012#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 24033#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25119#L661 assume 1 == ~t5_pc~0; 24189#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 24190#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25037#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25404#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 25151#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25152#L680 assume !(1 == ~t6_pc~0); 24605#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 24606#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 24332#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 24333#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 25414#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25538#L699 assume 1 == ~t7_pc~0; 25000#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 25001#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25233#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 24893#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 24894#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 24789#L718 assume !(1 == ~t8_pc~0); 24790#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 24170#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 24171#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 24205#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 24206#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24338#L737 assume 1 == ~t9_pc~0; 25189#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 24469#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 24378#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 24379#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 24646#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 24647#L756 assume 1 == ~t10_pc~0; 25223#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 24884#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25139#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 24824#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 24448#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 24449#L775 assume !(1 == ~t11_pc~0); 24707#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 24708#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 25482#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 24104#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 24105#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 24286#L794 assume 1 == ~t12_pc~0; 24127#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 24107#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 23962#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 23963#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 24251#L1551-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24719#L1307 assume !(1 == ~M_E~0); 24720#L1307-2 assume !(1 == ~T1_E~0); 24828#L1312-1 assume !(1 == ~T2_E~0); 24748#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 24749#L1322-1 assume !(1 == ~T4_E~0); 24459#L1327-1 assume !(1 == ~T5_E~0); 24460#L1332-1 assume !(1 == ~T6_E~0); 25005#L1337-1 assume !(1 == ~T7_E~0); 24962#L1342-1 assume !(1 == ~T8_E~0); 24963#L1347-1 assume !(1 == ~T9_E~0); 25375#L1352-1 assume !(1 == ~T10_E~0); 25234#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 24624#L1362-1 assume !(1 == ~T12_E~0); 24625#L1367-1 assume !(1 == ~E_1~0); 24266#L1372-1 assume !(1 == ~E_2~0); 24267#L1377-1 assume !(1 == ~E_3~0); 24557#L1382-1 assume !(1 == ~E_4~0); 24558#L1387-1 assume !(1 == ~E_5~0); 25108#L1392-1 assume !(1 == ~E_6~0); 24575#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 24576#L1402-1 assume !(1 == ~E_8~0); 24281#L1407-1 assume !(1 == ~E_9~0); 24282#L1412-1 assume !(1 == ~E_10~0); 25300#L1417-1 assume !(1 == ~E_11~0); 25301#L1422-1 assume !(1 == ~E_12~0); 25535#L1427-1 assume { :end_inline_reset_delta_events } true; 24088#L1768-2 [2024-11-08 17:07:21,302 INFO L747 eck$LassoCheckResult]: Loop: 24088#L1768-2 assume !false; 24089#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 24752#L1149-1 assume !false; 25130#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 25357#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 24466#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 25282#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 25352#L976 assume !(0 != eval_~tmp~0#1); 24780#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 24509#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 24510#L1174-3 assume 0 == ~M_E~0;~M_E~0 := 1; 25310#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 25048#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 25049#L1184-3 assume !(0 == ~T3_E~0); 25235#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 24879#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 24242#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 24243#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 24479#L1209-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 23902#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 23903#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 24659#L1224-3 assume !(0 == ~T11_E~0); 24660#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 24674#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 24098#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 24099#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 24534#L1249-3 assume 0 == ~E_4~0;~E_4~0 := 1; 24992#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 25485#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 25091#L1264-3 assume !(0 == ~E_7~0); 24102#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 24103#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 25515#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 24655#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 24656#L1289-3 assume 0 == ~E_12~0;~E_12~0 := 1; 24643#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24322#L566-39 assume 1 == ~m_pc~0; 24323#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 24922#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24923#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 24975#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 25166#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25167#L585-39 assume 1 == ~t1_pc~0; 25296#L586-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 24331#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24531#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 25479#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25204#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 24899#L604-39 assume 1 == ~t2_pc~0; 24900#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 24538#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24539#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24718#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 24952#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24520#L623-39 assume !(1 == ~t3_pc~0); 23921#L623-41 is_transmit3_triggered_~__retres1~3#1 := 0; 23920#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25184#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24373#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 24374#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25126#L642-39 assume 1 == ~t4_pc~0; 24709#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 24710#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24874#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 24875#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 25356#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 24292#L661-39 assume 1 == ~t5_pc~0; 24293#L662-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 23928#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 24906#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 24907#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 25186#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25187#L680-39 assume 1 == ~t6_pc~0; 23994#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 23995#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25435#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 24446#L1503-39 assume !(0 != activate_threads_~tmp___5~0#1); 24447#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25491#L699-39 assume 1 == ~t7_pc~0; 24881#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 24608#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 24609#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25191#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 25431#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25428#L718-39 assume 1 == ~t8_pc~0; 24793#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 24794#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25287#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 25288#L1519-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 25036#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 25013#L737-39 assume 1 == ~t9_pc~0; 24427#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 24428#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 24022#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 24023#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 25403#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25340#L756-39 assume !(1 == ~t10_pc~0); 24807#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 24808#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25478#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 24692#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 24693#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 24043#L775-39 assume 1 == ~t11_pc~0; 24044#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 24683#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 24684#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 24933#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 25084#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 24734#L794-39 assume !(1 == ~t12_pc~0); 24423#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 24424#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 24517#is_transmit12_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 24518#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 23985#L1551-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 23986#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 25462#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 25463#L1312-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 25576#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 25153#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 25154#L1327-3 assume !(1 == ~T5_E~0); 24119#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 24094#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 24095#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 24822#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 24955#L1352-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 24956#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 25411#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 25571#L1367-3 assume !(1 == ~E_1~0); 25562#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 23915#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 23916#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 24541#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 24542#L1392-3 assume 1 == ~E_6~0;~E_6~0 := 2; 25261#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 25529#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 24921#L1407-3 assume !(1 == ~E_9~0); 24201#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 24202#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 24836#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 24837#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 24209#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 24210#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 24277#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 24278#L1787 assume !(0 == start_simulation_~tmp~3#1); 24925#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 25471#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 24186#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 23934#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 23935#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 24527#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 24528#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 25438#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 24088#L1768-2 [2024-11-08 17:07:21,303 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 17:07:21,303 INFO L85 PathProgramCache]: Analyzing trace with hash -1846000687, now seen corresponding path program 1 times [2024-11-08 17:07:21,303 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 17:07:21,305 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [304658926] [2024-11-08 17:07:21,305 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 17:07:21,305 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 17:07:21,321 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:07:21,369 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 17:07:21,369 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 17:07:21,369 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [304658926] [2024-11-08 17:07:21,369 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [304658926] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 17:07:21,370 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 17:07:21,370 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 17:07:21,370 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [876191504] [2024-11-08 17:07:21,370 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 17:07:21,371 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 17:07:21,371 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 17:07:21,371 INFO L85 PathProgramCache]: Analyzing trace with hash -902611780, now seen corresponding path program 1 times [2024-11-08 17:07:21,371 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 17:07:21,372 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1665643785] [2024-11-08 17:07:21,372 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 17:07:21,372 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 17:07:21,391 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:07:21,449 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 17:07:21,449 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 17:07:21,449 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1665643785] [2024-11-08 17:07:21,449 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1665643785] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 17:07:21,449 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 17:07:21,450 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 17:07:21,450 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1845805136] [2024-11-08 17:07:21,450 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 17:07:21,450 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 17:07:21,450 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 17:07:21,451 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 17:07:21,451 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 17:07:21,451 INFO L87 Difference]: Start difference. First operand 1701 states and 2511 transitions. cyclomatic complexity: 811 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 17:07:21,489 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 17:07:21,490 INFO L93 Difference]: Finished difference Result 1701 states and 2510 transitions. [2024-11-08 17:07:21,490 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1701 states and 2510 transitions. [2024-11-08 17:07:21,499 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1540 [2024-11-08 17:07:21,507 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1701 states to 1701 states and 2510 transitions. [2024-11-08 17:07:21,508 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1701 [2024-11-08 17:07:21,510 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1701 [2024-11-08 17:07:21,510 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1701 states and 2510 transitions. [2024-11-08 17:07:21,512 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 17:07:21,512 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1701 states and 2510 transitions. [2024-11-08 17:07:21,515 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1701 states and 2510 transitions. [2024-11-08 17:07:21,562 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1701 to 1701. [2024-11-08 17:07:21,566 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1701 states, 1701 states have (on average 1.475602586713698) internal successors, (2510), 1700 states have internal predecessors, (2510), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 17:07:21,573 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1701 states to 1701 states and 2510 transitions. [2024-11-08 17:07:21,574 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1701 states and 2510 transitions. [2024-11-08 17:07:21,574 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 17:07:21,578 INFO L425 stractBuchiCegarLoop]: Abstraction has 1701 states and 2510 transitions. [2024-11-08 17:07:21,578 INFO L332 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-11-08 17:07:21,578 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1701 states and 2510 transitions. [2024-11-08 17:07:21,588 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1540 [2024-11-08 17:07:21,588 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 17:07:21,588 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 17:07:21,591 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 17:07:21,591 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 17:07:21,592 INFO L745 eck$LassoCheckResult]: Stem: 27565#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 27566#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 28358#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 28359#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 28226#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 28227#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 28320#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 28619#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 28754#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 28755#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 27541#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 27542#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 28686#L856-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 28124#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 28125#L866-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 28035#L871-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 28036#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 28429#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 27780#L1174 assume !(0 == ~M_E~0); 27781#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 27632#L1179-1 assume !(0 == ~T2_E~0); 27538#L1184-1 assume !(0 == ~T3_E~0); 27539#L1189-1 assume !(0 == ~T4_E~0); 27581#L1194-1 assume !(0 == ~T5_E~0); 27674#L1199-1 assume !(0 == ~T6_E~0); 28553#L1204-1 assume !(0 == ~T7_E~0); 28474#L1209-1 assume !(0 == ~T8_E~0); 28475#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 28898#L1219-1 assume !(0 == ~T10_E~0); 28983#L1224-1 assume !(0 == ~T11_E~0); 27897#L1229-1 assume !(0 == ~T12_E~0); 27468#L1234-1 assume !(0 == ~E_1~0); 27469#L1239-1 assume !(0 == ~E_2~0); 27501#L1244-1 assume !(0 == ~E_3~0); 27502#L1249-1 assume !(0 == ~E_4~0); 28144#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 27398#L1259-1 assume !(0 == ~E_6~0); 27351#L1264-1 assume !(0 == ~E_7~0); 27352#L1269-1 assume !(0 == ~E_8~0); 28986#L1274-1 assume !(0 == ~E_9~0); 28925#L1279-1 assume !(0 == ~E_10~0); 27585#L1284-1 assume !(0 == ~E_11~0); 27586#L1289-1 assume !(0 == ~E_12~0); 28196#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28197#L566 assume 1 == ~m_pc~0; 27368#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 27369#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28240#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 28241#L1455 assume !(0 != activate_threads_~tmp~1#1); 27807#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 27808#L585 assume 1 == ~t1_pc~0; 27465#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 27466#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28609#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 28610#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 28954#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28950#L604 assume !(1 == ~t2_pc~0); 28515#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 28516#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27750#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 27751#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 28714#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28715#L623 assume 1 == ~t3_pc~0; 27981#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 27327#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28584#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 28585#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 28748#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 27365#L642 assume !(1 == ~t4_pc~0); 27366#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 27818#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 27420#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 27421#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 27442#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 28528#L661 assume 1 == ~t5_pc~0; 27598#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 27599#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28446#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 28813#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 28560#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 28561#L680 assume !(1 == ~t6_pc~0); 28014#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 28015#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 27741#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 27742#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 28823#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 28947#L699 assume 1 == ~t7_pc~0; 28409#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 28410#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 28642#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 28302#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 28303#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 28198#L718 assume !(1 == ~t8_pc~0); 28199#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 27579#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 27580#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 27614#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 27615#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 27747#L737 assume 1 == ~t9_pc~0; 28598#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 27878#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 27787#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 27788#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 28055#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 28056#L756 assume 1 == ~t10_pc~0; 28632#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 28293#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 28548#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 28233#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 27857#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 27858#L775 assume !(1 == ~t11_pc~0); 28116#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 28117#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 28891#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 27513#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 27514#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 27695#L794 assume 1 == ~t12_pc~0; 27536#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 27516#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 27371#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 27372#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 27660#L1551-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28128#L1307 assume !(1 == ~M_E~0); 28129#L1307-2 assume !(1 == ~T1_E~0); 28237#L1312-1 assume !(1 == ~T2_E~0); 28157#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 28158#L1322-1 assume !(1 == ~T4_E~0); 27868#L1327-1 assume !(1 == ~T5_E~0); 27869#L1332-1 assume !(1 == ~T6_E~0); 28414#L1337-1 assume !(1 == ~T7_E~0); 28371#L1342-1 assume !(1 == ~T8_E~0); 28372#L1347-1 assume !(1 == ~T9_E~0); 28784#L1352-1 assume !(1 == ~T10_E~0); 28643#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 28033#L1362-1 assume !(1 == ~T12_E~0); 28034#L1367-1 assume !(1 == ~E_1~0); 27675#L1372-1 assume !(1 == ~E_2~0); 27676#L1377-1 assume !(1 == ~E_3~0); 27966#L1382-1 assume !(1 == ~E_4~0); 27967#L1387-1 assume !(1 == ~E_5~0); 28517#L1392-1 assume !(1 == ~E_6~0); 27984#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 27985#L1402-1 assume !(1 == ~E_8~0); 27690#L1407-1 assume !(1 == ~E_9~0); 27691#L1412-1 assume !(1 == ~E_10~0); 28709#L1417-1 assume !(1 == ~E_11~0); 28710#L1422-1 assume !(1 == ~E_12~0); 28944#L1427-1 assume { :end_inline_reset_delta_events } true; 27497#L1768-2 [2024-11-08 17:07:21,592 INFO L747 eck$LassoCheckResult]: Loop: 27497#L1768-2 assume !false; 27498#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 28161#L1149-1 assume !false; 28539#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 28766#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 27875#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 28691#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 28761#L976 assume !(0 != eval_~tmp~0#1); 28189#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 27918#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 27919#L1174-3 assume 0 == ~M_E~0;~M_E~0 := 1; 28719#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 28457#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 28458#L1184-3 assume !(0 == ~T3_E~0); 28644#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 28288#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 27651#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 27652#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 27888#L1209-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 27311#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 27312#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 28068#L1224-3 assume !(0 == ~T11_E~0); 28069#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 28083#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 27507#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 27508#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 27943#L1249-3 assume 0 == ~E_4~0;~E_4~0 := 1; 28401#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 28894#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 28500#L1264-3 assume !(0 == ~E_7~0); 27511#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 27512#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 28924#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 28064#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 28065#L1289-3 assume 0 == ~E_12~0;~E_12~0 := 1; 28052#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 27731#L566-39 assume 1 == ~m_pc~0; 27732#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 28331#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28332#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 28384#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 28575#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28576#L585-39 assume 1 == ~t1_pc~0; 28705#L586-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 27740#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27940#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 28888#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 28613#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28308#L604-39 assume 1 == ~t2_pc~0; 28309#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 27947#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27948#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 28127#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 28361#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 27929#L623-39 assume 1 == ~t3_pc~0; 27328#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 27329#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28593#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 27782#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 27783#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28535#L642-39 assume 1 == ~t4_pc~0; 28118#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 28119#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28283#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 28284#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 28765#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 27701#L661-39 assume 1 == ~t5_pc~0; 27702#L662-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 27337#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28315#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 28316#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 28595#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 28596#L680-39 assume 1 == ~t6_pc~0; 27403#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 27404#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 28844#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 27855#L1503-39 assume !(0 != activate_threads_~tmp___5~0#1); 27856#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 28900#L699-39 assume 1 == ~t7_pc~0; 28290#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 28017#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 28018#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 28600#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 28840#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 28837#L718-39 assume 1 == ~t8_pc~0; 28202#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 28203#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 28696#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 28697#L1519-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 28445#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 28422#L737-39 assume 1 == ~t9_pc~0; 27836#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 27837#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 27431#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 27432#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 28812#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 28749#L756-39 assume !(1 == ~t10_pc~0); 28216#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 28217#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 28887#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 28101#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 28102#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 27452#L775-39 assume 1 == ~t11_pc~0; 27453#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 28092#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 28093#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 28342#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 28493#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 28143#L794-39 assume !(1 == ~t12_pc~0); 27832#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 27833#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 27926#is_transmit12_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 27927#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 27394#L1551-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27395#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 28871#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 28872#L1312-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 28985#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 28562#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 28563#L1327-3 assume !(1 == ~T5_E~0); 27528#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 27503#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 27504#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 28231#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 28364#L1352-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 28365#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 28820#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 28980#L1367-3 assume !(1 == ~E_1~0); 28971#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 27324#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 27325#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 27950#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 27951#L1392-3 assume 1 == ~E_6~0;~E_6~0 := 2; 28670#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 28938#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 28330#L1407-3 assume !(1 == ~E_9~0); 27610#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 27611#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 28245#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 28246#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 27618#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 27619#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 27686#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 27687#L1787 assume !(0 == start_simulation_~tmp~3#1); 28334#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 28880#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 27595#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 27343#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 27344#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 27936#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 27937#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 28847#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 27497#L1768-2 [2024-11-08 17:07:21,593 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 17:07:21,593 INFO L85 PathProgramCache]: Analyzing trace with hash -1915648561, now seen corresponding path program 1 times [2024-11-08 17:07:21,594 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 17:07:21,595 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [535015081] [2024-11-08 17:07:21,595 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 17:07:21,595 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 17:07:21,619 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:07:21,667 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 17:07:21,668 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 17:07:21,668 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [535015081] [2024-11-08 17:07:21,668 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [535015081] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 17:07:21,668 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 17:07:21,669 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 17:07:21,669 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [575670172] [2024-11-08 17:07:21,669 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 17:07:21,669 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 17:07:21,670 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 17:07:21,670 INFO L85 PathProgramCache]: Analyzing trace with hash 966586333, now seen corresponding path program 1 times [2024-11-08 17:07:21,671 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 17:07:21,671 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [740178327] [2024-11-08 17:07:21,671 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 17:07:21,671 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 17:07:21,699 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:07:21,779 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 17:07:21,779 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 17:07:21,780 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [740178327] [2024-11-08 17:07:21,780 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [740178327] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 17:07:21,780 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 17:07:21,780 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 17:07:21,780 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1624283145] [2024-11-08 17:07:21,781 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 17:07:21,781 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 17:07:21,781 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 17:07:21,782 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 17:07:21,782 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 17:07:21,782 INFO L87 Difference]: Start difference. First operand 1701 states and 2510 transitions. cyclomatic complexity: 810 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 17:07:21,827 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 17:07:21,827 INFO L93 Difference]: Finished difference Result 1701 states and 2509 transitions. [2024-11-08 17:07:21,827 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1701 states and 2509 transitions. [2024-11-08 17:07:21,837 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1540 [2024-11-08 17:07:21,845 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1701 states to 1701 states and 2509 transitions. [2024-11-08 17:07:21,845 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1701 [2024-11-08 17:07:21,847 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1701 [2024-11-08 17:07:21,847 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1701 states and 2509 transitions. [2024-11-08 17:07:21,849 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 17:07:21,850 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1701 states and 2509 transitions. [2024-11-08 17:07:21,852 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1701 states and 2509 transitions. [2024-11-08 17:07:21,871 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1701 to 1701. [2024-11-08 17:07:21,875 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1701 states, 1701 states have (on average 1.4750146972369194) internal successors, (2509), 1700 states have internal predecessors, (2509), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 17:07:21,880 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1701 states to 1701 states and 2509 transitions. [2024-11-08 17:07:21,880 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1701 states and 2509 transitions. [2024-11-08 17:07:21,880 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 17:07:21,881 INFO L425 stractBuchiCegarLoop]: Abstraction has 1701 states and 2509 transitions. [2024-11-08 17:07:21,881 INFO L332 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-11-08 17:07:21,881 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1701 states and 2509 transitions. [2024-11-08 17:07:21,889 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1540 [2024-11-08 17:07:21,889 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 17:07:21,889 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 17:07:21,891 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 17:07:21,892 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 17:07:21,892 INFO L745 eck$LassoCheckResult]: Stem: 30974#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 30975#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 31767#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 31768#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 31635#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 31636#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 31729#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 32028#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 32163#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 32164#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 30950#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 30951#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 32095#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 31533#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 31534#L866-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 31444#L871-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 31445#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 31838#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 31189#L1174 assume !(0 == ~M_E~0); 31190#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 31041#L1179-1 assume !(0 == ~T2_E~0); 30947#L1184-1 assume !(0 == ~T3_E~0); 30948#L1189-1 assume !(0 == ~T4_E~0); 30990#L1194-1 assume !(0 == ~T5_E~0); 31083#L1199-1 assume !(0 == ~T6_E~0); 31962#L1204-1 assume !(0 == ~T7_E~0); 31883#L1209-1 assume !(0 == ~T8_E~0); 31884#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 32307#L1219-1 assume !(0 == ~T10_E~0); 32392#L1224-1 assume !(0 == ~T11_E~0); 31306#L1229-1 assume !(0 == ~T12_E~0); 30877#L1234-1 assume !(0 == ~E_1~0); 30878#L1239-1 assume !(0 == ~E_2~0); 30910#L1244-1 assume !(0 == ~E_3~0); 30911#L1249-1 assume !(0 == ~E_4~0); 31553#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 30807#L1259-1 assume !(0 == ~E_6~0); 30760#L1264-1 assume !(0 == ~E_7~0); 30761#L1269-1 assume !(0 == ~E_8~0); 32395#L1274-1 assume !(0 == ~E_9~0); 32334#L1279-1 assume !(0 == ~E_10~0); 30994#L1284-1 assume !(0 == ~E_11~0); 30995#L1289-1 assume !(0 == ~E_12~0); 31605#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 31606#L566 assume 1 == ~m_pc~0; 30777#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 30778#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31649#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 31650#L1455 assume !(0 != activate_threads_~tmp~1#1); 31216#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 31217#L585 assume 1 == ~t1_pc~0; 30874#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 30875#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 32018#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 32019#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 32363#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 32359#L604 assume !(1 == ~t2_pc~0); 31924#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 31925#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 31159#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 31160#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 32123#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 32124#L623 assume 1 == ~t3_pc~0; 31390#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 30736#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 31993#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 31994#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 32157#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30774#L642 assume !(1 == ~t4_pc~0); 30775#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 31227#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30829#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 30830#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 30851#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 31937#L661 assume 1 == ~t5_pc~0; 31007#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 31008#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 31855#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 32222#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 31969#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 31970#L680 assume !(1 == ~t6_pc~0); 31423#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 31424#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 31150#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 31151#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 32232#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 32356#L699 assume 1 == ~t7_pc~0; 31818#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 31819#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 32051#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 31711#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 31712#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 31607#L718 assume !(1 == ~t8_pc~0); 31608#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 30988#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 30989#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 31023#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 31024#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 31156#L737 assume 1 == ~t9_pc~0; 32007#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 31287#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 31196#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 31197#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 31464#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 31465#L756 assume 1 == ~t10_pc~0; 32041#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 31702#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 31957#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 31642#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 31266#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 31267#L775 assume !(1 == ~t11_pc~0); 31525#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 31526#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 32300#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 30922#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 30923#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 31104#L794 assume 1 == ~t12_pc~0; 30945#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 30925#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 30780#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 30781#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 31069#L1551-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 31537#L1307 assume !(1 == ~M_E~0); 31538#L1307-2 assume !(1 == ~T1_E~0); 31646#L1312-1 assume !(1 == ~T2_E~0); 31566#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 31567#L1322-1 assume !(1 == ~T4_E~0); 31277#L1327-1 assume !(1 == ~T5_E~0); 31278#L1332-1 assume !(1 == ~T6_E~0); 31823#L1337-1 assume !(1 == ~T7_E~0); 31780#L1342-1 assume !(1 == ~T8_E~0); 31781#L1347-1 assume !(1 == ~T9_E~0); 32193#L1352-1 assume !(1 == ~T10_E~0); 32052#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 31442#L1362-1 assume !(1 == ~T12_E~0); 31443#L1367-1 assume !(1 == ~E_1~0); 31084#L1372-1 assume !(1 == ~E_2~0); 31085#L1377-1 assume !(1 == ~E_3~0); 31375#L1382-1 assume !(1 == ~E_4~0); 31376#L1387-1 assume !(1 == ~E_5~0); 31926#L1392-1 assume !(1 == ~E_6~0); 31393#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 31394#L1402-1 assume !(1 == ~E_8~0); 31099#L1407-1 assume !(1 == ~E_9~0); 31100#L1412-1 assume !(1 == ~E_10~0); 32118#L1417-1 assume !(1 == ~E_11~0); 32119#L1422-1 assume !(1 == ~E_12~0); 32353#L1427-1 assume { :end_inline_reset_delta_events } true; 30906#L1768-2 [2024-11-08 17:07:21,893 INFO L747 eck$LassoCheckResult]: Loop: 30906#L1768-2 assume !false; 30907#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 31570#L1149-1 assume !false; 31948#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 32175#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 31284#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 32100#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 32170#L976 assume !(0 != eval_~tmp~0#1); 31598#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 31327#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 31328#L1174-3 assume 0 == ~M_E~0;~M_E~0 := 1; 32128#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 31866#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 31867#L1184-3 assume !(0 == ~T3_E~0); 32053#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 31697#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 31060#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 31061#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 31297#L1209-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 30720#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 30721#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 31477#L1224-3 assume !(0 == ~T11_E~0); 31478#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 31492#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 30916#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 30917#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 31352#L1249-3 assume 0 == ~E_4~0;~E_4~0 := 1; 31810#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 32303#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 31909#L1264-3 assume !(0 == ~E_7~0); 30920#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 30921#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 32333#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 31473#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 31474#L1289-3 assume 0 == ~E_12~0;~E_12~0 := 1; 31461#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 31140#L566-39 assume 1 == ~m_pc~0; 31141#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 31740#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31741#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 31793#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 31984#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 31985#L585-39 assume 1 == ~t1_pc~0; 32114#L586-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 31149#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 31349#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 32297#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 32022#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 31717#L604-39 assume 1 == ~t2_pc~0; 31718#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 31356#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 31357#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 31536#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 31770#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 31338#L623-39 assume 1 == ~t3_pc~0; 30737#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 30738#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 32002#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 31191#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 31192#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 31944#L642-39 assume 1 == ~t4_pc~0; 31527#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 31528#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 31692#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 31693#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 32174#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 31110#L661-39 assume 1 == ~t5_pc~0; 31111#L662-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 30746#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 31724#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 31725#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 32004#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 32005#L680-39 assume 1 == ~t6_pc~0; 30812#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 30813#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 32253#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 31264#L1503-39 assume !(0 != activate_threads_~tmp___5~0#1); 31265#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 32309#L699-39 assume 1 == ~t7_pc~0; 31699#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 31426#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 31427#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 32009#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 32249#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 32246#L718-39 assume 1 == ~t8_pc~0; 31611#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 31612#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 32105#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 32106#L1519-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 31854#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 31831#L737-39 assume 1 == ~t9_pc~0; 31245#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 31246#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 30840#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 30841#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 32221#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 32158#L756-39 assume !(1 == ~t10_pc~0); 31625#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 31626#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 32296#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 31510#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 31511#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 30861#L775-39 assume 1 == ~t11_pc~0; 30862#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 31501#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 31502#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 31751#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 31902#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 31552#L794-39 assume 1 == ~t12_pc~0; 31248#L795-13 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 31242#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 31335#is_transmit12_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 31336#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 30803#L1551-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30804#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 32280#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 32281#L1312-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 32394#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 31971#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 31972#L1327-3 assume !(1 == ~T5_E~0); 30937#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 30912#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 30913#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 31640#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 31773#L1352-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 31774#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 32229#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 32389#L1367-3 assume !(1 == ~E_1~0); 32380#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 30733#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 30734#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 31359#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 31360#L1392-3 assume 1 == ~E_6~0;~E_6~0 := 2; 32079#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 32347#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 31739#L1407-3 assume !(1 == ~E_9~0); 31019#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 31020#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 31654#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 31655#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 31027#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 31028#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 31095#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 31096#L1787 assume !(0 == start_simulation_~tmp~3#1); 31743#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 32289#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 31004#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 30752#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 30753#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 31345#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 31346#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 32256#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 30906#L1768-2 [2024-11-08 17:07:21,893 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 17:07:21,893 INFO L85 PathProgramCache]: Analyzing trace with hash 1961430033, now seen corresponding path program 1 times [2024-11-08 17:07:21,893 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 17:07:21,894 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1043707628] [2024-11-08 17:07:21,894 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 17:07:21,894 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 17:07:21,910 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:07:21,947 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 17:07:21,948 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 17:07:21,948 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1043707628] [2024-11-08 17:07:21,948 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1043707628] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 17:07:21,948 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 17:07:21,948 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 17:07:21,948 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [779246372] [2024-11-08 17:07:21,948 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 17:07:21,949 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 17:07:21,949 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 17:07:21,949 INFO L85 PathProgramCache]: Analyzing trace with hash -2053278274, now seen corresponding path program 1 times [2024-11-08 17:07:21,950 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 17:07:21,950 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1865789764] [2024-11-08 17:07:21,950 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 17:07:21,950 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 17:07:21,967 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:07:22,018 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 17:07:22,018 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 17:07:22,018 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1865789764] [2024-11-08 17:07:22,019 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1865789764] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 17:07:22,019 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 17:07:22,019 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 17:07:22,019 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [272502606] [2024-11-08 17:07:22,019 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 17:07:22,019 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 17:07:22,020 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 17:07:22,020 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 17:07:22,020 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 17:07:22,020 INFO L87 Difference]: Start difference. First operand 1701 states and 2509 transitions. cyclomatic complexity: 809 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 17:07:22,053 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 17:07:22,053 INFO L93 Difference]: Finished difference Result 1701 states and 2508 transitions. [2024-11-08 17:07:22,053 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1701 states and 2508 transitions. [2024-11-08 17:07:22,062 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1540 [2024-11-08 17:07:22,070 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1701 states to 1701 states and 2508 transitions. [2024-11-08 17:07:22,070 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1701 [2024-11-08 17:07:22,072 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1701 [2024-11-08 17:07:22,072 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1701 states and 2508 transitions. [2024-11-08 17:07:22,075 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 17:07:22,075 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1701 states and 2508 transitions. [2024-11-08 17:07:22,077 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1701 states and 2508 transitions. [2024-11-08 17:07:22,096 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1701 to 1701. [2024-11-08 17:07:22,100 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1701 states, 1701 states have (on average 1.474426807760141) internal successors, (2508), 1700 states have internal predecessors, (2508), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 17:07:22,105 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1701 states to 1701 states and 2508 transitions. [2024-11-08 17:07:22,105 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1701 states and 2508 transitions. [2024-11-08 17:07:22,106 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 17:07:22,106 INFO L425 stractBuchiCegarLoop]: Abstraction has 1701 states and 2508 transitions. [2024-11-08 17:07:22,107 INFO L332 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-11-08 17:07:22,107 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1701 states and 2508 transitions. [2024-11-08 17:07:22,114 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1540 [2024-11-08 17:07:22,115 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 17:07:22,115 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 17:07:22,117 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 17:07:22,117 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 17:07:22,118 INFO L745 eck$LassoCheckResult]: Stem: 34383#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 34384#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 35177#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 35178#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 35044#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 35045#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 35138#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 35442#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 35572#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 35573#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 34359#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 34360#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 35504#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 34942#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 34943#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 34855#L871-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 34856#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 35247#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 34598#L1174 assume !(0 == ~M_E~0); 34599#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 34452#L1179-1 assume !(0 == ~T2_E~0); 34356#L1184-1 assume !(0 == ~T3_E~0); 34357#L1189-1 assume !(0 == ~T4_E~0); 34399#L1194-1 assume !(0 == ~T5_E~0); 34494#L1199-1 assume !(0 == ~T6_E~0); 35371#L1204-1 assume !(0 == ~T7_E~0); 35292#L1209-1 assume !(0 == ~T8_E~0); 35293#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 35716#L1219-1 assume !(0 == ~T10_E~0); 35801#L1224-1 assume !(0 == ~T11_E~0); 34717#L1229-1 assume !(0 == ~T12_E~0); 34286#L1234-1 assume !(0 == ~E_1~0); 34287#L1239-1 assume !(0 == ~E_2~0); 34321#L1244-1 assume !(0 == ~E_3~0); 34322#L1249-1 assume !(0 == ~E_4~0); 34962#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 34216#L1259-1 assume !(0 == ~E_6~0); 34169#L1264-1 assume !(0 == ~E_7~0); 34170#L1269-1 assume !(0 == ~E_8~0); 35804#L1274-1 assume !(0 == ~E_9~0); 35744#L1279-1 assume !(0 == ~E_10~0); 34403#L1284-1 assume !(0 == ~E_11~0); 34404#L1289-1 assume !(0 == ~E_12~0); 35014#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 35015#L566 assume 1 == ~m_pc~0; 34186#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 34187#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 35058#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 35059#L1455 assume !(0 != activate_threads_~tmp~1#1); 34625#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 34626#L585 assume 1 == ~t1_pc~0; 34283#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 34284#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 35427#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 35428#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 35772#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 35768#L604 assume !(1 == ~t2_pc~0); 35333#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 35334#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 34573#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 34574#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 35534#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 35535#L623 assume 1 == ~t3_pc~0; 34799#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 34145#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 35405#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 35406#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 35566#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 34183#L642 assume !(1 == ~t4_pc~0); 34184#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 34636#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 34244#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 34245#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 34260#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 35346#L661 assume 1 == ~t5_pc~0; 34416#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 34417#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 35264#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 35631#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 35380#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 35381#L680 assume !(1 == ~t6_pc~0); 34832#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 34833#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 34562#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 34563#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 35641#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 35766#L699 assume 1 == ~t7_pc~0; 35227#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 35228#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 35460#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 35120#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 35121#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 35016#L718 assume !(1 == ~t8_pc~0); 35017#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 34397#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 34398#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 34434#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 34435#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 34565#L737 assume 1 == ~t9_pc~0; 35418#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 34698#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 34605#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 34606#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 34873#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 34874#L756 assume 1 == ~t10_pc~0; 35450#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 35112#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 35366#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 35051#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 34675#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 34676#L775 assume !(1 == ~t11_pc~0); 34934#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 34935#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 35709#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 34331#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 34332#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 34513#L794 assume 1 == ~t12_pc~0; 34355#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 34334#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 34191#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 34192#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 34480#L1551-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 34946#L1307 assume !(1 == ~M_E~0); 34947#L1307-2 assume !(1 == ~T1_E~0); 35055#L1312-1 assume !(1 == ~T2_E~0); 34975#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 34976#L1322-1 assume !(1 == ~T4_E~0); 34686#L1327-1 assume !(1 == ~T5_E~0); 34687#L1332-1 assume !(1 == ~T6_E~0); 35232#L1337-1 assume !(1 == ~T7_E~0); 35190#L1342-1 assume !(1 == ~T8_E~0); 35191#L1347-1 assume !(1 == ~T9_E~0); 35602#L1352-1 assume !(1 == ~T10_E~0); 35461#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 34851#L1362-1 assume !(1 == ~T12_E~0); 34852#L1367-1 assume !(1 == ~E_1~0); 34495#L1372-1 assume !(1 == ~E_2~0); 34496#L1377-1 assume !(1 == ~E_3~0); 34784#L1382-1 assume !(1 == ~E_4~0); 34785#L1387-1 assume !(1 == ~E_5~0); 35335#L1392-1 assume !(1 == ~E_6~0); 34804#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 34805#L1402-1 assume !(1 == ~E_8~0); 34511#L1407-1 assume !(1 == ~E_9~0); 34512#L1412-1 assume !(1 == ~E_10~0); 35527#L1417-1 assume !(1 == ~E_11~0); 35528#L1422-1 assume !(1 == ~E_12~0); 35762#L1427-1 assume { :end_inline_reset_delta_events } true; 34315#L1768-2 [2024-11-08 17:07:22,119 INFO L747 eck$LassoCheckResult]: Loop: 34315#L1768-2 assume !false; 34316#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 34979#L1149-1 assume !false; 35359#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 35584#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 34693#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 35509#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 35579#L976 assume !(0 != eval_~tmp~0#1); 35007#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 34736#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 34737#L1174-3 assume 0 == ~M_E~0;~M_E~0 := 1; 35537#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 35275#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 35276#L1184-3 assume !(0 == ~T3_E~0); 35463#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 35106#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 34472#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 34473#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 34706#L1209-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 34129#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 34130#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 34886#L1224-3 assume !(0 == ~T11_E~0); 34887#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 34901#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 34323#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 34324#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 34761#L1249-3 assume 0 == ~E_4~0;~E_4~0 := 1; 35219#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 35712#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 35318#L1264-3 assume !(0 == ~E_7~0); 34329#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 34330#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 35742#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 34882#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 34883#L1289-3 assume 0 == ~E_12~0;~E_12~0 := 1; 34870#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 34546#L566-39 assume 1 == ~m_pc~0; 34547#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 35149#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 35150#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 35202#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 35393#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 35394#L585-39 assume 1 == ~t1_pc~0; 35523#L586-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 34558#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 34758#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 35706#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 35431#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 35126#L604-39 assume 1 == ~t2_pc~0; 35127#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 34765#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 34766#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 34945#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 35179#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34747#L623-39 assume 1 == ~t3_pc~0; 34146#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 34147#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 35411#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 34600#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 34601#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 35353#L642-39 assume 1 == ~t4_pc~0; 34936#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 34937#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 35101#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 35102#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 35583#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 34519#L661-39 assume 1 == ~t5_pc~0; 34520#L662-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 34155#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 35133#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 35134#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 35413#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 35414#L680-39 assume 1 == ~t6_pc~0; 34221#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 34222#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 35662#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 34673#L1503-39 assume !(0 != activate_threads_~tmp___5~0#1); 34674#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 35718#L699-39 assume 1 == ~t7_pc~0; 35108#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 34835#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 34836#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 35417#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 35658#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 35655#L718-39 assume 1 == ~t8_pc~0; 35020#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 35021#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 35514#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 35515#L1519-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 35263#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 35240#L737-39 assume !(1 == ~t9_pc~0); 34656#L737-41 is_transmit9_triggered_~__retres1~9#1 := 0; 34655#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 34249#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 34250#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 35630#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 35567#L756-39 assume 1 == ~t10_pc~0; 35568#L757-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 35035#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 35705#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 34919#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 34920#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 34270#L775-39 assume !(1 == ~t11_pc~0); 34272#L775-41 is_transmit11_triggered_~__retres1~11#1 := 0; 34910#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 34911#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 35160#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 35311#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 34961#L794-39 assume 1 == ~t12_pc~0; 34657#L795-13 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 34651#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 34744#is_transmit12_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 34745#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 34212#L1551-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 34213#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 35689#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 35690#L1312-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 35803#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 35378#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 35379#L1327-3 assume !(1 == ~T5_E~0); 34346#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 34319#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 34320#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 35049#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 35182#L1352-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 35183#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 35638#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 35798#L1367-3 assume !(1 == ~E_1~0); 35789#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 34139#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 34140#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 34768#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 34769#L1392-3 assume 1 == ~E_6~0;~E_6~0 := 2; 35488#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 35756#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 35148#L1407-3 assume !(1 == ~E_9~0); 34428#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 34429#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 35063#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 35064#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 34436#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 34437#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 34504#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 34505#L1787 assume !(0 == start_simulation_~tmp~3#1); 35151#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 35698#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 34413#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 34158#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 34159#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 34754#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 34755#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 35665#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 34315#L1768-2 [2024-11-08 17:07:22,119 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 17:07:22,120 INFO L85 PathProgramCache]: Analyzing trace with hash -716096813, now seen corresponding path program 1 times [2024-11-08 17:07:22,120 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 17:07:22,120 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1226744663] [2024-11-08 17:07:22,120 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 17:07:22,120 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 17:07:22,164 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:07:22,203 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 17:07:22,204 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 17:07:22,204 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1226744663] [2024-11-08 17:07:22,204 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1226744663] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 17:07:22,204 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 17:07:22,205 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 17:07:22,205 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1102588621] [2024-11-08 17:07:22,205 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 17:07:22,205 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 17:07:22,206 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 17:07:22,207 INFO L85 PathProgramCache]: Analyzing trace with hash -1971639971, now seen corresponding path program 1 times [2024-11-08 17:07:22,207 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 17:07:22,208 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1180044089] [2024-11-08 17:07:22,208 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 17:07:22,208 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 17:07:22,226 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:07:22,274 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 17:07:22,275 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 17:07:22,275 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1180044089] [2024-11-08 17:07:22,275 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1180044089] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 17:07:22,275 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 17:07:22,276 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 17:07:22,276 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1050760596] [2024-11-08 17:07:22,276 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 17:07:22,276 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 17:07:22,276 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 17:07:22,277 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 17:07:22,279 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 17:07:22,279 INFO L87 Difference]: Start difference. First operand 1701 states and 2508 transitions. cyclomatic complexity: 808 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 17:07:22,311 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 17:07:22,312 INFO L93 Difference]: Finished difference Result 1701 states and 2507 transitions. [2024-11-08 17:07:22,312 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1701 states and 2507 transitions. [2024-11-08 17:07:22,320 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1540 [2024-11-08 17:07:22,332 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1701 states to 1701 states and 2507 transitions. [2024-11-08 17:07:22,333 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1701 [2024-11-08 17:07:22,335 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1701 [2024-11-08 17:07:22,335 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1701 states and 2507 transitions. [2024-11-08 17:07:22,337 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 17:07:22,338 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1701 states and 2507 transitions. [2024-11-08 17:07:22,340 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1701 states and 2507 transitions. [2024-11-08 17:07:22,362 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1701 to 1701. [2024-11-08 17:07:22,366 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1701 states, 1701 states have (on average 1.4738389182833627) internal successors, (2507), 1700 states have internal predecessors, (2507), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 17:07:22,375 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1701 states to 1701 states and 2507 transitions. [2024-11-08 17:07:22,375 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1701 states and 2507 transitions. [2024-11-08 17:07:22,379 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 17:07:22,380 INFO L425 stractBuchiCegarLoop]: Abstraction has 1701 states and 2507 transitions. [2024-11-08 17:07:22,380 INFO L332 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-11-08 17:07:22,380 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1701 states and 2507 transitions. [2024-11-08 17:07:22,388 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1540 [2024-11-08 17:07:22,388 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 17:07:22,388 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 17:07:22,391 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 17:07:22,391 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 17:07:22,391 INFO L745 eck$LassoCheckResult]: Stem: 37792#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 37793#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 38585#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 38586#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 38453#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 38454#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 38547#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 38848#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 38981#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 38982#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 37768#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 37769#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 38913#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 38351#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 38352#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 38262#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 38263#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 38656#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 38007#L1174 assume !(0 == ~M_E~0); 38008#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 37861#L1179-1 assume !(0 == ~T2_E~0); 37765#L1184-1 assume !(0 == ~T3_E~0); 37766#L1189-1 assume !(0 == ~T4_E~0); 37808#L1194-1 assume !(0 == ~T5_E~0); 37901#L1199-1 assume !(0 == ~T6_E~0); 38780#L1204-1 assume !(0 == ~T7_E~0); 38701#L1209-1 assume !(0 == ~T8_E~0); 38702#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 39125#L1219-1 assume !(0 == ~T10_E~0); 39210#L1224-1 assume !(0 == ~T11_E~0); 38124#L1229-1 assume !(0 == ~T12_E~0); 37695#L1234-1 assume !(0 == ~E_1~0); 37696#L1239-1 assume !(0 == ~E_2~0); 37730#L1244-1 assume !(0 == ~E_3~0); 37731#L1249-1 assume !(0 == ~E_4~0); 38371#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 37625#L1259-1 assume !(0 == ~E_6~0); 37578#L1264-1 assume !(0 == ~E_7~0); 37579#L1269-1 assume !(0 == ~E_8~0); 39213#L1274-1 assume !(0 == ~E_9~0); 39153#L1279-1 assume !(0 == ~E_10~0); 37812#L1284-1 assume !(0 == ~E_11~0); 37813#L1289-1 assume !(0 == ~E_12~0); 38423#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 38424#L566 assume 1 == ~m_pc~0; 37595#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 37596#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 38467#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 38468#L1455 assume !(0 != activate_threads_~tmp~1#1); 38034#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 38035#L585 assume 1 == ~t1_pc~0; 37692#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 37693#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 38836#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 38837#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 39181#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 39177#L604 assume !(1 == ~t2_pc~0); 38742#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 38743#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 37982#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 37983#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 38943#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 38944#L623 assume 1 == ~t3_pc~0; 38208#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 37554#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38814#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 38815#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 38975#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 37592#L642 assume !(1 == ~t4_pc~0); 37593#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 38045#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 37650#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 37651#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 37669#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 38755#L661 assume 1 == ~t5_pc~0; 37825#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 37826#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 38673#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 39040#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 38789#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 38790#L680 assume !(1 == ~t6_pc~0); 38241#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 38242#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 37968#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 37969#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 39050#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 39175#L699 assume 1 == ~t7_pc~0; 38636#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 38637#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 38869#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 38529#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 38530#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 38425#L718 assume !(1 == ~t8_pc~0); 38426#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 37806#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 37807#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 37841#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 37842#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 37974#L737 assume 1 == ~t9_pc~0; 38827#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 38105#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 38014#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 38015#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 38282#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 38283#L756 assume 1 == ~t10_pc~0; 38859#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 38520#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 38775#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 38460#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 38084#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 38085#L775 assume !(1 == ~t11_pc~0); 38343#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 38344#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 39118#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 37740#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 37741#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 37922#L794 assume 1 == ~t12_pc~0; 37764#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 37743#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 37600#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 37601#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 37889#L1551-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 38355#L1307 assume !(1 == ~M_E~0); 38356#L1307-2 assume !(1 == ~T1_E~0); 38464#L1312-1 assume !(1 == ~T2_E~0); 38384#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 38385#L1322-1 assume !(1 == ~T4_E~0); 38095#L1327-1 assume !(1 == ~T5_E~0); 38096#L1332-1 assume !(1 == ~T6_E~0); 38641#L1337-1 assume !(1 == ~T7_E~0); 38598#L1342-1 assume !(1 == ~T8_E~0); 38599#L1347-1 assume !(1 == ~T9_E~0); 39011#L1352-1 assume !(1 == ~T10_E~0); 38870#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 38260#L1362-1 assume !(1 == ~T12_E~0); 38261#L1367-1 assume !(1 == ~E_1~0); 37902#L1372-1 assume !(1 == ~E_2~0); 37903#L1377-1 assume !(1 == ~E_3~0); 38193#L1382-1 assume !(1 == ~E_4~0); 38194#L1387-1 assume !(1 == ~E_5~0); 38744#L1392-1 assume !(1 == ~E_6~0); 38213#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 38214#L1402-1 assume !(1 == ~E_8~0); 37917#L1407-1 assume !(1 == ~E_9~0); 37918#L1412-1 assume !(1 == ~E_10~0); 38936#L1417-1 assume !(1 == ~E_11~0); 38937#L1422-1 assume !(1 == ~E_12~0); 39171#L1427-1 assume { :end_inline_reset_delta_events } true; 37724#L1768-2 [2024-11-08 17:07:22,392 INFO L747 eck$LassoCheckResult]: Loop: 37724#L1768-2 assume !false; 37725#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 38388#L1149-1 assume !false; 38768#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 38993#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 38102#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 38918#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 38988#L976 assume !(0 != eval_~tmp~0#1); 38416#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 38145#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 38146#L1174-3 assume 0 == ~M_E~0;~M_E~0 := 1; 38946#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 38684#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 38685#L1184-3 assume !(0 == ~T3_E~0); 38871#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 38515#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 37881#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 37882#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 38115#L1209-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 37538#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 37539#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 38295#L1224-3 assume !(0 == ~T11_E~0); 38296#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 38310#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 37734#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 37735#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 38170#L1249-3 assume 0 == ~E_4~0;~E_4~0 := 1; 38628#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 39121#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 38727#L1264-3 assume !(0 == ~E_7~0); 37738#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 37739#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 39151#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 38291#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 38292#L1289-3 assume 0 == ~E_12~0;~E_12~0 := 1; 38279#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37958#L566-39 assume 1 == ~m_pc~0; 37959#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 38558#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 38559#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 38611#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 38802#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 38803#L585-39 assume 1 == ~t1_pc~0; 38932#L586-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 37967#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 38167#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 39115#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 38840#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38535#L604-39 assume 1 == ~t2_pc~0; 38536#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 38174#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 38175#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 38354#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 38592#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 38156#L623-39 assume 1 == ~t3_pc~0; 37557#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 37558#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38820#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 38009#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 38010#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 38762#L642-39 assume 1 == ~t4_pc~0; 38347#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 38348#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 38510#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 38511#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 38992#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 37930#L661-39 assume 1 == ~t5_pc~0; 37931#L662-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 37564#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 38542#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 38543#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 38822#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 38823#L680-39 assume !(1 == ~t6_pc~0); 37632#L680-41 is_transmit6_triggered_~__retres1~6#1 := 0; 37631#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 39071#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 38082#L1503-39 assume !(0 != activate_threads_~tmp___5~0#1); 38083#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 39127#L699-39 assume 1 == ~t7_pc~0; 38517#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 38244#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 38245#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 38826#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 39065#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 39064#L718-39 assume 1 == ~t8_pc~0; 38429#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 38430#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 38922#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 38923#L1519-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 38672#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 38649#L737-39 assume !(1 == ~t9_pc~0); 38065#L737-41 is_transmit9_triggered_~__retres1~9#1 := 0; 38064#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 37657#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 37658#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 39039#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 38976#L756-39 assume 1 == ~t10_pc~0; 38977#L757-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 38444#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 39114#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 38328#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 38329#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 37679#L775-39 assume 1 == ~t11_pc~0; 37680#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 38319#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 38320#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 38569#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 38720#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 38370#L794-39 assume 1 == ~t12_pc~0; 38066#L795-13 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 38060#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 38151#is_transmit12_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 38152#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 37621#L1551-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37622#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 39098#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 39099#L1312-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 39212#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 38787#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 38788#L1327-3 assume !(1 == ~T5_E~0); 37753#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 37728#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 37729#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 38458#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 38590#L1352-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 38591#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 39047#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 39207#L1367-3 assume !(1 == ~E_1~0); 39198#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 37548#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 37549#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 38177#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 38178#L1392-3 assume 1 == ~E_6~0;~E_6~0 := 2; 38897#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 39165#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 38557#L1407-3 assume !(1 == ~E_9~0); 37837#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 37838#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 38471#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 38472#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 37845#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 37846#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 37912#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 37913#L1787 assume !(0 == start_simulation_~tmp~3#1); 38560#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 39107#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 37822#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 37567#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 37568#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 38163#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 38164#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 39074#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 37724#L1768-2 [2024-11-08 17:07:22,393 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 17:07:22,393 INFO L85 PathProgramCache]: Analyzing trace with hash -1079563311, now seen corresponding path program 1 times [2024-11-08 17:07:22,393 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 17:07:22,393 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2003761954] [2024-11-08 17:07:22,394 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 17:07:22,394 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 17:07:22,409 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:07:22,458 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 17:07:22,459 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 17:07:22,459 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2003761954] [2024-11-08 17:07:22,459 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2003761954] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 17:07:22,459 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 17:07:22,460 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 17:07:22,460 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [500172008] [2024-11-08 17:07:22,460 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 17:07:22,460 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 17:07:22,461 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 17:07:22,461 INFO L85 PathProgramCache]: Analyzing trace with hash 775624989, now seen corresponding path program 1 times [2024-11-08 17:07:22,461 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 17:07:22,461 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1231138885] [2024-11-08 17:07:22,461 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 17:07:22,462 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 17:07:22,477 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:07:22,524 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 17:07:22,524 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 17:07:22,524 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1231138885] [2024-11-08 17:07:22,524 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1231138885] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 17:07:22,525 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 17:07:22,525 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 17:07:22,525 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1700698041] [2024-11-08 17:07:22,525 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 17:07:22,525 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 17:07:22,525 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 17:07:22,526 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 17:07:22,526 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 17:07:22,526 INFO L87 Difference]: Start difference. First operand 1701 states and 2507 transitions. cyclomatic complexity: 807 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 17:07:22,560 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 17:07:22,560 INFO L93 Difference]: Finished difference Result 1701 states and 2506 transitions. [2024-11-08 17:07:22,561 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1701 states and 2506 transitions. [2024-11-08 17:07:22,570 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1540 [2024-11-08 17:07:22,579 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1701 states to 1701 states and 2506 transitions. [2024-11-08 17:07:22,579 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1701 [2024-11-08 17:07:22,581 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1701 [2024-11-08 17:07:22,581 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1701 states and 2506 transitions. [2024-11-08 17:07:22,583 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 17:07:22,584 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1701 states and 2506 transitions. [2024-11-08 17:07:22,586 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1701 states and 2506 transitions. [2024-11-08 17:07:22,606 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1701 to 1701. [2024-11-08 17:07:22,609 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1701 states, 1701 states have (on average 1.4732510288065843) internal successors, (2506), 1700 states have internal predecessors, (2506), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 17:07:22,615 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1701 states to 1701 states and 2506 transitions. [2024-11-08 17:07:22,615 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1701 states and 2506 transitions. [2024-11-08 17:07:22,615 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 17:07:22,616 INFO L425 stractBuchiCegarLoop]: Abstraction has 1701 states and 2506 transitions. [2024-11-08 17:07:22,616 INFO L332 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-11-08 17:07:22,616 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1701 states and 2506 transitions. [2024-11-08 17:07:22,624 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1540 [2024-11-08 17:07:22,624 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 17:07:22,624 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 17:07:22,627 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 17:07:22,627 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 17:07:22,627 INFO L745 eck$LassoCheckResult]: Stem: 41201#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 41202#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 41994#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 41995#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 41862#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 41863#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 41956#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 42255#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 42390#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 42391#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 41177#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 41178#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 42322#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 41760#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 41761#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 41671#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 41672#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 42065#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 41416#L1174 assume !(0 == ~M_E~0); 41417#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 41268#L1179-1 assume !(0 == ~T2_E~0); 41174#L1184-1 assume !(0 == ~T3_E~0); 41175#L1189-1 assume !(0 == ~T4_E~0); 41217#L1194-1 assume !(0 == ~T5_E~0); 41310#L1199-1 assume !(0 == ~T6_E~0); 42189#L1204-1 assume !(0 == ~T7_E~0); 42110#L1209-1 assume !(0 == ~T8_E~0); 42111#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 42534#L1219-1 assume !(0 == ~T10_E~0); 42619#L1224-1 assume !(0 == ~T11_E~0); 41533#L1229-1 assume !(0 == ~T12_E~0); 41104#L1234-1 assume !(0 == ~E_1~0); 41105#L1239-1 assume !(0 == ~E_2~0); 41137#L1244-1 assume !(0 == ~E_3~0); 41138#L1249-1 assume !(0 == ~E_4~0); 41780#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 41034#L1259-1 assume !(0 == ~E_6~0); 40987#L1264-1 assume !(0 == ~E_7~0); 40988#L1269-1 assume !(0 == ~E_8~0); 42622#L1274-1 assume !(0 == ~E_9~0); 42561#L1279-1 assume !(0 == ~E_10~0); 41221#L1284-1 assume !(0 == ~E_11~0); 41222#L1289-1 assume !(0 == ~E_12~0); 41832#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 41833#L566 assume 1 == ~m_pc~0; 41004#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 41005#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41876#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 41877#L1455 assume !(0 != activate_threads_~tmp~1#1); 41443#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 41444#L585 assume 1 == ~t1_pc~0; 41101#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 41102#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 42245#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 42246#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 42590#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 42586#L604 assume !(1 == ~t2_pc~0); 42151#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 42152#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 41386#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 41387#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 42350#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 42351#L623 assume 1 == ~t3_pc~0; 41617#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 40963#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 42220#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 42221#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 42384#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 41001#L642 assume !(1 == ~t4_pc~0); 41002#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 41454#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 41056#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 41057#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 41078#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 42164#L661 assume 1 == ~t5_pc~0; 41234#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 41235#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 42082#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 42449#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 42196#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 42197#L680 assume !(1 == ~t6_pc~0); 41650#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 41651#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 41377#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 41378#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 42459#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 42583#L699 assume 1 == ~t7_pc~0; 42045#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 42046#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 42278#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 41938#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 41939#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 41834#L718 assume !(1 == ~t8_pc~0); 41835#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 41215#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 41216#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 41250#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 41251#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 41383#L737 assume 1 == ~t9_pc~0; 42234#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 41514#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 41423#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 41424#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 41691#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 41692#L756 assume 1 == ~t10_pc~0; 42268#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 41929#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 42184#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 41869#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 41493#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 41494#L775 assume !(1 == ~t11_pc~0); 41752#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 41753#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 42527#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 41149#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 41150#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 41331#L794 assume 1 == ~t12_pc~0; 41172#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 41152#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 41007#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 41008#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 41296#L1551-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41764#L1307 assume !(1 == ~M_E~0); 41765#L1307-2 assume !(1 == ~T1_E~0); 41873#L1312-1 assume !(1 == ~T2_E~0); 41793#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 41794#L1322-1 assume !(1 == ~T4_E~0); 41504#L1327-1 assume !(1 == ~T5_E~0); 41505#L1332-1 assume !(1 == ~T6_E~0); 42050#L1337-1 assume !(1 == ~T7_E~0); 42007#L1342-1 assume !(1 == ~T8_E~0); 42008#L1347-1 assume !(1 == ~T9_E~0); 42420#L1352-1 assume !(1 == ~T10_E~0); 42279#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 41669#L1362-1 assume !(1 == ~T12_E~0); 41670#L1367-1 assume !(1 == ~E_1~0); 41311#L1372-1 assume !(1 == ~E_2~0); 41312#L1377-1 assume !(1 == ~E_3~0); 41602#L1382-1 assume !(1 == ~E_4~0); 41603#L1387-1 assume !(1 == ~E_5~0); 42153#L1392-1 assume !(1 == ~E_6~0); 41620#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 41621#L1402-1 assume !(1 == ~E_8~0); 41326#L1407-1 assume !(1 == ~E_9~0); 41327#L1412-1 assume !(1 == ~E_10~0); 42345#L1417-1 assume !(1 == ~E_11~0); 42346#L1422-1 assume !(1 == ~E_12~0); 42580#L1427-1 assume { :end_inline_reset_delta_events } true; 41133#L1768-2 [2024-11-08 17:07:22,628 INFO L747 eck$LassoCheckResult]: Loop: 41133#L1768-2 assume !false; 41134#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 41797#L1149-1 assume !false; 42175#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 42402#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 41511#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 42327#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 42397#L976 assume !(0 != eval_~tmp~0#1); 41825#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 41554#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 41555#L1174-3 assume 0 == ~M_E~0;~M_E~0 := 1; 42355#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 42093#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 42094#L1184-3 assume !(0 == ~T3_E~0); 42280#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 41924#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 41287#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 41288#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 41524#L1209-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 40947#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 40948#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 41704#L1224-3 assume !(0 == ~T11_E~0); 41705#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 41719#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 41143#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 41144#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 41579#L1249-3 assume 0 == ~E_4~0;~E_4~0 := 1; 42037#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 42530#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 42136#L1264-3 assume !(0 == ~E_7~0); 41147#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 41148#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 42560#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 41700#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 41701#L1289-3 assume 0 == ~E_12~0;~E_12~0 := 1; 41688#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 41367#L566-39 assume 1 == ~m_pc~0; 41368#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 41967#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41968#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 42020#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 42211#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 42212#L585-39 assume 1 == ~t1_pc~0; 42341#L586-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 41376#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 41576#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 42524#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 42249#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 41944#L604-39 assume 1 == ~t2_pc~0; 41945#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 41583#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 41584#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 41763#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 41997#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 41565#L623-39 assume 1 == ~t3_pc~0; 40964#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 40965#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 42229#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 41418#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 41419#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 42171#L642-39 assume 1 == ~t4_pc~0; 41754#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 41755#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 41919#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 41920#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 42401#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 41337#L661-39 assume 1 == ~t5_pc~0; 41338#L662-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 40973#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 41951#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 41952#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 42231#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 42232#L680-39 assume !(1 == ~t6_pc~0); 41041#L680-41 is_transmit6_triggered_~__retres1~6#1 := 0; 41040#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 42480#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 41491#L1503-39 assume !(0 != activate_threads_~tmp___5~0#1); 41492#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 42536#L699-39 assume 1 == ~t7_pc~0; 41926#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 41653#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 41654#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 42236#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 42476#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 42473#L718-39 assume !(1 == ~t8_pc~0); 41840#L718-41 is_transmit8_triggered_~__retres1~8#1 := 0; 41839#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 42332#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 42333#L1519-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 42081#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 42058#L737-39 assume 1 == ~t9_pc~0; 41472#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 41473#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 41067#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 41068#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 42448#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 42385#L756-39 assume 1 == ~t10_pc~0; 42386#L757-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 41853#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 42523#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 41737#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 41738#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 41088#L775-39 assume 1 == ~t11_pc~0; 41089#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 41728#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 41729#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 41978#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 42129#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 41779#L794-39 assume 1 == ~t12_pc~0; 41475#L795-13 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 41469#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 41562#is_transmit12_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 41563#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 41030#L1551-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41031#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 42507#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 42508#L1312-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 42621#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 42198#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 42199#L1327-3 assume !(1 == ~T5_E~0); 41164#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 41139#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 41140#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 41867#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 42000#L1352-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 42001#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 42456#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 42616#L1367-3 assume !(1 == ~E_1~0); 42607#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 40960#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 40961#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 41586#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 41587#L1392-3 assume 1 == ~E_6~0;~E_6~0 := 2; 42306#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 42574#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 41966#L1407-3 assume !(1 == ~E_9~0); 41246#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 41247#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 41881#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 41882#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 41254#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 41255#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 41322#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 41323#L1787 assume !(0 == start_simulation_~tmp~3#1); 41970#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 42516#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 41231#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 40979#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 40980#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 41572#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 41573#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 42483#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 41133#L1768-2 [2024-11-08 17:07:22,629 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 17:07:22,629 INFO L85 PathProgramCache]: Analyzing trace with hash -1368382701, now seen corresponding path program 1 times [2024-11-08 17:07:22,629 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 17:07:22,629 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [275110484] [2024-11-08 17:07:22,629 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 17:07:22,630 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 17:07:22,645 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:07:22,701 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 17:07:22,701 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 17:07:22,701 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [275110484] [2024-11-08 17:07:22,701 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [275110484] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 17:07:22,702 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 17:07:22,702 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-08 17:07:22,702 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1779588326] [2024-11-08 17:07:22,702 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 17:07:22,703 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 17:07:22,703 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 17:07:22,704 INFO L85 PathProgramCache]: Analyzing trace with hash 793712093, now seen corresponding path program 1 times [2024-11-08 17:07:22,704 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 17:07:22,704 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [565393825] [2024-11-08 17:07:22,704 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 17:07:22,704 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 17:07:22,725 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:07:22,807 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 17:07:22,807 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 17:07:22,808 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [565393825] [2024-11-08 17:07:22,808 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [565393825] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 17:07:22,808 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 17:07:22,808 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 17:07:22,808 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [410756631] [2024-11-08 17:07:22,809 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 17:07:22,809 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 17:07:22,810 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 17:07:22,810 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 17:07:22,811 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 17:07:22,812 INFO L87 Difference]: Start difference. First operand 1701 states and 2506 transitions. cyclomatic complexity: 806 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 2 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 17:07:22,867 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 17:07:22,870 INFO L93 Difference]: Finished difference Result 1701 states and 2501 transitions. [2024-11-08 17:07:22,870 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1701 states and 2501 transitions. [2024-11-08 17:07:22,884 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1540 [2024-11-08 17:07:22,899 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1701 states to 1701 states and 2501 transitions. [2024-11-08 17:07:22,899 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1701 [2024-11-08 17:07:22,901 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1701 [2024-11-08 17:07:22,902 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1701 states and 2501 transitions. [2024-11-08 17:07:22,904 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 17:07:22,904 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1701 states and 2501 transitions. [2024-11-08 17:07:22,907 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1701 states and 2501 transitions. [2024-11-08 17:07:22,929 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1701 to 1701. [2024-11-08 17:07:22,932 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1701 states, 1701 states have (on average 1.4703115814226926) internal successors, (2501), 1700 states have internal predecessors, (2501), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 17:07:22,939 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1701 states to 1701 states and 2501 transitions. [2024-11-08 17:07:22,939 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1701 states and 2501 transitions. [2024-11-08 17:07:22,940 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 17:07:22,941 INFO L425 stractBuchiCegarLoop]: Abstraction has 1701 states and 2501 transitions. [2024-11-08 17:07:22,942 INFO L332 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2024-11-08 17:07:22,942 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1701 states and 2501 transitions. [2024-11-08 17:07:22,951 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1540 [2024-11-08 17:07:22,951 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 17:07:22,951 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 17:07:22,954 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 17:07:22,954 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 17:07:22,955 INFO L745 eck$LassoCheckResult]: Stem: 44610#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 44611#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 45403#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 45404#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 45271#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 45272#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 45365#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 45664#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 45799#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 45800#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 44586#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 44587#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 45731#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 45169#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 45170#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 45080#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 45081#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 45474#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 44825#L1174 assume !(0 == ~M_E~0); 44826#L1174-2 assume !(0 == ~T1_E~0); 44677#L1179-1 assume !(0 == ~T2_E~0); 44583#L1184-1 assume !(0 == ~T3_E~0); 44584#L1189-1 assume !(0 == ~T4_E~0); 44626#L1194-1 assume !(0 == ~T5_E~0); 44719#L1199-1 assume !(0 == ~T6_E~0); 45598#L1204-1 assume !(0 == ~T7_E~0); 45519#L1209-1 assume !(0 == ~T8_E~0); 45520#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 45943#L1219-1 assume !(0 == ~T10_E~0); 46028#L1224-1 assume !(0 == ~T11_E~0); 44942#L1229-1 assume !(0 == ~T12_E~0); 44513#L1234-1 assume !(0 == ~E_1~0); 44514#L1239-1 assume !(0 == ~E_2~0); 44546#L1244-1 assume !(0 == ~E_3~0); 44547#L1249-1 assume !(0 == ~E_4~0); 45189#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 44443#L1259-1 assume !(0 == ~E_6~0); 44396#L1264-1 assume !(0 == ~E_7~0); 44397#L1269-1 assume !(0 == ~E_8~0); 46031#L1274-1 assume !(0 == ~E_9~0); 45970#L1279-1 assume !(0 == ~E_10~0); 44630#L1284-1 assume !(0 == ~E_11~0); 44631#L1289-1 assume !(0 == ~E_12~0); 45241#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 45242#L566 assume 1 == ~m_pc~0; 44413#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 44414#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 45285#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 45286#L1455 assume !(0 != activate_threads_~tmp~1#1); 44852#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 44853#L585 assume 1 == ~t1_pc~0; 44510#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 44511#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 45654#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 45655#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 45999#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 45995#L604 assume !(1 == ~t2_pc~0); 45560#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 45561#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 44795#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 44796#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 45759#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 45760#L623 assume 1 == ~t3_pc~0; 45026#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 44372#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 45629#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 45630#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 45793#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 44410#L642 assume !(1 == ~t4_pc~0); 44411#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 44863#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 44465#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 44466#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 44487#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 45573#L661 assume 1 == ~t5_pc~0; 44643#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 44644#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 45491#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 45858#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 45605#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 45606#L680 assume !(1 == ~t6_pc~0); 45059#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 45060#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 44786#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 44787#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 45868#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 45992#L699 assume 1 == ~t7_pc~0; 45454#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 45455#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 45687#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 45347#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 45348#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 45243#L718 assume !(1 == ~t8_pc~0); 45244#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 44624#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 44625#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 44659#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 44660#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 44792#L737 assume 1 == ~t9_pc~0; 45643#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 44923#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 44832#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 44833#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 45100#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 45101#L756 assume 1 == ~t10_pc~0; 45677#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 45338#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 45593#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 45278#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 44902#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 44903#L775 assume !(1 == ~t11_pc~0); 45161#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 45162#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 45936#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 44558#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 44559#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 44740#L794 assume 1 == ~t12_pc~0; 44581#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 44561#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 44416#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 44417#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 44705#L1551-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 45173#L1307 assume !(1 == ~M_E~0); 45174#L1307-2 assume !(1 == ~T1_E~0); 45282#L1312-1 assume !(1 == ~T2_E~0); 45202#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 45203#L1322-1 assume !(1 == ~T4_E~0); 44913#L1327-1 assume !(1 == ~T5_E~0); 44914#L1332-1 assume !(1 == ~T6_E~0); 45459#L1337-1 assume !(1 == ~T7_E~0); 45416#L1342-1 assume !(1 == ~T8_E~0); 45417#L1347-1 assume !(1 == ~T9_E~0); 45829#L1352-1 assume !(1 == ~T10_E~0); 45688#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 45078#L1362-1 assume !(1 == ~T12_E~0); 45079#L1367-1 assume !(1 == ~E_1~0); 44720#L1372-1 assume !(1 == ~E_2~0); 44721#L1377-1 assume !(1 == ~E_3~0); 45011#L1382-1 assume !(1 == ~E_4~0); 45012#L1387-1 assume !(1 == ~E_5~0); 45562#L1392-1 assume !(1 == ~E_6~0); 45029#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 45030#L1402-1 assume !(1 == ~E_8~0); 44735#L1407-1 assume !(1 == ~E_9~0); 44736#L1412-1 assume !(1 == ~E_10~0); 45754#L1417-1 assume !(1 == ~E_11~0); 45755#L1422-1 assume !(1 == ~E_12~0); 45989#L1427-1 assume { :end_inline_reset_delta_events } true; 44542#L1768-2 [2024-11-08 17:07:22,956 INFO L747 eck$LassoCheckResult]: Loop: 44542#L1768-2 assume !false; 44543#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 45206#L1149-1 assume !false; 45584#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 45811#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 44920#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 45736#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 45806#L976 assume !(0 != eval_~tmp~0#1); 45234#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 44963#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 44964#L1174-3 assume 0 == ~M_E~0;~M_E~0 := 1; 45764#L1174-5 assume !(0 == ~T1_E~0); 45502#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 45503#L1184-3 assume !(0 == ~T3_E~0); 45689#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 45333#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 44696#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 44697#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 44933#L1209-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 44356#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 44357#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 45113#L1224-3 assume !(0 == ~T11_E~0); 45114#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 45128#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 44552#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 44553#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 44988#L1249-3 assume 0 == ~E_4~0;~E_4~0 := 1; 45446#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 45939#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 45545#L1264-3 assume !(0 == ~E_7~0); 44556#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 44557#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 45969#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 45109#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 45110#L1289-3 assume 0 == ~E_12~0;~E_12~0 := 1; 45097#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 44776#L566-39 assume 1 == ~m_pc~0; 44777#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 45376#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 45377#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 45429#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 45620#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 45621#L585-39 assume !(1 == ~t1_pc~0); 44784#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 44785#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 44985#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 45933#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 45658#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 45353#L604-39 assume 1 == ~t2_pc~0; 45354#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 44992#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 44993#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 45172#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 45406#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 44974#L623-39 assume 1 == ~t3_pc~0; 44373#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 44374#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 45638#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 44827#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 44828#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 45580#L642-39 assume 1 == ~t4_pc~0; 45163#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 45164#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 45328#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 45329#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 45810#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 44746#L661-39 assume 1 == ~t5_pc~0; 44747#L662-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 44382#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 45360#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 45361#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 45640#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 45641#L680-39 assume 1 == ~t6_pc~0; 44448#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 44449#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 45889#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 44900#L1503-39 assume !(0 != activate_threads_~tmp___5~0#1); 44901#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 45945#L699-39 assume 1 == ~t7_pc~0; 45335#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 45062#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 45063#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 45645#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 45885#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 45882#L718-39 assume !(1 == ~t8_pc~0); 45249#L718-41 is_transmit8_triggered_~__retres1~8#1 := 0; 45248#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 45741#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 45742#L1519-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 45490#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 45467#L737-39 assume 1 == ~t9_pc~0; 44881#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 44882#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 44476#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 44477#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 45857#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 45794#L756-39 assume 1 == ~t10_pc~0; 45795#L757-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 45262#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 45932#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 45146#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 45147#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 44497#L775-39 assume 1 == ~t11_pc~0; 44498#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 45137#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 45138#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 45387#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 45538#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 45188#L794-39 assume 1 == ~t12_pc~0; 44884#L795-13 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 44878#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 44971#is_transmit12_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 44972#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 44439#L1551-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 44440#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 45916#L1307-5 assume !(1 == ~T1_E~0); 45917#L1312-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 46030#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 45607#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 45608#L1327-3 assume !(1 == ~T5_E~0); 44573#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 44548#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 44549#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 45276#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 45409#L1352-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 45410#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 45865#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 46025#L1367-3 assume !(1 == ~E_1~0); 46016#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 44369#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 44370#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 44995#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 44996#L1392-3 assume 1 == ~E_6~0;~E_6~0 := 2; 45715#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 45983#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 45375#L1407-3 assume !(1 == ~E_9~0); 44655#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 44656#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 45290#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 45291#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 44663#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 44664#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 44731#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 44732#L1787 assume !(0 == start_simulation_~tmp~3#1); 45379#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 45925#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 44640#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 44388#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 44389#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 44981#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 44982#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 45892#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 44542#L1768-2 [2024-11-08 17:07:22,956 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 17:07:22,957 INFO L85 PathProgramCache]: Analyzing trace with hash 1978532629, now seen corresponding path program 1 times [2024-11-08 17:07:22,957 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 17:07:22,957 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [122508959] [2024-11-08 17:07:22,958 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 17:07:22,958 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 17:07:22,979 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:07:23,074 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 17:07:23,074 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 17:07:23,075 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [122508959] [2024-11-08 17:07:23,075 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [122508959] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 17:07:23,075 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 17:07:23,075 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 17:07:23,076 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2060738420] [2024-11-08 17:07:23,076 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 17:07:23,076 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 17:07:23,076 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 17:07:23,077 INFO L85 PathProgramCache]: Analyzing trace with hash 442272161, now seen corresponding path program 1 times [2024-11-08 17:07:23,077 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 17:07:23,077 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1246686401] [2024-11-08 17:07:23,077 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 17:07:23,077 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 17:07:23,097 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:07:23,147 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 17:07:23,147 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 17:07:23,147 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1246686401] [2024-11-08 17:07:23,147 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1246686401] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 17:07:23,147 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 17:07:23,148 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 17:07:23,148 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [533114266] [2024-11-08 17:07:23,148 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 17:07:23,148 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 17:07:23,149 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 17:07:23,149 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-08 17:07:23,149 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-08 17:07:23,149 INFO L87 Difference]: Start difference. First operand 1701 states and 2501 transitions. cyclomatic complexity: 801 Second operand has 4 states, 4 states have (on average 37.0) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 17:07:23,335 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 17:07:23,336 INFO L93 Difference]: Finished difference Result 3264 states and 4792 transitions. [2024-11-08 17:07:23,336 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3264 states and 4792 transitions. [2024-11-08 17:07:23,353 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3080 [2024-11-08 17:07:23,370 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3264 states to 3264 states and 4792 transitions. [2024-11-08 17:07:23,371 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3264 [2024-11-08 17:07:23,375 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3264 [2024-11-08 17:07:23,375 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3264 states and 4792 transitions. [2024-11-08 17:07:23,379 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 17:07:23,380 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3264 states and 4792 transitions. [2024-11-08 17:07:23,384 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3264 states and 4792 transitions. [2024-11-08 17:07:23,429 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3264 to 3264. [2024-11-08 17:07:23,434 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3264 states, 3264 states have (on average 1.4681372549019607) internal successors, (4792), 3263 states have internal predecessors, (4792), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 17:07:23,443 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3264 states to 3264 states and 4792 transitions. [2024-11-08 17:07:23,443 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3264 states and 4792 transitions. [2024-11-08 17:07:23,443 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-08 17:07:23,444 INFO L425 stractBuchiCegarLoop]: Abstraction has 3264 states and 4792 transitions. [2024-11-08 17:07:23,444 INFO L332 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2024-11-08 17:07:23,444 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3264 states and 4792 transitions. [2024-11-08 17:07:23,458 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3080 [2024-11-08 17:07:23,459 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 17:07:23,459 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 17:07:23,461 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 17:07:23,461 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 17:07:23,462 INFO L745 eck$LassoCheckResult]: Stem: 49586#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 49587#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 50382#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 50383#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 50248#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 50249#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 50343#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 50653#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 50800#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 50801#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 49562#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 49563#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 50728#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 50146#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 50147#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 50057#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 50058#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 50458#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 49801#L1174 assume !(0 == ~M_E~0); 49802#L1174-2 assume !(0 == ~T1_E~0); 49653#L1179-1 assume !(0 == ~T2_E~0); 49559#L1184-1 assume !(0 == ~T3_E~0); 49560#L1189-1 assume !(0 == ~T4_E~0); 49602#L1194-1 assume !(0 == ~T5_E~0); 49695#L1199-1 assume !(0 == ~T6_E~0); 50584#L1204-1 assume !(0 == ~T7_E~0); 50504#L1209-1 assume !(0 == ~T8_E~0); 50505#L1214-1 assume !(0 == ~T9_E~0); 50951#L1219-1 assume !(0 == ~T10_E~0); 51084#L1224-1 assume !(0 == ~T11_E~0); 49918#L1229-1 assume !(0 == ~T12_E~0); 49489#L1234-1 assume !(0 == ~E_1~0); 49490#L1239-1 assume !(0 == ~E_2~0); 49522#L1244-1 assume !(0 == ~E_3~0); 49523#L1249-1 assume !(0 == ~E_4~0); 50166#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 49419#L1259-1 assume !(0 == ~E_6~0); 49371#L1264-1 assume !(0 == ~E_7~0); 49372#L1269-1 assume !(0 == ~E_8~0); 51090#L1274-1 assume !(0 == ~E_9~0); 50983#L1279-1 assume !(0 == ~E_10~0); 49606#L1284-1 assume !(0 == ~E_11~0); 49607#L1289-1 assume !(0 == ~E_12~0); 50218#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 50219#L566 assume 1 == ~m_pc~0; 49388#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 49389#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 50262#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 50263#L1455 assume !(0 != activate_threads_~tmp~1#1); 49828#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 49829#L585 assume 1 == ~t1_pc~0; 49486#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 49487#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 50643#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 50644#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 51020#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 51014#L604 assume !(1 == ~t2_pc~0); 50546#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 50547#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 49771#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 49772#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 50758#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 50759#L623 assume 1 == ~t3_pc~0; 50002#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 49347#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 50617#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 50618#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 50792#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 49385#L642 assume !(1 == ~t4_pc~0); 49386#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 49839#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 49441#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 49442#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 49463#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 50559#L661 assume 1 == ~t5_pc~0; 49619#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 49620#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 50475#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 50861#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 50592#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 50593#L680 assume !(1 == ~t6_pc~0); 50036#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 50037#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 49762#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 49763#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 50871#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 51011#L699 assume 1 == ~t7_pc~0; 50436#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 50437#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 50678#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 50325#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 50326#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 50220#L718 assume !(1 == ~t8_pc~0); 50221#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 49600#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 49601#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 49635#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 49636#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 49768#L737 assume 1 == ~t9_pc~0; 50631#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 49899#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 49808#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 49809#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 50077#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 50078#L756 assume 1 == ~t10_pc~0; 50666#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 50316#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 50579#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 50255#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 49878#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 49879#L775 assume !(1 == ~t11_pc~0); 50138#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 50139#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 50944#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 49534#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 49535#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 49716#L794 assume 1 == ~t12_pc~0; 49558#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 49537#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 49394#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 49395#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 49681#L1551-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 50150#L1307 assume !(1 == ~M_E~0); 50151#L1307-2 assume !(1 == ~T1_E~0); 50259#L1312-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 50179#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 50180#L1322-1 assume !(1 == ~T4_E~0); 49889#L1327-1 assume !(1 == ~T5_E~0); 49890#L1332-1 assume !(1 == ~T6_E~0); 50441#L1337-1 assume !(1 == ~T7_E~0); 50396#L1342-1 assume !(1 == ~T8_E~0); 50397#L1347-1 assume !(1 == ~T9_E~0); 50832#L1352-1 assume !(1 == ~T10_E~0); 50679#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 50055#L1362-1 assume !(1 == ~T12_E~0); 50056#L1367-1 assume !(1 == ~E_1~0); 49696#L1372-1 assume !(1 == ~E_2~0); 49697#L1377-1 assume !(1 == ~E_3~0); 49987#L1382-1 assume !(1 == ~E_4~0); 49988#L1387-1 assume !(1 == ~E_5~0); 50548#L1392-1 assume !(1 == ~E_6~0); 50005#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 50006#L1402-1 assume !(1 == ~E_8~0); 49711#L1407-1 assume !(1 == ~E_9~0); 49712#L1412-1 assume !(1 == ~E_10~0); 51066#L1417-1 assume !(1 == ~E_11~0); 51142#L1422-1 assume !(1 == ~E_12~0); 51135#L1427-1 assume { :end_inline_reset_delta_events } true; 51129#L1768-2 [2024-11-08 17:07:23,463 INFO L747 eck$LassoCheckResult]: Loop: 51129#L1768-2 assume !false; 51124#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 51120#L1149-1 assume !false; 51119#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 51111#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 51105#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 51104#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 51102#L976 assume !(0 != eval_~tmp~0#1); 51101#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 51100#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 51099#L1174-3 assume 0 == ~M_E~0;~M_E~0 := 1; 51098#L1174-5 assume !(0 == ~T1_E~0); 51096#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 51097#L1184-3 assume !(0 == ~T3_E~0); 52495#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 52494#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 52493#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 52492#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 52491#L1209-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 52490#L1214-3 assume !(0 == ~T9_E~0); 52489#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 52488#L1224-3 assume !(0 == ~T11_E~0); 52487#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 52486#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 52485#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 52484#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 52483#L1249-3 assume 0 == ~E_4~0;~E_4~0 := 1; 52482#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 52481#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 52480#L1264-3 assume !(0 == ~E_7~0); 52479#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 52478#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 52477#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 52476#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 52475#L1289-3 assume 0 == ~E_12~0;~E_12~0 := 1; 52474#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 52473#L566-39 assume 1 == ~m_pc~0; 52471#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 52470#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 52469#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 52468#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 52467#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 52466#L585-39 assume !(1 == ~t1_pc~0); 52464#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 52463#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 52462#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 52461#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 52460#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 52459#L604-39 assume 1 == ~t2_pc~0; 52457#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 52456#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 52455#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 52454#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 52453#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 52452#L623-39 assume !(1 == ~t3_pc~0); 52450#L623-41 is_transmit3_triggered_~__retres1~3#1 := 0; 52449#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 52448#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 52447#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 52446#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 52445#L642-39 assume 1 == ~t4_pc~0; 52443#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 52442#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 52441#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 52440#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 52439#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 52438#L661-39 assume !(1 == ~t5_pc~0); 52436#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 52435#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 52434#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 52433#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 52432#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 52431#L680-39 assume 1 == ~t6_pc~0; 52429#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 52428#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 52427#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 52426#L1503-39 assume !(0 != activate_threads_~tmp___5~0#1); 52425#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 52424#L699-39 assume 1 == ~t7_pc~0; 52422#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 52421#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 52420#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 52419#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 52418#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 52417#L718-39 assume !(1 == ~t8_pc~0); 52416#L718-41 is_transmit8_triggered_~__retres1~8#1 := 0; 52414#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 52413#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 52412#L1519-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 52411#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 52410#L737-39 assume 1 == ~t9_pc~0; 52408#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 52407#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 52406#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 52405#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 52404#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 52403#L756-39 assume !(1 == ~t10_pc~0); 52401#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 52400#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 52399#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 52398#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 52397#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 52396#L775-39 assume 1 == ~t11_pc~0; 52394#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 52393#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 52392#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 52391#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 52390#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 52389#L794-39 assume !(1 == ~t12_pc~0); 52312#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 52310#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 52308#is_transmit12_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 52306#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 52305#L1551-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 52304#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 52303#L1307-5 assume !(1 == ~T1_E~0); 52302#L1312-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 51089#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 52300#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 52298#L1327-3 assume !(1 == ~T5_E~0); 52296#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 52294#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 52292#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 52289#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 50741#L1352-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 52286#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 52284#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 52282#L1367-3 assume !(1 == ~E_1~0); 52280#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 52278#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 52276#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 52275#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 52273#L1392-3 assume 1 == ~E_6~0;~E_6~0 := 2; 52271#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 52269#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 52267#L1407-3 assume !(1 == ~E_9~0); 52265#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 52263#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 52262#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 52260#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 52246#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 52233#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 52232#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 52231#L1787 assume !(0 == start_simulation_~tmp~3#1); 52229#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 52221#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 52215#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 52214#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 52213#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 51149#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 51143#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 51136#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 51129#L1768-2 [2024-11-08 17:07:23,464 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 17:07:23,464 INFO L85 PathProgramCache]: Analyzing trace with hash -1694374055, now seen corresponding path program 1 times [2024-11-08 17:07:23,464 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 17:07:23,464 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [336348415] [2024-11-08 17:07:23,464 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 17:07:23,465 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 17:07:23,482 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:07:23,588 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 17:07:23,589 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 17:07:23,589 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [336348415] [2024-11-08 17:07:23,589 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [336348415] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 17:07:23,589 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 17:07:23,589 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 17:07:23,590 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1658777617] [2024-11-08 17:07:23,590 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 17:07:23,590 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 17:07:23,590 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 17:07:23,590 INFO L85 PathProgramCache]: Analyzing trace with hash -1408891233, now seen corresponding path program 1 times [2024-11-08 17:07:23,591 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 17:07:23,591 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [752908721] [2024-11-08 17:07:23,591 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 17:07:23,591 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 17:07:23,612 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:07:23,665 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 17:07:23,665 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 17:07:23,666 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [752908721] [2024-11-08 17:07:23,666 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [752908721] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 17:07:23,666 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 17:07:23,666 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 17:07:23,666 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [133772263] [2024-11-08 17:07:23,666 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 17:07:23,667 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 17:07:23,667 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 17:07:23,667 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-08 17:07:23,668 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-08 17:07:23,668 INFO L87 Difference]: Start difference. First operand 3264 states and 4792 transitions. cyclomatic complexity: 1530 Second operand has 4 states, 4 states have (on average 37.0) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 17:07:23,967 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 17:07:23,967 INFO L93 Difference]: Finished difference Result 6184 states and 9069 transitions. [2024-11-08 17:07:23,967 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6184 states and 9069 transitions. [2024-11-08 17:07:24,008 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5974 [2024-11-08 17:07:24,031 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6184 states to 6184 states and 9069 transitions. [2024-11-08 17:07:24,032 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6184 [2024-11-08 17:07:24,038 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6184 [2024-11-08 17:07:24,038 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6184 states and 9069 transitions. [2024-11-08 17:07:24,047 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 17:07:24,047 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6184 states and 9069 transitions. [2024-11-08 17:07:24,054 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6184 states and 9069 transitions. [2024-11-08 17:07:24,126 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6184 to 6182. [2024-11-08 17:07:24,135 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6182 states, 6182 states have (on average 1.4666774506632159) internal successors, (9067), 6181 states have internal predecessors, (9067), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 17:07:24,151 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6182 states to 6182 states and 9067 transitions. [2024-11-08 17:07:24,151 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6182 states and 9067 transitions. [2024-11-08 17:07:24,152 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-08 17:07:24,152 INFO L425 stractBuchiCegarLoop]: Abstraction has 6182 states and 9067 transitions. [2024-11-08 17:07:24,152 INFO L332 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2024-11-08 17:07:24,152 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6182 states and 9067 transitions. [2024-11-08 17:07:24,177 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5974 [2024-11-08 17:07:24,177 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 17:07:24,177 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 17:07:24,180 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 17:07:24,180 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 17:07:24,180 INFO L745 eck$LassoCheckResult]: Stem: 59044#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 59045#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 59844#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 59845#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 59711#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 59712#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 59806#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 60109#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 60258#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 60259#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 59020#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 59021#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 60182#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 59607#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 59608#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 59518#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 59519#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 59917#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 59262#L1174 assume !(0 == ~M_E~0); 59263#L1174-2 assume !(0 == ~T1_E~0); 59113#L1179-1 assume !(0 == ~T2_E~0); 59017#L1184-1 assume !(0 == ~T3_E~0); 59018#L1189-1 assume !(0 == ~T4_E~0); 59062#L1194-1 assume !(0 == ~T5_E~0); 59155#L1199-1 assume !(0 == ~T6_E~0); 60043#L1204-1 assume !(0 == ~T7_E~0); 59962#L1209-1 assume !(0 == ~T8_E~0); 59963#L1214-1 assume !(0 == ~T9_E~0); 60422#L1219-1 assume !(0 == ~T10_E~0); 60531#L1224-1 assume !(0 == ~T11_E~0); 59379#L1229-1 assume !(0 == ~T12_E~0); 58947#L1234-1 assume !(0 == ~E_1~0); 58948#L1239-1 assume !(0 == ~E_2~0); 58980#L1244-1 assume !(0 == ~E_3~0); 58981#L1249-1 assume !(0 == ~E_4~0); 59627#L1254-1 assume !(0 == ~E_5~0); 58877#L1259-1 assume !(0 == ~E_6~0); 58829#L1264-1 assume !(0 == ~E_7~0); 58830#L1269-1 assume !(0 == ~E_8~0); 60540#L1274-1 assume !(0 == ~E_9~0); 60455#L1279-1 assume !(0 == ~E_10~0); 59066#L1284-1 assume !(0 == ~E_11~0); 59067#L1289-1 assume !(0 == ~E_12~0); 59681#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 59682#L566 assume 1 == ~m_pc~0; 58846#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 58847#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 59725#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 59726#L1455 assume !(0 != activate_threads_~tmp~1#1); 59289#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 59290#L585 assume 1 == ~t1_pc~0; 58944#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 58945#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 60099#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 60100#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 60487#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 60483#L604 assume !(1 == ~t2_pc~0); 60004#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 60005#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 59232#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 59233#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 60215#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 60216#L623 assume 1 == ~t3_pc~0; 59464#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 58805#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 60074#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 60075#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 60252#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 58843#L642 assume !(1 == ~t4_pc~0); 58844#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 59300#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 58899#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 58900#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 58921#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 60018#L661 assume 1 == ~t5_pc~0; 59079#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 59080#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 59934#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 60324#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 60050#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 60051#L680 assume !(1 == ~t6_pc~0); 59497#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 59498#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 59223#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 59224#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 60336#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 60478#L699 assume 1 == ~t7_pc~0; 59895#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 59896#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 60136#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 59788#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 59789#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 59683#L718 assume !(1 == ~t8_pc~0); 59684#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 59060#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 59061#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 59095#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 59096#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 59229#L737 assume 1 == ~t9_pc~0; 60088#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 59360#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 59269#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 59270#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 59538#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 59539#L756 assume 1 == ~t10_pc~0; 60125#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 59779#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 60038#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 59718#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 59339#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 59340#L775 assume !(1 == ~t11_pc~0); 59599#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 59600#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 60413#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 58992#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 58993#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 59177#L794 assume 1 == ~t12_pc~0; 59015#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 58995#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 58849#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 58850#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 59141#L1551-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 59611#L1307 assume !(1 == ~M_E~0); 59612#L1307-2 assume !(1 == ~T1_E~0); 59722#L1312-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 60499#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 60934#L1322-1 assume !(1 == ~T4_E~0); 60933#L1327-1 assume !(1 == ~T5_E~0); 60932#L1332-1 assume !(1 == ~T6_E~0); 60931#L1337-1 assume !(1 == ~T7_E~0); 60930#L1342-1 assume !(1 == ~T8_E~0); 60454#L1347-1 assume !(1 == ~T9_E~0); 60292#L1352-1 assume !(1 == ~T10_E~0); 60137#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 59516#L1362-1 assume !(1 == ~T12_E~0); 59517#L1367-1 assume !(1 == ~E_1~0); 59156#L1372-1 assume !(1 == ~E_2~0); 59157#L1377-1 assume !(1 == ~E_3~0); 59655#L1382-1 assume !(1 == ~E_4~0); 60869#L1387-1 assume !(1 == ~E_5~0); 60865#L1392-1 assume !(1 == ~E_6~0); 60668#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 60664#L1402-1 assume !(1 == ~E_8~0); 60625#L1407-1 assume !(1 == ~E_9~0); 60621#L1412-1 assume !(1 == ~E_10~0); 60609#L1417-1 assume !(1 == ~E_11~0); 60599#L1422-1 assume !(1 == ~E_12~0); 60590#L1427-1 assume { :end_inline_reset_delta_events } true; 60583#L1768-2 [2024-11-08 17:07:24,181 INFO L747 eck$LassoCheckResult]: Loop: 60583#L1768-2 assume !false; 60577#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 60573#L1149-1 assume !false; 60572#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 60564#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 60558#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 60557#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 60555#L976 assume !(0 != eval_~tmp~0#1); 60554#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 60553#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 60552#L1174-3 assume 0 == ~M_E~0;~M_E~0 := 1; 60551#L1174-5 assume !(0 == ~T1_E~0); 60549#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 60550#L1184-3 assume !(0 == ~T3_E~0); 63064#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 63062#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 63060#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 63058#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 63056#L1209-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 63054#L1214-3 assume !(0 == ~T9_E~0); 63051#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 63049#L1224-3 assume !(0 == ~T11_E~0); 63047#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 63045#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 63043#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 63041#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 63038#L1249-3 assume 0 == ~E_4~0;~E_4~0 := 1; 63036#L1254-3 assume !(0 == ~E_5~0); 63034#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 63032#L1264-3 assume !(0 == ~E_7~0); 63030#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 63028#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 63027#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 63026#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 63025#L1289-3 assume 0 == ~E_12~0;~E_12~0 := 1; 63023#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 63022#L566-39 assume 1 == ~m_pc~0; 63019#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 62913#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 62912#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 62911#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 62910#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 62909#L585-39 assume !(1 == ~t1_pc~0); 62907#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 62906#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 62904#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 62901#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 62899#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 62897#L604-39 assume 1 == ~t2_pc~0; 62894#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 62892#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 62890#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 62889#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 62888#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 62887#L623-39 assume !(1 == ~t3_pc~0); 62884#L623-41 is_transmit3_triggered_~__retres1~3#1 := 0; 62882#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 62880#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 62878#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 62875#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 62873#L642-39 assume 1 == ~t4_pc~0; 62870#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 62868#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 62866#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 62864#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 62863#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 62862#L661-39 assume !(1 == ~t5_pc~0); 62860#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 62858#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 62856#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 62854#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 62852#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 62850#L680-39 assume 1 == ~t6_pc~0; 62794#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 62784#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 62776#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 62771#L1503-39 assume !(0 != activate_threads_~tmp___5~0#1); 62768#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 62765#L699-39 assume 1 == ~t7_pc~0; 62763#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 59500#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 59501#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 60090#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 60357#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 60354#L718-39 assume 1 == ~t8_pc~0; 59687#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 59688#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 60193#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 60194#L1519-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 59933#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 59908#L737-39 assume 1 == ~t9_pc~0; 59909#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 62043#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 62041#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 62039#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 62037#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 62035#L756-39 assume !(1 == ~t10_pc~0); 62032#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 62029#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 62027#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 62025#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 62023#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 62021#L775-39 assume 1 == ~t11_pc~0; 62018#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 62015#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 62013#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 62011#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 62009#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 62007#L794-39 assume !(1 == ~t12_pc~0); 62004#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 62001#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 61999#is_transmit12_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 61997#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 61995#L1551-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 61993#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 61991#L1307-5 assume !(1 == ~T1_E~0); 61988#L1312-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 60539#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 61985#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 61983#L1327-3 assume !(1 == ~T5_E~0); 61970#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 61964#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 61860#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 61093#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 61089#L1352-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 61087#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 61085#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 61082#L1367-3 assume !(1 == ~E_1~0); 61080#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 61078#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 61076#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 61074#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 61070#L1392-3 assume 1 == ~E_6~0;~E_6~0 := 2; 61067#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 61065#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 61063#L1407-3 assume !(1 == ~E_9~0); 61061#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 61059#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 61057#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 61054#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 60723#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 60710#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 60708#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 60707#L1787 assume !(0 == start_simulation_~tmp~3#1); 60705#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 60638#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 60632#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 60628#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 60626#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 60610#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 60600#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 60591#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 60583#L1768-2 [2024-11-08 17:07:24,182 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 17:07:24,182 INFO L85 PathProgramCache]: Analyzing trace with hash 32770907, now seen corresponding path program 1 times [2024-11-08 17:07:24,182 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 17:07:24,182 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1475859578] [2024-11-08 17:07:24,182 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 17:07:24,183 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 17:07:24,199 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:07:24,249 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 17:07:24,249 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 17:07:24,249 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1475859578] [2024-11-08 17:07:24,249 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1475859578] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 17:07:24,249 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 17:07:24,249 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-08 17:07:24,250 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [749356694] [2024-11-08 17:07:24,250 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 17:07:24,250 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 17:07:24,250 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 17:07:24,250 INFO L85 PathProgramCache]: Analyzing trace with hash 341666434, now seen corresponding path program 1 times [2024-11-08 17:07:24,251 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 17:07:24,251 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1481033039] [2024-11-08 17:07:24,251 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 17:07:24,251 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 17:07:24,267 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:07:24,365 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 17:07:24,365 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 17:07:24,366 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1481033039] [2024-11-08 17:07:24,366 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1481033039] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 17:07:24,366 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 17:07:24,366 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 17:07:24,367 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1272753998] [2024-11-08 17:07:24,367 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 17:07:24,367 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 17:07:24,367 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 17:07:24,368 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 17:07:24,368 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 17:07:24,368 INFO L87 Difference]: Start difference. First operand 6182 states and 9067 transitions. cyclomatic complexity: 2889 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 2 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 17:07:24,582 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 17:07:24,582 INFO L93 Difference]: Finished difference Result 12097 states and 17623 transitions. [2024-11-08 17:07:24,582 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 12097 states and 17623 transitions. [2024-11-08 17:07:24,649 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11882 [2024-11-08 17:07:24,694 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 12097 states to 12097 states and 17623 transitions. [2024-11-08 17:07:24,695 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12097 [2024-11-08 17:07:24,706 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12097 [2024-11-08 17:07:24,707 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12097 states and 17623 transitions. [2024-11-08 17:07:24,719 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 17:07:24,719 INFO L218 hiAutomatonCegarLoop]: Abstraction has 12097 states and 17623 transitions. [2024-11-08 17:07:24,732 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12097 states and 17623 transitions. [2024-11-08 17:07:24,869 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12097 to 11729. [2024-11-08 17:07:24,887 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11729 states, 11729 states have (on average 1.4585216130957457) internal successors, (17107), 11728 states have internal predecessors, (17107), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 17:07:24,915 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11729 states to 11729 states and 17107 transitions. [2024-11-08 17:07:24,916 INFO L240 hiAutomatonCegarLoop]: Abstraction has 11729 states and 17107 transitions. [2024-11-08 17:07:24,916 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 17:07:24,917 INFO L425 stractBuchiCegarLoop]: Abstraction has 11729 states and 17107 transitions. [2024-11-08 17:07:24,917 INFO L332 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2024-11-08 17:07:24,917 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11729 states and 17107 transitions. [2024-11-08 17:07:24,954 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11514 [2024-11-08 17:07:24,954 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 17:07:24,954 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 17:07:24,957 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 17:07:24,957 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 17:07:24,957 INFO L745 eck$LassoCheckResult]: Stem: 77327#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 77328#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 78146#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 78147#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 78008#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 78009#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 78103#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 78447#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 78613#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 78614#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 77303#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 77304#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 78524#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 77898#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 77899#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 77807#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 77808#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 78229#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 77541#L1174 assume !(0 == ~M_E~0); 77542#L1174-2 assume !(0 == ~T1_E~0); 77396#L1179-1 assume !(0 == ~T2_E~0); 77301#L1184-1 assume !(0 == ~T3_E~0); 77302#L1189-1 assume !(0 == ~T4_E~0); 77343#L1194-1 assume !(0 == ~T5_E~0); 77438#L1199-1 assume !(0 == ~T6_E~0); 78365#L1204-1 assume !(0 == ~T7_E~0); 78275#L1209-1 assume !(0 == ~T8_E~0); 78276#L1214-1 assume !(0 == ~T9_E~0); 78782#L1219-1 assume !(0 == ~T10_E~0); 78928#L1224-1 assume !(0 == ~T11_E~0); 77664#L1229-1 assume !(0 == ~T12_E~0); 77230#L1234-1 assume !(0 == ~E_1~0); 77231#L1239-1 assume !(0 == ~E_2~0); 77265#L1244-1 assume !(0 == ~E_3~0); 77266#L1249-1 assume !(0 == ~E_4~0); 77919#L1254-1 assume !(0 == ~E_5~0); 77160#L1259-1 assume !(0 == ~E_6~0); 77115#L1264-1 assume !(0 == ~E_7~0); 77116#L1269-1 assume !(0 == ~E_8~0); 78942#L1274-1 assume !(0 == ~E_9~0); 78829#L1279-1 assume !(0 == ~E_10~0); 77347#L1284-1 assume !(0 == ~E_11~0); 77348#L1289-1 assume !(0 == ~E_12~0); 77977#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 77978#L566 assume !(1 == ~m_pc~0); 78438#L566-2 is_master_triggered_~__retres1~0#1 := 0; 78439#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 78022#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 78023#L1455 assume !(0 != activate_threads_~tmp~1#1); 77568#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 77569#L585 assume 1 == ~t1_pc~0; 77227#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 77228#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 78428#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 78429#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 78865#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 78861#L604 assume !(1 == ~t2_pc~0); 78323#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 78324#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 77515#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 77516#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 78571#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 78572#L623 assume 1 == ~t3_pc~0; 77751#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 77091#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 78402#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 78403#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 78606#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 77129#L642 assume !(1 == ~t4_pc~0); 77130#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 77581#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 77188#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 77189#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 77204#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 78338#L661 assume 1 == ~t5_pc~0; 77360#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 77361#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 78246#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 78678#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 78374#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 78375#L680 assume !(1 == ~t6_pc~0); 77784#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 77785#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 77504#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 77505#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 78693#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 78859#L699 assume 1 == ~t7_pc~0; 78207#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 78208#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 78466#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 78085#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 78086#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 77979#L718 assume !(1 == ~t8_pc~0); 77980#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 77341#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 77342#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 77378#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 77379#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 77507#L737 assume 1 == ~t9_pc~0; 78417#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 77646#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 77548#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 77549#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 77826#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 77827#L756 assume 1 == ~t10_pc~0; 78457#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 78077#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 78360#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 78015#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 77622#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 77623#L775 assume !(1 == ~t11_pc~0); 77890#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 77891#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 78775#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 77275#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 77276#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 77457#L794 assume 1 == ~t12_pc~0; 77299#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 77278#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 77135#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 77136#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 77424#L1551-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 77902#L1307 assume !(1 == ~M_E~0); 77903#L1307-2 assume !(1 == ~T1_E~0); 78019#L1312-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 77935#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 77936#L1322-1 assume !(1 == ~T4_E~0); 77634#L1327-1 assume !(1 == ~T5_E~0); 77635#L1332-1 assume !(1 == ~T6_E~0); 78212#L1337-1 assume !(1 == ~T7_E~0); 78161#L1342-1 assume !(1 == ~T8_E~0); 78162#L1347-1 assume !(1 == ~T9_E~0); 78648#L1352-1 assume !(1 == ~T10_E~0); 78467#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 77803#L1362-1 assume !(1 == ~T12_E~0); 77804#L1367-1 assume !(1 == ~E_1~0); 87604#L1372-1 assume !(1 == ~E_2~0); 77949#L1377-1 assume !(1 == ~E_3~0); 77950#L1382-1 assume !(1 == ~E_4~0); 85614#L1387-1 assume !(1 == ~E_5~0); 85256#L1392-1 assume !(1 == ~E_6~0); 85253#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 84897#L1402-1 assume !(1 == ~E_8~0); 84895#L1407-1 assume !(1 == ~E_9~0); 84853#L1412-1 assume !(1 == ~E_10~0); 84841#L1417-1 assume !(1 == ~E_11~0); 84831#L1422-1 assume !(1 == ~E_12~0); 84822#L1427-1 assume { :end_inline_reset_delta_events } true; 84815#L1768-2 [2024-11-08 17:07:24,958 INFO L747 eck$LassoCheckResult]: Loop: 84815#L1768-2 assume !false; 84809#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 84805#L1149-1 assume !false; 84804#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 84796#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 84790#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 84789#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 84787#L976 assume !(0 != eval_~tmp~0#1); 84788#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 87690#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 87689#L1174-3 assume 0 == ~M_E~0;~M_E~0 := 1; 87688#L1174-5 assume !(0 == ~T1_E~0); 87687#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 87686#L1184-3 assume !(0 == ~T3_E~0); 87685#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 87681#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 87678#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 87675#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 87673#L1209-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 87671#L1214-3 assume !(0 == ~T9_E~0); 87669#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 87666#L1224-3 assume !(0 == ~T11_E~0); 87664#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 77856#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 77267#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 77268#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 77712#L1249-3 assume 0 == ~E_4~0;~E_4~0 := 1; 78196#L1254-3 assume !(0 == ~E_5~0); 78778#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 78307#L1264-3 assume !(0 == ~E_7~0); 77273#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 77274#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 78825#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 77837#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 77838#L1289-3 assume 0 == ~E_12~0;~E_12~0 := 1; 77823#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 77489#L566-39 assume !(1 == ~m_pc~0); 77490#L566-41 is_master_triggered_~__retres1~0#1 := 0; 87349#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 87348#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 87347#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 87346#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 87345#L585-39 assume 1 == ~t1_pc~0; 87344#L586-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 87342#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 78901#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 78772#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 78433#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 78091#L604-39 assume !(1 == ~t2_pc~0); 78093#L604-41 is_transmit2_triggered_~__retres1~2#1 := 0; 87338#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 87337#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 78148#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 78149#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 77694#L623-39 assume 1 == ~t3_pc~0; 77092#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 77093#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 78410#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 77543#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 77544#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 78346#L642-39 assume !(1 == ~t4_pc~0); 87328#L642-41 is_transmit4_triggered_~__retres1~4#1 := 0; 78291#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 78292#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 78625#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 78626#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 77463#L661-39 assume 1 == ~t5_pc~0; 77464#L662-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 77101#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 78098#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 78099#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 87320#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 87319#L680-39 assume 1 == ~t6_pc~0; 87317#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 78714#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 78715#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 77620#L1503-39 assume !(0 != activate_threads_~tmp___5~0#1); 77621#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 78903#L699-39 assume 1 == ~t7_pc~0; 78073#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 77787#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 77788#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 78416#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 78710#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 78707#L718-39 assume 1 == ~t8_pc~0; 77984#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 77985#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 78538#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 78539#L1519-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 86303#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 86301#L737-39 assume !(1 == ~t9_pc~0); 86299#L737-41 is_transmit9_triggered_~__retres1~9#1 := 0; 86296#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 86294#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 86292#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 86289#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 86287#L756-39 assume 1 == ~t10_pc~0; 86285#L757-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 86282#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 86280#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 86278#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 86275#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 86273#L775-39 assume 1 == ~t11_pc~0; 86269#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 86267#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 86265#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 86262#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 86260#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 86258#L794-39 assume 1 == ~t12_pc~0; 85983#L795-13 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 85979#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 85977#is_transmit12_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 85975#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 85973#L1551-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 85971#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 85969#L1307-5 assume !(1 == ~T1_E~0); 85967#L1312-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 78941#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 85964#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 85962#L1327-3 assume !(1 == ~T5_E~0); 85960#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 85935#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 85927#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 85916#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 78542#L1352-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 85900#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 85894#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 85887#L1367-3 assume !(1 == ~E_1~0); 85881#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 85873#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 85866#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 85857#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 85848#L1392-3 assume 1 == ~E_6~0;~E_6~0 := 2; 85839#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 85830#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 85823#L1407-3 assume !(1 == ~E_9~0); 85817#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 85803#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 85795#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 85789#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 85357#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 85344#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 85342#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 84947#L1787 assume !(0 == start_simulation_~tmp~3#1); 84944#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 84867#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 84860#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 84858#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 84857#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 84842#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 84832#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 84823#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 84815#L1768-2 [2024-11-08 17:07:24,959 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 17:07:24,959 INFO L85 PathProgramCache]: Analyzing trace with hash -1204882182, now seen corresponding path program 1 times [2024-11-08 17:07:24,959 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 17:07:24,959 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1560075402] [2024-11-08 17:07:24,960 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 17:07:24,960 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 17:07:24,978 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:07:25,041 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 17:07:25,041 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 17:07:25,041 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1560075402] [2024-11-08 17:07:25,041 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1560075402] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 17:07:25,041 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 17:07:25,042 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-08 17:07:25,042 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1709273187] [2024-11-08 17:07:25,042 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 17:07:25,042 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 17:07:25,042 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 17:07:25,043 INFO L85 PathProgramCache]: Analyzing trace with hash -470002845, now seen corresponding path program 1 times [2024-11-08 17:07:25,043 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 17:07:25,043 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1720090709] [2024-11-08 17:07:25,043 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 17:07:25,043 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 17:07:25,063 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:07:25,170 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 17:07:25,171 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 17:07:25,171 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1720090709] [2024-11-08 17:07:25,171 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1720090709] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 17:07:25,171 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 17:07:25,171 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 17:07:25,172 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [672182613] [2024-11-08 17:07:25,172 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 17:07:25,172 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 17:07:25,172 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 17:07:25,173 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 17:07:25,173 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 17:07:25,173 INFO L87 Difference]: Start difference. First operand 11729 states and 17107 transitions. cyclomatic complexity: 5386 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 2 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 17:07:25,377 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 17:07:25,377 INFO L93 Difference]: Finished difference Result 22406 states and 32528 transitions. [2024-11-08 17:07:25,378 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 22406 states and 32528 transitions. [2024-11-08 17:07:25,468 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 22168 [2024-11-08 17:07:25,542 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 22406 states to 22406 states and 32528 transitions. [2024-11-08 17:07:25,542 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22406 [2024-11-08 17:07:25,564 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22406 [2024-11-08 17:07:25,568 INFO L73 IsDeterministic]: Start isDeterministic. Operand 22406 states and 32528 transitions. [2024-11-08 17:07:25,590 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 17:07:25,590 INFO L218 hiAutomatonCegarLoop]: Abstraction has 22406 states and 32528 transitions. [2024-11-08 17:07:25,613 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22406 states and 32528 transitions. [2024-11-08 17:07:26,069 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22406 to 22390. [2024-11-08 17:07:26,099 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 22390 states, 22390 states have (on average 1.4520768200089325) internal successors, (32512), 22389 states have internal predecessors, (32512), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 17:07:26,146 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22390 states to 22390 states and 32512 transitions. [2024-11-08 17:07:26,146 INFO L240 hiAutomatonCegarLoop]: Abstraction has 22390 states and 32512 transitions. [2024-11-08 17:07:26,147 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 17:07:26,147 INFO L425 stractBuchiCegarLoop]: Abstraction has 22390 states and 32512 transitions. [2024-11-08 17:07:26,147 INFO L332 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2024-11-08 17:07:26,147 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 22390 states and 32512 transitions. [2024-11-08 17:07:26,214 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 22152 [2024-11-08 17:07:26,214 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 17:07:26,214 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 17:07:26,217 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 17:07:26,217 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 17:07:26,218 INFO L745 eck$LassoCheckResult]: Stem: 111463#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 111464#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 112315#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 112316#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 112166#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 112167#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 112268#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 112624#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 112795#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 112796#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 111439#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 111440#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 112702#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 112057#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 112058#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 111965#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 111966#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 112397#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 111684#L1174 assume !(0 == ~M_E~0); 111685#L1174-2 assume !(0 == ~T1_E~0); 111537#L1179-1 assume !(0 == ~T2_E~0); 111437#L1184-1 assume !(0 == ~T3_E~0); 111438#L1189-1 assume !(0 == ~T4_E~0); 111480#L1194-1 assume !(0 == ~T5_E~0); 111579#L1199-1 assume !(0 == ~T6_E~0); 112538#L1204-1 assume !(0 == ~T7_E~0); 112445#L1209-1 assume !(0 == ~T8_E~0); 112446#L1214-1 assume !(0 == ~T9_E~0); 112986#L1219-1 assume !(0 == ~T10_E~0); 113161#L1224-1 assume !(0 == ~T11_E~0); 111813#L1229-1 assume !(0 == ~T12_E~0); 111367#L1234-1 assume !(0 == ~E_1~0); 111368#L1239-1 assume !(0 == ~E_2~0); 111402#L1244-1 assume !(0 == ~E_3~0); 111403#L1249-1 assume !(0 == ~E_4~0); 112080#L1254-1 assume !(0 == ~E_5~0); 111300#L1259-1 assume !(0 == ~E_6~0); 111256#L1264-1 assume !(0 == ~E_7~0); 111257#L1269-1 assume !(0 == ~E_8~0); 113175#L1274-1 assume !(0 == ~E_9~0); 113039#L1279-1 assume !(0 == ~E_10~0); 111484#L1284-1 assume !(0 == ~E_11~0); 111485#L1289-1 assume !(0 == ~E_12~0); 112134#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 112135#L566 assume !(1 == ~m_pc~0); 112615#L566-2 is_master_triggered_~__retres1~0#1 := 0; 112616#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 112181#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 112182#L1455 assume !(0 != activate_threads_~tmp~1#1); 111711#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 111712#L585 assume !(1 == ~t1_pc~0); 111907#L585-2 is_transmit1_triggered_~__retres1~1#1 := 0; 111908#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 112606#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 112607#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 113093#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 113084#L604 assume !(1 == ~t2_pc~0); 112495#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 112496#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 111659#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 111660#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 112747#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 112748#L623 assume 1 == ~t3_pc~0; 111906#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 111232#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 112579#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 112580#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 112787#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 111270#L642 assume !(1 == ~t4_pc~0); 111271#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 111724#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 111328#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 111329#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 111344#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 112509#L661 assume 1 == ~t5_pc~0; 111499#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 111500#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 112414#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 112874#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 112547#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 112548#L680 assume !(1 == ~t6_pc~0); 111941#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 111942#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 111648#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 111649#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 112890#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 113081#L699 assume 1 == ~t7_pc~0; 112375#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 112376#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 112645#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 112248#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 112249#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 112136#L718 assume !(1 == ~t8_pc~0); 112137#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 111478#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 111479#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 111519#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 111520#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 111651#L737 assume 1 == ~t9_pc~0; 112597#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 111792#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 111691#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 111692#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 111983#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 111984#L756 assume 1 == ~t10_pc~0; 112634#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 112238#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 112531#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 112174#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 111767#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 111768#L775 assume !(1 == ~t11_pc~0); 112049#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 112050#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 112978#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 111412#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 111413#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 111598#L794 assume 1 == ~t12_pc~0; 111435#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 111415#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 111275#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 111276#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 111565#L1551-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 112063#L1307 assume !(1 == ~M_E~0); 112064#L1307-2 assume !(1 == ~T1_E~0); 112178#L1312-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 112093#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 112094#L1322-1 assume !(1 == ~T4_E~0); 111780#L1327-1 assume !(1 == ~T5_E~0); 111781#L1332-1 assume !(1 == ~T6_E~0); 112380#L1337-1 assume !(1 == ~T7_E~0); 112328#L1342-1 assume !(1 == ~T8_E~0); 112329#L1347-1 assume !(1 == ~T9_E~0); 112831#L1352-1 assume !(1 == ~T10_E~0); 112646#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 111961#L1362-1 assume !(1 == ~T12_E~0); 111962#L1367-1 assume !(1 == ~E_1~0); 111580#L1372-1 assume !(1 == ~E_2~0); 111581#L1377-1 assume !(1 == ~E_3~0); 111891#L1382-1 assume !(1 == ~E_4~0); 111892#L1387-1 assume !(1 == ~E_5~0); 112497#L1392-1 assume !(1 == ~E_6~0); 122960#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 122958#L1402-1 assume !(1 == ~E_8~0); 122956#L1407-1 assume !(1 == ~E_9~0); 122953#L1412-1 assume !(1 == ~E_10~0); 122951#L1417-1 assume !(1 == ~E_11~0); 122923#L1422-1 assume !(1 == ~E_12~0); 122912#L1427-1 assume { :end_inline_reset_delta_events } true; 122903#L1768-2 [2024-11-08 17:07:26,218 INFO L747 eck$LassoCheckResult]: Loop: 122903#L1768-2 assume !false; 122894#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 119038#L1149-1 assume !false; 119033#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 118787#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 118778#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 118776#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 118773#L976 assume !(0 != eval_~tmp~0#1); 118774#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 123866#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 123865#L1174-3 assume 0 == ~M_E~0;~M_E~0 := 1; 123864#L1174-5 assume !(0 == ~T1_E~0); 123863#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 123862#L1184-3 assume !(0 == ~T3_E~0); 123861#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 123860#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 123859#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 123858#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 123857#L1209-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 123855#L1214-3 assume !(0 == ~T9_E~0); 123853#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 123851#L1224-3 assume !(0 == ~T11_E~0); 123849#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 123847#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 123845#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 123843#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 123841#L1249-3 assume 0 == ~E_4~0;~E_4~0 := 1; 123839#L1254-3 assume !(0 == ~E_5~0); 123837#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 123834#L1264-3 assume !(0 == ~E_7~0); 123832#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 123830#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 123828#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 123826#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 123824#L1289-3 assume 0 == ~E_12~0;~E_12~0 := 1; 123821#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 123819#L566-39 assume !(1 == ~m_pc~0); 123817#L566-41 is_master_triggered_~__retres1~0#1 := 0; 123815#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 123813#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 123811#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 123808#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 123806#L585-39 assume !(1 == ~t1_pc~0); 123804#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 123802#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 123800#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 123798#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 123795#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 123793#L604-39 assume !(1 == ~t2_pc~0); 123791#L604-41 is_transmit2_triggered_~__retres1~2#1 := 0; 123788#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 123786#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 123784#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 123781#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 123779#L623-39 assume 1 == ~t3_pc~0; 123744#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 123741#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 123739#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 123737#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 123735#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 123733#L642-39 assume 1 == ~t4_pc~0; 123729#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 123727#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 123725#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 123723#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 123721#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 123719#L661-39 assume !(1 == ~t5_pc~0); 123715#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 123709#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 123706#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 123704#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 123702#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 123700#L680-39 assume 1 == ~t6_pc~0; 123697#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 123696#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 123694#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 123692#L1503-39 assume !(0 != activate_threads_~tmp___5~0#1); 123690#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 123688#L699-39 assume 1 == ~t7_pc~0; 123685#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 123683#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 123681#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 123679#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 123677#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 123675#L718-39 assume !(1 == ~t8_pc~0); 123673#L718-41 is_transmit8_triggered_~__retres1~8#1 := 0; 123670#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 123669#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 123668#L1519-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 123666#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 123663#L737-39 assume 1 == ~t9_pc~0; 123659#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 123656#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 123653#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 123650#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 123647#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 123629#L756-39 assume !(1 == ~t10_pc~0); 123625#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 123622#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 123620#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 123618#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 123616#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 123613#L775-39 assume 1 == ~t11_pc~0; 123609#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 123604#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 123599#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 123595#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 123591#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 123587#L794-39 assume 1 == ~t12_pc~0; 123583#L795-13 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 123577#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 123572#is_transmit12_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 123568#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 123564#L1551-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 123560#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 123556#L1307-5 assume !(1 == ~T1_E~0); 123551#L1312-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 120634#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 123542#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 123538#L1327-3 assume !(1 == ~T5_E~0); 123534#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 123530#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 123525#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 123519#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 122243#L1352-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 123512#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 123507#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 123502#L1367-3 assume !(1 == ~E_1~0); 123496#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 123489#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 123484#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 123479#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 120607#L1392-3 assume 1 == ~E_6~0;~E_6~0 := 2; 123470#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 123464#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 123457#L1407-3 assume !(1 == ~E_9~0); 123452#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 123447#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 123442#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 123437#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 123336#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 123318#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 123311#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 123304#L1787 assume !(0 == start_simulation_~tmp~3#1); 123300#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 122979#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 122972#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 122970#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 122968#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 122966#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 122924#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 122913#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 122903#L1768-2 [2024-11-08 17:07:26,219 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 17:07:26,219 INFO L85 PathProgramCache]: Analyzing trace with hash 1220887001, now seen corresponding path program 1 times [2024-11-08 17:07:26,219 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 17:07:26,219 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [235905175] [2024-11-08 17:07:26,220 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 17:07:26,220 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 17:07:26,237 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:07:26,419 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 17:07:26,419 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 17:07:26,420 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [235905175] [2024-11-08 17:07:26,420 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [235905175] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 17:07:26,420 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 17:07:26,420 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-08 17:07:26,420 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1827760610] [2024-11-08 17:07:26,420 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 17:07:26,421 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 17:07:26,421 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 17:07:26,421 INFO L85 PathProgramCache]: Analyzing trace with hash -2028745375, now seen corresponding path program 1 times [2024-11-08 17:07:26,421 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 17:07:26,422 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1099145552] [2024-11-08 17:07:26,422 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 17:07:26,422 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 17:07:26,444 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:07:26,504 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 17:07:26,504 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 17:07:26,504 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1099145552] [2024-11-08 17:07:26,505 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1099145552] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 17:07:26,505 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 17:07:26,505 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 17:07:26,505 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1593052144] [2024-11-08 17:07:26,505 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 17:07:26,506 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 17:07:26,506 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 17:07:26,506 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-08 17:07:26,507 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-08 17:07:26,507 INFO L87 Difference]: Start difference. First operand 22390 states and 32512 transitions. cyclomatic complexity: 10138 Second operand has 5 states, 5 states have (on average 29.6) internal successors, (148), 5 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 17:07:27,111 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 17:07:27,111 INFO L93 Difference]: Finished difference Result 22993 states and 33115 transitions. [2024-11-08 17:07:27,112 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 22993 states and 33115 transitions. [2024-11-08 17:07:27,196 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 22752 [2024-11-08 17:07:27,263 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 22993 states to 22993 states and 33115 transitions. [2024-11-08 17:07:27,264 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22993 [2024-11-08 17:07:27,275 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22993 [2024-11-08 17:07:27,275 INFO L73 IsDeterministic]: Start isDeterministic. Operand 22993 states and 33115 transitions. [2024-11-08 17:07:27,292 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 17:07:27,293 INFO L218 hiAutomatonCegarLoop]: Abstraction has 22993 states and 33115 transitions. [2024-11-08 17:07:27,312 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22993 states and 33115 transitions. [2024-11-08 17:07:27,652 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22993 to 22993. [2024-11-08 17:07:27,676 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 22993 states, 22993 states have (on average 1.4402209368068544) internal successors, (33115), 22992 states have internal predecessors, (33115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 17:07:27,716 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22993 states to 22993 states and 33115 transitions. [2024-11-08 17:07:27,717 INFO L240 hiAutomatonCegarLoop]: Abstraction has 22993 states and 33115 transitions. [2024-11-08 17:07:27,718 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-08 17:07:27,718 INFO L425 stractBuchiCegarLoop]: Abstraction has 22993 states and 33115 transitions. [2024-11-08 17:07:27,718 INFO L332 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2024-11-08 17:07:27,718 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 22993 states and 33115 transitions. [2024-11-08 17:07:27,789 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 22752 [2024-11-08 17:07:27,789 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 17:07:27,789 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 17:07:27,791 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 17:07:27,792 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 17:07:27,792 INFO L745 eck$LassoCheckResult]: Stem: 156857#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 156858#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 157699#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 157700#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 157556#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 157557#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 157658#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 158004#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 158174#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 158175#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 156833#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 156834#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 158084#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 157443#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 157444#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 157350#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 157351#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 157784#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 157077#L1174 assume !(0 == ~M_E~0); 157078#L1174-2 assume !(0 == ~T1_E~0); 156926#L1179-1 assume !(0 == ~T2_E~0); 156829#L1184-1 assume !(0 == ~T3_E~0); 156830#L1189-1 assume !(0 == ~T4_E~0); 156874#L1194-1 assume !(0 == ~T5_E~0); 156968#L1199-1 assume !(0 == ~T6_E~0); 157925#L1204-1 assume !(0 == ~T7_E~0); 157834#L1209-1 assume !(0 == ~T8_E~0); 157835#L1214-1 assume !(0 == ~T9_E~0); 158377#L1219-1 assume !(0 == ~T10_E~0); 158570#L1224-1 assume !(0 == ~T11_E~0); 157206#L1229-1 assume !(0 == ~T12_E~0); 156760#L1234-1 assume !(0 == ~E_1~0); 156761#L1239-1 assume !(0 == ~E_2~0); 156793#L1244-1 assume !(0 == ~E_3~0); 156794#L1249-1 assume !(0 == ~E_4~0); 157463#L1254-1 assume !(0 == ~E_5~0); 156692#L1259-1 assume !(0 == ~E_6~0); 156648#L1264-1 assume !(0 == ~E_7~0); 156649#L1269-1 assume !(0 == ~E_8~0); 158597#L1274-1 assume !(0 == ~E_9~0); 158437#L1279-1 assume !(0 == ~E_10~0); 156877#L1284-1 assume !(0 == ~E_11~0); 156878#L1289-1 assume !(0 == ~E_12~0); 157523#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 157524#L566 assume !(1 == ~m_pc~0); 157999#L566-2 is_master_triggered_~__retres1~0#1 := 0; 158000#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 157574#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 157575#L1455 assume !(0 != activate_threads_~tmp~1#1); 157104#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 157105#L585 assume !(1 == ~t1_pc~0); 157294#L585-2 is_transmit1_triggered_~__retres1~1#1 := 0; 157295#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 157990#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 157991#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 158495#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 158489#L604 assume !(1 == ~t2_pc~0); 157881#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 157882#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 157047#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 157048#L1471 assume !(0 != activate_threads_~tmp___1~0#1); 158125#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 158126#L623 assume 1 == ~t3_pc~0; 157293#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 156624#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 157963#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 157964#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 158168#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 156662#L642 assume !(1 == ~t4_pc~0); 156663#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 157120#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 156714#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 156715#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 156737#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 157898#L661 assume 1 == ~t5_pc~0; 156892#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 156893#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 157803#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 158253#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 157932#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 157933#L680 assume !(1 == ~t6_pc~0); 157329#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 157330#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 157038#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 157039#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 158267#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 158486#L699 assume 1 == ~t7_pc~0; 157761#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 157762#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 158031#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 157639#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 157640#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 157525#L718 assume !(1 == ~t8_pc~0); 157526#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 156872#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 156873#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 156908#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 156909#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 157044#L737 assume 1 == ~t9_pc~0; 157979#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 157187#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 157084#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 157085#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 157371#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 157372#L756 assume 1 == ~t10_pc~0; 158019#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 157630#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 157919#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 157564#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 157163#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 157164#L775 assume !(1 == ~t11_pc~0); 157435#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 157436#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 158366#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 156805#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 156806#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 156990#L794 assume 1 == ~t12_pc~0; 156827#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 156808#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 156665#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 156666#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 156954#L1551-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 157448#L1307 assume !(1 == ~M_E~0); 157449#L1307-2 assume !(1 == ~T1_E~0); 157568#L1312-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 158519#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 157720#L1322-1 assume !(1 == ~T4_E~0); 157176#L1327-1 assume !(1 == ~T5_E~0); 157177#L1332-1 assume !(1 == ~T6_E~0); 162964#L1337-1 assume !(1 == ~T7_E~0); 162962#L1342-1 assume !(1 == ~T8_E~0); 158435#L1347-1 assume !(1 == ~T9_E~0); 158436#L1352-1 assume !(1 == ~T10_E~0); 163255#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 163253#L1362-1 assume !(1 == ~T12_E~0); 163251#L1367-1 assume !(1 == ~E_1~0); 162951#L1372-1 assume !(1 == ~E_2~0); 157495#L1377-1 assume !(1 == ~E_3~0); 157278#L1382-1 assume !(1 == ~E_4~0); 157279#L1387-1 assume !(1 == ~E_5~0); 162826#L1392-1 assume !(1 == ~E_6~0); 162824#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 162822#L1402-1 assume !(1 == ~E_8~0); 162819#L1407-1 assume !(1 == ~E_9~0); 161646#L1412-1 assume !(1 == ~E_10~0); 161558#L1417-1 assume !(1 == ~E_11~0); 161556#L1422-1 assume !(1 == ~E_12~0); 161490#L1427-1 assume { :end_inline_reset_delta_events } true; 161486#L1768-2 [2024-11-08 17:07:27,792 INFO L747 eck$LassoCheckResult]: Loop: 161486#L1768-2 assume !false; 161434#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 161429#L1149-1 assume !false; 161426#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 161375#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 161347#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 161316#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 161283#L976 assume !(0 != eval_~tmp~0#1); 161284#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 163820#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 163818#L1174-3 assume 0 == ~M_E~0;~M_E~0 := 1; 163816#L1174-5 assume !(0 == ~T1_E~0); 163814#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 163811#L1184-3 assume !(0 == ~T3_E~0); 163809#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 163807#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 163805#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 163803#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 163801#L1209-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 163798#L1214-3 assume !(0 == ~T9_E~0); 163796#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 163794#L1224-3 assume !(0 == ~T11_E~0); 163792#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 163790#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 163788#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 163785#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 163783#L1249-3 assume 0 == ~E_4~0;~E_4~0 := 1; 163781#L1254-3 assume !(0 == ~E_5~0); 163779#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 163777#L1264-3 assume !(0 == ~E_7~0); 163775#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 163772#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 163770#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 163768#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 163767#L1289-3 assume 0 == ~E_12~0;~E_12~0 := 1; 163766#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 163765#L566-39 assume !(1 == ~m_pc~0); 163764#L566-41 is_master_triggered_~__retres1~0#1 := 0; 163763#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 163762#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 163761#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 163760#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 163759#L585-39 assume !(1 == ~t1_pc~0); 163758#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 163757#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 163756#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 163755#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 163753#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 163752#L604-39 assume !(1 == ~t2_pc~0); 163750#L604-41 is_transmit2_triggered_~__retres1~2#1 := 0; 163748#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 163746#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 163745#L1471-39 assume !(0 != activate_threads_~tmp___1~0#1); 163743#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 163742#L623-39 assume !(1 == ~t3_pc~0); 163740#L623-41 is_transmit3_triggered_~__retres1~3#1 := 0; 163739#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 163737#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 163735#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 163733#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 163731#L642-39 assume !(1 == ~t4_pc~0); 163728#L642-41 is_transmit4_triggered_~__retres1~4#1 := 0; 163725#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 163723#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 163721#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 163719#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 163717#L661-39 assume !(1 == ~t5_pc~0); 163714#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 163710#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 163708#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 163706#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 163704#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 163701#L680-39 assume 1 == ~t6_pc~0; 163698#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 163696#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 163693#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 163691#L1503-39 assume !(0 != activate_threads_~tmp___5~0#1); 163689#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 163687#L699-39 assume 1 == ~t7_pc~0; 163684#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 163682#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 163679#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 163677#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 163675#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 163673#L718-39 assume 1 == ~t8_pc~0; 163670#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 163668#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 163665#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 163663#L1519-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 163661#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 163659#L737-39 assume 1 == ~t9_pc~0; 163656#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 163654#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 163651#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 163649#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 163647#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 163645#L756-39 assume !(1 == ~t10_pc~0); 163642#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 163640#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 163637#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 163635#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 163633#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 163631#L775-39 assume 1 == ~t11_pc~0; 163628#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 163626#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 163625#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 163624#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 163623#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 163622#L794-39 assume !(1 == ~t12_pc~0); 163620#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 163619#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 163618#is_transmit12_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 163617#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 163616#L1551-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 163615#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 163614#L1307-5 assume !(1 == ~T1_E~0); 163612#L1312-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 163417#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 163610#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 163609#L1327-3 assume !(1 == ~T5_E~0); 163608#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 163606#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 163605#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 163402#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 163398#L1352-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 163396#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 163394#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 163392#L1367-3 assume !(1 == ~E_1~0); 163390#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 163388#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 163386#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 163384#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 163185#L1392-3 assume 1 == ~E_6~0;~E_6~0 := 2; 163181#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 163179#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 163177#L1407-3 assume !(1 == ~E_9~0); 163175#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 163172#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 163170#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 163115#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 162930#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 162918#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 162917#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 162914#L1787 assume !(0 == start_simulation_~tmp~3#1); 162836#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 161660#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 161654#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 161563#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 161561#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 161559#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 161557#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 161491#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 161486#L1768-2 [2024-11-08 17:07:27,793 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 17:07:27,793 INFO L85 PathProgramCache]: Analyzing trace with hash 226193303, now seen corresponding path program 1 times [2024-11-08 17:07:27,793 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 17:07:27,793 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1246796490] [2024-11-08 17:07:27,793 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 17:07:27,793 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 17:07:27,811 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:07:27,868 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 17:07:27,869 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 17:07:27,869 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1246796490] [2024-11-08 17:07:27,869 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1246796490] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 17:07:27,869 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 17:07:27,869 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-08 17:07:27,869 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [683204954] [2024-11-08 17:07:27,869 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 17:07:27,870 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 17:07:27,871 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 17:07:27,871 INFO L85 PathProgramCache]: Analyzing trace with hash 1850042397, now seen corresponding path program 1 times [2024-11-08 17:07:27,871 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 17:07:27,871 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1557320571] [2024-11-08 17:07:27,872 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 17:07:27,872 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 17:07:27,993 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:07:28,057 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 17:07:28,057 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 17:07:28,057 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1557320571] [2024-11-08 17:07:28,057 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1557320571] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 17:07:28,057 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 17:07:28,058 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 17:07:28,058 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1767804403] [2024-11-08 17:07:28,058 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 17:07:28,059 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 17:07:28,059 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 17:07:28,060 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 17:07:28,060 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 17:07:28,060 INFO L87 Difference]: Start difference. First operand 22993 states and 33115 transitions. cyclomatic complexity: 10138 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 2 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 17:07:28,332 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 17:07:28,333 INFO L93 Difference]: Finished difference Result 44040 states and 63164 transitions. [2024-11-08 17:07:28,333 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 44040 states and 63164 transitions. [2024-11-08 17:07:28,680 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 43752 [2024-11-08 17:07:28,840 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 44040 states to 44040 states and 63164 transitions. [2024-11-08 17:07:28,840 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 44040 [2024-11-08 17:07:28,869 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 44040 [2024-11-08 17:07:28,869 INFO L73 IsDeterministic]: Start isDeterministic. Operand 44040 states and 63164 transitions. [2024-11-08 17:07:29,003 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 17:07:29,004 INFO L218 hiAutomatonCegarLoop]: Abstraction has 44040 states and 63164 transitions. [2024-11-08 17:07:29,052 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 44040 states and 63164 transitions. [2024-11-08 17:07:29,577 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 44040 to 44008. [2024-11-08 17:07:29,616 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 44008 states, 44008 states have (on average 1.4345573532085076) internal successors, (63132), 44007 states have internal predecessors, (63132), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 17:07:29,692 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44008 states to 44008 states and 63132 transitions. [2024-11-08 17:07:29,692 INFO L240 hiAutomatonCegarLoop]: Abstraction has 44008 states and 63132 transitions. [2024-11-08 17:07:29,693 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 17:07:29,693 INFO L425 stractBuchiCegarLoop]: Abstraction has 44008 states and 63132 transitions. [2024-11-08 17:07:29,693 INFO L332 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2024-11-08 17:07:29,694 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 44008 states and 63132 transitions. [2024-11-08 17:07:29,944 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 43720 [2024-11-08 17:07:29,944 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 17:07:29,944 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 17:07:29,946 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 17:07:29,947 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 17:07:29,947 INFO L745 eck$LassoCheckResult]: Stem: 223899#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 223900#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 224732#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 224733#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 224591#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 224592#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 224690#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 225032#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 225207#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 225208#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 223875#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 223876#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 225118#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 224480#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 224481#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 224390#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 224391#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 224813#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 224121#L1174 assume !(0 == ~M_E~0); 224122#L1174-2 assume !(0 == ~T1_E~0); 223970#L1179-1 assume !(0 == ~T2_E~0); 223873#L1184-1 assume !(0 == ~T3_E~0); 223874#L1189-1 assume !(0 == ~T4_E~0); 223916#L1194-1 assume !(0 == ~T5_E~0); 224014#L1199-1 assume !(0 == ~T6_E~0); 224950#L1204-1 assume !(0 == ~T7_E~0); 224863#L1209-1 assume !(0 == ~T8_E~0); 224864#L1214-1 assume !(0 == ~T9_E~0); 225383#L1219-1 assume !(0 == ~T10_E~0); 225552#L1224-1 assume !(0 == ~T11_E~0); 224249#L1229-1 assume !(0 == ~T12_E~0); 223801#L1234-1 assume !(0 == ~E_1~0); 223802#L1239-1 assume !(0 == ~E_2~0); 223836#L1244-1 assume !(0 == ~E_3~0); 223837#L1249-1 assume !(0 == ~E_4~0); 224503#L1254-1 assume !(0 == ~E_5~0); 223734#L1259-1 assume !(0 == ~E_6~0); 223689#L1264-1 assume !(0 == ~E_7~0); 223690#L1269-1 assume !(0 == ~E_8~0); 225569#L1274-1 assume !(0 == ~E_9~0); 225430#L1279-1 assume !(0 == ~E_10~0); 223919#L1284-1 assume !(0 == ~E_11~0); 223920#L1289-1 assume !(0 == ~E_12~0); 224559#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 224560#L566 assume !(1 == ~m_pc~0); 225023#L566-2 is_master_triggered_~__retres1~0#1 := 0; 225024#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 224607#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 224608#L1455 assume !(0 != activate_threads_~tmp~1#1); 224148#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 224149#L585 assume !(1 == ~t1_pc~0); 224333#L585-2 is_transmit1_triggered_~__retres1~1#1 := 0; 224334#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 225014#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 225015#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 225485#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 225479#L604 assume !(1 == ~t2_pc~0); 224909#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 224910#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 224094#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 224095#L1471 assume !(0 != activate_threads_~tmp___1~0#1); 225159#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 225160#L623 assume !(1 == ~t3_pc~0); 223663#L623-2 is_transmit3_triggered_~__retres1~3#1 := 0; 223664#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 224989#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 224990#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 225198#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 223703#L642 assume !(1 == ~t4_pc~0); 223704#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 224163#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 223762#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 223763#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 223778#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 224924#L661 assume 1 == ~t5_pc~0; 223934#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 223935#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 224830#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 225275#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 224959#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 224960#L680 assume !(1 == ~t6_pc~0); 224367#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 224368#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 224083#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 224084#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 225285#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 225477#L699 assume 1 == ~t7_pc~0; 224791#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 224792#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 225057#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 224671#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 224672#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 224561#L718 assume !(1 == ~t8_pc~0); 224562#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 223914#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 223915#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 223952#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 223953#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 224086#L737 assume 1 == ~t9_pc~0; 225005#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 224231#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 224128#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 224129#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 224408#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 224409#L756 assume 1 == ~t10_pc~0; 225045#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 224662#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 224945#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 224598#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 224205#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 224206#L775 assume !(1 == ~t11_pc~0); 224472#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 224473#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 225375#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 223846#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 223847#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 224033#L794 assume 1 == ~t12_pc~0; 223869#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 223849#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 223709#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 223710#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 223999#L1551-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 224486#L1307 assume !(1 == ~M_E~0); 224487#L1307-2 assume !(1 == ~T1_E~0); 224603#L1312-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 224517#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 224518#L1322-1 assume !(1 == ~T4_E~0); 224218#L1327-1 assume !(1 == ~T5_E~0); 224219#L1332-1 assume !(1 == ~T6_E~0); 224796#L1337-1 assume !(1 == ~T7_E~0); 224746#L1342-1 assume !(1 == ~T8_E~0); 224747#L1347-1 assume !(1 == ~T9_E~0); 225425#L1352-1 assume !(1 == ~T10_E~0); 239123#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 239121#L1362-1 assume !(1 == ~T12_E~0); 239119#L1367-1 assume !(1 == ~E_1~0); 239117#L1372-1 assume !(1 == ~E_2~0); 239115#L1377-1 assume !(1 == ~E_3~0); 239113#L1382-1 assume !(1 == ~E_4~0); 239111#L1387-1 assume !(1 == ~E_5~0); 224911#L1392-1 assume !(1 == ~E_6~0); 239096#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 239094#L1402-1 assume !(1 == ~E_8~0); 239092#L1407-1 assume !(1 == ~E_9~0); 239090#L1412-1 assume !(1 == ~E_10~0); 239088#L1417-1 assume !(1 == ~E_11~0); 239084#L1422-1 assume !(1 == ~E_12~0); 239071#L1427-1 assume { :end_inline_reset_delta_events } true; 239060#L1768-2 [2024-11-08 17:07:29,948 INFO L747 eck$LassoCheckResult]: Loop: 239060#L1768-2 assume !false; 239049#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 239043#L1149-1 assume !false; 239040#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 230736#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 230728#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 230726#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 230723#L976 assume !(0 != eval_~tmp~0#1); 230724#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 239587#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 239585#L1174-3 assume 0 == ~M_E~0;~M_E~0 := 1; 239583#L1174-5 assume !(0 == ~T1_E~0); 239581#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 239579#L1184-3 assume !(0 == ~T3_E~0); 239577#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 239574#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 239572#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 239570#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 239568#L1209-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 239566#L1214-3 assume !(0 == ~T9_E~0); 239564#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 239561#L1224-3 assume !(0 == ~T11_E~0); 239559#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 239557#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 239555#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 239553#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 239551#L1249-3 assume 0 == ~E_4~0;~E_4~0 := 1; 239548#L1254-3 assume !(0 == ~E_5~0); 239546#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 239544#L1264-3 assume !(0 == ~E_7~0); 239542#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 239540#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 239538#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 239535#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 239533#L1289-3 assume 0 == ~E_12~0;~E_12~0 := 1; 239531#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 239529#L566-39 assume !(1 == ~m_pc~0); 239527#L566-41 is_master_triggered_~__retres1~0#1 := 0; 239525#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 239522#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 239520#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 239518#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 239516#L585-39 assume !(1 == ~t1_pc~0); 239514#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 239512#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 239509#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 239507#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 239505#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 239503#L604-39 assume !(1 == ~t2_pc~0); 239499#L604-41 is_transmit2_triggered_~__retres1~2#1 := 0; 239497#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 239494#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 239492#L1471-39 assume !(0 != activate_threads_~tmp___1~0#1); 239489#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 239487#L623-39 assume !(1 == ~t3_pc~0); 239485#L623-41 is_transmit3_triggered_~__retres1~3#1 := 0; 239483#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 239480#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 239478#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 239476#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 239474#L642-39 assume !(1 == ~t4_pc~0); 239472#L642-41 is_transmit4_triggered_~__retres1~4#1 := 0; 239469#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 239466#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 239464#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 239462#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 239460#L661-39 assume 1 == ~t5_pc~0; 239458#L662-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 239455#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 239453#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 239452#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 239451#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 239450#L680-39 assume !(1 == ~t6_pc~0); 239449#L680-41 is_transmit6_triggered_~__retres1~6#1 := 0; 239447#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 239446#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 239445#L1503-39 assume !(0 != activate_threads_~tmp___5~0#1); 239443#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 239442#L699-39 assume !(1 == ~t7_pc~0); 239441#L699-41 is_transmit7_triggered_~__retres1~7#1 := 0; 239439#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 239438#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 239437#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 239436#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 239434#L718-39 assume 1 == ~t8_pc~0; 239431#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 239429#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 239427#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 239425#L1519-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 239423#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 239421#L737-39 assume !(1 == ~t9_pc~0); 239419#L737-41 is_transmit9_triggered_~__retres1~9#1 := 0; 239416#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 239414#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 239412#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 239410#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 239409#L756-39 assume 1 == ~t10_pc~0; 239405#L757-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 239402#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 239400#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 239398#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 239395#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 239393#L775-39 assume !(1 == ~t11_pc~0); 239391#L775-41 is_transmit11_triggered_~__retres1~11#1 := 0; 239388#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 239386#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 239384#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 239382#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 239380#L794-39 assume 1 == ~t12_pc~0; 239378#L795-13 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 239374#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 239372#is_transmit12_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 239370#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 239368#L1551-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 239366#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 239364#L1307-5 assume !(1 == ~T1_E~0); 239361#L1312-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 232171#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 239356#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 239354#L1327-3 assume !(1 == ~T5_E~0); 239352#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 239350#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 239347#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 239345#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 237363#L1352-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 239342#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 239340#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 239338#L1367-3 assume !(1 == ~E_1~0); 239335#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 239333#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 239331#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 239329#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 239325#L1392-3 assume 1 == ~E_6~0;~E_6~0 := 2; 239323#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 239320#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 239318#L1407-3 assume !(1 == ~E_9~0); 239316#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 239314#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 239312#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 239310#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 239304#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 239291#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 239289#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 239286#L1787 assume !(0 == start_simulation_~tmp~3#1); 239284#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 239103#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 239097#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 239095#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 239093#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 239091#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 239089#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 239072#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 239060#L1768-2 [2024-11-08 17:07:29,948 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 17:07:29,948 INFO L85 PathProgramCache]: Analyzing trace with hash 1148113654, now seen corresponding path program 1 times [2024-11-08 17:07:29,949 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 17:07:29,949 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [96326451] [2024-11-08 17:07:29,949 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 17:07:29,949 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 17:07:29,969 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:07:30,049 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 17:07:30,050 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 17:07:30,050 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [96326451] [2024-11-08 17:07:30,050 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [96326451] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 17:07:30,050 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 17:07:30,051 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-08 17:07:30,051 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1554370502] [2024-11-08 17:07:30,051 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 17:07:30,051 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 17:07:30,052 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 17:07:30,052 INFO L85 PathProgramCache]: Analyzing trace with hash 673943228, now seen corresponding path program 1 times [2024-11-08 17:07:30,052 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 17:07:30,052 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [198425143] [2024-11-08 17:07:30,052 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 17:07:30,053 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 17:07:30,068 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:07:30,110 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 17:07:30,111 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 17:07:30,111 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [198425143] [2024-11-08 17:07:30,111 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [198425143] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 17:07:30,111 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 17:07:30,111 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 17:07:30,112 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [642450285] [2024-11-08 17:07:30,112 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 17:07:30,112 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 17:07:30,112 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 17:07:30,113 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 17:07:30,113 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 17:07:30,113 INFO L87 Difference]: Start difference. First operand 44008 states and 63132 transitions. cyclomatic complexity: 19156 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 2 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 17:07:30,760 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 17:07:30,760 INFO L93 Difference]: Finished difference Result 84399 states and 120633 transitions. [2024-11-08 17:07:30,760 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 84399 states and 120633 transitions. [2024-11-08 17:07:31,308 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 83968 [2024-11-08 17:07:31,524 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 84399 states to 84399 states and 120633 transitions. [2024-11-08 17:07:31,524 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 84399 [2024-11-08 17:07:31,574 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 84399 [2024-11-08 17:07:31,574 INFO L73 IsDeterministic]: Start isDeterministic. Operand 84399 states and 120633 transitions. [2024-11-08 17:07:31,644 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 17:07:31,645 INFO L218 hiAutomatonCegarLoop]: Abstraction has 84399 states and 120633 transitions. [2024-11-08 17:07:31,706 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 84399 states and 120633 transitions. [2024-11-08 17:07:32,845 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 84399 to 84335. [2024-11-08 17:07:32,941 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 84335 states, 84335 states have (on average 1.4296436829311674) internal successors, (120569), 84334 states have internal predecessors, (120569), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 17:07:33,216 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 84335 states to 84335 states and 120569 transitions. [2024-11-08 17:07:33,217 INFO L240 hiAutomatonCegarLoop]: Abstraction has 84335 states and 120569 transitions. [2024-11-08 17:07:33,218 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 17:07:33,219 INFO L425 stractBuchiCegarLoop]: Abstraction has 84335 states and 120569 transitions. [2024-11-08 17:07:33,220 INFO L332 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2024-11-08 17:07:33,220 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 84335 states and 120569 transitions. [2024-11-08 17:07:33,471 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 83904 [2024-11-08 17:07:33,471 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 17:07:33,472 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 17:07:33,474 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 17:07:33,475 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 17:07:33,475 INFO L745 eck$LassoCheckResult]: Stem: 352310#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 352311#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 353139#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 353140#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 353000#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 353001#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 353099#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 353441#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 353610#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 353611#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 352286#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 352287#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 353521#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 352893#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 352894#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 352796#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 352797#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 353218#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 352527#L1174 assume !(0 == ~M_E~0); 352528#L1174-2 assume !(0 == ~T1_E~0); 352375#L1179-1 assume !(0 == ~T2_E~0); 352282#L1184-1 assume !(0 == ~T3_E~0); 352283#L1189-1 assume !(0 == ~T4_E~0); 352328#L1194-1 assume !(0 == ~T5_E~0); 352418#L1199-1 assume !(0 == ~T6_E~0); 353361#L1204-1 assume !(0 == ~T7_E~0); 353268#L1209-1 assume !(0 == ~T8_E~0); 353269#L1214-1 assume !(0 == ~T9_E~0); 353802#L1219-1 assume !(0 == ~T10_E~0); 353964#L1224-1 assume !(0 == ~T11_E~0); 352649#L1229-1 assume !(0 == ~T12_E~0); 352213#L1234-1 assume !(0 == ~E_1~0); 352214#L1239-1 assume !(0 == ~E_2~0); 352246#L1244-1 assume !(0 == ~E_3~0); 352247#L1249-1 assume !(0 == ~E_4~0); 352915#L1254-1 assume !(0 == ~E_5~0); 352146#L1259-1 assume !(0 == ~E_6~0); 352102#L1264-1 assume !(0 == ~E_7~0); 352103#L1269-1 assume !(0 == ~E_8~0); 353984#L1274-1 assume !(0 == ~E_9~0); 353848#L1279-1 assume !(0 == ~E_10~0); 352331#L1284-1 assume !(0 == ~E_11~0); 352332#L1289-1 assume !(0 == ~E_12~0); 352970#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 352971#L566 assume !(1 == ~m_pc~0); 353436#L566-2 is_master_triggered_~__retres1~0#1 := 0; 353437#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 353015#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 353016#L1455 assume !(0 != activate_threads_~tmp~1#1); 352554#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 352555#L585 assume !(1 == ~t1_pc~0); 352740#L585-2 is_transmit1_triggered_~__retres1~1#1 := 0; 352741#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 353427#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 353428#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 353910#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 353905#L604 assume !(1 == ~t2_pc~0); 353318#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 353319#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 352496#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 352497#L1471 assume !(0 != activate_threads_~tmp___1~0#1); 353562#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 353563#L623 assume !(1 == ~t3_pc~0); 352077#L623-2 is_transmit3_triggered_~__retres1~3#1 := 0; 352078#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 353397#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 353398#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 353603#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 352116#L642 assume !(1 == ~t4_pc~0); 352117#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 352567#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 352168#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 352169#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 352190#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 353333#L661 assume !(1 == ~t5_pc~0); 353528#L661-2 is_transmit5_triggered_~__retres1~5#1 := 0; 353235#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 353236#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 353691#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 353369#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 353370#L680 assume !(1 == ~t6_pc~0); 352776#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 352777#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 352487#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 352488#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 353704#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 353902#L699 assume 1 == ~t7_pc~0; 353197#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 353198#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 353466#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 353081#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 353082#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 352972#L718 assume !(1 == ~t8_pc~0); 352973#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 352326#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 352327#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 352357#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 352358#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 352493#L737 assume 1 == ~t9_pc~0; 353412#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 352631#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 352534#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 352535#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 352819#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 352820#L756 assume 1 == ~t10_pc~0; 353456#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 353072#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 353355#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 353007#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 352609#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 352610#L775 assume !(1 == ~t11_pc~0); 352885#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 352886#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 353794#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 352258#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 352259#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 352439#L794 assume 1 == ~t12_pc~0; 352280#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 352261#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 352119#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 352120#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 352403#L1551-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 352897#L1307 assume !(1 == ~M_E~0); 352898#L1307-2 assume !(1 == ~T1_E~0); 353012#L1312-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 352927#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 352928#L1322-1 assume !(1 == ~T4_E~0); 352621#L1327-1 assume !(1 == ~T5_E~0); 352622#L1332-1 assume !(1 == ~T6_E~0); 353202#L1337-1 assume !(1 == ~T7_E~0); 353153#L1342-1 assume !(1 == ~T8_E~0); 353154#L1347-1 assume !(1 == ~T9_E~0); 353655#L1352-1 assume !(1 == ~T10_E~0); 353467#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 352794#L1362-1 assume !(1 == ~T12_E~0); 352795#L1367-1 assume !(1 == ~E_1~0); 352419#L1372-1 assume !(1 == ~E_2~0); 352420#L1377-1 assume !(1 == ~E_3~0); 352941#L1382-1 assume !(1 == ~E_4~0); 353320#L1387-1 assume !(1 == ~E_5~0); 353321#L1392-1 assume !(1 == ~E_6~0); 374318#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 374316#L1402-1 assume !(1 == ~E_8~0); 374021#L1407-1 assume !(1 == ~E_9~0); 374015#L1412-1 assume !(1 == ~E_10~0); 373007#L1417-1 assume !(1 == ~E_11~0); 373005#L1422-1 assume !(1 == ~E_12~0); 372720#L1427-1 assume { :end_inline_reset_delta_events } true; 372716#L1768-2 [2024-11-08 17:07:33,476 INFO L747 eck$LassoCheckResult]: Loop: 372716#L1768-2 assume !false; 372715#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 372711#L1149-1 assume !false; 372710#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 372683#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 372672#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 372666#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 372659#L976 assume !(0 != eval_~tmp~0#1); 372660#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 375802#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 375801#L1174-3 assume 0 == ~M_E~0;~M_E~0 := 1; 375800#L1174-5 assume !(0 == ~T1_E~0); 375799#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 375798#L1184-3 assume !(0 == ~T3_E~0); 375797#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 375795#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 375794#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 375793#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 375792#L1209-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 375791#L1214-3 assume !(0 == ~T9_E~0); 375789#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 375788#L1224-3 assume !(0 == ~T11_E~0); 375787#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 375786#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 375784#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 375782#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 375780#L1249-3 assume 0 == ~E_4~0;~E_4~0 := 1; 375778#L1254-3 assume !(0 == ~E_5~0); 375776#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 375774#L1264-3 assume !(0 == ~E_7~0); 375772#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 375770#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 375768#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 375766#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 375764#L1289-3 assume 0 == ~E_12~0;~E_12~0 := 1; 375762#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 375758#L566-39 assume !(1 == ~m_pc~0); 375756#L566-41 is_master_triggered_~__retres1~0#1 := 0; 375754#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 375752#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 375749#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 375747#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 375745#L585-39 assume !(1 == ~t1_pc~0); 375743#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 375741#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 375739#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 375737#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 375735#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 375733#L604-39 assume !(1 == ~t2_pc~0); 375728#L604-41 is_transmit2_triggered_~__retres1~2#1 := 0; 375726#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 375724#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 375722#L1471-39 assume !(0 != activate_threads_~tmp___1~0#1); 375719#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 375717#L623-39 assume !(1 == ~t3_pc~0); 375715#L623-41 is_transmit3_triggered_~__retres1~3#1 := 0; 375713#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 375711#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 375709#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 375707#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 375705#L642-39 assume 1 == ~t4_pc~0; 375701#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 375699#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 375697#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 375695#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 375693#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 375691#L661-39 assume !(1 == ~t5_pc~0); 375688#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 375686#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 375684#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 375682#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 375680#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 375678#L680-39 assume !(1 == ~t6_pc~0); 375675#L680-41 is_transmit6_triggered_~__retres1~6#1 := 0; 373645#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 373642#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 373640#L1503-39 assume !(0 != activate_threads_~tmp___5~0#1); 373638#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 373636#L699-39 assume 1 == ~t7_pc~0; 373633#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 373631#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 373628#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 373626#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 373624#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 373622#L718-39 assume !(1 == ~t8_pc~0); 373620#L718-41 is_transmit8_triggered_~__retres1~8#1 := 0; 373617#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 373614#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 373612#L1519-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 373610#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 373608#L737-39 assume 1 == ~t9_pc~0; 373605#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 373603#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 373600#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 373598#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 373596#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 373594#L756-39 assume !(1 == ~t10_pc~0); 373591#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 373589#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 373587#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 373586#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 373585#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 373584#L775-39 assume 1 == ~t11_pc~0; 373581#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 373579#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 373577#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 373575#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 373573#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 373571#L794-39 assume 1 == ~t12_pc~0; 373569#L795-13 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 373566#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 373564#is_transmit12_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 373562#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 373560#L1551-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 373558#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 373554#L1307-5 assume !(1 == ~T1_E~0); 373552#L1312-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 372952#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 373547#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 373544#L1327-3 assume !(1 == ~T5_E~0); 373542#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 373540#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 373538#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 373536#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 373532#L1352-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 373530#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 373528#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 373526#L1367-3 assume !(1 == ~E_1~0); 373523#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 373521#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 373391#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 372920#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 372914#L1392-3 assume 1 == ~E_6~0;~E_6~0 := 2; 372912#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 372910#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 372908#L1407-3 assume !(1 == ~E_9~0); 372905#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 372903#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 372901#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 372899#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 372894#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 372881#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 372879#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 372875#L1787 assume !(0 == start_simulation_~tmp~3#1); 372872#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 372739#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 372732#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 372730#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 372729#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 372726#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 372725#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 372721#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 372716#L1768-2 [2024-11-08 17:07:33,477 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 17:07:33,477 INFO L85 PathProgramCache]: Analyzing trace with hash -1479734059, now seen corresponding path program 1 times [2024-11-08 17:07:33,477 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 17:07:33,477 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [275929527] [2024-11-08 17:07:33,478 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 17:07:33,478 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 17:07:33,500 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:07:33,594 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 17:07:33,594 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 17:07:33,594 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [275929527] [2024-11-08 17:07:33,594 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [275929527] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 17:07:33,595 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 17:07:33,595 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 17:07:33,595 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [129328441] [2024-11-08 17:07:33,595 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 17:07:33,596 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 17:07:33,596 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 17:07:33,596 INFO L85 PathProgramCache]: Analyzing trace with hash -983518819, now seen corresponding path program 1 times [2024-11-08 17:07:33,597 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 17:07:33,597 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [768079198] [2024-11-08 17:07:33,597 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 17:07:33,597 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 17:07:33,617 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:07:33,673 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 17:07:33,673 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 17:07:33,673 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [768079198] [2024-11-08 17:07:33,673 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [768079198] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 17:07:33,674 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 17:07:33,674 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 17:07:33,674 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [433509570] [2024-11-08 17:07:33,674 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 17:07:33,674 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 17:07:33,675 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 17:07:33,675 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-08 17:07:33,675 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-08 17:07:33,676 INFO L87 Difference]: Start difference. First operand 84335 states and 120569 transitions. cyclomatic complexity: 36298 Second operand has 4 states, 4 states have (on average 37.0) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 17:07:35,275 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 17:07:35,275 INFO L93 Difference]: Finished difference Result 201366 states and 286422 transitions. [2024-11-08 17:07:35,275 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 201366 states and 286422 transitions. [2024-11-08 17:07:36,370 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 200392 [2024-11-08 17:07:36,705 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 201366 states to 201366 states and 286422 transitions. [2024-11-08 17:07:36,705 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 201366 [2024-11-08 17:07:36,792 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 201366 [2024-11-08 17:07:36,792 INFO L73 IsDeterministic]: Start isDeterministic. Operand 201366 states and 286422 transitions. [2024-11-08 17:07:36,950 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 17:07:36,950 INFO L218 hiAutomatonCegarLoop]: Abstraction has 201366 states and 286422 transitions. [2024-11-08 17:07:37,058 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 201366 states and 286422 transitions. [2024-11-08 17:07:38,999 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 201366 to 161582. [2024-11-08 17:07:39,106 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 161582 states, 161582 states have (on average 1.4251463653129681) internal successors, (230278), 161581 states have internal predecessors, (230278), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 17:07:39,449 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 161582 states to 161582 states and 230278 transitions. [2024-11-08 17:07:39,449 INFO L240 hiAutomatonCegarLoop]: Abstraction has 161582 states and 230278 transitions. [2024-11-08 17:07:39,449 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-08 17:07:39,450 INFO L425 stractBuchiCegarLoop]: Abstraction has 161582 states and 230278 transitions. [2024-11-08 17:07:39,450 INFO L332 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2024-11-08 17:07:39,450 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 161582 states and 230278 transitions. [2024-11-08 17:07:40,496 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 160928 [2024-11-08 17:07:40,496 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 17:07:40,496 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 17:07:40,504 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 17:07:40,508 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 17:07:40,509 INFO L745 eck$LassoCheckResult]: Stem: 638020#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 638021#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 638844#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 638845#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 638698#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 638699#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 638804#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 639146#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 639301#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 639302#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 637996#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 637997#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 639221#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 638595#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 638596#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 638505#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 638506#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 638932#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 638234#L1174 assume !(0 == ~M_E~0); 638235#L1174-2 assume !(0 == ~T1_E~0); 638086#L1179-1 assume !(0 == ~T2_E~0); 637994#L1184-1 assume !(0 == ~T3_E~0); 637995#L1189-1 assume !(0 == ~T4_E~0); 638036#L1194-1 assume !(0 == ~T5_E~0); 638129#L1199-1 assume !(0 == ~T6_E~0); 639065#L1204-1 assume !(0 == ~T7_E~0); 638982#L1209-1 assume !(0 == ~T8_E~0); 638983#L1214-1 assume !(0 == ~T9_E~0); 639466#L1219-1 assume !(0 == ~T10_E~0); 639610#L1224-1 assume !(0 == ~T11_E~0); 638355#L1229-1 assume !(0 == ~T12_E~0); 637922#L1234-1 assume !(0 == ~E_1~0); 637923#L1239-1 assume !(0 == ~E_2~0); 637957#L1244-1 assume !(0 == ~E_3~0); 637958#L1249-1 assume !(0 == ~E_4~0); 638615#L1254-1 assume !(0 == ~E_5~0); 637855#L1259-1 assume !(0 == ~E_6~0); 637812#L1264-1 assume !(0 == ~E_7~0); 637813#L1269-1 assume !(0 == ~E_8~0); 639626#L1274-1 assume !(0 == ~E_9~0); 639504#L1279-1 assume !(0 == ~E_10~0); 638040#L1284-1 assume !(0 == ~E_11~0); 638041#L1289-1 assume !(0 == ~E_12~0); 638669#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 638670#L566 assume !(1 == ~m_pc~0); 639137#L566-2 is_master_triggered_~__retres1~0#1 := 0; 639138#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 638716#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 638717#L1455 assume !(0 != activate_threads_~tmp~1#1); 638261#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 638262#L585 assume !(1 == ~t1_pc~0); 638442#L585-2 is_transmit1_triggered_~__retres1~1#1 := 0; 638443#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 639126#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 639127#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 639548#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 639543#L604 assume !(1 == ~t2_pc~0); 639026#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 639027#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 638209#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 638210#L1471 assume !(0 != activate_threads_~tmp___1~0#1); 639258#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 639259#L623 assume !(1 == ~t3_pc~0); 637787#L623-2 is_transmit3_triggered_~__retres1~3#1 := 0; 637788#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 639101#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 639102#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 639295#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 637826#L642 assume !(1 == ~t4_pc~0); 637827#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 638272#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 637883#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 637884#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 637899#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 639041#L661 assume !(1 == ~t5_pc~0); 639226#L661-2 is_transmit5_triggered_~__retres1~5#1 := 0; 638949#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 638950#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 639365#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 639074#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 639075#L680 assume !(1 == ~t6_pc~0); 638481#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 638482#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 638198#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 638199#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 639377#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 639539#L699 assume !(1 == ~t7_pc~0); 639540#L699-2 is_transmit7_triggered_~__retres1~7#1 := 0; 639165#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 639166#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 638784#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 638785#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 638671#L718 assume !(1 == ~t8_pc~0); 638672#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 638034#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 638035#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 638068#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 638069#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 638201#L737 assume 1 == ~t9_pc~0; 639117#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 638337#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 638241#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 638242#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 638523#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 638524#L756 assume 1 == ~t10_pc~0; 639155#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 638776#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 639060#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 638708#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 638313#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 638314#L775 assume !(1 == ~t11_pc~0); 638587#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 638588#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 639459#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 637967#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 637968#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 638148#L794 assume 1 == ~t12_pc~0; 637991#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 637970#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 637831#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 637832#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 638115#L1551-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 638599#L1307 assume !(1 == ~M_E~0); 638600#L1307-2 assume !(1 == ~T1_E~0); 638713#L1312-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 639570#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 638868#L1322-1 assume !(1 == ~T4_E~0); 638869#L1327-1 assume !(1 == ~T5_E~0); 638911#L1332-1 assume !(1 == ~T6_E~0); 638912#L1337-1 assume !(1 == ~T7_E~0); 638858#L1342-1 assume !(1 == ~T8_E~0); 638859#L1347-1 assume !(1 == ~T9_E~0); 653398#L1352-1 assume !(1 == ~T10_E~0); 653399#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 638501#L1362-1 assume !(1 == ~T12_E~0); 638502#L1367-1 assume !(1 == ~E_1~0); 638130#L1372-1 assume !(1 == ~E_2~0); 638131#L1377-1 assume !(1 == ~E_3~0); 638427#L1382-1 assume !(1 == ~E_4~0); 638428#L1387-1 assume !(1 == ~E_5~0); 653289#L1392-1 assume !(1 == ~E_6~0); 653288#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 653287#L1402-1 assume !(1 == ~E_8~0); 653286#L1407-1 assume !(1 == ~E_9~0); 653285#L1412-1 assume !(1 == ~E_10~0); 653284#L1417-1 assume !(1 == ~E_11~0); 653283#L1422-1 assume !(1 == ~E_12~0); 653281#L1427-1 assume { :end_inline_reset_delta_events } true; 653277#L1768-2 [2024-11-08 17:07:40,509 INFO L747 eck$LassoCheckResult]: Loop: 653277#L1768-2 assume !false; 653266#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 653259#L1149-1 assume !false; 653255#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 653167#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 653153#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 653145#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 653135#L976 assume !(0 != eval_~tmp~0#1); 653136#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 657644#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 657642#L1174-3 assume 0 == ~M_E~0;~M_E~0 := 1; 657638#L1174-5 assume !(0 == ~T1_E~0); 657636#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 657634#L1184-3 assume !(0 == ~T3_E~0); 657632#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 657629#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 657627#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 657625#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 657623#L1209-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 657621#L1214-3 assume !(0 == ~T9_E~0); 657619#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 657617#L1224-3 assume !(0 == ~T11_E~0); 657615#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 657613#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 657610#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 657608#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 657606#L1249-3 assume 0 == ~E_4~0;~E_4~0 := 1; 657604#L1254-3 assume !(0 == ~E_5~0); 657602#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 657600#L1264-3 assume !(0 == ~E_7~0); 657598#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 657596#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 657594#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 657592#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 657590#L1289-3 assume 0 == ~E_12~0;~E_12~0 := 1; 657588#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 657585#L566-39 assume !(1 == ~m_pc~0); 657583#L566-41 is_master_triggered_~__retres1~0#1 := 0; 657581#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 657579#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 657577#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 657575#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 657574#L585-39 assume !(1 == ~t1_pc~0); 657572#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 657570#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 657568#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 657566#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 657564#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 657561#L604-39 assume 1 == ~t2_pc~0; 657559#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 657560#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 657661#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 657550#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 657548#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 657545#L623-39 assume !(1 == ~t3_pc~0); 657543#L623-41 is_transmit3_triggered_~__retres1~3#1 := 0; 657541#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 657539#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 657537#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 657535#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 657532#L642-39 assume !(1 == ~t4_pc~0); 657530#L642-41 is_transmit4_triggered_~__retres1~4#1 := 0; 657527#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 657525#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 657523#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 657521#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 657518#L661-39 assume !(1 == ~t5_pc~0); 657516#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 657514#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 657512#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 657510#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 657508#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 657505#L680-39 assume 1 == ~t6_pc~0; 657502#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 657500#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 657498#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 657496#L1503-39 assume !(0 != activate_threads_~tmp___5~0#1); 657495#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 657493#L699-39 assume !(1 == ~t7_pc~0); 645610#L699-41 is_transmit7_triggered_~__retres1~7#1 := 0; 657488#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 657486#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 657485#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 657482#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 657481#L718-39 assume !(1 == ~t8_pc~0); 657480#L718-41 is_transmit8_triggered_~__retres1~8#1 := 0; 657476#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 657390#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 657379#L1519-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 657328#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 657327#L737-39 assume !(1 == ~t9_pc~0); 657326#L737-41 is_transmit9_triggered_~__retres1~9#1 := 0; 657321#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 657308#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 657243#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 657239#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 657228#L756-39 assume !(1 == ~t10_pc~0); 657219#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 657215#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 657214#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 657213#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 657212#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 657211#L775-39 assume !(1 == ~t11_pc~0); 657210#L775-41 is_transmit11_triggered_~__retres1~11#1 := 0; 657207#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 657205#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 657203#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 657201#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 657199#L794-39 assume !(1 == ~t12_pc~0); 657196#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 657194#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 657191#is_transmit12_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 657189#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 657187#L1551-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 657185#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 657183#L1307-5 assume !(1 == ~T1_E~0); 657181#L1312-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 654742#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 657177#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 657175#L1327-3 assume !(1 == ~T5_E~0); 657173#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 657171#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 657169#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 656756#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 656751#L1352-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 656749#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 656747#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 656745#L1367-3 assume !(1 == ~E_1~0); 656743#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 656741#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 656739#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 656737#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 656543#L1392-3 assume 1 == ~E_6~0;~E_6~0 := 2; 656702#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 656697#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 656693#L1407-3 assume !(1 == ~E_9~0); 656688#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 656664#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 656663#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 656662#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 656333#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 656282#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 656273#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 656263#L1787 assume !(0 == start_simulation_~tmp~3#1); 656257#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 655340#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 655327#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 653517#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 653513#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 653509#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 653505#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 653282#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 653277#L1768-2 [2024-11-08 17:07:40,509 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 17:07:40,509 INFO L85 PathProgramCache]: Analyzing trace with hash 339991860, now seen corresponding path program 1 times [2024-11-08 17:07:40,510 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 17:07:40,514 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1604560199] [2024-11-08 17:07:40,514 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 17:07:40,515 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 17:07:40,547 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:07:40,627 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 17:07:40,627 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 17:07:40,627 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1604560199] [2024-11-08 17:07:40,627 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1604560199] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 17:07:40,627 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 17:07:40,627 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-08 17:07:40,627 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [796196281] [2024-11-08 17:07:40,627 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 17:07:40,628 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 17:07:40,628 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 17:07:40,628 INFO L85 PathProgramCache]: Analyzing trace with hash 489552892, now seen corresponding path program 1 times [2024-11-08 17:07:40,628 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 17:07:40,628 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [890587003] [2024-11-08 17:07:40,628 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 17:07:40,629 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 17:07:40,643 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:07:40,723 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 17:07:40,723 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 17:07:40,723 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [890587003] [2024-11-08 17:07:40,723 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [890587003] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 17:07:40,723 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 17:07:40,723 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 17:07:40,724 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1294777916] [2024-11-08 17:07:40,724 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 17:07:40,724 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 17:07:40,724 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 17:07:40,724 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 17:07:40,724 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 17:07:40,725 INFO L87 Difference]: Start difference. First operand 161582 states and 230278 transitions. cyclomatic complexity: 68760 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 2 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 17:07:41,698 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 17:07:41,698 INFO L93 Difference]: Finished difference Result 309581 states and 439811 transitions. [2024-11-08 17:07:41,698 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 309581 states and 439811 transitions. [2024-11-08 17:07:43,527 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 308224 [2024-11-08 17:07:44,793 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 309581 states to 309581 states and 439811 transitions. [2024-11-08 17:07:44,793 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 309581 [2024-11-08 17:07:44,894 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 309581 [2024-11-08 17:07:44,894 INFO L73 IsDeterministic]: Start isDeterministic. Operand 309581 states and 439811 transitions. [2024-11-08 17:07:44,986 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 17:07:44,987 INFO L218 hiAutomatonCegarLoop]: Abstraction has 309581 states and 439811 transitions. [2024-11-08 17:07:45,107 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 309581 states and 439811 transitions. [2024-11-08 17:07:48,487 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 309581 to 309325. [2024-11-08 17:07:48,677 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 309325 states, 309325 states have (on average 1.4210134971308495) internal successors, (439555), 309324 states have internal predecessors, (439555), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 17:07:50,328 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 309325 states to 309325 states and 439555 transitions. [2024-11-08 17:07:50,328 INFO L240 hiAutomatonCegarLoop]: Abstraction has 309325 states and 439555 transitions. [2024-11-08 17:07:50,331 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 17:07:50,331 INFO L425 stractBuchiCegarLoop]: Abstraction has 309325 states and 439555 transitions. [2024-11-08 17:07:50,331 INFO L332 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2024-11-08 17:07:50,332 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 309325 states and 439555 transitions. [2024-11-08 17:07:50,949 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 307968 [2024-11-08 17:07:50,949 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 17:07:50,949 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 17:07:50,951 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 17:07:50,951 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 17:07:50,952 INFO L745 eck$LassoCheckResult]: Stem: 1109189#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 1109190#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 1110021#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1110022#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1109872#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 1109873#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1109980#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1110331#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1110507#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1110508#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1109166#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1109167#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1110410#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1109768#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1109769#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1109675#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1109676#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 1110111#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1109408#L1174 assume !(0 == ~M_E~0); 1109409#L1174-2 assume !(0 == ~T1_E~0); 1109255#L1179-1 assume !(0 == ~T2_E~0); 1109163#L1184-1 assume !(0 == ~T3_E~0); 1109164#L1189-1 assume !(0 == ~T4_E~0); 1109204#L1194-1 assume !(0 == ~T5_E~0); 1109297#L1199-1 assume !(0 == ~T6_E~0); 1110253#L1204-1 assume !(0 == ~T7_E~0); 1110165#L1209-1 assume !(0 == ~T8_E~0); 1110166#L1214-1 assume !(0 == ~T9_E~0); 1110686#L1219-1 assume !(0 == ~T10_E~0); 1110858#L1224-1 assume !(0 == ~T11_E~0); 1109529#L1229-1 assume !(0 == ~T12_E~0); 1109094#L1234-1 assume !(0 == ~E_1~0); 1109095#L1239-1 assume !(0 == ~E_2~0); 1109128#L1244-1 assume !(0 == ~E_3~0); 1109129#L1249-1 assume !(0 == ~E_4~0); 1109788#L1254-1 assume !(0 == ~E_5~0); 1109027#L1259-1 assume !(0 == ~E_6~0); 1108983#L1264-1 assume !(0 == ~E_7~0); 1108984#L1269-1 assume !(0 == ~E_8~0); 1110881#L1274-1 assume !(0 == ~E_9~0); 1110736#L1279-1 assume !(0 == ~E_10~0); 1109207#L1284-1 assume !(0 == ~E_11~0); 1109208#L1289-1 assume !(0 == ~E_12~0); 1109843#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1109844#L566 assume !(1 == ~m_pc~0); 1110324#L566-2 is_master_triggered_~__retres1~0#1 := 0; 1110325#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1109890#is_master_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1109891#L1455 assume !(0 != activate_threads_~tmp~1#1); 1109435#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1109436#L585 assume !(1 == ~t1_pc~0); 1109613#L585-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1109614#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1110317#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1110318#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 1110781#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1110776#L604 assume !(1 == ~t2_pc~0); 1110208#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1110209#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1109382#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1109383#L1471 assume !(0 != activate_threads_~tmp___1~0#1); 1110456#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1110457#L623 assume !(1 == ~t3_pc~0); 1108958#L623-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1108959#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1110291#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1110292#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 1110499#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1108997#L642 assume !(1 == ~t4_pc~0); 1108998#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1109448#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1109052#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1109053#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 1109071#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1110226#L661 assume !(1 == ~t5_pc~0); 1110414#L661-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1110128#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1110129#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1110579#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 1110264#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1110265#L680 assume !(1 == ~t6_pc~0); 1109653#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1109654#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1109367#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1109368#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 1110592#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1110771#L699 assume !(1 == ~t7_pc~0); 1110772#L699-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1110355#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1110356#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1109960#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 1109961#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1109845#L718 assume !(1 == ~t8_pc~0); 1109846#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1109202#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1109203#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1109235#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 1109236#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1109374#L737 assume !(1 == ~t9_pc~0); 1109510#L737-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1109511#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1109415#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1109416#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 1109696#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1109697#L756 assume 1 == ~t10_pc~0; 1110344#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1109951#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1110247#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1109882#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 1109490#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1109491#L775 assume !(1 == ~t11_pc~0); 1109759#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 1109760#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1110678#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1109138#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1109139#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1109317#L794 assume 1 == ~t12_pc~0; 1109162#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 1109141#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1109002#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1109003#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 1109283#L1551-2 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1109772#L1307 assume !(1 == ~M_E~0); 1109773#L1307-2 assume !(1 == ~T1_E~0); 1109887#L1312-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1110803#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1130013#L1322-1 assume !(1 == ~T4_E~0); 1130010#L1327-1 assume !(1 == ~T5_E~0); 1130008#L1332-1 assume !(1 == ~T6_E~0); 1130006#L1337-1 assume !(1 == ~T7_E~0); 1130004#L1342-1 assume !(1 == ~T8_E~0); 1130002#L1347-1 assume !(1 == ~T9_E~0); 1130000#L1352-1 assume !(1 == ~T10_E~0); 1129998#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1129996#L1362-1 assume !(1 == ~T12_E~0); 1129994#L1367-1 assume !(1 == ~E_1~0); 1129992#L1372-1 assume !(1 == ~E_2~0); 1129990#L1377-1 assume !(1 == ~E_3~0); 1129988#L1382-1 assume !(1 == ~E_4~0); 1129985#L1387-1 assume !(1 == ~E_5~0); 1129983#L1392-1 assume !(1 == ~E_6~0); 1129981#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 1129979#L1402-1 assume !(1 == ~E_8~0); 1129977#L1407-1 assume !(1 == ~E_9~0); 1129975#L1412-1 assume !(1 == ~E_10~0); 1129972#L1417-1 assume !(1 == ~E_11~0); 1129970#L1422-1 assume !(1 == ~E_12~0); 1129654#L1427-1 assume { :end_inline_reset_delta_events } true; 1129652#L1768-2 [2024-11-08 17:07:50,952 INFO L747 eck$LassoCheckResult]: Loop: 1129652#L1768-2 assume !false; 1129650#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1129644#L1149-1 assume !false; 1129642#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1129623#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1129616#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1129613#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1129610#L976 assume !(0 != eval_~tmp~0#1); 1129611#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1140180#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1140178#L1174-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1140176#L1174-5 assume !(0 == ~T1_E~0); 1140174#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1140173#L1184-3 assume !(0 == ~T3_E~0); 1140171#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1140169#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1140167#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1140165#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1140163#L1209-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1140160#L1214-3 assume !(0 == ~T9_E~0); 1140158#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 1140156#L1224-3 assume !(0 == ~T11_E~0); 1140154#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 1140152#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1140150#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1140148#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1140146#L1249-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1140144#L1254-3 assume !(0 == ~E_5~0); 1140142#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1140140#L1264-3 assume !(0 == ~E_7~0); 1140138#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1140137#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1140136#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1140134#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1140133#L1289-3 assume 0 == ~E_12~0;~E_12~0 := 1; 1140132#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1140128#L566-39 assume !(1 == ~m_pc~0); 1140126#L566-41 is_master_triggered_~__retres1~0#1 := 0; 1140124#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1140122#is_master_triggered_returnLabel#14 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1140119#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1140117#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1140115#L585-39 assume !(1 == ~t1_pc~0); 1139983#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 1139979#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1139974#is_transmit1_triggered_returnLabel#14 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1139969#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1139963#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1139958#L604-39 assume !(1 == ~t2_pc~0); 1139952#L604-41 is_transmit2_triggered_~__retres1~2#1 := 0; 1139947#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1139942#is_transmit2_triggered_returnLabel#14 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1139936#L1471-39 assume !(0 != activate_threads_~tmp___1~0#1); 1139930#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1139924#L623-39 assume !(1 == ~t3_pc~0); 1139917#L623-41 is_transmit3_triggered_~__retres1~3#1 := 0; 1139911#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1139905#is_transmit3_triggered_returnLabel#14 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1139899#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1139894#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1139888#L642-39 assume 1 == ~t4_pc~0; 1139881#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1139875#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1139868#is_transmit4_triggered_returnLabel#14 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1139862#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1139855#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1139848#L661-39 assume !(1 == ~t5_pc~0); 1139840#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 1139832#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1139825#is_transmit5_triggered_returnLabel#14 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1139818#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1139811#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1139803#L680-39 assume 1 == ~t6_pc~0; 1139795#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1139788#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1139782#is_transmit6_triggered_returnLabel#14 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1139775#L1503-39 assume !(0 != activate_threads_~tmp___5~0#1); 1139767#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1139760#L699-39 assume !(1 == ~t7_pc~0); 1130975#L699-41 is_transmit7_triggered_~__retres1~7#1 := 0; 1139747#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1139740#is_transmit7_triggered_returnLabel#14 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1139734#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1139727#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1139720#L718-39 assume !(1 == ~t8_pc~0); 1139712#L718-41 is_transmit8_triggered_~__retres1~8#1 := 0; 1139703#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1139695#is_transmit8_triggered_returnLabel#14 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1139687#L1519-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1139679#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1139672#L737-39 assume !(1 == ~t9_pc~0); 1139665#L737-41 is_transmit9_triggered_~__retres1~9#1 := 0; 1139658#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1139650#is_transmit9_triggered_returnLabel#14 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1139641#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1139634#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1139625#L756-39 assume 1 == ~t10_pc~0; 1139617#L757-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1139609#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1139602#is_transmit10_triggered_returnLabel#14 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1139594#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1139586#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1139578#L775-39 assume 1 == ~t11_pc~0; 1139569#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1139561#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1139552#is_transmit11_triggered_returnLabel#14 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1139547#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1139541#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1139534#L794-39 assume !(1 == ~t12_pc~0); 1139525#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 1139518#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1139511#is_transmit12_triggered_returnLabel#14 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1139434#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1139428#L1551-41 havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1139419#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1139412#L1307-5 assume !(1 == ~T1_E~0); 1139405#L1312-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1133748#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1139391#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1139384#L1327-3 assume !(1 == ~T5_E~0); 1139377#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1139370#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1139363#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1139356#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1139346#L1352-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1139340#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1139313#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1139305#L1367-3 assume !(1 == ~E_1~0); 1139297#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1139288#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1139280#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1139275#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1133713#L1392-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1139079#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1139044#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1139034#L1407-3 assume !(1 == ~E_9~0); 1139025#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1133403#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1133402#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 1133242#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1129701#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1129688#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1129686#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 1129684#L1787 assume !(0 == start_simulation_~tmp~3#1); 1129682#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1129672#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1129665#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1129663#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 1129661#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1129659#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1129657#stop_simulation_returnLabel#1 start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 1129655#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 1129652#L1768-2 [2024-11-08 17:07:50,952 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 17:07:50,952 INFO L85 PathProgramCache]: Analyzing trace with hash -1390345197, now seen corresponding path program 1 times [2024-11-08 17:07:50,953 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 17:07:50,953 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [848906502] [2024-11-08 17:07:50,953 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 17:07:50,953 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 17:07:50,975 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:07:51,030 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 17:07:51,030 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 17:07:51,030 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [848906502] [2024-11-08 17:07:51,030 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [848906502] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 17:07:51,031 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 17:07:51,031 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-08 17:07:51,031 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1378782950] [2024-11-08 17:07:51,031 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 17:07:51,031 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 17:07:51,032 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 17:07:51,032 INFO L85 PathProgramCache]: Analyzing trace with hash 203545532, now seen corresponding path program 1 times [2024-11-08 17:07:51,032 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 17:07:51,032 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1773837609] [2024-11-08 17:07:51,032 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 17:07:51,033 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 17:07:51,047 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:07:51,086 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 17:07:51,086 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 17:07:51,086 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1773837609] [2024-11-08 17:07:51,086 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1773837609] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 17:07:51,086 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 17:07:51,087 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 17:07:51,087 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1029426583] [2024-11-08 17:07:51,087 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 17:07:51,087 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 17:07:51,087 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 17:07:51,088 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 17:07:51,088 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 17:07:51,088 INFO L87 Difference]: Start difference. First operand 309325 states and 439555 transitions. cyclomatic complexity: 130358 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 2 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 17:07:54,444 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 17:07:54,444 INFO L93 Difference]: Finished difference Result 591948 states and 838720 transitions. [2024-11-08 17:07:54,444 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 591948 states and 838720 transitions. [2024-11-08 17:07:57,689 INFO L131 ngComponentsAnalysis]: Automaton has 256 accepting balls. 588928 [2024-11-08 17:07:59,550 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 591948 states to 591948 states and 838720 transitions. [2024-11-08 17:07:59,551 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 591948 [2024-11-08 17:07:59,738 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 591948 [2024-11-08 17:07:59,738 INFO L73 IsDeterministic]: Start isDeterministic. Operand 591948 states and 838720 transitions. [2024-11-08 17:07:59,918 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 17:07:59,918 INFO L218 hiAutomatonCegarLoop]: Abstraction has 591948 states and 838720 transitions. [2024-11-08 17:08:00,165 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 591948 states and 838720 transitions.