./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.unsafe_analog_estimation_convergence.c --full-output --architecture 64bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version a0165632 Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/config/AutomizerReach.xml -i ../../sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.unsafe_analog_estimation_convergence.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/config/svcomp-Reach-64bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(reach_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash 37235873cdbfb4a92a6d9a366e7d975c617138dc8eee2f80d6fd06796710e280 --- Real Ultimate output --- This is Ultimate 0.2.5-dev-a016563 [2024-11-08 17:00:43,854 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-08 17:00:43,979 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/config/svcomp-Reach-64bit-Automizer_Default.epf [2024-11-08 17:00:43,989 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-08 17:00:43,990 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-08 17:00:44,025 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-08 17:00:44,026 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-08 17:00:44,026 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-08 17:00:44,027 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-08 17:00:44,028 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-08 17:00:44,028 INFO L151 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2024-11-08 17:00:44,029 INFO L153 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2024-11-08 17:00:44,030 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-08 17:00:44,032 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-08 17:00:44,035 INFO L153 SettingsManager]: * Use SBE=true [2024-11-08 17:00:44,036 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-08 17:00:44,036 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2024-11-08 17:00:44,036 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-08 17:00:44,037 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-08 17:00:44,037 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2024-11-08 17:00:44,038 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2024-11-08 17:00:44,042 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2024-11-08 17:00:44,042 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-11-08 17:00:44,043 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-08 17:00:44,043 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-08 17:00:44,043 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-11-08 17:00:44,044 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-08 17:00:44,044 INFO L153 SettingsManager]: * Only consider context switches at boundaries of atomic blocks=true [2024-11-08 17:00:44,045 INFO L153 SettingsManager]: * SMT solver=External_DefaultMode [2024-11-08 17:00:44,045 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 [2024-11-08 17:00:44,045 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-08 17:00:44,047 INFO L153 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2024-11-08 17:00:44,048 INFO L153 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopHeads [2024-11-08 17:00:44,049 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-11-08 17:00:44,050 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2024-11-08 17:00:44,050 INFO L153 SettingsManager]: * Apply one-shot large block encoding in concurrent analysis=false [2024-11-08 17:00:44,051 INFO L153 SettingsManager]: * Automaton type used in concurrency analysis=PETRI_NET [2024-11-08 17:00:44,051 INFO L153 SettingsManager]: * Order on configurations for Petri net unfoldings=DBO [2024-11-08 17:00:44,052 INFO L153 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2024-11-08 17:00:44,052 INFO L153 SettingsManager]: * Looper check in Petri net analysis=SEMANTIC WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(reach_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 37235873cdbfb4a92a6d9a366e7d975c617138dc8eee2f80d6fd06796710e280 [2024-11-08 17:00:44,370 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-08 17:00:44,410 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-08 17:00:44,413 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-08 17:00:44,416 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-08 17:00:44,416 INFO L274 PluginConnector]: CDTParser initialized [2024-11-08 17:00:44,418 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/../../sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.unsafe_analog_estimation_convergence.c Unable to find full path for "g++" [2024-11-08 17:00:46,928 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-11-08 17:00:47,204 INFO L384 CDTParser]: Found 1 translation units. [2024-11-08 17:00:47,205 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.unsafe_analog_estimation_convergence.c [2024-11-08 17:00:47,220 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/data/c5a709c92/89ef50a195974029b3ae9f4559136a6c/FLAGe4dc87fd5 [2024-11-08 17:00:47,246 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/data/c5a709c92/89ef50a195974029b3ae9f4559136a6c [2024-11-08 17:00:47,249 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-08 17:00:47,251 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-08 17:00:47,253 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-08 17:00:47,253 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-08 17:00:47,260 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-08 17:00:47,261 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 08.11 05:00:47" (1/1) ... [2024-11-08 17:00:47,263 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@5dac0950 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 05:00:47, skipping insertion in model container [2024-11-08 17:00:47,263 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 08.11 05:00:47" (1/1) ... [2024-11-08 17:00:47,312 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-08 17:00:47,599 WARN L250 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.unsafe_analog_estimation_convergence.c[1289,1302] [2024-11-08 17:00:47,821 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-08 17:00:47,838 INFO L200 MainTranslator]: Completed pre-run [2024-11-08 17:00:47,852 WARN L250 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.unsafe_analog_estimation_convergence.c[1289,1302] [2024-11-08 17:00:47,989 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-08 17:00:48,012 INFO L204 MainTranslator]: Completed translation [2024-11-08 17:00:48,013 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 05:00:48 WrapperNode [2024-11-08 17:00:48,013 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-08 17:00:48,015 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-08 17:00:48,015 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-08 17:00:48,016 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-08 17:00:48,026 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 05:00:48" (1/1) ... [2024-11-08 17:00:48,052 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 05:00:48" (1/1) ... [2024-11-08 17:00:48,175 INFO L138 Inliner]: procedures = 17, calls = 10, calls flagged for inlining = 3, calls inlined = 3, statements flattened = 900 [2024-11-08 17:00:48,176 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-08 17:00:48,177 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-08 17:00:48,177 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-08 17:00:48,178 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-08 17:00:48,196 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 05:00:48" (1/1) ... [2024-11-08 17:00:48,196 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 05:00:48" (1/1) ... [2024-11-08 17:00:48,235 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 05:00:48" (1/1) ... [2024-11-08 17:00:48,296 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-11-08 17:00:48,304 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 05:00:48" (1/1) ... [2024-11-08 17:00:48,304 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 05:00:48" (1/1) ... [2024-11-08 17:00:48,345 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 05:00:48" (1/1) ... [2024-11-08 17:00:48,364 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 05:00:48" (1/1) ... [2024-11-08 17:00:48,379 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 05:00:48" (1/1) ... [2024-11-08 17:00:48,399 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 05:00:48" (1/1) ... [2024-11-08 17:00:48,416 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-08 17:00:48,417 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-11-08 17:00:48,417 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-11-08 17:00:48,418 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-11-08 17:00:48,419 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 05:00:48" (1/1) ... [2024-11-08 17:00:48,427 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 [2024-11-08 17:00:48,442 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/z3 [2024-11-08 17:00:48,462 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (exit command is (exit), workingDir is null) [2024-11-08 17:00:48,470 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (1)] Waiting until timeout for monitored process [2024-11-08 17:00:48,510 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-08 17:00:48,511 INFO L130 BoogieDeclarations]: Found specification of procedure assume_abort_if_not [2024-11-08 17:00:48,511 INFO L138 BoogieDeclarations]: Found implementation of procedure assume_abort_if_not [2024-11-08 17:00:48,512 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-11-08 17:00:48,512 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-08 17:00:48,512 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-08 17:00:48,750 INFO L238 CfgBuilder]: Building ICFG [2024-11-08 17:00:48,753 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-08 17:00:50,643 INFO L? ?]: Removed 480 outVars from TransFormulas that were not future-live. [2024-11-08 17:00:50,644 INFO L287 CfgBuilder]: Performing block encoding [2024-11-08 17:00:50,668 INFO L311 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-08 17:00:50,671 INFO L316 CfgBuilder]: Removed 1 assume(true) statements. [2024-11-08 17:00:50,672 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 08.11 05:00:50 BoogieIcfgContainer [2024-11-08 17:00:50,673 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-11-08 17:00:50,676 INFO L112 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2024-11-08 17:00:50,676 INFO L270 PluginConnector]: Initializing TraceAbstraction... [2024-11-08 17:00:50,681 INFO L274 PluginConnector]: TraceAbstraction initialized [2024-11-08 17:00:50,681 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 08.11 05:00:47" (1/3) ... [2024-11-08 17:00:50,682 INFO L204 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@2699989b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 08.11 05:00:50, skipping insertion in model container [2024-11-08 17:00:50,683 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 05:00:48" (2/3) ... [2024-11-08 17:00:50,684 INFO L204 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@2699989b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 08.11 05:00:50, skipping insertion in model container [2024-11-08 17:00:50,686 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 08.11 05:00:50" (3/3) ... [2024-11-08 17:00:50,688 INFO L112 eAbstractionObserver]: Analyzing ICFG btor2c-lazyMod.unsafe_analog_estimation_convergence.c [2024-11-08 17:00:50,714 INFO L214 ceAbstractionStarter]: Automizer settings: Hoare:LoopHeads NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2024-11-08 17:00:50,714 INFO L154 ceAbstractionStarter]: Applying trace abstraction to program that has 1 error locations. [2024-11-08 17:00:50,811 INFO L332 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2024-11-08 17:00:50,823 INFO L333 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mAutomataTypeConcurrency=PETRI_NET, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopHeads, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=[Lde.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings;@2b909ec8, mLbeIndependenceSettings=[IndependenceType=SEMANTIC, AbstractionType=NONE, UseConditional=false, UseSemiCommutativity=true, Solver=Z3, SolverTimeout=1000ms] [2024-11-08 17:00:50,824 INFO L334 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2024-11-08 17:00:50,833 INFO L276 IsEmpty]: Start isEmpty. Operand has 281 states, 276 states have (on average 1.4963768115942029) internal successors, (413), 277 states have internal predecessors, (413), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2024-11-08 17:00:50,858 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 124 [2024-11-08 17:00:50,859 INFO L207 NwaCegarLoop]: Found error trace [2024-11-08 17:00:50,862 INFO L215 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 17:00:50,864 INFO L396 AbstractCegarLoop]: === Iteration 1 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-08 17:00:50,872 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 17:00:50,874 INFO L85 PathProgramCache]: Analyzing trace with hash -214923661, now seen corresponding path program 1 times [2024-11-08 17:00:50,887 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 17:00:50,888 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2096903553] [2024-11-08 17:00:50,889 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 17:00:50,890 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 17:00:51,157 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:00:51,599 INFO L368 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 21 [2024-11-08 17:00:51,603 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:00:51,610 INFO L368 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 35 [2024-11-08 17:00:51,615 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:00:51,622 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-11-08 17:00:51,624 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 17:00:51,625 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2096903553] [2024-11-08 17:00:51,626 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2096903553] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 17:00:51,626 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 17:00:51,626 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-08 17:00:51,629 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1264029994] [2024-11-08 17:00:51,631 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 17:00:51,638 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 2 states [2024-11-08 17:00:51,638 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 17:00:51,692 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2024-11-08 17:00:51,693 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2024-11-08 17:00:51,699 INFO L87 Difference]: Start difference. First operand has 281 states, 276 states have (on average 1.4963768115942029) internal successors, (413), 277 states have internal predecessors, (413), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) Second operand has 2 states, 2 states have (on average 58.0) internal successors, (116), 2 states have internal predecessors, (116), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 2 states have call successors, (2) [2024-11-08 17:00:51,769 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 17:00:51,770 INFO L93 Difference]: Finished difference Result 536 states and 801 transitions. [2024-11-08 17:00:51,771 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-11-08 17:00:51,773 INFO L78 Accepts]: Start accepts. Automaton has has 2 states, 2 states have (on average 58.0) internal successors, (116), 2 states have internal predecessors, (116), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 2 states have call successors, (2) Word has length 123 [2024-11-08 17:00:51,774 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-08 17:00:51,788 INFO L225 Difference]: With dead ends: 536 [2024-11-08 17:00:51,789 INFO L226 Difference]: Without dead ends: 277 [2024-11-08 17:00:51,793 INFO L431 NwaCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 8 SyntacticMatches, 0 SemanticMatches, 0 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2024-11-08 17:00:51,800 INFO L432 NwaCegarLoop]: 410 mSDtfsCounter, 0 mSDsluCounter, 0 mSDsCounter, 0 mSdLazyCounter, 0 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 410 SdHoareTripleChecker+Invalid, 0 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 0 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-08 17:00:51,801 INFO L433 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 410 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 0 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-08 17:00:51,835 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 277 states. [2024-11-08 17:00:51,887 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 277 to 277. [2024-11-08 17:00:51,890 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 277 states, 273 states have (on average 1.4871794871794872) internal successors, (406), 273 states have internal predecessors, (406), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2024-11-08 17:00:51,893 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 277 states to 277 states and 410 transitions. [2024-11-08 17:00:51,895 INFO L78 Accepts]: Start accepts. Automaton has 277 states and 410 transitions. Word has length 123 [2024-11-08 17:00:51,896 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-08 17:00:51,896 INFO L471 AbstractCegarLoop]: Abstraction has 277 states and 410 transitions. [2024-11-08 17:00:51,897 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 2 states, 2 states have (on average 58.0) internal successors, (116), 2 states have internal predecessors, (116), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 2 states have call successors, (2) [2024-11-08 17:00:51,897 INFO L276 IsEmpty]: Start isEmpty. Operand 277 states and 410 transitions. [2024-11-08 17:00:51,903 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 124 [2024-11-08 17:00:51,903 INFO L207 NwaCegarLoop]: Found error trace [2024-11-08 17:00:51,904 INFO L215 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 17:00:51,904 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable0 [2024-11-08 17:00:51,905 INFO L396 AbstractCegarLoop]: === Iteration 2 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-08 17:00:51,906 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 17:00:51,906 INFO L85 PathProgramCache]: Analyzing trace with hash -276001681, now seen corresponding path program 1 times [2024-11-08 17:00:51,906 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 17:00:51,907 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [665909211] [2024-11-08 17:00:51,907 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 17:00:51,907 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 17:00:52,158 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:00:53,349 INFO L368 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 21 [2024-11-08 17:00:53,351 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:00:53,354 INFO L368 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 35 [2024-11-08 17:00:53,357 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:00:53,363 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-11-08 17:00:53,364 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 17:00:53,364 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [665909211] [2024-11-08 17:00:53,364 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [665909211] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 17:00:53,364 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 17:00:53,365 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-08 17:00:53,365 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [429482815] [2024-11-08 17:00:53,365 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 17:00:53,369 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-11-08 17:00:53,370 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 17:00:53,374 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-08 17:00:53,374 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-08 17:00:53,375 INFO L87 Difference]: Start difference. First operand 277 states and 410 transitions. Second operand has 4 states, 4 states have (on average 29.0) internal successors, (116), 4 states have internal predecessors, (116), 1 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) [2024-11-08 17:00:53,446 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 17:00:53,447 INFO L93 Difference]: Finished difference Result 281 states and 414 transitions. [2024-11-08 17:00:53,447 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-08 17:00:53,448 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 29.0) internal successors, (116), 4 states have internal predecessors, (116), 1 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) Word has length 123 [2024-11-08 17:00:53,448 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-08 17:00:53,450 INFO L225 Difference]: With dead ends: 281 [2024-11-08 17:00:53,451 INFO L226 Difference]: Without dead ends: 279 [2024-11-08 17:00:53,452 INFO L431 NwaCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 6 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-08 17:00:53,453 INFO L432 NwaCegarLoop]: 408 mSDtfsCounter, 0 mSDsluCounter, 810 mSDsCounter, 0 mSdLazyCounter, 11 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 1218 SdHoareTripleChecker+Invalid, 11 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 11 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-08 17:00:53,454 INFO L433 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 1218 Invalid, 11 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 11 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-08 17:00:53,455 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 279 states. [2024-11-08 17:00:53,470 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 279 to 279. [2024-11-08 17:00:53,471 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 279 states, 275 states have (on average 1.4836363636363636) internal successors, (408), 275 states have internal predecessors, (408), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2024-11-08 17:00:53,473 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 279 states to 279 states and 412 transitions. [2024-11-08 17:00:53,474 INFO L78 Accepts]: Start accepts. Automaton has 279 states and 412 transitions. Word has length 123 [2024-11-08 17:00:53,475 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-08 17:00:53,476 INFO L471 AbstractCegarLoop]: Abstraction has 279 states and 412 transitions. [2024-11-08 17:00:53,476 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 29.0) internal successors, (116), 4 states have internal predecessors, (116), 1 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) [2024-11-08 17:00:53,476 INFO L276 IsEmpty]: Start isEmpty. Operand 279 states and 412 transitions. [2024-11-08 17:00:53,479 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 125 [2024-11-08 17:00:53,480 INFO L207 NwaCegarLoop]: Found error trace [2024-11-08 17:00:53,480 INFO L215 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 17:00:53,480 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable1 [2024-11-08 17:00:53,481 INFO L396 AbstractCegarLoop]: === Iteration 3 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-08 17:00:53,481 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 17:00:53,482 INFO L85 PathProgramCache]: Analyzing trace with hash 35578341, now seen corresponding path program 1 times [2024-11-08 17:00:53,482 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 17:00:53,482 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1543738674] [2024-11-08 17:00:53,482 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 17:00:53,483 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 17:00:53,601 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:00:54,106 INFO L368 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 21 [2024-11-08 17:00:54,109 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:00:54,114 INFO L368 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 35 [2024-11-08 17:00:54,116 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:00:54,122 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-11-08 17:00:54,125 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 17:00:54,125 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1543738674] [2024-11-08 17:00:54,126 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1543738674] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 17:00:54,126 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 17:00:54,126 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-08 17:00:54,126 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1248779930] [2024-11-08 17:00:54,126 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 17:00:54,127 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-08 17:00:54,127 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 17:00:54,128 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-08 17:00:54,128 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-08 17:00:54,131 INFO L87 Difference]: Start difference. First operand 279 states and 412 transitions. Second operand has 5 states, 5 states have (on average 23.4) internal successors, (117), 5 states have internal predecessors, (117), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2024-11-08 17:00:54,515 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 17:00:54,516 INFO L93 Difference]: Finished difference Result 761 states and 1129 transitions. [2024-11-08 17:00:54,516 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-11-08 17:00:54,517 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 23.4) internal successors, (117), 5 states have internal predecessors, (117), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) Word has length 124 [2024-11-08 17:00:54,518 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-08 17:00:54,520 INFO L225 Difference]: With dead ends: 761 [2024-11-08 17:00:54,520 INFO L226 Difference]: Without dead ends: 279 [2024-11-08 17:00:54,522 INFO L431 NwaCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 6 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2024-11-08 17:00:54,524 INFO L432 NwaCegarLoop]: 686 mSDtfsCounter, 635 mSDsluCounter, 1028 mSDsCounter, 0 mSdLazyCounter, 133 mSolverCounterSat, 12 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 636 SdHoareTripleChecker+Valid, 1714 SdHoareTripleChecker+Invalid, 145 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 12 IncrementalHoareTripleChecker+Valid, 133 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2024-11-08 17:00:54,524 INFO L433 NwaCegarLoop]: SdHoareTripleChecker [636 Valid, 1714 Invalid, 145 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [12 Valid, 133 Invalid, 0 Unknown, 0 Unchecked, 0.3s Time] [2024-11-08 17:00:54,526 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 279 states. [2024-11-08 17:00:54,538 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 279 to 279. [2024-11-08 17:00:54,539 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 279 states, 275 states have (on average 1.48) internal successors, (407), 275 states have internal predecessors, (407), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2024-11-08 17:00:54,541 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 279 states to 279 states and 411 transitions. [2024-11-08 17:00:54,541 INFO L78 Accepts]: Start accepts. Automaton has 279 states and 411 transitions. Word has length 124 [2024-11-08 17:00:54,542 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-08 17:00:54,542 INFO L471 AbstractCegarLoop]: Abstraction has 279 states and 411 transitions. [2024-11-08 17:00:54,543 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 23.4) internal successors, (117), 5 states have internal predecessors, (117), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2024-11-08 17:00:54,543 INFO L276 IsEmpty]: Start isEmpty. Operand 279 states and 411 transitions. [2024-11-08 17:00:54,545 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 126 [2024-11-08 17:00:54,546 INFO L207 NwaCegarLoop]: Found error trace [2024-11-08 17:00:54,546 INFO L215 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 17:00:54,547 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable2 [2024-11-08 17:00:54,547 INFO L396 AbstractCegarLoop]: === Iteration 4 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-08 17:00:54,547 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 17:00:54,548 INFO L85 PathProgramCache]: Analyzing trace with hash 228074486, now seen corresponding path program 1 times [2024-11-08 17:00:54,548 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 17:00:54,548 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [542077510] [2024-11-08 17:00:54,549 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 17:00:54,549 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 17:00:54,676 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:00:55,125 INFO L368 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 21 [2024-11-08 17:00:55,127 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:00:55,130 INFO L368 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 36 [2024-11-08 17:00:55,131 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:00:55,137 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-11-08 17:00:55,137 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 17:00:55,137 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [542077510] [2024-11-08 17:00:55,138 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [542077510] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 17:00:55,138 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 17:00:55,138 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-08 17:00:55,138 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [444434223] [2024-11-08 17:00:55,138 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 17:00:55,139 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-11-08 17:00:55,139 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 17:00:55,142 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-08 17:00:55,142 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-08 17:00:55,143 INFO L87 Difference]: Start difference. First operand 279 states and 411 transitions. Second operand has 4 states, 4 states have (on average 29.5) internal successors, (118), 4 states have internal predecessors, (118), 1 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) [2024-11-08 17:00:55,190 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 17:00:55,191 INFO L93 Difference]: Finished difference Result 538 states and 793 transitions. [2024-11-08 17:00:55,191 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-08 17:00:55,192 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 29.5) internal successors, (118), 4 states have internal predecessors, (118), 1 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) Word has length 125 [2024-11-08 17:00:55,193 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-08 17:00:55,196 INFO L225 Difference]: With dead ends: 538 [2024-11-08 17:00:55,196 INFO L226 Difference]: Without dead ends: 281 [2024-11-08 17:00:55,199 INFO L431 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 7 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-08 17:00:55,202 INFO L432 NwaCegarLoop]: 407 mSDtfsCounter, 0 mSDsluCounter, 804 mSDsCounter, 0 mSdLazyCounter, 15 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 1211 SdHoareTripleChecker+Invalid, 15 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 15 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-08 17:00:55,203 INFO L433 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 1211 Invalid, 15 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 15 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-08 17:00:55,205 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 281 states. [2024-11-08 17:00:55,216 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 281 to 281. [2024-11-08 17:00:55,218 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 281 states, 277 states have (on average 1.476534296028881) internal successors, (409), 277 states have internal predecessors, (409), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2024-11-08 17:00:55,219 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 281 states to 281 states and 413 transitions. [2024-11-08 17:00:55,220 INFO L78 Accepts]: Start accepts. Automaton has 281 states and 413 transitions. Word has length 125 [2024-11-08 17:00:55,221 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-08 17:00:55,221 INFO L471 AbstractCegarLoop]: Abstraction has 281 states and 413 transitions. [2024-11-08 17:00:55,221 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 29.5) internal successors, (118), 4 states have internal predecessors, (118), 1 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) [2024-11-08 17:00:55,222 INFO L276 IsEmpty]: Start isEmpty. Operand 281 states and 413 transitions. [2024-11-08 17:00:55,226 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 127 [2024-11-08 17:00:55,226 INFO L207 NwaCegarLoop]: Found error trace [2024-11-08 17:00:55,227 INFO L215 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 17:00:55,227 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable3 [2024-11-08 17:00:55,227 INFO L396 AbstractCegarLoop]: === Iteration 5 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-08 17:00:55,228 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 17:00:55,228 INFO L85 PathProgramCache]: Analyzing trace with hash 1677376535, now seen corresponding path program 1 times [2024-11-08 17:00:55,228 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 17:00:55,229 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1812011554] [2024-11-08 17:00:55,230 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 17:00:55,230 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 17:00:55,435 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:00:56,121 INFO L368 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 21 [2024-11-08 17:00:56,123 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:00:56,129 INFO L368 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 36 [2024-11-08 17:00:56,135 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:00:56,144 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-11-08 17:00:56,149 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 17:00:56,149 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1812011554] [2024-11-08 17:00:56,149 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1812011554] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 17:00:56,150 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 17:00:56,150 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-08 17:00:56,150 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [970378074] [2024-11-08 17:00:56,150 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 17:00:56,151 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-11-08 17:00:56,151 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 17:00:56,152 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-08 17:00:56,152 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-08 17:00:56,153 INFO L87 Difference]: Start difference. First operand 281 states and 413 transitions. Second operand has 4 states, 4 states have (on average 29.75) internal successors, (119), 4 states have internal predecessors, (119), 1 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) [2024-11-08 17:00:56,263 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 17:00:56,263 INFO L93 Difference]: Finished difference Result 540 states and 794 transitions. [2024-11-08 17:00:56,264 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-08 17:00:56,264 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 29.75) internal successors, (119), 4 states have internal predecessors, (119), 1 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) Word has length 126 [2024-11-08 17:00:56,265 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-08 17:00:56,266 INFO L225 Difference]: With dead ends: 540 [2024-11-08 17:00:56,266 INFO L226 Difference]: Without dead ends: 281 [2024-11-08 17:00:56,267 INFO L431 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 6 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2024-11-08 17:00:56,269 INFO L432 NwaCegarLoop]: 393 mSDtfsCounter, 372 mSDsluCounter, 395 mSDsCounter, 0 mSdLazyCounter, 31 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 372 SdHoareTripleChecker+Valid, 788 SdHoareTripleChecker+Invalid, 31 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 31 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-08 17:00:56,273 INFO L433 NwaCegarLoop]: SdHoareTripleChecker [372 Valid, 788 Invalid, 31 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 31 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-08 17:00:56,274 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 281 states. [2024-11-08 17:00:56,297 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 281 to 281. [2024-11-08 17:00:56,298 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 281 states, 277 states have (on average 1.4729241877256318) internal successors, (408), 277 states have internal predecessors, (408), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2024-11-08 17:00:56,299 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 281 states to 281 states and 412 transitions. [2024-11-08 17:00:56,304 INFO L78 Accepts]: Start accepts. Automaton has 281 states and 412 transitions. Word has length 126 [2024-11-08 17:00:56,304 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-08 17:00:56,304 INFO L471 AbstractCegarLoop]: Abstraction has 281 states and 412 transitions. [2024-11-08 17:00:56,305 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 29.75) internal successors, (119), 4 states have internal predecessors, (119), 1 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) [2024-11-08 17:00:56,305 INFO L276 IsEmpty]: Start isEmpty. Operand 281 states and 412 transitions. [2024-11-08 17:00:56,307 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 128 [2024-11-08 17:00:56,307 INFO L207 NwaCegarLoop]: Found error trace [2024-11-08 17:00:56,307 INFO L215 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 17:00:56,307 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable4 [2024-11-08 17:00:56,312 INFO L396 AbstractCegarLoop]: === Iteration 6 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-08 17:00:56,313 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 17:00:56,313 INFO L85 PathProgramCache]: Analyzing trace with hash 827020357, now seen corresponding path program 1 times [2024-11-08 17:00:56,313 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 17:00:56,313 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [726608203] [2024-11-08 17:00:56,314 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 17:00:56,314 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 17:00:56,671 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:00:56,991 INFO L368 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 21 [2024-11-08 17:00:56,993 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:00:56,997 INFO L368 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 36 [2024-11-08 17:00:57,000 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:00:57,006 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-11-08 17:00:57,007 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 17:00:57,007 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [726608203] [2024-11-08 17:00:57,008 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [726608203] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 17:00:57,008 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 17:00:57,010 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-08 17:00:57,010 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [220309428] [2024-11-08 17:00:57,011 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 17:00:57,011 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-11-08 17:00:57,011 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 17:00:57,012 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-08 17:00:57,013 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-08 17:00:57,013 INFO L87 Difference]: Start difference. First operand 281 states and 412 transitions. Second operand has 4 states, 4 states have (on average 30.0) internal successors, (120), 4 states have internal predecessors, (120), 1 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) [2024-11-08 17:00:57,126 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 17:00:57,130 INFO L93 Difference]: Finished difference Result 540 states and 792 transitions. [2024-11-08 17:00:57,130 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-08 17:00:57,131 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 30.0) internal successors, (120), 4 states have internal predecessors, (120), 1 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) Word has length 127 [2024-11-08 17:00:57,131 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-08 17:00:57,133 INFO L225 Difference]: With dead ends: 540 [2024-11-08 17:00:57,133 INFO L226 Difference]: Without dead ends: 281 [2024-11-08 17:00:57,134 INFO L431 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 6 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2024-11-08 17:00:57,135 INFO L432 NwaCegarLoop]: 393 mSDtfsCounter, 370 mSDsluCounter, 395 mSDsCounter, 0 mSdLazyCounter, 29 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 370 SdHoareTripleChecker+Valid, 788 SdHoareTripleChecker+Invalid, 29 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 29 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-08 17:00:57,138 INFO L433 NwaCegarLoop]: SdHoareTripleChecker [370 Valid, 788 Invalid, 29 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 29 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-08 17:00:57,140 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 281 states. [2024-11-08 17:00:57,156 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 281 to 281. [2024-11-08 17:00:57,160 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 281 states, 277 states have (on average 1.4693140794223827) internal successors, (407), 277 states have internal predecessors, (407), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2024-11-08 17:00:57,161 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 281 states to 281 states and 411 transitions. [2024-11-08 17:00:57,162 INFO L78 Accepts]: Start accepts. Automaton has 281 states and 411 transitions. Word has length 127 [2024-11-08 17:00:57,162 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-08 17:00:57,163 INFO L471 AbstractCegarLoop]: Abstraction has 281 states and 411 transitions. [2024-11-08 17:00:57,163 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 30.0) internal successors, (120), 4 states have internal predecessors, (120), 1 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) [2024-11-08 17:00:57,163 INFO L276 IsEmpty]: Start isEmpty. Operand 281 states and 411 transitions. [2024-11-08 17:00:57,165 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 129 [2024-11-08 17:00:57,165 INFO L207 NwaCegarLoop]: Found error trace [2024-11-08 17:00:57,166 INFO L215 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 17:00:57,166 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable5 [2024-11-08 17:00:57,166 INFO L396 AbstractCegarLoop]: === Iteration 7 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-08 17:00:57,167 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 17:00:57,167 INFO L85 PathProgramCache]: Analyzing trace with hash -435430156, now seen corresponding path program 1 times [2024-11-08 17:00:57,168 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 17:00:57,168 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [910423739] [2024-11-08 17:00:57,169 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 17:00:57,169 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 17:00:57,442 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:00:58,928 INFO L368 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 21 [2024-11-08 17:00:58,930 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:00:58,933 INFO L368 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 36 [2024-11-08 17:00:58,936 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:00:58,942 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-11-08 17:00:58,942 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 17:00:58,943 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [910423739] [2024-11-08 17:00:58,943 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [910423739] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 17:00:58,943 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 17:00:58,943 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2024-11-08 17:00:58,944 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [360808102] [2024-11-08 17:00:58,944 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 17:00:58,945 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2024-11-08 17:00:58,945 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 17:00:58,946 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2024-11-08 17:00:58,947 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=35, Unknown=0, NotChecked=0, Total=56 [2024-11-08 17:00:58,947 INFO L87 Difference]: Start difference. First operand 281 states and 411 transitions. Second operand has 8 states, 8 states have (on average 15.125) internal successors, (121), 8 states have internal predecessors, (121), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2024-11-08 17:00:59,499 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 17:00:59,499 INFO L93 Difference]: Finished difference Result 663 states and 974 transitions. [2024-11-08 17:00:59,501 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2024-11-08 17:00:59,501 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 15.125) internal successors, (121), 8 states have internal predecessors, (121), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) Word has length 128 [2024-11-08 17:00:59,502 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-08 17:00:59,503 INFO L225 Difference]: With dead ends: 663 [2024-11-08 17:00:59,504 INFO L226 Difference]: Without dead ends: 404 [2024-11-08 17:00:59,506 INFO L431 NwaCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 6 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=26, Invalid=46, Unknown=0, NotChecked=0, Total=72 [2024-11-08 17:00:59,507 INFO L432 NwaCegarLoop]: 335 mSDtfsCounter, 978 mSDsluCounter, 1294 mSDsCounter, 0 mSdLazyCounter, 391 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 979 SdHoareTripleChecker+Valid, 1629 SdHoareTripleChecker+Invalid, 394 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 391 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.5s IncrementalHoareTripleChecker+Time [2024-11-08 17:00:59,508 INFO L433 NwaCegarLoop]: SdHoareTripleChecker [979 Valid, 1629 Invalid, 394 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 391 Invalid, 0 Unknown, 0 Unchecked, 0.5s Time] [2024-11-08 17:00:59,511 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 404 states. [2024-11-08 17:00:59,525 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 404 to 403. [2024-11-08 17:00:59,526 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 403 states, 399 states have (on average 1.4761904761904763) internal successors, (589), 399 states have internal predecessors, (589), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2024-11-08 17:00:59,529 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 403 states to 403 states and 593 transitions. [2024-11-08 17:00:59,529 INFO L78 Accepts]: Start accepts. Automaton has 403 states and 593 transitions. Word has length 128 [2024-11-08 17:00:59,554 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-08 17:00:59,554 INFO L471 AbstractCegarLoop]: Abstraction has 403 states and 593 transitions. [2024-11-08 17:00:59,555 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 15.125) internal successors, (121), 8 states have internal predecessors, (121), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2024-11-08 17:00:59,555 INFO L276 IsEmpty]: Start isEmpty. Operand 403 states and 593 transitions. [2024-11-08 17:00:59,558 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 130 [2024-11-08 17:00:59,558 INFO L207 NwaCegarLoop]: Found error trace [2024-11-08 17:00:59,558 INFO L215 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 17:00:59,559 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable6 [2024-11-08 17:00:59,559 INFO L396 AbstractCegarLoop]: === Iteration 8 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-08 17:00:59,560 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 17:00:59,560 INFO L85 PathProgramCache]: Analyzing trace with hash 1423192204, now seen corresponding path program 1 times [2024-11-08 17:00:59,561 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 17:00:59,561 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1657390919] [2024-11-08 17:00:59,561 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 17:00:59,562 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 17:00:59,977 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:01:00,754 INFO L368 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 21 [2024-11-08 17:01:00,755 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:01:00,757 INFO L368 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 36 [2024-11-08 17:01:00,758 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:01:00,761 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-11-08 17:01:00,761 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 17:01:00,761 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1657390919] [2024-11-08 17:01:00,761 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1657390919] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 17:01:00,762 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 17:01:00,762 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2024-11-08 17:01:00,762 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1661209447] [2024-11-08 17:01:00,762 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 17:01:00,763 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2024-11-08 17:01:00,763 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 17:01:00,764 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2024-11-08 17:01:00,764 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=38, Unknown=0, NotChecked=0, Total=56 [2024-11-08 17:01:00,765 INFO L87 Difference]: Start difference. First operand 403 states and 593 transitions. Second operand has 8 states, 8 states have (on average 15.25) internal successors, (122), 8 states have internal predecessors, (122), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2024-11-08 17:01:01,377 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 17:01:01,378 INFO L93 Difference]: Finished difference Result 792 states and 1166 transitions. [2024-11-08 17:01:01,379 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-11-08 17:01:01,379 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 15.25) internal successors, (122), 8 states have internal predecessors, (122), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) Word has length 129 [2024-11-08 17:01:01,379 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-08 17:01:01,381 INFO L225 Difference]: With dead ends: 792 [2024-11-08 17:01:01,382 INFO L226 Difference]: Without dead ends: 411 [2024-11-08 17:01:01,383 INFO L431 NwaCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 6 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=18, Invalid=38, Unknown=0, NotChecked=0, Total=56 [2024-11-08 17:01:01,384 INFO L432 NwaCegarLoop]: 331 mSDtfsCounter, 407 mSDsluCounter, 1615 mSDsCounter, 0 mSdLazyCounter, 472 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.5s Time, 0 mProtectedPredicate, 0 mProtectedAction, 409 SdHoareTripleChecker+Valid, 1946 SdHoareTripleChecker+Invalid, 475 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 472 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.6s IncrementalHoareTripleChecker+Time [2024-11-08 17:01:01,384 INFO L433 NwaCegarLoop]: SdHoareTripleChecker [409 Valid, 1946 Invalid, 475 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 472 Invalid, 0 Unknown, 0 Unchecked, 0.6s Time] [2024-11-08 17:01:01,386 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 411 states. [2024-11-08 17:01:01,397 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 411 to 408. [2024-11-08 17:01:01,398 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 408 states, 404 states have (on average 1.4727722772277227) internal successors, (595), 404 states have internal predecessors, (595), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2024-11-08 17:01:01,401 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 408 states to 408 states and 599 transitions. [2024-11-08 17:01:01,401 INFO L78 Accepts]: Start accepts. Automaton has 408 states and 599 transitions. Word has length 129 [2024-11-08 17:01:01,402 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-08 17:01:01,402 INFO L471 AbstractCegarLoop]: Abstraction has 408 states and 599 transitions. [2024-11-08 17:01:01,403 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 15.25) internal successors, (122), 8 states have internal predecessors, (122), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2024-11-08 17:01:01,403 INFO L276 IsEmpty]: Start isEmpty. Operand 408 states and 599 transitions. [2024-11-08 17:01:01,405 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 131 [2024-11-08 17:01:01,405 INFO L207 NwaCegarLoop]: Found error trace [2024-11-08 17:01:01,406 INFO L215 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 17:01:01,406 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable7 [2024-11-08 17:01:01,406 INFO L396 AbstractCegarLoop]: === Iteration 9 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-08 17:01:01,407 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 17:01:01,407 INFO L85 PathProgramCache]: Analyzing trace with hash -880780331, now seen corresponding path program 1 times [2024-11-08 17:01:01,408 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 17:01:01,408 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [300557830] [2024-11-08 17:01:01,408 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 17:01:01,408 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 17:01:01,664 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:01:02,826 INFO L368 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 21 [2024-11-08 17:01:02,829 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:01:02,833 INFO L368 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 37 [2024-11-08 17:01:02,835 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:01:02,837 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-11-08 17:01:02,837 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 17:01:02,838 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [300557830] [2024-11-08 17:01:02,838 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [300557830] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 17:01:02,838 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 17:01:02,838 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2024-11-08 17:01:02,839 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [106738772] [2024-11-08 17:01:02,839 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 17:01:02,839 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2024-11-08 17:01:02,840 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 17:01:02,840 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2024-11-08 17:01:02,841 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=38, Unknown=0, NotChecked=0, Total=56 [2024-11-08 17:01:02,841 INFO L87 Difference]: Start difference. First operand 408 states and 599 transitions. Second operand has 8 states, 8 states have (on average 15.375) internal successors, (123), 8 states have internal predecessors, (123), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2024-11-08 17:01:03,418 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 17:01:03,419 INFO L93 Difference]: Finished difference Result 797 states and 1170 transitions. [2024-11-08 17:01:03,419 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-11-08 17:01:03,419 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 15.375) internal successors, (123), 8 states have internal predecessors, (123), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) Word has length 130 [2024-11-08 17:01:03,420 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-08 17:01:03,422 INFO L225 Difference]: With dead ends: 797 [2024-11-08 17:01:03,422 INFO L226 Difference]: Without dead ends: 411 [2024-11-08 17:01:03,423 INFO L431 NwaCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 7 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=18, Invalid=38, Unknown=0, NotChecked=0, Total=56 [2024-11-08 17:01:03,424 INFO L432 NwaCegarLoop]: 332 mSDtfsCounter, 378 mSDsluCounter, 1644 mSDsCounter, 0 mSdLazyCounter, 466 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 379 SdHoareTripleChecker+Valid, 1976 SdHoareTripleChecker+Invalid, 467 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 466 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.5s IncrementalHoareTripleChecker+Time [2024-11-08 17:01:03,424 INFO L433 NwaCegarLoop]: SdHoareTripleChecker [379 Valid, 1976 Invalid, 467 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 466 Invalid, 0 Unknown, 0 Unchecked, 0.5s Time] [2024-11-08 17:01:03,425 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 411 states. [2024-11-08 17:01:03,441 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 411 to 409. [2024-11-08 17:01:03,445 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 409 states, 405 states have (on average 1.471604938271605) internal successors, (596), 405 states have internal predecessors, (596), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2024-11-08 17:01:03,447 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 409 states to 409 states and 600 transitions. [2024-11-08 17:01:03,450 INFO L78 Accepts]: Start accepts. Automaton has 409 states and 600 transitions. Word has length 130 [2024-11-08 17:01:03,451 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-08 17:01:03,451 INFO L471 AbstractCegarLoop]: Abstraction has 409 states and 600 transitions. [2024-11-08 17:01:03,452 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 15.375) internal successors, (123), 8 states have internal predecessors, (123), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2024-11-08 17:01:03,452 INFO L276 IsEmpty]: Start isEmpty. Operand 409 states and 600 transitions. [2024-11-08 17:01:03,454 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 131 [2024-11-08 17:01:03,454 INFO L207 NwaCegarLoop]: Found error trace [2024-11-08 17:01:03,455 INFO L215 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 17:01:03,455 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable8 [2024-11-08 17:01:03,455 INFO L396 AbstractCegarLoop]: === Iteration 10 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-08 17:01:03,456 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 17:01:03,456 INFO L85 PathProgramCache]: Analyzing trace with hash -1430939134, now seen corresponding path program 1 times [2024-11-08 17:01:03,456 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 17:01:03,456 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1917919373] [2024-11-08 17:01:03,457 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 17:01:03,457 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 17:01:03,560 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:01:03,911 INFO L368 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 21 [2024-11-08 17:01:03,912 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:01:03,915 INFO L368 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 37 [2024-11-08 17:01:03,916 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:01:03,920 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-11-08 17:01:03,920 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 17:01:03,921 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1917919373] [2024-11-08 17:01:03,921 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1917919373] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 17:01:03,921 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 17:01:03,921 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-08 17:01:03,921 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1967292114] [2024-11-08 17:01:03,922 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 17:01:03,922 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-08 17:01:03,922 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 17:01:03,923 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-08 17:01:03,923 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-08 17:01:03,924 INFO L87 Difference]: Start difference. First operand 409 states and 600 transitions. Second operand has 5 states, 5 states have (on average 24.6) internal successors, (123), 5 states have internal predecessors, (123), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2024-11-08 17:01:04,044 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 17:01:04,045 INFO L93 Difference]: Finished difference Result 1161 states and 1705 transitions. [2024-11-08 17:01:04,045 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-08 17:01:04,046 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 24.6) internal successors, (123), 5 states have internal predecessors, (123), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) Word has length 130 [2024-11-08 17:01:04,046 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-08 17:01:04,049 INFO L225 Difference]: With dead ends: 1161 [2024-11-08 17:01:04,050 INFO L226 Difference]: Without dead ends: 774 [2024-11-08 17:01:04,052 INFO L431 NwaCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 7 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2024-11-08 17:01:04,052 INFO L432 NwaCegarLoop]: 400 mSDtfsCounter, 334 mSDsluCounter, 1183 mSDsCounter, 0 mSdLazyCounter, 44 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 335 SdHoareTripleChecker+Valid, 1583 SdHoareTripleChecker+Invalid, 44 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 44 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-08 17:01:04,054 INFO L433 NwaCegarLoop]: SdHoareTripleChecker [335 Valid, 1583 Invalid, 44 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 44 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-08 17:01:04,055 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 774 states. [2024-11-08 17:01:04,070 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 774 to 425. [2024-11-08 17:01:04,074 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 425 states, 420 states have (on average 1.4666666666666666) internal successors, (616), 420 states have internal predecessors, (616), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-11-08 17:01:04,078 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 425 states to 425 states and 622 transitions. [2024-11-08 17:01:04,079 INFO L78 Accepts]: Start accepts. Automaton has 425 states and 622 transitions. Word has length 130 [2024-11-08 17:01:04,079 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-08 17:01:04,079 INFO L471 AbstractCegarLoop]: Abstraction has 425 states and 622 transitions. [2024-11-08 17:01:04,080 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 24.6) internal successors, (123), 5 states have internal predecessors, (123), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2024-11-08 17:01:04,080 INFO L276 IsEmpty]: Start isEmpty. Operand 425 states and 622 transitions. [2024-11-08 17:01:04,082 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 132 [2024-11-08 17:01:04,082 INFO L207 NwaCegarLoop]: Found error trace [2024-11-08 17:01:04,083 INFO L215 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 17:01:04,083 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable9 [2024-11-08 17:01:04,083 INFO L396 AbstractCegarLoop]: === Iteration 11 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-08 17:01:04,084 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 17:01:04,084 INFO L85 PathProgramCache]: Analyzing trace with hash -1557374353, now seen corresponding path program 1 times [2024-11-08 17:01:04,084 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 17:01:04,085 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2031431330] [2024-11-08 17:01:04,085 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 17:01:04,085 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 17:01:04,508 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:01:06,460 INFO L368 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 21 [2024-11-08 17:01:06,462 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:01:06,466 INFO L368 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 38 [2024-11-08 17:01:06,467 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:01:06,473 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-11-08 17:01:06,473 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 17:01:06,474 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2031431330] [2024-11-08 17:01:06,474 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2031431330] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 17:01:06,474 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 17:01:06,474 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2024-11-08 17:01:06,475 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1235199763] [2024-11-08 17:01:06,475 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 17:01:06,475 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 10 states [2024-11-08 17:01:06,476 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 17:01:06,476 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2024-11-08 17:01:06,478 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=71, Unknown=0, NotChecked=0, Total=90 [2024-11-08 17:01:06,479 INFO L87 Difference]: Start difference. First operand 425 states and 622 transitions. Second operand has 10 states, 10 states have (on average 12.4) internal successors, (124), 10 states have internal predecessors, (124), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2024-11-08 17:01:07,443 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 17:01:07,444 INFO L93 Difference]: Finished difference Result 1546 states and 2268 transitions. [2024-11-08 17:01:07,444 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2024-11-08 17:01:07,445 INFO L78 Accepts]: Start accepts. Automaton has has 10 states, 10 states have (on average 12.4) internal successors, (124), 10 states have internal predecessors, (124), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) Word has length 131 [2024-11-08 17:01:07,445 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-08 17:01:07,450 INFO L225 Difference]: With dead ends: 1546 [2024-11-08 17:01:07,451 INFO L226 Difference]: Without dead ends: 1143 [2024-11-08 17:01:07,452 INFO L431 NwaCegarLoop]: 0 DeclaredPredicates, 23 GetRequests, 8 SyntacticMatches, 0 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 19 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=67, Invalid=205, Unknown=0, NotChecked=0, Total=272 [2024-11-08 17:01:07,453 INFO L432 NwaCegarLoop]: 360 mSDtfsCounter, 2067 mSDsluCounter, 2261 mSDsCounter, 0 mSdLazyCounter, 521 mSolverCounterSat, 4 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.6s Time, 0 mProtectedPredicate, 0 mProtectedAction, 2069 SdHoareTripleChecker+Valid, 2621 SdHoareTripleChecker+Invalid, 525 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 4 IncrementalHoareTripleChecker+Valid, 521 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.7s IncrementalHoareTripleChecker+Time [2024-11-08 17:01:07,454 INFO L433 NwaCegarLoop]: SdHoareTripleChecker [2069 Valid, 2621 Invalid, 525 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [4 Valid, 521 Invalid, 0 Unknown, 0 Unchecked, 0.7s Time] [2024-11-08 17:01:07,456 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1143 states. [2024-11-08 17:01:07,478 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1143 to 763. [2024-11-08 17:01:07,480 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 763 states, 755 states have (on average 1.471523178807947) internal successors, (1111), 755 states have internal predecessors, (1111), 6 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2024-11-08 17:01:07,484 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 763 states to 763 states and 1123 transitions. [2024-11-08 17:01:07,485 INFO L78 Accepts]: Start accepts. Automaton has 763 states and 1123 transitions. Word has length 131 [2024-11-08 17:01:07,485 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-08 17:01:07,486 INFO L471 AbstractCegarLoop]: Abstraction has 763 states and 1123 transitions. [2024-11-08 17:01:07,486 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 10 states, 10 states have (on average 12.4) internal successors, (124), 10 states have internal predecessors, (124), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2024-11-08 17:01:07,486 INFO L276 IsEmpty]: Start isEmpty. Operand 763 states and 1123 transitions. [2024-11-08 17:01:07,489 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 133 [2024-11-08 17:01:07,489 INFO L207 NwaCegarLoop]: Found error trace [2024-11-08 17:01:07,490 INFO L215 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 17:01:07,490 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable10 [2024-11-08 17:01:07,490 INFO L396 AbstractCegarLoop]: === Iteration 12 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-08 17:01:07,491 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 17:01:07,491 INFO L85 PathProgramCache]: Analyzing trace with hash -1032179454, now seen corresponding path program 1 times [2024-11-08 17:01:07,491 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 17:01:07,491 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [186809024] [2024-11-08 17:01:07,492 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 17:01:07,492 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 17:01:07,788 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:01:08,208 INFO L368 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 21 [2024-11-08 17:01:08,210 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:01:08,238 INFO L368 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 38 [2024-11-08 17:01:08,239 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:01:08,241 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-11-08 17:01:08,242 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 17:01:08,242 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [186809024] [2024-11-08 17:01:08,242 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [186809024] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-08 17:01:08,242 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [122508959] [2024-11-08 17:01:08,243 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 17:01:08,243 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-08 17:01:08,243 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/z3 [2024-11-08 17:01:08,245 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-08 17:01:08,248 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2024-11-08 17:01:08,774 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:01:08,781 INFO L255 TraceCheckSpWp]: Trace formula consists of 699 conjuncts, 11 conjuncts are in the unsatisfiable core [2024-11-08 17:01:08,796 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-08 17:01:08,873 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 17:01:08,873 INFO L307 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-11-08 17:01:08,874 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [122508959] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 17:01:08,874 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-11-08 17:01:08,874 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [6] total 6 [2024-11-08 17:01:08,874 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [982273824] [2024-11-08 17:01:08,874 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 17:01:08,875 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-11-08 17:01:08,875 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 17:01:08,876 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-11-08 17:01:08,876 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2024-11-08 17:01:08,876 INFO L87 Difference]: Start difference. First operand 763 states and 1123 transitions. Second operand has 6 states, 5 states have (on average 25.6) internal successors, (128), 6 states have internal predecessors, (128), 2 states have call successors, (2), 2 states have call predecessors, (2), 2 states have return successors, (2), 1 states have call predecessors, (2), 2 states have call successors, (2) [2024-11-08 17:01:08,960 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 17:01:08,960 INFO L93 Difference]: Finished difference Result 1484 states and 2184 transitions. [2024-11-08 17:01:08,961 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-11-08 17:01:08,961 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 5 states have (on average 25.6) internal successors, (128), 6 states have internal predecessors, (128), 2 states have call successors, (2), 2 states have call predecessors, (2), 2 states have return successors, (2), 1 states have call predecessors, (2), 2 states have call successors, (2) Word has length 132 [2024-11-08 17:01:08,962 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-08 17:01:08,965 INFO L225 Difference]: With dead ends: 1484 [2024-11-08 17:01:08,965 INFO L226 Difference]: Without dead ends: 763 [2024-11-08 17:01:08,967 INFO L431 NwaCegarLoop]: 0 DeclaredPredicates, 140 GetRequests, 136 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2024-11-08 17:01:08,967 INFO L432 NwaCegarLoop]: 403 mSDtfsCounter, 0 mSDsluCounter, 1599 mSDsCounter, 0 mSdLazyCounter, 29 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 2002 SdHoareTripleChecker+Invalid, 29 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 29 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-08 17:01:08,968 INFO L433 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 2002 Invalid, 29 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 29 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-08 17:01:08,970 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 763 states. [2024-11-08 17:01:08,988 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 763 to 763. [2024-11-08 17:01:08,990 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 763 states, 755 states have (on average 1.466225165562914) internal successors, (1107), 755 states have internal predecessors, (1107), 6 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2024-11-08 17:01:08,994 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 763 states to 763 states and 1119 transitions. [2024-11-08 17:01:08,995 INFO L78 Accepts]: Start accepts. Automaton has 763 states and 1119 transitions. Word has length 132 [2024-11-08 17:01:08,995 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-08 17:01:08,995 INFO L471 AbstractCegarLoop]: Abstraction has 763 states and 1119 transitions. [2024-11-08 17:01:08,996 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 5 states have (on average 25.6) internal successors, (128), 6 states have internal predecessors, (128), 2 states have call successors, (2), 2 states have call predecessors, (2), 2 states have return successors, (2), 1 states have call predecessors, (2), 2 states have call successors, (2) [2024-11-08 17:01:08,996 INFO L276 IsEmpty]: Start isEmpty. Operand 763 states and 1119 transitions. [2024-11-08 17:01:08,998 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 134 [2024-11-08 17:01:08,999 INFO L207 NwaCegarLoop]: Found error trace [2024-11-08 17:01:08,999 INFO L215 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 17:01:09,030 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Forceful destruction successful, exit code 0 [2024-11-08 17:01:09,204 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable11,2 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-08 17:01:09,205 INFO L396 AbstractCegarLoop]: === Iteration 13 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-08 17:01:09,205 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 17:01:09,206 INFO L85 PathProgramCache]: Analyzing trace with hash -2018451176, now seen corresponding path program 1 times [2024-11-08 17:01:09,206 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 17:01:09,206 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1413778060] [2024-11-08 17:01:09,206 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 17:01:09,207 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 17:01:09,430 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:01:10,238 INFO L368 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 22 [2024-11-08 17:01:10,239 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:01:10,241 INFO L368 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 39 [2024-11-08 17:01:10,242 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:01:10,245 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-11-08 17:01:10,246 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 17:01:10,246 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1413778060] [2024-11-08 17:01:10,246 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1413778060] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 17:01:10,246 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 17:01:10,246 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2024-11-08 17:01:10,247 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [176303537] [2024-11-08 17:01:10,247 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 17:01:10,247 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2024-11-08 17:01:10,248 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 17:01:10,248 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2024-11-08 17:01:10,249 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=38, Unknown=0, NotChecked=0, Total=56 [2024-11-08 17:01:10,250 INFO L87 Difference]: Start difference. First operand 763 states and 1119 transitions. Second operand has 8 states, 8 states have (on average 15.75) internal successors, (126), 8 states have internal predecessors, (126), 1 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) [2024-11-08 17:01:10,888 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 17:01:10,888 INFO L93 Difference]: Finished difference Result 1525 states and 2235 transitions. [2024-11-08 17:01:10,889 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-11-08 17:01:10,889 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 15.75) internal successors, (126), 8 states have internal predecessors, (126), 1 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) Word has length 133 [2024-11-08 17:01:10,890 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-08 17:01:10,893 INFO L225 Difference]: With dead ends: 1525 [2024-11-08 17:01:10,894 INFO L226 Difference]: Without dead ends: 794 [2024-11-08 17:01:10,895 INFO L431 NwaCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 7 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=18, Invalid=38, Unknown=0, NotChecked=0, Total=56 [2024-11-08 17:01:10,896 INFO L432 NwaCegarLoop]: 337 mSDtfsCounter, 422 mSDsluCounter, 1664 mSDsCounter, 0 mSdLazyCounter, 434 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.5s Time, 0 mProtectedPredicate, 0 mProtectedAction, 424 SdHoareTripleChecker+Valid, 2001 SdHoareTripleChecker+Invalid, 436 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 434 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.6s IncrementalHoareTripleChecker+Time [2024-11-08 17:01:10,897 INFO L433 NwaCegarLoop]: SdHoareTripleChecker [424 Valid, 2001 Invalid, 436 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 434 Invalid, 0 Unknown, 0 Unchecked, 0.6s Time] [2024-11-08 17:01:10,898 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 794 states. [2024-11-08 17:01:10,921 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 794 to 794. [2024-11-08 17:01:10,923 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 794 states, 786 states have (on average 1.4631043256997456) internal successors, (1150), 786 states have internal predecessors, (1150), 6 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2024-11-08 17:01:10,927 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 794 states to 794 states and 1162 transitions. [2024-11-08 17:01:10,928 INFO L78 Accepts]: Start accepts. Automaton has 794 states and 1162 transitions. Word has length 133 [2024-11-08 17:01:10,928 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-08 17:01:10,929 INFO L471 AbstractCegarLoop]: Abstraction has 794 states and 1162 transitions. [2024-11-08 17:01:10,929 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 15.75) internal successors, (126), 8 states have internal predecessors, (126), 1 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) [2024-11-08 17:01:10,929 INFO L276 IsEmpty]: Start isEmpty. Operand 794 states and 1162 transitions. [2024-11-08 17:01:10,932 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 135 [2024-11-08 17:01:10,932 INFO L207 NwaCegarLoop]: Found error trace [2024-11-08 17:01:10,933 INFO L215 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 17:01:10,933 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable12 [2024-11-08 17:01:10,934 INFO L396 AbstractCegarLoop]: === Iteration 14 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-08 17:01:10,934 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 17:01:10,934 INFO L85 PathProgramCache]: Analyzing trace with hash 1786840969, now seen corresponding path program 1 times [2024-11-08 17:01:10,935 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 17:01:10,935 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [546047330] [2024-11-08 17:01:10,935 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 17:01:10,935 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 17:01:11,034 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:01:11,418 INFO L368 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 23 [2024-11-08 17:01:11,419 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:01:11,422 INFO L368 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 40 [2024-11-08 17:01:11,423 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:01:11,426 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-11-08 17:01:11,426 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 17:01:11,426 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [546047330] [2024-11-08 17:01:11,426 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [546047330] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 17:01:11,427 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 17:01:11,427 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-08 17:01:11,427 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1340238749] [2024-11-08 17:01:11,427 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 17:01:11,429 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-08 17:01:11,429 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 17:01:11,430 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-08 17:01:11,430 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-08 17:01:11,430 INFO L87 Difference]: Start difference. First operand 794 states and 1162 transitions. Second operand has 5 states, 5 states have (on average 25.4) internal successors, (127), 5 states have internal predecessors, (127), 1 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) [2024-11-08 17:01:11,496 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 17:01:11,496 INFO L93 Difference]: Finished difference Result 1519 states and 2225 transitions. [2024-11-08 17:01:11,497 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-08 17:01:11,497 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 25.4) internal successors, (127), 5 states have internal predecessors, (127), 1 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) Word has length 134 [2024-11-08 17:01:11,498 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-08 17:01:11,501 INFO L225 Difference]: With dead ends: 1519 [2024-11-08 17:01:11,501 INFO L226 Difference]: Without dead ends: 763 [2024-11-08 17:01:11,505 INFO L431 NwaCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 7 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-08 17:01:11,507 INFO L432 NwaCegarLoop]: 404 mSDtfsCounter, 24 mSDsluCounter, 1200 mSDsCounter, 0 mSdLazyCounter, 19 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 24 SdHoareTripleChecker+Valid, 1604 SdHoareTripleChecker+Invalid, 19 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 19 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-08 17:01:11,507 INFO L433 NwaCegarLoop]: SdHoareTripleChecker [24 Valid, 1604 Invalid, 19 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 19 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-08 17:01:11,509 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 763 states. [2024-11-08 17:01:11,530 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 763 to 763. [2024-11-08 17:01:11,531 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 763 states, 755 states have (on average 1.4649006622516556) internal successors, (1106), 755 states have internal predecessors, (1106), 6 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2024-11-08 17:01:11,538 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 763 states to 763 states and 1118 transitions. [2024-11-08 17:01:11,538 INFO L78 Accepts]: Start accepts. Automaton has 763 states and 1118 transitions. Word has length 134 [2024-11-08 17:01:11,538 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-08 17:01:11,539 INFO L471 AbstractCegarLoop]: Abstraction has 763 states and 1118 transitions. [2024-11-08 17:01:11,539 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 25.4) internal successors, (127), 5 states have internal predecessors, (127), 1 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) [2024-11-08 17:01:11,539 INFO L276 IsEmpty]: Start isEmpty. Operand 763 states and 1118 transitions. [2024-11-08 17:01:11,542 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 135 [2024-11-08 17:01:11,542 INFO L207 NwaCegarLoop]: Found error trace [2024-11-08 17:01:11,543 INFO L215 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 17:01:11,543 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable13 [2024-11-08 17:01:11,543 INFO L396 AbstractCegarLoop]: === Iteration 15 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-08 17:01:11,544 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 17:01:11,544 INFO L85 PathProgramCache]: Analyzing trace with hash -786920612, now seen corresponding path program 1 times [2024-11-08 17:01:11,544 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 17:01:11,544 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1560519816] [2024-11-08 17:01:11,545 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 17:01:11,545 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 17:01:11,905 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 17:01:11,905 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 17:01:12,261 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 17:01:12,382 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 17:01:12,383 INFO L325 BasicCegarLoop]: Counterexample is feasible [2024-11-08 17:01:12,384 INFO L782 garLoopResultBuilder]: Registering result UNSAFE for location ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION (0 of 1 remaining) [2024-11-08 17:01:12,387 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable14 [2024-11-08 17:01:12,392 INFO L407 BasicCegarLoop]: Path program histogram: [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 17:01:12,564 WARN L290 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2024-11-08 17:01:12,598 INFO L170 ceAbstractionStarter]: Computing trace abstraction results [2024-11-08 17:01:12,603 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 08.11 05:01:12 BoogieIcfgContainer [2024-11-08 17:01:12,605 INFO L131 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2024-11-08 17:01:12,605 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2024-11-08 17:01:12,606 INFO L270 PluginConnector]: Initializing Witness Printer... [2024-11-08 17:01:12,606 INFO L274 PluginConnector]: Witness Printer initialized [2024-11-08 17:01:12,607 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 08.11 05:00:50" (3/4) ... [2024-11-08 17:01:12,613 INFO L145 WitnessPrinter]: No result that supports witness generation found [2024-11-08 17:01:12,615 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2024-11-08 17:01:12,616 INFO L158 Benchmark]: Toolchain (without parser) took 25365.09ms. Allocated memory was 184.5MB in the beginning and 507.5MB in the end (delta: 323.0MB). Free memory was 141.5MB in the beginning and 235.3MB in the end (delta: -93.8MB). Peak memory consumption was 231.8MB. Max. memory is 16.1GB. [2024-11-08 17:01:12,616 INFO L158 Benchmark]: CDTParser took 0.37ms. Allocated memory is still 132.1MB. Free memory is still 77.8MB. There was no memory consumed. Max. memory is 16.1GB. [2024-11-08 17:01:12,616 INFO L158 Benchmark]: CACSL2BoogieTranslator took 761.37ms. Allocated memory is still 184.5MB. Free memory was 141.0MB in the beginning and 115.9MB in the end (delta: 25.2MB). Peak memory consumption was 25.2MB. Max. memory is 16.1GB. [2024-11-08 17:01:12,617 INFO L158 Benchmark]: Boogie Procedure Inliner took 161.41ms. Allocated memory is still 184.5MB. Free memory was 115.9MB in the beginning and 100.6MB in the end (delta: 15.2MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. [2024-11-08 17:01:12,617 INFO L158 Benchmark]: Boogie Preprocessor took 239.09ms. Allocated memory is still 184.5MB. Free memory was 100.6MB in the beginning and 90.7MB in the end (delta: 9.9MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2024-11-08 17:01:12,617 INFO L158 Benchmark]: RCFGBuilder took 2256.50ms. Allocated memory is still 184.5MB. Free memory was 90.7MB in the beginning and 104.8MB in the end (delta: -14.1MB). Peak memory consumption was 35.2MB. Max. memory is 16.1GB. [2024-11-08 17:01:12,618 INFO L158 Benchmark]: TraceAbstraction took 21928.79ms. Allocated memory was 184.5MB in the beginning and 507.5MB in the end (delta: 323.0MB). Free memory was 103.7MB in the beginning and 235.3MB in the end (delta: -131.6MB). Peak memory consumption was 192.4MB. Max. memory is 16.1GB. [2024-11-08 17:01:12,618 INFO L158 Benchmark]: Witness Printer took 9.52ms. Allocated memory is still 507.5MB. Free memory is still 235.3MB. There was no memory consumed. Max. memory is 16.1GB. [2024-11-08 17:01:12,622 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.37ms. Allocated memory is still 132.1MB. Free memory is still 77.8MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 761.37ms. Allocated memory is still 184.5MB. Free memory was 141.0MB in the beginning and 115.9MB in the end (delta: 25.2MB). Peak memory consumption was 25.2MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 161.41ms. Allocated memory is still 184.5MB. Free memory was 115.9MB in the beginning and 100.6MB in the end (delta: 15.2MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. * Boogie Preprocessor took 239.09ms. Allocated memory is still 184.5MB. Free memory was 100.6MB in the beginning and 90.7MB in the end (delta: 9.9MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * RCFGBuilder took 2256.50ms. Allocated memory is still 184.5MB. Free memory was 90.7MB in the beginning and 104.8MB in the end (delta: -14.1MB). Peak memory consumption was 35.2MB. Max. memory is 16.1GB. * TraceAbstraction took 21928.79ms. Allocated memory was 184.5MB in the beginning and 507.5MB in the end (delta: 323.0MB). Free memory was 103.7MB in the beginning and 235.3MB in the end (delta: -131.6MB). Peak memory consumption was 192.4MB. Max. memory is 16.1GB. * Witness Printer took 9.52ms. Allocated memory is still 507.5MB. Free memory is still 235.3MB. There was no memory consumed. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: ErrorAutomatonStatistics NumberErrorTraces: 0, NumberStatementsAllTraces: 0, NumberRelevantStatements: 0, 0.0s ErrorAutomatonConstructionTimeTotal, 0.0s FaulLocalizationTime, NumberStatementsFirstTrace: -1, TraceLengthAvg: 0, 0.0s ErrorAutomatonConstructionTimeAvg, 0.0s ErrorAutomatonDifferenceTimeAvg, 0.0s ErrorAutomatonDifferenceTimeTotal, NumberOfNoEnhancement: 0, NumberOfFiniteEnhancement: 0, NumberOfInfiniteEnhancement: 0 - UnprovableResult [Line: 21]: Unable to prove that a call to reach_error is unreachable Unable to prove that a call to reach_error is unreachable Reason: overapproximation of bitwiseAnd at line 296. Possible FailurePath: [L26] const SORT_1 mask_SORT_1 = (SORT_1)-1 >> (sizeof(SORT_1) * 8 - 1); [L27] const SORT_1 msb_SORT_1 = (SORT_1)1 << (1 - 1); [L29] const SORT_9 mask_SORT_9 = (SORT_9)-1 >> (sizeof(SORT_9) * 8 - 31); [L30] const SORT_9 msb_SORT_9 = (SORT_9)1 << (31 - 1); [L32] const SORT_11 mask_SORT_11 = (SORT_11)-1 >> (sizeof(SORT_11) * 8 - 16); [L33] const SORT_11 msb_SORT_11 = (SORT_11)1 << (16 - 1); [L35] const SORT_12 mask_SORT_12 = (SORT_12)-1 >> (sizeof(SORT_12) * 8 - 8); [L36] const SORT_12 msb_SORT_12 = (SORT_12)1 << (8 - 1); [L38] const SORT_20 mask_SORT_20 = (SORT_20)-1 >> (sizeof(SORT_20) * 8 - 32); [L39] const SORT_20 msb_SORT_20 = (SORT_20)1 << (32 - 1); [L41] const SORT_23 mask_SORT_23 = (SORT_23)-1 >> (sizeof(SORT_23) * 8 - 17); [L42] const SORT_23 msb_SORT_23 = (SORT_23)1 << (17 - 1); [L44] const SORT_26 mask_SORT_26 = (SORT_26)-1 >> (sizeof(SORT_26) * 8 - 18); [L45] const SORT_26 msb_SORT_26 = (SORT_26)1 << (18 - 1); [L47] const SORT_29 mask_SORT_29 = (SORT_29)-1 >> (sizeof(SORT_29) * 8 - 19); [L48] const SORT_29 msb_SORT_29 = (SORT_29)1 << (19 - 1); [L50] const SORT_32 mask_SORT_32 = (SORT_32)-1 >> (sizeof(SORT_32) * 8 - 20); [L51] const SORT_32 msb_SORT_32 = (SORT_32)1 << (20 - 1); [L53] const SORT_35 mask_SORT_35 = (SORT_35)-1 >> (sizeof(SORT_35) * 8 - 21); [L54] const SORT_35 msb_SORT_35 = (SORT_35)1 << (21 - 1); [L56] const SORT_38 mask_SORT_38 = (SORT_38)-1 >> (sizeof(SORT_38) * 8 - 22); [L57] const SORT_38 msb_SORT_38 = (SORT_38)1 << (22 - 1); [L59] const SORT_41 mask_SORT_41 = (SORT_41)-1 >> (sizeof(SORT_41) * 8 - 23); [L60] const SORT_41 msb_SORT_41 = (SORT_41)1 << (23 - 1); [L62] const SORT_44 mask_SORT_44 = (SORT_44)-1 >> (sizeof(SORT_44) * 8 - 24); [L63] const SORT_44 msb_SORT_44 = (SORT_44)1 << (24 - 1); [L65] const SORT_47 mask_SORT_47 = (SORT_47)-1 >> (sizeof(SORT_47) * 8 - 25); [L66] const SORT_47 msb_SORT_47 = (SORT_47)1 << (25 - 1); [L68] const SORT_50 mask_SORT_50 = (SORT_50)-1 >> (sizeof(SORT_50) * 8 - 26); [L69] const SORT_50 msb_SORT_50 = (SORT_50)1 << (26 - 1); [L71] const SORT_53 mask_SORT_53 = (SORT_53)-1 >> (sizeof(SORT_53) * 8 - 27); [L72] const SORT_53 msb_SORT_53 = (SORT_53)1 << (27 - 1); [L74] const SORT_56 mask_SORT_56 = (SORT_56)-1 >> (sizeof(SORT_56) * 8 - 28); [L75] const SORT_56 msb_SORT_56 = (SORT_56)1 << (28 - 1); [L77] const SORT_59 mask_SORT_59 = (SORT_59)-1 >> (sizeof(SORT_59) * 8 - 29); [L78] const SORT_59 msb_SORT_59 = (SORT_59)1 << (29 - 1); [L80] const SORT_62 mask_SORT_62 = (SORT_62)-1 >> (sizeof(SORT_62) * 8 - 30); [L81] const SORT_62 msb_SORT_62 = (SORT_62)1 << (30 - 1); [L83] const SORT_72 mask_SORT_72 = (SORT_72)-1 >> (sizeof(SORT_72) * 8 - 3); [L84] const SORT_72 msb_SORT_72 = (SORT_72)1 << (3 - 1); [L86] const SORT_96 mask_SORT_96 = (SORT_96)-1 >> (sizeof(SORT_96) * 8 - 4); [L87] const SORT_96 msb_SORT_96 = (SORT_96)1 << (4 - 1); [L89] const SORT_101 mask_SORT_101 = (SORT_101)-1 >> (sizeof(SORT_101) * 8 - 6); [L90] const SORT_101 msb_SORT_101 = (SORT_101)1 << (6 - 1); [L92] const SORT_1 var_7 = 0; [L93] const SORT_1 var_8 = 1; [L94] const SORT_9 var_10 = 0; [L95] const SORT_12 var_13 = 0; [L96] const SORT_12 var_14 = 200; [L97] const SORT_72 var_73 = 5; [L98] const SORT_11 var_75 = 0; [L99] const SORT_11 var_108 = 200; [L100] const SORT_72 var_113 = 4; [L101] const SORT_72 var_116 = 6; [L102] const SORT_96 var_120 = 9; [L103] const SORT_72 var_137 = 0; [L104] const SORT_96 var_140 = 0; [L106] SORT_1 input_2; [L107] SORT_1 input_3; [L108] SORT_1 input_4; [L110] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_73=5, var_75=0, var_7=0, var_8=1] [L110] SORT_1 state_5 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L111] EXPR __VERIFIER_nondet_ushort() & mask_SORT_11 VAL [mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_5=1, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_73=5, var_75=0, var_7=0, var_8=1] [L111] SORT_11 state_17 = __VERIFIER_nondet_ushort() & mask_SORT_11; [L112] EXPR __VERIFIER_nondet_ushort() & mask_SORT_11 VAL [mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_17=0, state_5=1, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_73=5, var_75=0, var_7=0, var_8=1] [L112] SORT_11 state_76 = __VERIFIER_nondet_ushort() & mask_SORT_11; [L113] EXPR __VERIFIER_nondet_uchar() & mask_SORT_96 VAL [mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_17=0, state_5=1, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_73=5, var_75=0, var_7=0, var_8=1] [L113] SORT_96 state_97 = __VERIFIER_nondet_uchar() & mask_SORT_96; [L114] EXPR __VERIFIER_nondet_uchar() & mask_SORT_96 VAL [mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_17=0, state_5=1, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_73=5, var_75=0, var_7=0, var_8=1] [L114] SORT_96 state_100 = __VERIFIER_nondet_uchar() & mask_SORT_96; [L116] SORT_11 init_77_arg_1 = var_75; [L117] state_76 = init_77_arg_1 VAL [mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_5=1, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_73=5, var_75=0, var_7=0, var_8=1] [L120] input_2 = __VERIFIER_nondet_uchar() [L121] input_3 = __VERIFIER_nondet_uchar() [L122] EXPR input_3 & mask_SORT_1 VAL [mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_5=1, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_73=5, var_75=0, var_7=0, var_8=1] [L122] input_3 = input_3 & mask_SORT_1 [L123] input_4 = __VERIFIER_nondet_uchar() [L124] EXPR input_4 & mask_SORT_1 VAL [input_3=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_5=1, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_73=5, var_75=0, var_7=0, var_8=1] [L124] input_4 = input_4 & mask_SORT_1 [L126] SORT_1 var_84_arg_0 = state_5; [L127] SORT_1 var_84 = ~var_84_arg_0; [L128] SORT_1 var_85_arg_0 = var_84; [L129] SORT_1 var_85 = ~var_85_arg_0; [L130] SORT_1 var_86_arg_0 = state_5; [L131] SORT_1 var_86_arg_1 = var_85; VAL [input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_73=5, var_75=0, var_7=0, var_86_arg_0=1, var_86_arg_1=-255, var_8=1] [L132] EXPR var_86_arg_0 | var_86_arg_1 VAL [input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_73=5, var_75=0, var_7=0, var_8=1] [L132] SORT_1 var_86 = var_86_arg_0 | var_86_arg_1; [L133] EXPR var_86 & mask_SORT_1 VAL [input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_73=5, var_75=0, var_7=0, var_8=1] [L133] var_86 = var_86 & mask_SORT_1 [L134] SORT_1 constr_87_arg_0 = var_86; VAL [constr_87_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_73=5, var_75=0, var_7=0, var_8=1] [L135] CALL assume_abort_if_not(constr_87_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L135] RET assume_abort_if_not(constr_87_arg_0) VAL [constr_87_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_73=5, var_75=0, var_7=0, var_8=1] [L136] SORT_1 var_88_arg_0 = var_8; VAL [constr_87_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_73=5, var_75=0, var_7=0, var_88_arg_0=1, var_8=1] [L137] EXPR var_88_arg_0 & mask_SORT_1 VAL [constr_87_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_73=5, var_75=0, var_7=0, var_8=1] [L137] var_88_arg_0 = var_88_arg_0 & mask_SORT_1 [L138] SORT_11 var_88 = var_88_arg_0; [L139] SORT_11 var_89_arg_0 = state_76; [L140] SORT_11 var_89_arg_1 = var_88; [L141] SORT_1 var_89 = var_89_arg_0 <= var_89_arg_1; [L142] SORT_1 var_90_arg_0 = input_4; [L143] SORT_1 var_90_arg_1 = var_89; VAL [constr_87_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_73=5, var_75=0, var_7=0, var_8=1, var_90_arg_0=0, var_90_arg_1=1] [L144] EXPR var_90_arg_0 ^ var_90_arg_1 VAL [constr_87_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_73=5, var_75=0, var_7=0, var_8=1] [L144] SORT_1 var_90 = var_90_arg_0 ^ var_90_arg_1; [L145] SORT_1 var_91_arg_0 = var_90; [L146] SORT_1 var_91 = ~var_91_arg_0; [L147] SORT_1 var_92_arg_0 = var_90; [L148] SORT_1 var_92 = ~var_92_arg_0; [L149] SORT_1 var_93_arg_0 = var_91; [L150] SORT_1 var_93_arg_1 = var_92; VAL [constr_87_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_73=5, var_75=0, var_7=0, var_8=1, var_93_arg_0=-2, var_93_arg_1=-2] [L151] EXPR var_93_arg_0 | var_93_arg_1 VAL [constr_87_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_73=5, var_75=0, var_7=0, var_8=1] [L151] SORT_1 var_93 = var_93_arg_0 | var_93_arg_1; [L152] EXPR var_93 & mask_SORT_1 VAL [constr_87_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_73=5, var_75=0, var_7=0, var_8=1] [L152] var_93 = var_93 & mask_SORT_1 [L153] SORT_1 constr_94_arg_0 = var_93; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_73=5, var_75=0, var_7=0, var_8=1] [L154] CALL assume_abort_if_not(constr_94_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L154] RET assume_abort_if_not(constr_94_arg_0) VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_73=5, var_75=0, var_7=0, var_8=1] [L156] SORT_72 var_74_arg_0 = var_73; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_73=5, var_74_arg_0=5, var_75=0, var_7=0, var_8=1] [L157] EXPR var_74_arg_0 & mask_SORT_72 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_73=5, var_75=0, var_7=0, var_8=1] [L157] var_74_arg_0 = var_74_arg_0 & mask_SORT_72 [L158] SORT_11 var_74 = var_74_arg_0; [L159] SORT_11 var_78_arg_0 = var_74; [L160] SORT_11 var_78_arg_1 = state_76; [L161] SORT_1 var_78 = var_78_arg_0 < var_78_arg_1; [L162] SORT_1 var_15_arg_0 = input_3; [L163] SORT_12 var_15_arg_1 = var_14; [L164] SORT_12 var_15_arg_2 = var_13; [L165] SORT_12 var_15 = var_15_arg_0 ? var_15_arg_1 : var_15_arg_2; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_15=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L166] EXPR var_15 & mask_SORT_12 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L166] var_15 = var_15 & mask_SORT_12 [L167] SORT_12 var_16_arg_0 = var_13; [L168] SORT_12 var_16_arg_1 = var_15; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_16_arg_0=0, var_16_arg_1=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L169] EXPR ((SORT_11)var_16_arg_0 << 8) | var_16_arg_1 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L169] SORT_11 var_16 = ((SORT_11)var_16_arg_0 << 8) | var_16_arg_1; [L170] SORT_11 var_18_arg_0 = var_16; [L171] SORT_11 var_18_arg_1 = state_17; [L172] SORT_11 var_18 = var_18_arg_0 - var_18_arg_1; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_18=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L173] EXPR var_18 & mask_SORT_11 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L173] var_18 = var_18 & mask_SORT_11 [L174] SORT_11 var_19_arg_0 = var_18; [L175] SORT_1 var_19 = var_19_arg_0 >> 15; [L176] SORT_1 var_21_arg_0 = var_19; [L177] SORT_9 var_21_arg_1 = var_10; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_18=0, var_21_arg_0=0, var_21_arg_1=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L178] EXPR ((SORT_20)var_21_arg_0 << 31) | var_21_arg_1 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_18=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L178] SORT_20 var_21 = ((SORT_20)var_21_arg_0 << 31) | var_21_arg_1; [L179] EXPR var_21 & mask_SORT_20 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_18=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L179] var_21 = var_21 & mask_SORT_20 [L180] SORT_11 var_64_arg_0 = var_18; [L181] SORT_1 var_64 = var_64_arg_0 >> 15; [L182] SORT_11 var_61_arg_0 = var_18; [L183] SORT_1 var_61 = var_61_arg_0 >> 15; [L184] SORT_11 var_58_arg_0 = var_18; [L185] SORT_1 var_58 = var_58_arg_0 >> 15; [L186] SORT_11 var_55_arg_0 = var_18; [L187] SORT_1 var_55 = var_55_arg_0 >> 15; [L188] SORT_11 var_52_arg_0 = var_18; [L189] SORT_1 var_52 = var_52_arg_0 >> 15; [L190] SORT_11 var_49_arg_0 = var_18; [L191] SORT_1 var_49 = var_49_arg_0 >> 15; [L192] SORT_11 var_46_arg_0 = var_18; [L193] SORT_1 var_46 = var_46_arg_0 >> 15; [L194] SORT_11 var_43_arg_0 = var_18; [L195] SORT_1 var_43 = var_43_arg_0 >> 15; [L196] SORT_11 var_40_arg_0 = var_18; [L197] SORT_1 var_40 = var_40_arg_0 >> 15; [L198] SORT_11 var_37_arg_0 = var_18; [L199] SORT_1 var_37 = var_37_arg_0 >> 15; [L200] SORT_11 var_34_arg_0 = var_18; [L201] SORT_1 var_34 = var_34_arg_0 >> 15; [L202] SORT_11 var_31_arg_0 = var_18; [L203] SORT_1 var_31 = var_31_arg_0 >> 15; [L204] SORT_11 var_28_arg_0 = var_18; [L205] SORT_1 var_28 = var_28_arg_0 >> 15; [L206] SORT_11 var_25_arg_0 = var_18; [L207] SORT_1 var_25 = var_25_arg_0 >> 15; [L208] SORT_11 var_22_arg_0 = var_18; [L209] SORT_1 var_22 = var_22_arg_0 >> 15; [L210] SORT_1 var_24_arg_0 = var_22; [L211] SORT_11 var_24_arg_1 = var_18; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_24_arg_0=0, var_24_arg_1=0, var_25=0, var_28=0, var_31=0, var_34=0, var_37=0, var_40=0, var_43=0, var_46=0, var_49=0, var_52=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L212] EXPR ((SORT_23)var_24_arg_0 << 16) | var_24_arg_1 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_25=0, var_28=0, var_31=0, var_34=0, var_37=0, var_40=0, var_43=0, var_46=0, var_49=0, var_52=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L212] SORT_23 var_24 = ((SORT_23)var_24_arg_0 << 16) | var_24_arg_1; [L213] EXPR var_24 & mask_SORT_23 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_25=0, var_28=0, var_31=0, var_34=0, var_37=0, var_40=0, var_43=0, var_46=0, var_49=0, var_52=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L213] var_24 = var_24 & mask_SORT_23 [L214] SORT_1 var_27_arg_0 = var_25; [L215] SORT_23 var_27_arg_1 = var_24; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_27_arg_0=0, var_27_arg_1=0, var_28=0, var_31=0, var_34=0, var_37=0, var_40=0, var_43=0, var_46=0, var_49=0, var_52=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L216] EXPR ((SORT_26)var_27_arg_0 << 17) | var_27_arg_1 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_28=0, var_31=0, var_34=0, var_37=0, var_40=0, var_43=0, var_46=0, var_49=0, var_52=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L216] SORT_26 var_27 = ((SORT_26)var_27_arg_0 << 17) | var_27_arg_1; [L217] EXPR var_27 & mask_SORT_26 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_28=0, var_31=0, var_34=0, var_37=0, var_40=0, var_43=0, var_46=0, var_49=0, var_52=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L217] var_27 = var_27 & mask_SORT_26 [L218] SORT_1 var_30_arg_0 = var_28; [L219] SORT_26 var_30_arg_1 = var_27; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_30_arg_0=0, var_30_arg_1=0, var_31=0, var_34=0, var_37=0, var_40=0, var_43=0, var_46=0, var_49=0, var_52=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L220] EXPR ((SORT_29)var_30_arg_0 << 18) | var_30_arg_1 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_31=0, var_34=0, var_37=0, var_40=0, var_43=0, var_46=0, var_49=0, var_52=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L220] SORT_29 var_30 = ((SORT_29)var_30_arg_0 << 18) | var_30_arg_1; [L221] EXPR var_30 & mask_SORT_29 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_31=0, var_34=0, var_37=0, var_40=0, var_43=0, var_46=0, var_49=0, var_52=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L221] var_30 = var_30 & mask_SORT_29 [L222] SORT_1 var_33_arg_0 = var_31; [L223] SORT_29 var_33_arg_1 = var_30; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_33_arg_0=0, var_33_arg_1=0, var_34=0, var_37=0, var_40=0, var_43=0, var_46=0, var_49=0, var_52=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L224] EXPR ((SORT_32)var_33_arg_0 << 19) | var_33_arg_1 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_34=0, var_37=0, var_40=0, var_43=0, var_46=0, var_49=0, var_52=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L224] SORT_32 var_33 = ((SORT_32)var_33_arg_0 << 19) | var_33_arg_1; [L225] EXPR var_33 & mask_SORT_32 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_34=0, var_37=0, var_40=0, var_43=0, var_46=0, var_49=0, var_52=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L225] var_33 = var_33 & mask_SORT_32 [L226] SORT_1 var_36_arg_0 = var_34; [L227] SORT_32 var_36_arg_1 = var_33; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_36_arg_0=0, var_36_arg_1=0, var_37=0, var_40=0, var_43=0, var_46=0, var_49=0, var_52=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L228] EXPR ((SORT_35)var_36_arg_0 << 20) | var_36_arg_1 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_37=0, var_40=0, var_43=0, var_46=0, var_49=0, var_52=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L228] SORT_35 var_36 = ((SORT_35)var_36_arg_0 << 20) | var_36_arg_1; [L229] EXPR var_36 & mask_SORT_35 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_37=0, var_40=0, var_43=0, var_46=0, var_49=0, var_52=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L229] var_36 = var_36 & mask_SORT_35 [L230] SORT_1 var_39_arg_0 = var_37; [L231] SORT_35 var_39_arg_1 = var_36; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_39_arg_0=0, var_39_arg_1=0, var_40=0, var_43=0, var_46=0, var_49=0, var_52=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L232] EXPR ((SORT_38)var_39_arg_0 << 21) | var_39_arg_1 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_40=0, var_43=0, var_46=0, var_49=0, var_52=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L232] SORT_38 var_39 = ((SORT_38)var_39_arg_0 << 21) | var_39_arg_1; [L233] EXPR var_39 & mask_SORT_38 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_40=0, var_43=0, var_46=0, var_49=0, var_52=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L233] var_39 = var_39 & mask_SORT_38 [L234] SORT_1 var_42_arg_0 = var_40; [L235] SORT_38 var_42_arg_1 = var_39; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_42_arg_0=0, var_42_arg_1=0, var_43=0, var_46=0, var_49=0, var_52=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L236] EXPR ((SORT_41)var_42_arg_0 << 22) | var_42_arg_1 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_43=0, var_46=0, var_49=0, var_52=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L236] SORT_41 var_42 = ((SORT_41)var_42_arg_0 << 22) | var_42_arg_1; [L237] EXPR var_42 & mask_SORT_41 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_43=0, var_46=0, var_49=0, var_52=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L237] var_42 = var_42 & mask_SORT_41 [L238] SORT_1 var_45_arg_0 = var_43; [L239] SORT_41 var_45_arg_1 = var_42; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_45_arg_0=0, var_45_arg_1=0, var_46=0, var_49=0, var_52=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L240] EXPR ((SORT_44)var_45_arg_0 << 23) | var_45_arg_1 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_46=0, var_49=0, var_52=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L240] SORT_44 var_45 = ((SORT_44)var_45_arg_0 << 23) | var_45_arg_1; [L241] EXPR var_45 & mask_SORT_44 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_46=0, var_49=0, var_52=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L241] var_45 = var_45 & mask_SORT_44 [L242] SORT_1 var_48_arg_0 = var_46; [L243] SORT_44 var_48_arg_1 = var_45; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_48_arg_0=0, var_48_arg_1=0, var_49=0, var_52=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L244] EXPR ((SORT_47)var_48_arg_0 << 24) | var_48_arg_1 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_49=0, var_52=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L244] SORT_47 var_48 = ((SORT_47)var_48_arg_0 << 24) | var_48_arg_1; [L245] EXPR var_48 & mask_SORT_47 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_49=0, var_52=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L245] var_48 = var_48 & mask_SORT_47 [L246] SORT_1 var_51_arg_0 = var_49; [L247] SORT_47 var_51_arg_1 = var_48; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_51_arg_0=0, var_51_arg_1=0, var_52=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L248] EXPR ((SORT_50)var_51_arg_0 << 25) | var_51_arg_1 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_52=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L248] SORT_50 var_51 = ((SORT_50)var_51_arg_0 << 25) | var_51_arg_1; [L249] EXPR var_51 & mask_SORT_50 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_52=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L249] var_51 = var_51 & mask_SORT_50 [L250] SORT_1 var_54_arg_0 = var_52; [L251] SORT_50 var_54_arg_1 = var_51; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_54_arg_0=0, var_54_arg_1=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L252] EXPR ((SORT_53)var_54_arg_0 << 26) | var_54_arg_1 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L252] SORT_53 var_54 = ((SORT_53)var_54_arg_0 << 26) | var_54_arg_1; [L253] EXPR var_54 & mask_SORT_53 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_55=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L253] var_54 = var_54 & mask_SORT_53 [L254] SORT_1 var_57_arg_0 = var_55; [L255] SORT_53 var_57_arg_1 = var_54; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_57_arg_0=0, var_57_arg_1=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L256] EXPR ((SORT_56)var_57_arg_0 << 27) | var_57_arg_1 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L256] SORT_56 var_57 = ((SORT_56)var_57_arg_0 << 27) | var_57_arg_1; [L257] EXPR var_57 & mask_SORT_56 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_58=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L257] var_57 = var_57 & mask_SORT_56 [L258] SORT_1 var_60_arg_0 = var_58; [L259] SORT_56 var_60_arg_1 = var_57; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_60_arg_0=0, var_60_arg_1=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L260] EXPR ((SORT_59)var_60_arg_0 << 28) | var_60_arg_1 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L260] SORT_59 var_60 = ((SORT_59)var_60_arg_0 << 28) | var_60_arg_1; [L261] EXPR var_60 & mask_SORT_59 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_61=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L261] var_60 = var_60 & mask_SORT_59 [L262] SORT_1 var_63_arg_0 = var_61; [L263] SORT_59 var_63_arg_1 = var_60; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_63_arg_0=0, var_63_arg_1=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L264] EXPR ((SORT_62)var_63_arg_0 << 29) | var_63_arg_1 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L264] SORT_62 var_63 = ((SORT_62)var_63_arg_0 << 29) | var_63_arg_1; [L265] EXPR var_63 & mask_SORT_62 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_64=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L265] var_63 = var_63 & mask_SORT_62 [L266] SORT_1 var_65_arg_0 = var_64; [L267] SORT_62 var_65_arg_1 = var_63; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_65_arg_0=0, var_65_arg_1=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L268] EXPR ((SORT_9)var_65_arg_0 << 30) | var_65_arg_1 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L268] SORT_9 var_65 = ((SORT_9)var_65_arg_0 << 30) | var_65_arg_1; [L269] SORT_9 var_66_arg_0 = var_65; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_66_arg_0=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L270] EXPR var_66_arg_0 & mask_SORT_9 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_21=0, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L270] var_66_arg_0 = var_66_arg_0 & mask_SORT_9 [L271] SORT_20 var_66 = var_66_arg_0; [L272] SORT_20 var_67_arg_0 = var_21; [L273] SORT_20 var_67_arg_1 = var_66; [L274] SORT_1 var_67 = var_67_arg_0 <= var_67_arg_1; [L275] SORT_1 var_68_arg_0 = var_67; [L276] SORT_1 var_68_arg_1 = var_8; [L277] SORT_1 var_68_arg_2 = var_7; [L278] SORT_1 var_68 = var_68_arg_0 ? var_68_arg_1 : var_68_arg_2; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_68=1, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L279] EXPR var_68 & mask_SORT_1 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L279] var_68 = var_68 & mask_SORT_1 [L280] SORT_1 var_69_arg_0 = input_3; [L281] SORT_1 var_69_arg_1 = var_68; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_68=1, var_69_arg_0=0, var_69_arg_1=1, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L282] EXPR var_69_arg_0 ^ var_69_arg_1 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_68=1, var_73=5, var_75=0, var_78=0, var_7=0, var_8=1] [L282] SORT_1 var_69 = var_69_arg_0 ^ var_69_arg_1; [L283] SORT_1 var_70_arg_0 = var_69; [L284] SORT_1 var_70 = ~var_70_arg_0; [L285] SORT_1 var_79_arg_0 = var_78; [L286] SORT_1 var_79_arg_1 = var_70; [L287] SORT_1 var_79_arg_2 = var_8; [L288] SORT_1 var_79 = var_79_arg_0 ? var_79_arg_1 : var_79_arg_2; [L289] SORT_1 var_80_arg_0 = var_79; [L290] SORT_1 var_80 = ~var_80_arg_0; [L291] SORT_1 var_81_arg_0 = var_79; [L292] SORT_1 var_81 = ~var_81_arg_0; [L293] SORT_1 var_82_arg_0 = var_80; [L294] SORT_1 var_82_arg_1 = var_81; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_68=1, var_73=5, var_75=0, var_7=0, var_82_arg_0=-2, var_82_arg_1=-2, var_8=1] [L295] EXPR var_82_arg_0 & var_82_arg_1 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_68=1, var_73=5, var_75=0, var_7=0, var_8=1] [L295] SORT_1 var_82 = var_82_arg_0 & var_82_arg_1; [L296] EXPR var_82 & mask_SORT_1 VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=65535, mask_SORT_12=255, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=0, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=200, var_68=1, var_73=5, var_75=0, var_7=0, var_8=1] [L296] var_82 = var_82 & mask_SORT_1 [L297] SORT_1 bad_83_arg_0 = var_82; [L298] CALL __VERIFIER_assert(!(bad_83_arg_0)) [L21] COND TRUE !(cond) [L21] reach_error() - StatisticsResult: Ultimate Automizer benchmark data CFG has 2 procedures, 281 locations, 1 error locations. Started 1 CEGAR loops. OverallTime: 21.6s, OverallIterations: 15, TraceHistogramMax: 2, PathProgramHistogramMax: 1, EmptinessCheckTime: 0.1s, AutomataDifference: 4.7s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, InitialAbstractionConstructionTime: 0.0s, HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 5997 SdHoareTripleChecker+Valid, 3.5s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 5987 mSDsluCounter, 21491 SdHoareTripleChecker+Invalid, 2.9s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 15892 mSDsCounter, 25 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 2595 IncrementalHoareTripleChecker+Invalid, 2620 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 25 mSolverCounterUnsat, 5599 mSDtfsCounter, 2595 mSolverCounterSat, 0.2s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown, PredicateUnifierStatistics: 0 DeclaredPredicates, 290 GetRequests, 223 SyntacticMatches, 0 SemanticMatches, 67 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 25 ImplicationChecksByTransitivity, 0.9s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=794occurred in iteration=13, InterpolantAutomatonStates: 81, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 0.4s AutomataMinimizationTime, 14 MinimizatonAttempts, 735 StatesRemovedByMinimization, 5 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.3s SsaConstructionTime, 3.1s SatisfiabilityAnalysisTime, 11.2s InterpolantComputationTime, 2061 NumberOfCodeBlocks, 2061 NumberOfCodeBlocksAsserted, 16 NumberOfCheckSat, 1912 ConstructedInterpolants, 0 QuantifiedInterpolants, 5428 SizeOfPredicates, 0 NumberOfNonLiveVariables, 699 ConjunctsInSsa, 11 ConjunctsInUnsatCore, 15 InterpolantComputations, 14 PerfectInterpolantSequences, 57/60 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, ACCELERATED_INTERPOLATION: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate could not prove your program: unable to determine feasibility of some traces [2024-11-08 17:01:12,735 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Using bit-precise analysis Retrying with bit-precise analysis ### Bit-precise run ### Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/config/AutomizerReach.xml -i ../../sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.unsafe_analog_estimation_convergence.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/config/svcomp-Reach-64bit-Automizer_Bitvector.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(reach_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash 37235873cdbfb4a92a6d9a366e7d975c617138dc8eee2f80d6fd06796710e280 --- Real Ultimate output --- This is Ultimate 0.2.5-dev-a016563 [2024-11-08 17:01:15,755 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-08 17:01:15,880 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/config/svcomp-Reach-64bit-Automizer_Bitvector.epf [2024-11-08 17:01:15,889 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-08 17:01:15,890 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-08 17:01:15,935 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-08 17:01:15,938 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-08 17:01:15,939 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-08 17:01:15,940 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-08 17:01:15,941 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-08 17:01:15,941 INFO L151 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2024-11-08 17:01:15,942 INFO L153 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2024-11-08 17:01:15,943 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-08 17:01:15,944 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-08 17:01:15,946 INFO L153 SettingsManager]: * Use SBE=true [2024-11-08 17:01:15,947 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-08 17:01:15,948 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2024-11-08 17:01:15,948 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-08 17:01:15,948 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2024-11-08 17:01:15,949 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2024-11-08 17:01:15,949 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2024-11-08 17:01:15,954 INFO L153 SettingsManager]: * Adapt memory model on pointer casts if necessary=true [2024-11-08 17:01:15,954 INFO L153 SettingsManager]: * Use bitvectors instead of ints=true [2024-11-08 17:01:15,955 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-11-08 17:01:15,955 INFO L153 SettingsManager]: * Memory model=HoenickeLindenmann_4ByteResolution [2024-11-08 17:01:15,955 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-08 17:01:15,956 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-08 17:01:15,956 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-11-08 17:01:15,957 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-08 17:01:15,957 INFO L153 SettingsManager]: * Only consider context switches at boundaries of atomic blocks=true [2024-11-08 17:01:15,959 INFO L153 SettingsManager]: * SMT solver=External_DefaultMode [2024-11-08 17:01:15,960 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 [2024-11-08 17:01:15,962 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-08 17:01:15,962 INFO L153 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2024-11-08 17:01:15,962 INFO L153 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopHeads [2024-11-08 17:01:15,963 INFO L153 SettingsManager]: * Trace refinement strategy=FOX [2024-11-08 17:01:15,963 INFO L153 SettingsManager]: * Command for external solver=cvc4 --incremental --print-success --lang smt [2024-11-08 17:01:15,964 INFO L153 SettingsManager]: * Apply one-shot large block encoding in concurrent analysis=false [2024-11-08 17:01:15,964 INFO L153 SettingsManager]: * Automaton type used in concurrency analysis=PETRI_NET [2024-11-08 17:01:15,965 INFO L153 SettingsManager]: * Order on configurations for Petri net unfoldings=DBO [2024-11-08 17:01:15,965 INFO L153 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2024-11-08 17:01:15,966 INFO L153 SettingsManager]: * Looper check in Petri net analysis=SEMANTIC WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(reach_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 37235873cdbfb4a92a6d9a366e7d975c617138dc8eee2f80d6fd06796710e280 [2024-11-08 17:01:16,520 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-08 17:01:16,566 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-08 17:01:16,571 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-08 17:01:16,573 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-08 17:01:16,573 INFO L274 PluginConnector]: CDTParser initialized [2024-11-08 17:01:16,575 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/../../sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.unsafe_analog_estimation_convergence.c Unable to find full path for "g++" [2024-11-08 17:01:19,191 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-11-08 17:01:19,615 INFO L384 CDTParser]: Found 1 translation units. [2024-11-08 17:01:19,615 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.unsafe_analog_estimation_convergence.c [2024-11-08 17:01:19,634 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/data/16d3f03a5/be681beb93f148bf8bc679caddfde918/FLAG65215e5a9 [2024-11-08 17:01:19,660 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/data/16d3f03a5/be681beb93f148bf8bc679caddfde918 [2024-11-08 17:01:19,664 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-08 17:01:19,668 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-08 17:01:19,669 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-08 17:01:19,671 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-08 17:01:19,679 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-08 17:01:19,680 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 08.11 05:01:19" (1/1) ... [2024-11-08 17:01:19,682 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@501b5c66 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 05:01:19, skipping insertion in model container [2024-11-08 17:01:19,683 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 08.11 05:01:19" (1/1) ... [2024-11-08 17:01:19,750 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-08 17:01:20,029 WARN L250 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.unsafe_analog_estimation_convergence.c[1289,1302] [2024-11-08 17:01:20,280 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-08 17:01:20,311 INFO L200 MainTranslator]: Completed pre-run [2024-11-08 17:01:20,352 WARN L250 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.unsafe_analog_estimation_convergence.c[1289,1302] [2024-11-08 17:01:20,501 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-08 17:01:20,524 INFO L204 MainTranslator]: Completed translation [2024-11-08 17:01:20,525 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 05:01:20 WrapperNode [2024-11-08 17:01:20,525 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-08 17:01:20,527 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-08 17:01:20,527 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-08 17:01:20,528 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-08 17:01:20,538 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 05:01:20" (1/1) ... [2024-11-08 17:01:20,563 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 05:01:20" (1/1) ... [2024-11-08 17:01:20,617 INFO L138 Inliner]: procedures = 17, calls = 10, calls flagged for inlining = 3, calls inlined = 3, statements flattened = 376 [2024-11-08 17:01:20,618 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-08 17:01:20,618 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-08 17:01:20,619 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-08 17:01:20,619 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-08 17:01:20,637 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 05:01:20" (1/1) ... [2024-11-08 17:01:20,638 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 05:01:20" (1/1) ... [2024-11-08 17:01:20,659 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 05:01:20" (1/1) ... [2024-11-08 17:01:20,698 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-11-08 17:01:20,698 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 05:01:20" (1/1) ... [2024-11-08 17:01:20,699 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 05:01:20" (1/1) ... [2024-11-08 17:01:20,715 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 05:01:20" (1/1) ... [2024-11-08 17:01:20,723 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 05:01:20" (1/1) ... [2024-11-08 17:01:20,730 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 05:01:20" (1/1) ... [2024-11-08 17:01:20,737 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 05:01:20" (1/1) ... [2024-11-08 17:01:20,747 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-08 17:01:20,748 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-11-08 17:01:20,748 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-11-08 17:01:20,749 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-11-08 17:01:20,750 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 05:01:20" (1/1) ... [2024-11-08 17:01:20,759 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 [2024-11-08 17:01:20,774 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/z3 [2024-11-08 17:01:20,794 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (exit command is (exit), workingDir is null) [2024-11-08 17:01:20,808 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (1)] Waiting until timeout for monitored process [2024-11-08 17:01:20,842 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-08 17:01:20,843 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~intINTTYPE1#0 [2024-11-08 17:01:20,843 INFO L130 BoogieDeclarations]: Found specification of procedure assume_abort_if_not [2024-11-08 17:01:20,844 INFO L138 BoogieDeclarations]: Found implementation of procedure assume_abort_if_not [2024-11-08 17:01:20,844 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-08 17:01:20,844 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-08 17:01:21,074 INFO L238 CfgBuilder]: Building ICFG [2024-11-08 17:01:21,078 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-08 17:01:21,735 INFO L? ?]: Removed 176 outVars from TransFormulas that were not future-live. [2024-11-08 17:01:21,735 INFO L287 CfgBuilder]: Performing block encoding [2024-11-08 17:01:21,751 INFO L311 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-08 17:01:21,752 INFO L316 CfgBuilder]: Removed 1 assume(true) statements. [2024-11-08 17:01:21,752 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 08.11 05:01:21 BoogieIcfgContainer [2024-11-08 17:01:21,753 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-11-08 17:01:21,758 INFO L112 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2024-11-08 17:01:21,759 INFO L270 PluginConnector]: Initializing TraceAbstraction... [2024-11-08 17:01:21,764 INFO L274 PluginConnector]: TraceAbstraction initialized [2024-11-08 17:01:21,764 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 08.11 05:01:19" (1/3) ... [2024-11-08 17:01:21,765 INFO L204 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@3dfd1b07 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 08.11 05:01:21, skipping insertion in model container [2024-11-08 17:01:21,765 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 05:01:20" (2/3) ... [2024-11-08 17:01:21,766 INFO L204 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@3dfd1b07 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 08.11 05:01:21, skipping insertion in model container [2024-11-08 17:01:21,766 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 08.11 05:01:21" (3/3) ... [2024-11-08 17:01:21,767 INFO L112 eAbstractionObserver]: Analyzing ICFG btor2c-lazyMod.unsafe_analog_estimation_convergence.c [2024-11-08 17:01:21,793 INFO L214 ceAbstractionStarter]: Automizer settings: Hoare:LoopHeads NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2024-11-08 17:01:21,793 INFO L154 ceAbstractionStarter]: Applying trace abstraction to program that has 1 error locations. [2024-11-08 17:01:21,871 INFO L332 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2024-11-08 17:01:21,879 INFO L333 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mAutomataTypeConcurrency=PETRI_NET, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopHeads, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=[Lde.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings;@7f7abdfa, mLbeIndependenceSettings=[IndependenceType=SEMANTIC, AbstractionType=NONE, UseConditional=false, UseSemiCommutativity=true, Solver=Z3, SolverTimeout=1000ms] [2024-11-08 17:01:21,880 INFO L334 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2024-11-08 17:01:21,885 INFO L276 IsEmpty]: Start isEmpty. Operand has 19 states, 14 states have (on average 1.3571428571428572) internal successors, (19), 15 states have internal predecessors, (19), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2024-11-08 17:01:21,896 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2024-11-08 17:01:21,896 INFO L207 NwaCegarLoop]: Found error trace [2024-11-08 17:01:21,898 INFO L215 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 17:01:21,899 INFO L396 AbstractCegarLoop]: === Iteration 1 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-08 17:01:21,907 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 17:01:21,907 INFO L85 PathProgramCache]: Analyzing trace with hash -636159867, now seen corresponding path program 1 times [2024-11-08 17:01:21,925 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-11-08 17:01:21,926 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1973429979] [2024-11-08 17:01:21,926 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 17:01:21,927 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-08 17:01:21,927 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/z3 [2024-11-08 17:01:21,929 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-08 17:01:21,941 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2024-11-08 17:01:22,331 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:01:22,339 INFO L255 TraceCheckSpWp]: Trace formula consists of 240 conjuncts, 1 conjuncts are in the unsatisfiable core [2024-11-08 17:01:22,349 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-08 17:01:22,389 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-11-08 17:01:22,392 INFO L307 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-11-08 17:01:22,394 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-11-08 17:01:22,395 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1973429979] [2024-11-08 17:01:22,396 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1973429979] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 17:01:22,396 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 17:01:22,397 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-08 17:01:22,399 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [590889365] [2024-11-08 17:01:22,401 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 17:01:22,407 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 2 states [2024-11-08 17:01:22,407 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-11-08 17:01:22,446 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2024-11-08 17:01:22,447 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2024-11-08 17:01:22,450 INFO L87 Difference]: Start difference. First operand has 19 states, 14 states have (on average 1.3571428571428572) internal successors, (19), 15 states have internal predecessors, (19), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) Second operand has 2 states, 2 states have (on average 6.0) internal successors, (12), 2 states have internal predecessors, (12), 2 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 2 states have call successors, (2) [2024-11-08 17:01:22,474 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 17:01:22,475 INFO L93 Difference]: Finished difference Result 32 states and 43 transitions. [2024-11-08 17:01:22,476 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-11-08 17:01:22,478 INFO L78 Accepts]: Start accepts. Automaton has has 2 states, 2 states have (on average 6.0) internal successors, (12), 2 states have internal predecessors, (12), 2 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 2 states have call successors, (2) Word has length 17 [2024-11-08 17:01:22,479 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-08 17:01:22,487 INFO L225 Difference]: With dead ends: 32 [2024-11-08 17:01:22,488 INFO L226 Difference]: Without dead ends: 15 [2024-11-08 17:01:22,492 INFO L431 NwaCegarLoop]: 0 DeclaredPredicates, 16 GetRequests, 16 SyntacticMatches, 0 SemanticMatches, 0 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2024-11-08 17:01:22,499 INFO L432 NwaCegarLoop]: 16 mSDtfsCounter, 0 mSDsluCounter, 0 mSDsCounter, 0 mSdLazyCounter, 0 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 16 SdHoareTripleChecker+Invalid, 0 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 0 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-08 17:01:22,500 INFO L433 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 16 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 0 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-08 17:01:22,525 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15 states. [2024-11-08 17:01:22,545 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15 to 15. [2024-11-08 17:01:22,547 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 15 states, 11 states have (on average 1.0909090909090908) internal successors, (12), 11 states have internal predecessors, (12), 2 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2024-11-08 17:01:22,548 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15 states to 15 states and 16 transitions. [2024-11-08 17:01:22,550 INFO L78 Accepts]: Start accepts. Automaton has 15 states and 16 transitions. Word has length 17 [2024-11-08 17:01:22,551 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-08 17:01:22,552 INFO L471 AbstractCegarLoop]: Abstraction has 15 states and 16 transitions. [2024-11-08 17:01:22,552 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 2 states, 2 states have (on average 6.0) internal successors, (12), 2 states have internal predecessors, (12), 2 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 2 states have call successors, (2) [2024-11-08 17:01:22,552 INFO L276 IsEmpty]: Start isEmpty. Operand 15 states and 16 transitions. [2024-11-08 17:01:22,554 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2024-11-08 17:01:22,554 INFO L207 NwaCegarLoop]: Found error trace [2024-11-08 17:01:22,554 INFO L215 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 17:01:22,583 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Forceful destruction successful, exit code 0 [2024-11-08 17:01:22,758 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-08 17:01:22,759 INFO L396 AbstractCegarLoop]: === Iteration 2 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-08 17:01:22,760 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 17:01:22,760 INFO L85 PathProgramCache]: Analyzing trace with hash -320736127, now seen corresponding path program 1 times [2024-11-08 17:01:22,761 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-11-08 17:01:22,761 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1075629856] [2024-11-08 17:01:22,765 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 17:01:22,765 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-08 17:01:22,767 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/z3 [2024-11-08 17:01:22,769 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-08 17:01:22,772 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2024-11-08 17:01:23,119 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:01:23,125 INFO L255 TraceCheckSpWp]: Trace formula consists of 240 conjuncts, 23 conjuncts are in the unsatisfiable core [2024-11-08 17:01:23,135 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-08 17:01:23,709 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2024-11-08 17:01:23,710 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-08 17:01:24,051 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-11-08 17:01:24,051 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1075629856] [2024-11-08 17:01:24,051 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1075629856] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-08 17:01:24,052 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [1099037354] [2024-11-08 17:01:24,052 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 17:01:24,053 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2024-11-08 17:01:24,054 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/cvc4 [2024-11-08 17:01:24,056 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2024-11-08 17:01:24,059 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/cvc4 --incremental --print-success --lang smt (4)] Waiting until timeout for monitored process [2024-11-08 17:01:24,524 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:01:24,530 INFO L255 TraceCheckSpWp]: Trace formula consists of 240 conjuncts, 18 conjuncts are in the unsatisfiable core [2024-11-08 17:01:24,545 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-08 17:01:24,744 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-11-08 17:01:24,744 INFO L307 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-11-08 17:01:24,745 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [1099037354] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 17:01:24,745 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-11-08 17:01:24,745 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [7] total 7 [2024-11-08 17:01:24,746 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1351162427] [2024-11-08 17:01:24,746 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 17:01:24,748 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-11-08 17:01:24,748 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-11-08 17:01:24,750 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-08 17:01:24,751 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=53, Unknown=0, NotChecked=0, Total=72 [2024-11-08 17:01:24,752 INFO L87 Difference]: Start difference. First operand 15 states and 16 transitions. Second operand has 4 states, 4 states have (on average 2.5) internal successors, (10), 4 states have internal predecessors, (10), 1 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) [2024-11-08 17:01:24,888 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 17:01:24,888 INFO L93 Difference]: Finished difference Result 24 states and 27 transitions. [2024-11-08 17:01:24,889 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-08 17:01:24,889 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 2.5) internal successors, (10), 4 states have internal predecessors, (10), 1 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) Word has length 17 [2024-11-08 17:01:24,889 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-08 17:01:24,890 INFO L225 Difference]: With dead ends: 24 [2024-11-08 17:01:24,890 INFO L226 Difference]: Without dead ends: 22 [2024-11-08 17:01:24,891 INFO L431 NwaCegarLoop]: 0 DeclaredPredicates, 37 GetRequests, 29 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=25, Invalid=65, Unknown=0, NotChecked=0, Total=90 [2024-11-08 17:01:24,892 INFO L432 NwaCegarLoop]: 11 mSDtfsCounter, 2 mSDsluCounter, 21 mSDsCounter, 0 mSdLazyCounter, 15 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 2 SdHoareTripleChecker+Valid, 32 SdHoareTripleChecker+Invalid, 15 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 15 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-08 17:01:24,892 INFO L433 NwaCegarLoop]: SdHoareTripleChecker [2 Valid, 32 Invalid, 15 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 15 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-08 17:01:24,897 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22 states. [2024-11-08 17:01:24,903 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22 to 21. [2024-11-08 17:01:24,904 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21 states, 15 states have (on average 1.0666666666666667) internal successors, (16), 15 states have internal predecessors, (16), 4 states have call successors, (4), 1 states have call predecessors, (4), 1 states have return successors, (4), 4 states have call predecessors, (4), 4 states have call successors, (4) [2024-11-08 17:01:24,906 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21 states to 21 states and 24 transitions. [2024-11-08 17:01:24,907 INFO L78 Accepts]: Start accepts. Automaton has 21 states and 24 transitions. Word has length 17 [2024-11-08 17:01:24,908 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-08 17:01:24,908 INFO L471 AbstractCegarLoop]: Abstraction has 21 states and 24 transitions. [2024-11-08 17:01:24,909 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 2.5) internal successors, (10), 4 states have internal predecessors, (10), 1 states have call successors, (2), 1 states have call predecessors, (2), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) [2024-11-08 17:01:24,909 INFO L276 IsEmpty]: Start isEmpty. Operand 21 states and 24 transitions. [2024-11-08 17:01:24,910 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2024-11-08 17:01:24,910 INFO L207 NwaCegarLoop]: Found error trace [2024-11-08 17:01:24,911 INFO L215 NwaCegarLoop]: trace histogram [4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1] [2024-11-08 17:01:24,916 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/cvc4 --incremental --print-success --lang smt (4)] Ended with exit code 0 [2024-11-08 17:01:25,132 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Ended with exit code 0 [2024-11-08 17:01:25,314 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 4 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/cvc4 --incremental --print-success --lang smt,3 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-08 17:01:25,316 INFO L396 AbstractCegarLoop]: === Iteration 3 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-08 17:01:25,318 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 17:01:25,319 INFO L85 PathProgramCache]: Analyzing trace with hash -1487971485, now seen corresponding path program 1 times [2024-11-08 17:01:25,320 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-11-08 17:01:25,321 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [2036147290] [2024-11-08 17:01:25,325 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 17:01:25,325 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-08 17:01:25,325 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/z3 [2024-11-08 17:01:25,328 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-08 17:01:25,338 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process [2024-11-08 17:01:25,778 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:01:25,789 INFO L255 TraceCheckSpWp]: Trace formula consists of 409 conjuncts, 27 conjuncts are in the unsatisfiable core [2024-11-08 17:01:25,798 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-08 17:01:26,435 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2024-11-08 17:01:26,436 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-08 17:01:26,690 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-11-08 17:01:26,691 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2036147290] [2024-11-08 17:01:26,691 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2036147290] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-08 17:01:26,691 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [106274706] [2024-11-08 17:01:26,691 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 17:01:26,692 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2024-11-08 17:01:26,693 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/cvc4 [2024-11-08 17:01:26,695 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2024-11-08 17:01:26,700 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/cvc4 --incremental --print-success --lang smt (6)] Waiting until timeout for monitored process [2024-11-08 17:01:27,474 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 17:01:27,504 INFO L255 TraceCheckSpWp]: Trace formula consists of 409 conjuncts, 26 conjuncts are in the unsatisfiable core [2024-11-08 17:01:27,513 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-08 17:01:27,978 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2024-11-08 17:01:27,978 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-08 17:01:28,176 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [106274706] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-08 17:01:28,176 INFO L185 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2024-11-08 17:01:28,177 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 5] total 6 [2024-11-08 17:01:28,177 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [859937835] [2024-11-08 17:01:28,177 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2024-11-08 17:01:28,178 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-11-08 17:01:28,178 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-11-08 17:01:28,179 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-11-08 17:01:28,180 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=36, Unknown=0, NotChecked=0, Total=56 [2024-11-08 17:01:28,180 INFO L87 Difference]: Start difference. First operand 21 states and 24 transitions. Second operand has 6 states, 6 states have (on average 2.8333333333333335) internal successors, (17), 6 states have internal predecessors, (17), 2 states have call successors, (4), 1 states have call predecessors, (4), 1 states have return successors, (4), 2 states have call predecessors, (4), 2 states have call successors, (4) [2024-11-08 17:01:28,459 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 17:01:28,459 INFO L93 Difference]: Finished difference Result 31 states and 36 transitions. [2024-11-08 17:01:28,460 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-11-08 17:01:28,460 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 2.8333333333333335) internal successors, (17), 6 states have internal predecessors, (17), 2 states have call successors, (4), 1 states have call predecessors, (4), 1 states have return successors, (4), 2 states have call predecessors, (4), 2 states have call successors, (4) Word has length 32 [2024-11-08 17:01:28,461 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-08 17:01:28,462 INFO L225 Difference]: With dead ends: 31 [2024-11-08 17:01:28,462 INFO L226 Difference]: Without dead ends: 29 [2024-11-08 17:01:28,463 INFO L431 NwaCegarLoop]: 0 DeclaredPredicates, 72 GetRequests, 63 SyntacticMatches, 1 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=35, Invalid=55, Unknown=0, NotChecked=0, Total=90 [2024-11-08 17:01:28,464 INFO L432 NwaCegarLoop]: 11 mSDtfsCounter, 2 mSDsluCounter, 29 mSDsCounter, 0 mSdLazyCounter, 28 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 2 SdHoareTripleChecker+Valid, 40 SdHoareTripleChecker+Invalid, 28 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 28 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-11-08 17:01:28,465 INFO L433 NwaCegarLoop]: SdHoareTripleChecker [2 Valid, 40 Invalid, 28 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 28 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-11-08 17:01:28,466 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29 states. [2024-11-08 17:01:28,473 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29 to 28. [2024-11-08 17:01:28,473 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 28 states, 20 states have (on average 1.05) internal successors, (21), 20 states have internal predecessors, (21), 6 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2024-11-08 17:01:28,475 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28 states to 28 states and 33 transitions. [2024-11-08 17:01:28,475 INFO L78 Accepts]: Start accepts. Automaton has 28 states and 33 transitions. Word has length 32 [2024-11-08 17:01:28,476 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-08 17:01:28,476 INFO L471 AbstractCegarLoop]: Abstraction has 28 states and 33 transitions. [2024-11-08 17:01:28,476 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 2.8333333333333335) internal successors, (17), 6 states have internal predecessors, (17), 2 states have call successors, (4), 1 states have call predecessors, (4), 1 states have return successors, (4), 2 states have call predecessors, (4), 2 states have call successors, (4) [2024-11-08 17:01:28,477 INFO L276 IsEmpty]: Start isEmpty. Operand 28 states and 33 transitions. [2024-11-08 17:01:28,478 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2024-11-08 17:01:28,478 INFO L207 NwaCegarLoop]: Found error trace [2024-11-08 17:01:28,479 INFO L215 NwaCegarLoop]: trace histogram [6, 6, 6, 3, 3, 3, 3, 3, 3, 3, 2, 2, 1, 1, 1, 1] [2024-11-08 17:01:28,487 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/cvc4 --incremental --print-success --lang smt (6)] Ended with exit code 0 [2024-11-08 17:01:28,698 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Forceful destruction successful, exit code 0 [2024-11-08 17:01:28,879 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 6 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/cvc4 --incremental --print-success --lang smt,5 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-08 17:01:28,880 INFO L396 AbstractCegarLoop]: === Iteration 4 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-08 17:01:28,881 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 17:01:28,881 INFO L85 PathProgramCache]: Analyzing trace with hash 1718555713, now seen corresponding path program 2 times [2024-11-08 17:01:28,883 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-11-08 17:01:28,883 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1943351164] [2024-11-08 17:01:28,883 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-08 17:01:28,883 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-08 17:01:28,886 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/z3 [2024-11-08 17:01:28,889 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-08 17:01:28,891 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Waiting until timeout for monitored process [2024-11-08 17:01:29,439 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2024-11-08 17:01:29,439 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-08 17:01:29,449 INFO L255 TraceCheckSpWp]: Trace formula consists of 578 conjuncts, 25 conjuncts are in the unsatisfiable core [2024-11-08 17:01:29,458 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-08 17:01:30,231 INFO L134 CoverageAnalysis]: Checked inductivity of 79 backedges. 0 proven. 19 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-11-08 17:01:30,231 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-08 17:01:30,470 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-11-08 17:01:30,471 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1943351164] [2024-11-08 17:01:30,471 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1943351164] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-08 17:01:30,471 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [1891183454] [2024-11-08 17:01:30,471 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-08 17:01:30,472 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2024-11-08 17:01:30,472 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/cvc4 [2024-11-08 17:01:30,475 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2024-11-08 17:01:30,477 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/cvc4 --incremental --print-success --lang smt (8)] Waiting until timeout for monitored process [2024-11-08 17:01:31,573 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2024-11-08 17:01:31,573 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-08 17:01:31,584 INFO L255 TraceCheckSpWp]: Trace formula consists of 578 conjuncts, 28 conjuncts are in the unsatisfiable core [2024-11-08 17:01:31,592 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-08 17:01:32,238 INFO L134 CoverageAnalysis]: Checked inductivity of 79 backedges. 0 proven. 19 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-11-08 17:01:32,238 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-08 17:01:32,423 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [1891183454] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-08 17:01:32,423 INFO L185 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2024-11-08 17:01:32,423 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6] total 6 [2024-11-08 17:01:32,424 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [521733948] [2024-11-08 17:01:32,424 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2024-11-08 17:01:32,425 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-11-08 17:01:32,425 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-11-08 17:01:32,426 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-11-08 17:01:32,426 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=38, Unknown=0, NotChecked=0, Total=56 [2024-11-08 17:01:32,426 INFO L87 Difference]: Start difference. First operand 28 states and 33 transitions. Second operand has 6 states, 6 states have (on average 3.3333333333333335) internal successors, (20), 6 states have internal predecessors, (20), 3 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 3 states have call predecessors, (6), 3 states have call successors, (6) [2024-11-08 17:01:32,906 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 17:01:32,906 INFO L93 Difference]: Finished difference Result 38 states and 45 transitions. [2024-11-08 17:01:32,907 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-11-08 17:01:32,907 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 3.3333333333333335) internal successors, (20), 6 states have internal predecessors, (20), 3 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 3 states have call predecessors, (6), 3 states have call successors, (6) Word has length 47 [2024-11-08 17:01:32,908 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-08 17:01:32,908 INFO L225 Difference]: With dead ends: 38 [2024-11-08 17:01:32,909 INFO L226 Difference]: Without dead ends: 36 [2024-11-08 17:01:32,909 INFO L431 NwaCegarLoop]: 0 DeclaredPredicates, 103 GetRequests, 93 SyntacticMatches, 1 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=38, Invalid=72, Unknown=0, NotChecked=0, Total=110 [2024-11-08 17:01:32,910 INFO L432 NwaCegarLoop]: 15 mSDtfsCounter, 2 mSDsluCounter, 34 mSDsCounter, 0 mSdLazyCounter, 43 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 2 SdHoareTripleChecker+Valid, 49 SdHoareTripleChecker+Invalid, 44 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 43 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2024-11-08 17:01:32,915 INFO L433 NwaCegarLoop]: SdHoareTripleChecker [2 Valid, 49 Invalid, 44 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 43 Invalid, 0 Unknown, 0 Unchecked, 0.3s Time] [2024-11-08 17:01:32,916 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 36 states. [2024-11-08 17:01:32,931 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 36 to 35. [2024-11-08 17:01:32,934 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 35 states, 25 states have (on average 1.04) internal successors, (26), 25 states have internal predecessors, (26), 8 states have call successors, (8), 1 states have call predecessors, (8), 1 states have return successors, (8), 8 states have call predecessors, (8), 8 states have call successors, (8) [2024-11-08 17:01:32,935 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 35 states to 35 states and 42 transitions. [2024-11-08 17:01:32,936 INFO L78 Accepts]: Start accepts. Automaton has 35 states and 42 transitions. Word has length 47 [2024-11-08 17:01:32,936 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-08 17:01:32,936 INFO L471 AbstractCegarLoop]: Abstraction has 35 states and 42 transitions. [2024-11-08 17:01:32,937 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 3.3333333333333335) internal successors, (20), 6 states have internal predecessors, (20), 3 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 3 states have call predecessors, (6), 3 states have call successors, (6) [2024-11-08 17:01:32,937 INFO L276 IsEmpty]: Start isEmpty. Operand 35 states and 42 transitions. [2024-11-08 17:01:32,940 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 63 [2024-11-08 17:01:32,940 INFO L207 NwaCegarLoop]: Found error trace [2024-11-08 17:01:32,940 INFO L215 NwaCegarLoop]: trace histogram [8, 8, 8, 4, 4, 4, 4, 4, 4, 4, 3, 3, 1, 1, 1, 1] [2024-11-08 17:01:32,971 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Forceful destruction successful, exit code 0 [2024-11-08 17:01:33,148 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/cvc4 --incremental --print-success --lang smt (8)] Forceful destruction successful, exit code 0 [2024-11-08 17:01:33,341 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 7 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true,8 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/cvc4 --incremental --print-success --lang smt [2024-11-08 17:01:33,342 INFO L396 AbstractCegarLoop]: === Iteration 5 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-08 17:01:33,342 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 17:01:33,343 INFO L85 PathProgramCache]: Analyzing trace with hash 426165155, now seen corresponding path program 3 times [2024-11-08 17:01:33,345 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-11-08 17:01:33,346 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1979155834] [2024-11-08 17:01:33,346 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-11-08 17:01:33,347 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-08 17:01:33,347 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/z3 [2024-11-08 17:01:33,349 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-08 17:01:33,352 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Waiting until timeout for monitored process [2024-11-08 17:01:34,233 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 5 check-sat command(s) [2024-11-08 17:01:34,233 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-08 17:01:34,247 INFO L255 TraceCheckSpWp]: Trace formula consists of 724 conjuncts, 27 conjuncts are in the unsatisfiable core [2024-11-08 17:01:34,258 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-08 17:01:35,225 INFO L134 CoverageAnalysis]: Checked inductivity of 151 backedges. 0 proven. 39 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2024-11-08 17:01:35,225 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-08 17:01:35,480 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-11-08 17:01:35,480 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1979155834] [2024-11-08 17:01:35,480 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1979155834] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-08 17:01:35,480 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [1647779077] [2024-11-08 17:01:35,480 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-11-08 17:01:35,480 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2024-11-08 17:01:35,481 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/cvc4 [2024-11-08 17:01:35,482 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2024-11-08 17:01:35,485 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/cvc4 --incremental --print-success --lang smt (10)] Waiting until timeout for monitored process [2024-11-08 17:01:36,891 INFO L227 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 5 check-sat command(s) [2024-11-08 17:01:36,891 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-08 17:01:36,933 INFO L255 TraceCheckSpWp]: Trace formula consists of 724 conjuncts, 37 conjuncts are in the unsatisfiable core [2024-11-08 17:01:36,943 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-08 17:01:37,686 INFO L134 CoverageAnalysis]: Checked inductivity of 151 backedges. 0 proven. 39 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2024-11-08 17:01:37,686 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-08 17:01:37,888 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [1647779077] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-08 17:01:37,889 INFO L185 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2024-11-08 17:01:37,889 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7] total 7 [2024-11-08 17:01:37,889 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [935216668] [2024-11-08 17:01:37,889 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2024-11-08 17:01:37,890 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2024-11-08 17:01:37,890 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-11-08 17:01:37,891 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2024-11-08 17:01:37,891 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=52, Unknown=0, NotChecked=0, Total=72 [2024-11-08 17:01:37,892 INFO L87 Difference]: Start difference. First operand 35 states and 42 transitions. Second operand has 7 states, 7 states have (on average 3.5714285714285716) internal successors, (25), 7 states have internal predecessors, (25), 4 states have call successors, (8), 1 states have call predecessors, (8), 1 states have return successors, (8), 4 states have call predecessors, (8), 4 states have call successors, (8) [2024-11-08 17:01:38,381 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 17:01:38,381 INFO L93 Difference]: Finished difference Result 45 states and 54 transitions. [2024-11-08 17:01:38,381 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2024-11-08 17:01:38,382 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 3.5714285714285716) internal successors, (25), 7 states have internal predecessors, (25), 4 states have call successors, (8), 1 states have call predecessors, (8), 1 states have return successors, (8), 4 states have call predecessors, (8), 4 states have call successors, (8) Word has length 62 [2024-11-08 17:01:38,382 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-08 17:01:38,383 INFO L225 Difference]: With dead ends: 45 [2024-11-08 17:01:38,384 INFO L226 Difference]: Without dead ends: 43 [2024-11-08 17:01:38,384 INFO L431 NwaCegarLoop]: 0 DeclaredPredicates, 134 GetRequests, 122 SyntacticMatches, 1 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=44, Invalid=112, Unknown=0, NotChecked=0, Total=156 [2024-11-08 17:01:38,385 INFO L432 NwaCegarLoop]: 23 mSDtfsCounter, 2 mSDsluCounter, 78 mSDsCounter, 0 mSdLazyCounter, 126 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 2 SdHoareTripleChecker+Valid, 101 SdHoareTripleChecker+Invalid, 129 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 126 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.4s IncrementalHoareTripleChecker+Time [2024-11-08 17:01:38,386 INFO L433 NwaCegarLoop]: SdHoareTripleChecker [2 Valid, 101 Invalid, 129 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 126 Invalid, 0 Unknown, 0 Unchecked, 0.4s Time] [2024-11-08 17:01:38,387 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 43 states. [2024-11-08 17:01:38,397 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 43 to 42. [2024-11-08 17:01:38,398 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 42 states, 30 states have (on average 1.0333333333333334) internal successors, (31), 30 states have internal predecessors, (31), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-08 17:01:38,399 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42 states to 42 states and 51 transitions. [2024-11-08 17:01:38,400 INFO L78 Accepts]: Start accepts. Automaton has 42 states and 51 transitions. Word has length 62 [2024-11-08 17:01:38,400 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-08 17:01:38,401 INFO L471 AbstractCegarLoop]: Abstraction has 42 states and 51 transitions. [2024-11-08 17:01:38,401 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 3.5714285714285716) internal successors, (25), 7 states have internal predecessors, (25), 4 states have call successors, (8), 1 states have call predecessors, (8), 1 states have return successors, (8), 4 states have call predecessors, (8), 4 states have call successors, (8) [2024-11-08 17:01:38,401 INFO L276 IsEmpty]: Start isEmpty. Operand 42 states and 51 transitions. [2024-11-08 17:01:38,403 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 78 [2024-11-08 17:01:38,404 INFO L207 NwaCegarLoop]: Found error trace [2024-11-08 17:01:38,404 INFO L215 NwaCegarLoop]: trace histogram [10, 10, 10, 5, 5, 5, 5, 5, 5, 5, 4, 4, 1, 1, 1, 1] [2024-11-08 17:01:38,430 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Forceful destruction successful, exit code 0 [2024-11-08 17:01:38,616 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/cvc4 --incremental --print-success --lang smt (10)] Forceful destruction successful, exit code 0 [2024-11-08 17:01:38,808 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 9 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true,10 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/cvc4 --incremental --print-success --lang smt [2024-11-08 17:01:38,808 INFO L396 AbstractCegarLoop]: === Iteration 6 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-08 17:01:38,809 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 17:01:38,809 INFO L85 PathProgramCache]: Analyzing trace with hash 1242702849, now seen corresponding path program 4 times [2024-11-08 17:01:38,810 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-11-08 17:01:38,810 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1464506516] [2024-11-08 17:01:38,811 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2024-11-08 17:01:38,811 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-08 17:01:38,811 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/z3 [2024-11-08 17:01:38,812 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-08 17:01:38,814 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Waiting until timeout for monitored process [2024-11-08 17:01:39,664 INFO L227 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2024-11-08 17:01:39,665 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-08 17:01:39,677 INFO L255 TraceCheckSpWp]: Trace formula consists of 916 conjuncts, 31 conjuncts are in the unsatisfiable core [2024-11-08 17:01:39,688 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-08 17:01:40,766 INFO L134 CoverageAnalysis]: Checked inductivity of 246 backedges. 0 proven. 66 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2024-11-08 17:01:40,766 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-08 17:01:40,973 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-11-08 17:01:40,973 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1464506516] [2024-11-08 17:01:40,973 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1464506516] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-08 17:01:40,974 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [2124322579] [2024-11-08 17:01:40,974 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2024-11-08 17:01:40,974 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2024-11-08 17:01:40,974 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/cvc4 [2024-11-08 17:01:40,975 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2024-11-08 17:01:40,977 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/cvc4 --incremental --print-success --lang smt (12)] Waiting until timeout for monitored process [2024-11-08 17:01:42,730 INFO L227 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2024-11-08 17:01:42,730 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-08 17:01:42,804 INFO L255 TraceCheckSpWp]: Trace formula consists of 916 conjuncts, 33 conjuncts are in the unsatisfiable core [2024-11-08 17:01:42,830 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-08 17:01:43,863 INFO L134 CoverageAnalysis]: Checked inductivity of 246 backedges. 0 proven. 66 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2024-11-08 17:01:43,864 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-08 17:01:44,046 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [2124322579] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-08 17:01:44,046 INFO L185 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2024-11-08 17:01:44,046 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 8] total 9 [2024-11-08 17:01:44,047 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1090156878] [2024-11-08 17:01:44,047 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2024-11-08 17:01:44,048 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 9 states [2024-11-08 17:01:44,048 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-11-08 17:01:44,048 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2024-11-08 17:01:44,049 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=27, Invalid=83, Unknown=0, NotChecked=0, Total=110 [2024-11-08 17:01:44,049 INFO L87 Difference]: Start difference. First operand 42 states and 51 transitions. Second operand has 9 states, 9 states have (on average 3.5555555555555554) internal successors, (32), 9 states have internal predecessors, (32), 5 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 5 states have call predecessors, (10), 5 states have call successors, (10) [2024-11-08 17:01:44,741 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 17:01:44,742 INFO L93 Difference]: Finished difference Result 52 states and 63 transitions. [2024-11-08 17:01:44,743 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2024-11-08 17:01:44,743 INFO L78 Accepts]: Start accepts. Automaton has has 9 states, 9 states have (on average 3.5555555555555554) internal successors, (32), 9 states have internal predecessors, (32), 5 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 5 states have call predecessors, (10), 5 states have call successors, (10) Word has length 77 [2024-11-08 17:01:44,744 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-08 17:01:44,745 INFO L225 Difference]: With dead ends: 52 [2024-11-08 17:01:44,745 INFO L226 Difference]: Without dead ends: 50 [2024-11-08 17:01:44,745 INFO L431 NwaCegarLoop]: 0 DeclaredPredicates, 165 GetRequests, 150 SyntacticMatches, 1 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 23 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=58, Invalid=182, Unknown=0, NotChecked=0, Total=240 [2024-11-08 17:01:44,746 INFO L432 NwaCegarLoop]: 27 mSDtfsCounter, 2 mSDsluCounter, 121 mSDsCounter, 0 mSdLazyCounter, 228 mSolverCounterSat, 4 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.5s Time, 0 mProtectedPredicate, 0 mProtectedAction, 2 SdHoareTripleChecker+Valid, 148 SdHoareTripleChecker+Invalid, 232 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 4 IncrementalHoareTripleChecker+Valid, 228 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.5s IncrementalHoareTripleChecker+Time [2024-11-08 17:01:44,747 INFO L433 NwaCegarLoop]: SdHoareTripleChecker [2 Valid, 148 Invalid, 232 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [4 Valid, 228 Invalid, 0 Unknown, 0 Unchecked, 0.5s Time] [2024-11-08 17:01:44,748 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 50 states. [2024-11-08 17:01:44,760 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 50 to 49. [2024-11-08 17:01:44,761 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 49 states, 35 states have (on average 1.0285714285714285) internal successors, (36), 35 states have internal predecessors, (36), 12 states have call successors, (12), 1 states have call predecessors, (12), 1 states have return successors, (12), 12 states have call predecessors, (12), 12 states have call successors, (12) [2024-11-08 17:01:44,762 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49 states to 49 states and 60 transitions. [2024-11-08 17:01:44,762 INFO L78 Accepts]: Start accepts. Automaton has 49 states and 60 transitions. Word has length 77 [2024-11-08 17:01:44,763 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-08 17:01:44,763 INFO L471 AbstractCegarLoop]: Abstraction has 49 states and 60 transitions. [2024-11-08 17:01:44,763 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 9 states, 9 states have (on average 3.5555555555555554) internal successors, (32), 9 states have internal predecessors, (32), 5 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 5 states have call predecessors, (10), 5 states have call successors, (10) [2024-11-08 17:01:44,763 INFO L276 IsEmpty]: Start isEmpty. Operand 49 states and 60 transitions. [2024-11-08 17:01:44,765 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 93 [2024-11-08 17:01:44,766 INFO L207 NwaCegarLoop]: Found error trace [2024-11-08 17:01:44,766 INFO L215 NwaCegarLoop]: trace histogram [12, 12, 12, 6, 6, 6, 6, 6, 6, 6, 5, 5, 1, 1, 1, 1] [2024-11-08 17:01:44,789 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Forceful destruction successful, exit code 0 [2024-11-08 17:01:44,978 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/cvc4 --incremental --print-success --lang smt (12)] Forceful destruction successful, exit code 0 [2024-11-08 17:01:45,167 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 11 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true,12 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/cvc4 --incremental --print-success --lang smt [2024-11-08 17:01:45,167 INFO L396 AbstractCegarLoop]: === Iteration 7 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-08 17:01:45,167 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 17:01:45,168 INFO L85 PathProgramCache]: Analyzing trace with hash -724943901, now seen corresponding path program 5 times [2024-11-08 17:01:45,169 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-11-08 17:01:45,169 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1654632931] [2024-11-08 17:01:45,173 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2024-11-08 17:01:45,173 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-08 17:01:45,173 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/z3 [2024-11-08 17:01:45,175 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-08 17:01:45,177 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Waiting until timeout for monitored process [2024-11-08 17:01:46,464 INFO L227 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 9 check-sat command(s) [2024-11-08 17:01:46,465 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-08 17:01:46,480 INFO L255 TraceCheckSpWp]: Trace formula consists of 1085 conjuncts, 32 conjuncts are in the unsatisfiable core [2024-11-08 17:01:46,487 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-08 17:01:47,670 INFO L134 CoverageAnalysis]: Checked inductivity of 364 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 264 trivial. 0 not checked. [2024-11-08 17:01:47,671 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-08 17:01:47,879 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-11-08 17:01:47,879 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1654632931] [2024-11-08 17:01:47,879 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1654632931] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-08 17:01:47,880 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [1845185969] [2024-11-08 17:01:47,880 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2024-11-08 17:01:47,880 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2024-11-08 17:01:47,880 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/cvc4 [2024-11-08 17:01:47,882 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2024-11-08 17:01:47,884 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/cvc4 --incremental --print-success --lang smt (14)] Waiting until timeout for monitored process [2024-11-08 17:01:50,181 INFO L227 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 9 check-sat command(s) [2024-11-08 17:01:50,181 INFO L228 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-08 17:01:50,235 INFO L255 TraceCheckSpWp]: Trace formula consists of 1085 conjuncts, 34 conjuncts are in the unsatisfiable core [2024-11-08 17:01:50,248 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-08 17:01:51,334 INFO L134 CoverageAnalysis]: Checked inductivity of 364 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 264 trivial. 0 not checked. [2024-11-08 17:01:51,335 INFO L311 TraceCheckSpWp]: Computing backward predicates... [2024-11-08 17:01:51,517 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [1845185969] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-08 17:01:51,518 INFO L185 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2024-11-08 17:01:51,518 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 9] total 10 [2024-11-08 17:01:51,518 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [603749232] [2024-11-08 17:01:51,518 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2024-11-08 17:01:51,519 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 10 states [2024-11-08 17:01:51,519 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-11-08 17:01:51,520 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2024-11-08 17:01:51,522 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=30, Invalid=102, Unknown=0, NotChecked=0, Total=132 [2024-11-08 17:01:51,523 INFO L87 Difference]: Start difference. First operand 49 states and 60 transitions. Second operand has 10 states, 10 states have (on average 3.7) internal successors, (37), 10 states have internal predecessors, (37), 6 states have call successors, (12), 1 states have call predecessors, (12), 1 states have return successors, (12), 6 states have call predecessors, (12), 6 states have call successors, (12) [2024-11-08 17:01:52,394 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 17:01:52,394 INFO L93 Difference]: Finished difference Result 59 states and 72 transitions. [2024-11-08 17:01:52,394 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2024-11-08 17:01:52,395 INFO L78 Accepts]: Start accepts. Automaton has has 10 states, 10 states have (on average 3.7) internal successors, (37), 10 states have internal predecessors, (37), 6 states have call successors, (12), 1 states have call predecessors, (12), 1 states have return successors, (12), 6 states have call predecessors, (12), 6 states have call successors, (12) Word has length 92 [2024-11-08 17:01:52,395 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-08 17:01:52,396 INFO L225 Difference]: With dead ends: 59 [2024-11-08 17:01:52,397 INFO L226 Difference]: Without dead ends: 57 [2024-11-08 17:01:52,397 INFO L431 NwaCegarLoop]: 0 DeclaredPredicates, 196 GetRequests, 179 SyntacticMatches, 1 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 33 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=67, Invalid=239, Unknown=0, NotChecked=0, Total=306 [2024-11-08 17:01:52,398 INFO L432 NwaCegarLoop]: 31 mSDtfsCounter, 2 mSDsluCounter, 138 mSDsCounter, 0 mSdLazyCounter, 278 mSolverCounterSat, 5 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.6s Time, 0 mProtectedPredicate, 0 mProtectedAction, 2 SdHoareTripleChecker+Valid, 169 SdHoareTripleChecker+Invalid, 283 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 5 IncrementalHoareTripleChecker+Valid, 278 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.7s IncrementalHoareTripleChecker+Time [2024-11-08 17:01:52,399 INFO L433 NwaCegarLoop]: SdHoareTripleChecker [2 Valid, 169 Invalid, 283 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [5 Valid, 278 Invalid, 0 Unknown, 0 Unchecked, 0.7s Time] [2024-11-08 17:01:52,399 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 57 states. [2024-11-08 17:01:52,411 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 57 to 56. [2024-11-08 17:01:52,412 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 56 states, 40 states have (on average 1.025) internal successors, (41), 40 states have internal predecessors, (41), 14 states have call successors, (14), 1 states have call predecessors, (14), 1 states have return successors, (14), 14 states have call predecessors, (14), 14 states have call successors, (14) [2024-11-08 17:01:52,413 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 56 states to 56 states and 69 transitions. [2024-11-08 17:01:52,413 INFO L78 Accepts]: Start accepts. Automaton has 56 states and 69 transitions. Word has length 92 [2024-11-08 17:01:52,414 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-08 17:01:52,414 INFO L471 AbstractCegarLoop]: Abstraction has 56 states and 69 transitions. [2024-11-08 17:01:52,414 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 10 states, 10 states have (on average 3.7) internal successors, (37), 10 states have internal predecessors, (37), 6 states have call successors, (12), 1 states have call predecessors, (12), 1 states have return successors, (12), 6 states have call predecessors, (12), 6 states have call successors, (12) [2024-11-08 17:01:52,415 INFO L276 IsEmpty]: Start isEmpty. Operand 56 states and 69 transitions. [2024-11-08 17:01:52,417 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 108 [2024-11-08 17:01:52,417 INFO L207 NwaCegarLoop]: Found error trace [2024-11-08 17:01:52,417 INFO L215 NwaCegarLoop]: trace histogram [14, 14, 14, 7, 7, 7, 7, 7, 7, 7, 6, 6, 1, 1, 1, 1] [2024-11-08 17:01:52,434 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/cvc4 --incremental --print-success --lang smt (14)] Forceful destruction successful, exit code 0 [2024-11-08 17:01:52,651 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Ended with exit code 0 [2024-11-08 17:01:52,818 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 14 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/cvc4 --incremental --print-success --lang smt,13 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-08 17:01:52,819 INFO L396 AbstractCegarLoop]: === Iteration 8 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-08 17:01:52,819 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 17:01:52,819 INFO L85 PathProgramCache]: Analyzing trace with hash -1060691007, now seen corresponding path program 6 times [2024-11-08 17:01:52,821 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-11-08 17:01:52,821 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [382445667] [2024-11-08 17:01:52,822 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2024-11-08 17:01:52,822 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-08 17:01:52,823 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/z3 [2024-11-08 17:01:52,825 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-08 17:01:52,828 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Waiting until timeout for monitored process [2024-11-08 17:01:54,385 INFO L227 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 10 check-sat command(s) [2024-11-08 17:01:54,385 INFO L228 tOrderPrioritization]: Conjunction of SSA is sat [2024-11-08 17:01:54,386 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 17:01:54,982 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 17:01:55,362 INFO L130 FreeRefinementEngine]: Strategy FOX found a feasible trace [2024-11-08 17:01:55,362 INFO L325 BasicCegarLoop]: Counterexample is feasible [2024-11-08 17:01:55,365 INFO L782 garLoopResultBuilder]: Registering result UNSAFE for location ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION (0 of 1 remaining) [2024-11-08 17:01:55,409 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Forceful destruction successful, exit code 0 [2024-11-08 17:01:55,567 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 15 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-08 17:01:55,571 INFO L407 BasicCegarLoop]: Path program histogram: [6, 1, 1] [2024-11-08 17:01:55,705 WARN L290 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2024-11-08 17:01:55,705 WARN L290 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2024-11-08 17:01:55,705 WARN L290 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2024-11-08 17:01:55,706 WARN L290 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2024-11-08 17:01:55,706 WARN L290 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2024-11-08 17:01:55,706 WARN L290 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2024-11-08 17:01:55,706 WARN L290 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2024-11-08 17:01:55,779 INFO L170 ceAbstractionStarter]: Computing trace abstraction results [2024-11-08 17:01:55,783 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 08.11 05:01:55 BoogieIcfgContainer [2024-11-08 17:01:55,783 INFO L131 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2024-11-08 17:01:55,784 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2024-11-08 17:01:55,784 INFO L270 PluginConnector]: Initializing Witness Printer... [2024-11-08 17:01:55,784 INFO L274 PluginConnector]: Witness Printer initialized [2024-11-08 17:01:55,785 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 08.11 05:01:21" (3/4) ... [2024-11-08 17:01:55,786 INFO L136 WitnessPrinter]: Generating witness for reachability counterexample [2024-11-08 17:01:55,827 WARN L290 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2024-11-08 17:01:55,828 WARN L290 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2024-11-08 17:01:55,828 WARN L290 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2024-11-08 17:01:55,828 WARN L290 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2024-11-08 17:01:55,828 WARN L290 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2024-11-08 17:01:55,829 WARN L290 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2024-11-08 17:01:55,829 WARN L290 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2024-11-08 17:01:56,114 INFO L149 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/witness.graphml [2024-11-08 17:01:56,114 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2024-11-08 17:01:56,115 INFO L158 Benchmark]: Toolchain (without parser) took 36448.84ms. Allocated memory was 79.7MB in the beginning and 373.3MB in the end (delta: 293.6MB). Free memory was 55.2MB in the beginning and 159.7MB in the end (delta: -104.6MB). Peak memory consumption was 188.6MB. Max. memory is 16.1GB. [2024-11-08 17:01:56,117 INFO L158 Benchmark]: CDTParser took 0.43ms. Allocated memory is still 79.7MB. Free memory was 56.4MB in the beginning and 56.3MB in the end (delta: 148.1kB). There was no memory consumed. Max. memory is 16.1GB. [2024-11-08 17:01:56,117 INFO L158 Benchmark]: CACSL2BoogieTranslator took 856.68ms. Allocated memory was 79.7MB in the beginning and 117.4MB in the end (delta: 37.7MB). Free memory was 54.9MB in the beginning and 89.4MB in the end (delta: -34.4MB). Peak memory consumption was 21.0MB. Max. memory is 16.1GB. [2024-11-08 17:01:56,117 INFO L158 Benchmark]: Boogie Procedure Inliner took 90.82ms. Allocated memory is still 117.4MB. Free memory was 89.4MB in the beginning and 85.7MB in the end (delta: 3.7MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2024-11-08 17:01:56,118 INFO L158 Benchmark]: Boogie Preprocessor took 128.62ms. Allocated memory is still 117.4MB. Free memory was 85.7MB in the beginning and 81.0MB in the end (delta: 4.6MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2024-11-08 17:01:56,119 INFO L158 Benchmark]: RCFGBuilder took 1004.68ms. Allocated memory is still 117.4MB. Free memory was 81.0MB in the beginning and 71.3MB in the end (delta: 9.7MB). Peak memory consumption was 24.1MB. Max. memory is 16.1GB. [2024-11-08 17:01:56,119 INFO L158 Benchmark]: TraceAbstraction took 34025.32ms. Allocated memory was 117.4MB in the beginning and 373.3MB in the end (delta: 255.9MB). Free memory was 70.8MB in the beginning and 198.3MB in the end (delta: -127.6MB). Peak memory consumption was 129.0MB. Max. memory is 16.1GB. [2024-11-08 17:01:56,119 INFO L158 Benchmark]: Witness Printer took 330.69ms. Allocated memory is still 373.3MB. Free memory was 198.3MB in the beginning and 159.7MB in the end (delta: 38.6MB). Peak memory consumption was 35.7MB. Max. memory is 16.1GB. [2024-11-08 17:01:56,122 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.43ms. Allocated memory is still 79.7MB. Free memory was 56.4MB in the beginning and 56.3MB in the end (delta: 148.1kB). There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 856.68ms. Allocated memory was 79.7MB in the beginning and 117.4MB in the end (delta: 37.7MB). Free memory was 54.9MB in the beginning and 89.4MB in the end (delta: -34.4MB). Peak memory consumption was 21.0MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 90.82ms. Allocated memory is still 117.4MB. Free memory was 89.4MB in the beginning and 85.7MB in the end (delta: 3.7MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Boogie Preprocessor took 128.62ms. Allocated memory is still 117.4MB. Free memory was 85.7MB in the beginning and 81.0MB in the end (delta: 4.6MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * RCFGBuilder took 1004.68ms. Allocated memory is still 117.4MB. Free memory was 81.0MB in the beginning and 71.3MB in the end (delta: 9.7MB). Peak memory consumption was 24.1MB. Max. memory is 16.1GB. * TraceAbstraction took 34025.32ms. Allocated memory was 117.4MB in the beginning and 373.3MB in the end (delta: 255.9MB). Free memory was 70.8MB in the beginning and 198.3MB in the end (delta: -127.6MB). Peak memory consumption was 129.0MB. Max. memory is 16.1GB. * Witness Printer took 330.69ms. Allocated memory is still 373.3MB. Free memory was 198.3MB in the beginning and 159.7MB in the end (delta: 38.6MB). Peak memory consumption was 35.7MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: ErrorAutomatonStatistics NumberErrorTraces: 0, NumberStatementsAllTraces: 0, NumberRelevantStatements: 0, 0.0s ErrorAutomatonConstructionTimeTotal, 0.0s FaulLocalizationTime, NumberStatementsFirstTrace: -1, TraceLengthAvg: 0, 0.0s ErrorAutomatonConstructionTimeAvg, 0.0s ErrorAutomatonDifferenceTimeAvg, 0.0s ErrorAutomatonDifferenceTimeTotal, NumberOfNoEnhancement: 0, NumberOfFiniteEnhancement: 0, NumberOfInfiniteEnhancement: 0 - CounterExampleResult [Line: 21]: a call to reach_error is reachable a call to reach_error is reachable We found a FailurePath: [L26] const SORT_1 mask_SORT_1 = (SORT_1)-1 >> (sizeof(SORT_1) * 8 - 1); [L27] const SORT_1 msb_SORT_1 = (SORT_1)1 << (1 - 1); [L29] const SORT_9 mask_SORT_9 = (SORT_9)-1 >> (sizeof(SORT_9) * 8 - 31); [L30] const SORT_9 msb_SORT_9 = (SORT_9)1 << (31 - 1); [L32] const SORT_11 mask_SORT_11 = (SORT_11)-1 >> (sizeof(SORT_11) * 8 - 16); [L33] const SORT_11 msb_SORT_11 = (SORT_11)1 << (16 - 1); [L35] const SORT_12 mask_SORT_12 = (SORT_12)-1 >> (sizeof(SORT_12) * 8 - 8); [L36] const SORT_12 msb_SORT_12 = (SORT_12)1 << (8 - 1); [L38] const SORT_20 mask_SORT_20 = (SORT_20)-1 >> (sizeof(SORT_20) * 8 - 32); [L39] const SORT_20 msb_SORT_20 = (SORT_20)1 << (32 - 1); [L41] const SORT_23 mask_SORT_23 = (SORT_23)-1 >> (sizeof(SORT_23) * 8 - 17); [L42] const SORT_23 msb_SORT_23 = (SORT_23)1 << (17 - 1); [L44] const SORT_26 mask_SORT_26 = (SORT_26)-1 >> (sizeof(SORT_26) * 8 - 18); [L45] const SORT_26 msb_SORT_26 = (SORT_26)1 << (18 - 1); [L47] const SORT_29 mask_SORT_29 = (SORT_29)-1 >> (sizeof(SORT_29) * 8 - 19); [L48] const SORT_29 msb_SORT_29 = (SORT_29)1 << (19 - 1); [L50] const SORT_32 mask_SORT_32 = (SORT_32)-1 >> (sizeof(SORT_32) * 8 - 20); [L51] const SORT_32 msb_SORT_32 = (SORT_32)1 << (20 - 1); [L53] const SORT_35 mask_SORT_35 = (SORT_35)-1 >> (sizeof(SORT_35) * 8 - 21); [L54] const SORT_35 msb_SORT_35 = (SORT_35)1 << (21 - 1); [L56] const SORT_38 mask_SORT_38 = (SORT_38)-1 >> (sizeof(SORT_38) * 8 - 22); [L57] const SORT_38 msb_SORT_38 = (SORT_38)1 << (22 - 1); [L59] const SORT_41 mask_SORT_41 = (SORT_41)-1 >> (sizeof(SORT_41) * 8 - 23); [L60] const SORT_41 msb_SORT_41 = (SORT_41)1 << (23 - 1); [L62] const SORT_44 mask_SORT_44 = (SORT_44)-1 >> (sizeof(SORT_44) * 8 - 24); [L63] const SORT_44 msb_SORT_44 = (SORT_44)1 << (24 - 1); [L65] const SORT_47 mask_SORT_47 = (SORT_47)-1 >> (sizeof(SORT_47) * 8 - 25); [L66] const SORT_47 msb_SORT_47 = (SORT_47)1 << (25 - 1); [L68] const SORT_50 mask_SORT_50 = (SORT_50)-1 >> (sizeof(SORT_50) * 8 - 26); [L69] const SORT_50 msb_SORT_50 = (SORT_50)1 << (26 - 1); [L71] const SORT_53 mask_SORT_53 = (SORT_53)-1 >> (sizeof(SORT_53) * 8 - 27); [L72] const SORT_53 msb_SORT_53 = (SORT_53)1 << (27 - 1); [L74] const SORT_56 mask_SORT_56 = (SORT_56)-1 >> (sizeof(SORT_56) * 8 - 28); [L75] const SORT_56 msb_SORT_56 = (SORT_56)1 << (28 - 1); [L77] const SORT_59 mask_SORT_59 = (SORT_59)-1 >> (sizeof(SORT_59) * 8 - 29); [L78] const SORT_59 msb_SORT_59 = (SORT_59)1 << (29 - 1); [L80] const SORT_62 mask_SORT_62 = (SORT_62)-1 >> (sizeof(SORT_62) * 8 - 30); [L81] const SORT_62 msb_SORT_62 = (SORT_62)1 << (30 - 1); [L83] const SORT_72 mask_SORT_72 = (SORT_72)-1 >> (sizeof(SORT_72) * 8 - 3); [L84] const SORT_72 msb_SORT_72 = (SORT_72)1 << (3 - 1); [L86] const SORT_96 mask_SORT_96 = (SORT_96)-1 >> (sizeof(SORT_96) * 8 - 4); [L87] const SORT_96 msb_SORT_96 = (SORT_96)1 << (4 - 1); [L89] const SORT_101 mask_SORT_101 = (SORT_101)-1 >> (sizeof(SORT_101) * 8 - 6); [L90] const SORT_101 msb_SORT_101 = (SORT_101)1 << (6 - 1); [L92] const SORT_1 var_7 = 0; [L93] const SORT_1 var_8 = 1; [L94] const SORT_9 var_10 = 0; [L95] const SORT_12 var_13 = 0; [L96] const SORT_12 var_14 = 200; [L97] const SORT_72 var_73 = 5; [L98] const SORT_11 var_75 = 0; [L99] const SORT_11 var_108 = 200; [L100] const SORT_72 var_113 = 4; [L101] const SORT_72 var_116 = 6; [L102] const SORT_96 var_120 = 9; [L103] const SORT_72 var_137 = 0; [L104] const SORT_96 var_140 = 0; [L106] SORT_1 input_2; [L107] SORT_1 input_3; [L108] SORT_1 input_4; [L110] SORT_1 state_5 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L111] SORT_11 state_17 = __VERIFIER_nondet_ushort() & mask_SORT_11; [L112] SORT_11 state_76 = __VERIFIER_nondet_ushort() & mask_SORT_11; [L113] SORT_96 state_97 = __VERIFIER_nondet_uchar() & mask_SORT_96; [L114] SORT_96 state_100 = __VERIFIER_nondet_uchar() & mask_SORT_96; [L116] SORT_11 init_77_arg_1 = var_75; [L117] state_76 = init_77_arg_1 VAL [mask_SORT_11=-1, mask_SORT_12=-1, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=15, state_17=-986, state_5=1, state_76=0, state_97=1, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=-56, var_73=5, var_75=0, var_7=0, var_8=1] [L120] input_2 = __VERIFIER_nondet_uchar() [L121] input_3 = __VERIFIER_nondet_uchar() [L122] input_3 = input_3 & mask_SORT_1 [L123] input_4 = __VERIFIER_nondet_uchar() [L124] input_4 = input_4 & mask_SORT_1 [L126] SORT_1 var_84_arg_0 = state_5; [L127] SORT_1 var_84 = ~var_84_arg_0; [L128] SORT_1 var_85_arg_0 = var_84; [L129] SORT_1 var_85 = ~var_85_arg_0; [L130] SORT_1 var_86_arg_0 = state_5; [L131] SORT_1 var_86_arg_1 = var_85; [L132] SORT_1 var_86 = var_86_arg_0 | var_86_arg_1; [L133] var_86 = var_86 & mask_SORT_1 [L134] SORT_1 constr_87_arg_0 = var_86; VAL [constr_87_arg_0=1, input_3=1, input_4=1, mask_SORT_11=-1, mask_SORT_12=-1, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=15, state_17=-986, state_76=0, state_97=1, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=-56, var_73=5, var_75=0, var_7=0, var_8=1] [L135] CALL assume_abort_if_not(constr_87_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L135] RET assume_abort_if_not(constr_87_arg_0) VAL [constr_87_arg_0=1, input_3=1, input_4=1, mask_SORT_11=-1, mask_SORT_12=-1, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=15, state_17=-986, state_76=0, state_97=1, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=-56, var_73=5, var_75=0, var_7=0, var_8=1] [L136] SORT_1 var_88_arg_0 = var_8; [L137] var_88_arg_0 = var_88_arg_0 & mask_SORT_1 [L138] SORT_11 var_88 = var_88_arg_0; [L139] SORT_11 var_89_arg_0 = state_76; [L140] SORT_11 var_89_arg_1 = var_88; [L141] SORT_1 var_89 = var_89_arg_0 <= var_89_arg_1; [L142] SORT_1 var_90_arg_0 = input_4; [L143] SORT_1 var_90_arg_1 = var_89; [L144] SORT_1 var_90 = var_90_arg_0 ^ var_90_arg_1; [L145] SORT_1 var_91_arg_0 = var_90; [L146] SORT_1 var_91 = ~var_91_arg_0; [L147] SORT_1 var_92_arg_0 = var_90; [L148] SORT_1 var_92 = ~var_92_arg_0; [L149] SORT_1 var_93_arg_0 = var_91; [L150] SORT_1 var_93_arg_1 = var_92; [L151] SORT_1 var_93 = var_93_arg_0 | var_93_arg_1; [L152] var_93 = var_93 & mask_SORT_1 [L153] SORT_1 constr_94_arg_0 = var_93; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=1, input_4=1, mask_SORT_11=-1, mask_SORT_12=-1, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=15, state_17=-986, state_76=0, state_97=1, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=-56, var_73=5, var_75=0, var_7=0, var_8=1] [L154] CALL assume_abort_if_not(constr_94_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L154] RET assume_abort_if_not(constr_94_arg_0) VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=1, input_4=1, mask_SORT_11=-1, mask_SORT_12=-1, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=15, state_17=-986, state_76=0, state_97=1, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=-56, var_73=5, var_75=0, var_7=0, var_8=1] [L156] SORT_72 var_74_arg_0 = var_73; [L157] var_74_arg_0 = var_74_arg_0 & mask_SORT_72 [L158] SORT_11 var_74 = var_74_arg_0; [L159] SORT_11 var_78_arg_0 = var_74; [L160] SORT_11 var_78_arg_1 = state_76; [L161] SORT_1 var_78 = var_78_arg_0 < var_78_arg_1; [L162] SORT_1 var_15_arg_0 = input_3; [L163] SORT_12 var_15_arg_1 = var_14; [L164] SORT_12 var_15_arg_2 = var_13; [L165] SORT_12 var_15 = var_15_arg_0 ? var_15_arg_1 : var_15_arg_2; [L166] var_15 = var_15 & mask_SORT_12 [L167] SORT_12 var_16_arg_0 = var_13; [L168] SORT_12 var_16_arg_1 = var_15; [L169] SORT_11 var_16 = ((SORT_11)var_16_arg_0 << 8) | var_16_arg_1; [L170] SORT_11 var_18_arg_0 = var_16; [L171] SORT_11 var_18_arg_1 = state_17; [L172] SORT_11 var_18 = var_18_arg_0 - var_18_arg_1; [L173] var_18 = var_18 & mask_SORT_11 [L174] SORT_11 var_19_arg_0 = var_18; [L175] SORT_1 var_19 = var_19_arg_0 >> 15; [L176] SORT_1 var_21_arg_0 = var_19; [L177] SORT_9 var_21_arg_1 = var_10; [L178] SORT_20 var_21 = ((SORT_20)var_21_arg_0 << 31) | var_21_arg_1; [L179] var_21 = var_21 & mask_SORT_20 [L180] SORT_11 var_64_arg_0 = var_18; [L181] SORT_1 var_64 = var_64_arg_0 >> 15; [L182] SORT_11 var_61_arg_0 = var_18; [L183] SORT_1 var_61 = var_61_arg_0 >> 15; [L184] SORT_11 var_58_arg_0 = var_18; [L185] SORT_1 var_58 = var_58_arg_0 >> 15; [L186] SORT_11 var_55_arg_0 = var_18; [L187] SORT_1 var_55 = var_55_arg_0 >> 15; [L188] SORT_11 var_52_arg_0 = var_18; [L189] SORT_1 var_52 = var_52_arg_0 >> 15; [L190] SORT_11 var_49_arg_0 = var_18; [L191] SORT_1 var_49 = var_49_arg_0 >> 15; [L192] SORT_11 var_46_arg_0 = var_18; [L193] SORT_1 var_46 = var_46_arg_0 >> 15; [L194] SORT_11 var_43_arg_0 = var_18; [L195] SORT_1 var_43 = var_43_arg_0 >> 15; [L196] SORT_11 var_40_arg_0 = var_18; [L197] SORT_1 var_40 = var_40_arg_0 >> 15; [L198] SORT_11 var_37_arg_0 = var_18; [L199] SORT_1 var_37 = var_37_arg_0 >> 15; [L200] SORT_11 var_34_arg_0 = var_18; [L201] SORT_1 var_34 = var_34_arg_0 >> 15; [L202] SORT_11 var_31_arg_0 = var_18; [L203] SORT_1 var_31 = var_31_arg_0 >> 15; [L204] SORT_11 var_28_arg_0 = var_18; [L205] SORT_1 var_28 = var_28_arg_0 >> 15; [L206] SORT_11 var_25_arg_0 = var_18; [L207] SORT_1 var_25 = var_25_arg_0 >> 15; [L208] SORT_11 var_22_arg_0 = var_18; [L209] SORT_1 var_22 = var_22_arg_0 >> 15; [L210] SORT_1 var_24_arg_0 = var_22; [L211] SORT_11 var_24_arg_1 = var_18; [L212] SORT_23 var_24 = ((SORT_23)var_24_arg_0 << 16) | var_24_arg_1; [L213] var_24 = var_24 & mask_SORT_23 [L214] SORT_1 var_27_arg_0 = var_25; [L215] SORT_23 var_27_arg_1 = var_24; [L216] SORT_26 var_27 = ((SORT_26)var_27_arg_0 << 17) | var_27_arg_1; [L217] var_27 = var_27 & mask_SORT_26 [L218] SORT_1 var_30_arg_0 = var_28; [L219] SORT_26 var_30_arg_1 = var_27; [L220] SORT_29 var_30 = ((SORT_29)var_30_arg_0 << 18) | var_30_arg_1; [L221] var_30 = var_30 & mask_SORT_29 [L222] SORT_1 var_33_arg_0 = var_31; [L223] SORT_29 var_33_arg_1 = var_30; [L224] SORT_32 var_33 = ((SORT_32)var_33_arg_0 << 19) | var_33_arg_1; [L225] var_33 = var_33 & mask_SORT_32 [L226] SORT_1 var_36_arg_0 = var_34; [L227] SORT_32 var_36_arg_1 = var_33; [L228] SORT_35 var_36 = ((SORT_35)var_36_arg_0 << 20) | var_36_arg_1; [L229] var_36 = var_36 & mask_SORT_35 [L230] SORT_1 var_39_arg_0 = var_37; [L231] SORT_35 var_39_arg_1 = var_36; [L232] SORT_38 var_39 = ((SORT_38)var_39_arg_0 << 21) | var_39_arg_1; [L233] var_39 = var_39 & mask_SORT_38 [L234] SORT_1 var_42_arg_0 = var_40; [L235] SORT_38 var_42_arg_1 = var_39; [L236] SORT_41 var_42 = ((SORT_41)var_42_arg_0 << 22) | var_42_arg_1; [L237] var_42 = var_42 & mask_SORT_41 [L238] SORT_1 var_45_arg_0 = var_43; [L239] SORT_41 var_45_arg_1 = var_42; [L240] SORT_44 var_45 = ((SORT_44)var_45_arg_0 << 23) | var_45_arg_1; [L241] var_45 = var_45 & mask_SORT_44 [L242] SORT_1 var_48_arg_0 = var_46; [L243] SORT_44 var_48_arg_1 = var_45; [L244] SORT_47 var_48 = ((SORT_47)var_48_arg_0 << 24) | var_48_arg_1; [L245] var_48 = var_48 & mask_SORT_47 [L246] SORT_1 var_51_arg_0 = var_49; [L247] SORT_47 var_51_arg_1 = var_48; [L248] SORT_50 var_51 = ((SORT_50)var_51_arg_0 << 25) | var_51_arg_1; [L249] var_51 = var_51 & mask_SORT_50 [L250] SORT_1 var_54_arg_0 = var_52; [L251] SORT_50 var_54_arg_1 = var_51; [L252] SORT_53 var_54 = ((SORT_53)var_54_arg_0 << 26) | var_54_arg_1; [L253] var_54 = var_54 & mask_SORT_53 [L254] SORT_1 var_57_arg_0 = var_55; [L255] SORT_53 var_57_arg_1 = var_54; [L256] SORT_56 var_57 = ((SORT_56)var_57_arg_0 << 27) | var_57_arg_1; [L257] var_57 = var_57 & mask_SORT_56 [L258] SORT_1 var_60_arg_0 = var_58; [L259] SORT_56 var_60_arg_1 = var_57; [L260] SORT_59 var_60 = ((SORT_59)var_60_arg_0 << 28) | var_60_arg_1; [L261] var_60 = var_60 & mask_SORT_59 [L262] SORT_1 var_63_arg_0 = var_61; [L263] SORT_59 var_63_arg_1 = var_60; [L264] SORT_62 var_63 = ((SORT_62)var_63_arg_0 << 29) | var_63_arg_1; [L265] var_63 = var_63 & mask_SORT_62 [L266] SORT_1 var_65_arg_0 = var_64; [L267] SORT_62 var_65_arg_1 = var_63; [L268] SORT_9 var_65 = ((SORT_9)var_65_arg_0 << 30) | var_65_arg_1; [L269] SORT_9 var_66_arg_0 = var_65; [L270] var_66_arg_0 = var_66_arg_0 & mask_SORT_9 [L271] SORT_20 var_66 = var_66_arg_0; [L272] SORT_20 var_67_arg_0 = var_21; [L273] SORT_20 var_67_arg_1 = var_66; [L274] SORT_1 var_67 = var_67_arg_0 <= var_67_arg_1; [L275] SORT_1 var_68_arg_0 = var_67; [L276] SORT_1 var_68_arg_1 = var_8; [L277] SORT_1 var_68_arg_2 = var_7; [L278] SORT_1 var_68 = var_68_arg_0 ? var_68_arg_1 : var_68_arg_2; [L279] var_68 = var_68 & mask_SORT_1 [L280] SORT_1 var_69_arg_0 = input_3; [L281] SORT_1 var_69_arg_1 = var_68; [L282] SORT_1 var_69 = var_69_arg_0 ^ var_69_arg_1; [L283] SORT_1 var_70_arg_0 = var_69; [L284] SORT_1 var_70 = ~var_70_arg_0; [L285] SORT_1 var_79_arg_0 = var_78; [L286] SORT_1 var_79_arg_1 = var_70; [L287] SORT_1 var_79_arg_2 = var_8; [L288] SORT_1 var_79 = var_79_arg_0 ? var_79_arg_1 : var_79_arg_2; [L289] SORT_1 var_80_arg_0 = var_79; [L290] SORT_1 var_80 = ~var_80_arg_0; [L291] SORT_1 var_81_arg_0 = var_79; [L292] SORT_1 var_81 = ~var_81_arg_0; [L293] SORT_1 var_82_arg_0 = var_80; [L294] SORT_1 var_82_arg_1 = var_81; [L295] SORT_1 var_82 = var_82_arg_0 & var_82_arg_1; [L296] var_82 = var_82 & mask_SORT_1 [L297] SORT_1 bad_83_arg_0 = var_82; [L298] CALL __VERIFIER_assert(!(bad_83_arg_0)) [L21] COND FALSE !(!(cond)) [L298] RET __VERIFIER_assert(!(bad_83_arg_0)) [L300] SORT_96 var_121_arg_0 = state_100; [L301] SORT_96 var_121_arg_1 = var_120; [L302] SORT_1 var_121 = var_121_arg_0 == var_121_arg_1; [L303] SORT_72 var_114_arg_0 = var_113; [L304] var_114_arg_0 = var_114_arg_0 & mask_SORT_72 [L305] SORT_96 var_114 = var_114_arg_0; [L306] SORT_96 var_115_arg_0 = var_114; [L307] SORT_96 var_115_arg_1 = state_97; [L308] SORT_1 var_115 = var_115_arg_0 <= var_115_arg_1; [L309] SORT_72 var_117_arg_0 = var_116; [L310] var_117_arg_0 = var_117_arg_0 & mask_SORT_72 [L311] SORT_96 var_117 = var_117_arg_0; [L312] SORT_96 var_118_arg_0 = state_97; [L313] SORT_96 var_118_arg_1 = var_117; [L314] SORT_1 var_118 = var_118_arg_0 <= var_118_arg_1; [L315] SORT_1 var_119_arg_0 = var_115; [L316] SORT_1 var_119_arg_1 = var_118; [L317] SORT_1 var_119 = var_119_arg_0 & var_119_arg_1; [L318] SORT_1 var_122_arg_0 = var_121; [L319] SORT_1 var_122_arg_1 = var_119; [L320] SORT_1 var_122_arg_2 = var_8; [L321] SORT_1 var_122 = var_122_arg_0 ? var_122_arg_1 : var_122_arg_2; [L322] SORT_1 var_123_arg_0 = input_4; [L323] SORT_1 var_123_arg_1 = var_8; [L324] SORT_1 var_123_arg_2 = var_122; [L325] SORT_1 var_123 = var_123_arg_0 ? var_123_arg_1 : var_123_arg_2; [L326] SORT_1 next_124_arg_1 = var_123; [L327] SORT_1 var_127_arg_0 = var_8; [L328] var_127_arg_0 = var_127_arg_0 & mask_SORT_1 [L329] SORT_11 var_127 = var_127_arg_0; [L330] SORT_11 var_128_arg_0 = state_17; [L331] SORT_11 var_128_arg_1 = var_127; [L332] SORT_11 var_128 = var_128_arg_0 + var_128_arg_1; [L333] SORT_1 var_125_arg_0 = var_8; [L334] var_125_arg_0 = var_125_arg_0 & mask_SORT_1 [L335] SORT_11 var_125 = var_125_arg_0; [L336] SORT_11 var_126_arg_0 = state_17; [L337] SORT_11 var_126_arg_1 = var_125; [L338] SORT_11 var_126 = var_126_arg_0 - var_126_arg_1; [L339] SORT_1 var_129_arg_0 = var_68; [L340] SORT_11 var_129_arg_1 = var_128; [L341] SORT_11 var_129_arg_2 = var_126; [L342] SORT_11 var_129 = var_129_arg_0 ? var_129_arg_1 : var_129_arg_2; [L343] SORT_1 var_130_arg_0 = input_4; [L344] SORT_11 var_130_arg_1 = var_75; [L345] SORT_11 var_130_arg_2 = var_129; [L346] SORT_11 var_130 = var_130_arg_0 ? var_130_arg_1 : var_130_arg_2; [L347] SORT_11 next_131_arg_1 = var_130; [L348] SORT_1 var_132_arg_0 = var_8; [L349] var_132_arg_0 = var_132_arg_0 & mask_SORT_1 [L350] SORT_11 var_132 = var_132_arg_0; [L351] SORT_11 var_133_arg_0 = state_76; [L352] SORT_11 var_133_arg_1 = var_132; [L353] SORT_11 var_133 = var_133_arg_0 + var_133_arg_1; [L354] var_133 = var_133 & mask_SORT_11 [L355] SORT_11 next_134_arg_1 = var_133; [L356] SORT_72 var_138_arg_0 = var_137; [L357] SORT_1 var_138_arg_1 = input_3; [L358] SORT_96 var_138 = ((SORT_96)var_138_arg_0 << 1) | var_138_arg_1; [L359] SORT_1 var_135_arg_0 = input_3; [L360] var_135_arg_0 = var_135_arg_0 & mask_SORT_1 [L361] SORT_96 var_135 = var_135_arg_0; [L362] SORT_96 var_136_arg_0 = state_97; [L363] SORT_96 var_136_arg_1 = var_135; [L364] SORT_96 var_136 = var_136_arg_0 + var_136_arg_1; [L365] SORT_1 var_139_arg_0 = var_121; [L366] SORT_96 var_139_arg_1 = var_138; [L367] SORT_96 var_139_arg_2 = var_136; [L368] SORT_96 var_139 = var_139_arg_0 ? var_139_arg_1 : var_139_arg_2; [L369] SORT_1 var_141_arg_0 = input_4; [L370] SORT_96 var_141_arg_1 = var_140; [L371] SORT_96 var_141_arg_2 = var_139; [L372] SORT_96 var_141 = var_141_arg_0 ? var_141_arg_1 : var_141_arg_2; [L373] var_141 = var_141 & mask_SORT_96 [L374] SORT_96 next_142_arg_1 = var_141; [L375] SORT_1 var_143_arg_0 = var_8; [L376] var_143_arg_0 = var_143_arg_0 & mask_SORT_1 [L377] SORT_96 var_143 = var_143_arg_0; [L378] SORT_96 var_144_arg_0 = state_100; [L379] SORT_96 var_144_arg_1 = var_143; [L380] SORT_96 var_144 = var_144_arg_0 + var_144_arg_1; [L381] SORT_1 var_145_arg_0 = var_121; [L382] SORT_96 var_145_arg_1 = var_140; [L383] SORT_96 var_145_arg_2 = var_144; [L384] SORT_96 var_145 = var_145_arg_0 ? var_145_arg_1 : var_145_arg_2; [L385] SORT_1 var_146_arg_0 = input_4; [L386] SORT_96 var_146_arg_1 = var_140; [L387] SORT_96 var_146_arg_2 = var_145; [L388] SORT_96 var_146 = var_146_arg_0 ? var_146_arg_1 : var_146_arg_2; [L389] var_146 = var_146 & mask_SORT_96 [L390] SORT_96 next_147_arg_1 = var_146; [L392] state_5 = next_124_arg_1 [L393] state_17 = next_131_arg_1 [L394] state_76 = next_134_arg_1 [L395] state_97 = next_142_arg_1 [L396] state_100 = next_147_arg_1 [L120] input_2 = __VERIFIER_nondet_uchar() [L121] input_3 = __VERIFIER_nondet_uchar() [L122] input_3 = input_3 & mask_SORT_1 [L123] input_4 = __VERIFIER_nondet_uchar() [L124] input_4 = input_4 & mask_SORT_1 [L126] SORT_1 var_84_arg_0 = state_5; [L127] SORT_1 var_84 = ~var_84_arg_0; [L128] SORT_1 var_85_arg_0 = var_84; [L129] SORT_1 var_85 = ~var_85_arg_0; [L130] SORT_1 var_86_arg_0 = state_5; [L131] SORT_1 var_86_arg_1 = var_85; [L132] SORT_1 var_86 = var_86_arg_0 | var_86_arg_1; [L133] var_86 = var_86 & mask_SORT_1 [L134] SORT_1 constr_87_arg_0 = var_86; VAL [constr_87_arg_0=1, input_3=0, input_4=1, mask_SORT_11=-1, mask_SORT_12=-1, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=1, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=-56, var_73=5, var_75=0, var_7=0, var_8=1] [L135] CALL assume_abort_if_not(constr_87_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L135] RET assume_abort_if_not(constr_87_arg_0) VAL [constr_87_arg_0=1, input_3=0, input_4=1, mask_SORT_11=-1, mask_SORT_12=-1, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=1, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=-56, var_73=5, var_75=0, var_7=0, var_8=1] [L136] SORT_1 var_88_arg_0 = var_8; [L137] var_88_arg_0 = var_88_arg_0 & mask_SORT_1 [L138] SORT_11 var_88 = var_88_arg_0; [L139] SORT_11 var_89_arg_0 = state_76; [L140] SORT_11 var_89_arg_1 = var_88; [L141] SORT_1 var_89 = var_89_arg_0 <= var_89_arg_1; [L142] SORT_1 var_90_arg_0 = input_4; [L143] SORT_1 var_90_arg_1 = var_89; [L144] SORT_1 var_90 = var_90_arg_0 ^ var_90_arg_1; [L145] SORT_1 var_91_arg_0 = var_90; [L146] SORT_1 var_91 = ~var_91_arg_0; [L147] SORT_1 var_92_arg_0 = var_90; [L148] SORT_1 var_92 = ~var_92_arg_0; [L149] SORT_1 var_93_arg_0 = var_91; [L150] SORT_1 var_93_arg_1 = var_92; [L151] SORT_1 var_93 = var_93_arg_0 | var_93_arg_1; [L152] var_93 = var_93 & mask_SORT_1 [L153] SORT_1 constr_94_arg_0 = var_93; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=1, mask_SORT_11=-1, mask_SORT_12=-1, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=1, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=-56, var_73=5, var_75=0, var_7=0, var_8=1] [L154] CALL assume_abort_if_not(constr_94_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L154] RET assume_abort_if_not(constr_94_arg_0) VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=1, mask_SORT_11=-1, mask_SORT_12=-1, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=1, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=-56, var_73=5, var_75=0, var_7=0, var_8=1] [L156] SORT_72 var_74_arg_0 = var_73; [L157] var_74_arg_0 = var_74_arg_0 & mask_SORT_72 [L158] SORT_11 var_74 = var_74_arg_0; [L159] SORT_11 var_78_arg_0 = var_74; [L160] SORT_11 var_78_arg_1 = state_76; [L161] SORT_1 var_78 = var_78_arg_0 < var_78_arg_1; [L162] SORT_1 var_15_arg_0 = input_3; [L163] SORT_12 var_15_arg_1 = var_14; [L164] SORT_12 var_15_arg_2 = var_13; [L165] SORT_12 var_15 = var_15_arg_0 ? var_15_arg_1 : var_15_arg_2; [L166] var_15 = var_15 & mask_SORT_12 [L167] SORT_12 var_16_arg_0 = var_13; [L168] SORT_12 var_16_arg_1 = var_15; [L169] SORT_11 var_16 = ((SORT_11)var_16_arg_0 << 8) | var_16_arg_1; [L170] SORT_11 var_18_arg_0 = var_16; [L171] SORT_11 var_18_arg_1 = state_17; [L172] SORT_11 var_18 = var_18_arg_0 - var_18_arg_1; [L173] var_18 = var_18 & mask_SORT_11 [L174] SORT_11 var_19_arg_0 = var_18; [L175] SORT_1 var_19 = var_19_arg_0 >> 15; [L176] SORT_1 var_21_arg_0 = var_19; [L177] SORT_9 var_21_arg_1 = var_10; [L178] SORT_20 var_21 = ((SORT_20)var_21_arg_0 << 31) | var_21_arg_1; [L179] var_21 = var_21 & mask_SORT_20 [L180] SORT_11 var_64_arg_0 = var_18; [L181] SORT_1 var_64 = var_64_arg_0 >> 15; [L182] SORT_11 var_61_arg_0 = var_18; [L183] SORT_1 var_61 = var_61_arg_0 >> 15; [L184] SORT_11 var_58_arg_0 = var_18; [L185] SORT_1 var_58 = var_58_arg_0 >> 15; [L186] SORT_11 var_55_arg_0 = var_18; [L187] SORT_1 var_55 = var_55_arg_0 >> 15; [L188] SORT_11 var_52_arg_0 = var_18; [L189] SORT_1 var_52 = var_52_arg_0 >> 15; [L190] SORT_11 var_49_arg_0 = var_18; [L191] SORT_1 var_49 = var_49_arg_0 >> 15; [L192] SORT_11 var_46_arg_0 = var_18; [L193] SORT_1 var_46 = var_46_arg_0 >> 15; [L194] SORT_11 var_43_arg_0 = var_18; [L195] SORT_1 var_43 = var_43_arg_0 >> 15; [L196] SORT_11 var_40_arg_0 = var_18; [L197] SORT_1 var_40 = var_40_arg_0 >> 15; [L198] SORT_11 var_37_arg_0 = var_18; [L199] SORT_1 var_37 = var_37_arg_0 >> 15; [L200] SORT_11 var_34_arg_0 = var_18; [L201] SORT_1 var_34 = var_34_arg_0 >> 15; [L202] SORT_11 var_31_arg_0 = var_18; [L203] SORT_1 var_31 = var_31_arg_0 >> 15; [L204] SORT_11 var_28_arg_0 = var_18; [L205] SORT_1 var_28 = var_28_arg_0 >> 15; [L206] SORT_11 var_25_arg_0 = var_18; [L207] SORT_1 var_25 = var_25_arg_0 >> 15; [L208] SORT_11 var_22_arg_0 = var_18; [L209] SORT_1 var_22 = var_22_arg_0 >> 15; [L210] SORT_1 var_24_arg_0 = var_22; [L211] SORT_11 var_24_arg_1 = var_18; [L212] SORT_23 var_24 = ((SORT_23)var_24_arg_0 << 16) | var_24_arg_1; [L213] var_24 = var_24 & mask_SORT_23 [L214] SORT_1 var_27_arg_0 = var_25; [L215] SORT_23 var_27_arg_1 = var_24; [L216] SORT_26 var_27 = ((SORT_26)var_27_arg_0 << 17) | var_27_arg_1; [L217] var_27 = var_27 & mask_SORT_26 [L218] SORT_1 var_30_arg_0 = var_28; [L219] SORT_26 var_30_arg_1 = var_27; [L220] SORT_29 var_30 = ((SORT_29)var_30_arg_0 << 18) | var_30_arg_1; [L221] var_30 = var_30 & mask_SORT_29 [L222] SORT_1 var_33_arg_0 = var_31; [L223] SORT_29 var_33_arg_1 = var_30; [L224] SORT_32 var_33 = ((SORT_32)var_33_arg_0 << 19) | var_33_arg_1; [L225] var_33 = var_33 & mask_SORT_32 [L226] SORT_1 var_36_arg_0 = var_34; [L227] SORT_32 var_36_arg_1 = var_33; [L228] SORT_35 var_36 = ((SORT_35)var_36_arg_0 << 20) | var_36_arg_1; [L229] var_36 = var_36 & mask_SORT_35 [L230] SORT_1 var_39_arg_0 = var_37; [L231] SORT_35 var_39_arg_1 = var_36; [L232] SORT_38 var_39 = ((SORT_38)var_39_arg_0 << 21) | var_39_arg_1; [L233] var_39 = var_39 & mask_SORT_38 [L234] SORT_1 var_42_arg_0 = var_40; [L235] SORT_38 var_42_arg_1 = var_39; [L236] SORT_41 var_42 = ((SORT_41)var_42_arg_0 << 22) | var_42_arg_1; [L237] var_42 = var_42 & mask_SORT_41 [L238] SORT_1 var_45_arg_0 = var_43; [L239] SORT_41 var_45_arg_1 = var_42; [L240] SORT_44 var_45 = ((SORT_44)var_45_arg_0 << 23) | var_45_arg_1; [L241] var_45 = var_45 & mask_SORT_44 [L242] SORT_1 var_48_arg_0 = var_46; [L243] SORT_44 var_48_arg_1 = var_45; [L244] SORT_47 var_48 = ((SORT_47)var_48_arg_0 << 24) | var_48_arg_1; [L245] var_48 = var_48 & mask_SORT_47 [L246] SORT_1 var_51_arg_0 = var_49; [L247] SORT_47 var_51_arg_1 = var_48; [L248] SORT_50 var_51 = ((SORT_50)var_51_arg_0 << 25) | var_51_arg_1; [L249] var_51 = var_51 & mask_SORT_50 [L250] SORT_1 var_54_arg_0 = var_52; [L251] SORT_50 var_54_arg_1 = var_51; [L252] SORT_53 var_54 = ((SORT_53)var_54_arg_0 << 26) | var_54_arg_1; [L253] var_54 = var_54 & mask_SORT_53 [L254] SORT_1 var_57_arg_0 = var_55; [L255] SORT_53 var_57_arg_1 = var_54; [L256] SORT_56 var_57 = ((SORT_56)var_57_arg_0 << 27) | var_57_arg_1; [L257] var_57 = var_57 & mask_SORT_56 [L258] SORT_1 var_60_arg_0 = var_58; [L259] SORT_56 var_60_arg_1 = var_57; [L260] SORT_59 var_60 = ((SORT_59)var_60_arg_0 << 28) | var_60_arg_1; [L261] var_60 = var_60 & mask_SORT_59 [L262] SORT_1 var_63_arg_0 = var_61; [L263] SORT_59 var_63_arg_1 = var_60; [L264] SORT_62 var_63 = ((SORT_62)var_63_arg_0 << 29) | var_63_arg_1; [L265] var_63 = var_63 & mask_SORT_62 [L266] SORT_1 var_65_arg_0 = var_64; [L267] SORT_62 var_65_arg_1 = var_63; [L268] SORT_9 var_65 = ((SORT_9)var_65_arg_0 << 30) | var_65_arg_1; [L269] SORT_9 var_66_arg_0 = var_65; [L270] var_66_arg_0 = var_66_arg_0 & mask_SORT_9 [L271] SORT_20 var_66 = var_66_arg_0; [L272] SORT_20 var_67_arg_0 = var_21; [L273] SORT_20 var_67_arg_1 = var_66; [L274] SORT_1 var_67 = var_67_arg_0 <= var_67_arg_1; [L275] SORT_1 var_68_arg_0 = var_67; [L276] SORT_1 var_68_arg_1 = var_8; [L277] SORT_1 var_68_arg_2 = var_7; [L278] SORT_1 var_68 = var_68_arg_0 ? var_68_arg_1 : var_68_arg_2; [L279] var_68 = var_68 & mask_SORT_1 [L280] SORT_1 var_69_arg_0 = input_3; [L281] SORT_1 var_69_arg_1 = var_68; [L282] SORT_1 var_69 = var_69_arg_0 ^ var_69_arg_1; [L283] SORT_1 var_70_arg_0 = var_69; [L284] SORT_1 var_70 = ~var_70_arg_0; [L285] SORT_1 var_79_arg_0 = var_78; [L286] SORT_1 var_79_arg_1 = var_70; [L287] SORT_1 var_79_arg_2 = var_8; [L288] SORT_1 var_79 = var_79_arg_0 ? var_79_arg_1 : var_79_arg_2; [L289] SORT_1 var_80_arg_0 = var_79; [L290] SORT_1 var_80 = ~var_80_arg_0; [L291] SORT_1 var_81_arg_0 = var_79; [L292] SORT_1 var_81 = ~var_81_arg_0; [L293] SORT_1 var_82_arg_0 = var_80; [L294] SORT_1 var_82_arg_1 = var_81; [L295] SORT_1 var_82 = var_82_arg_0 & var_82_arg_1; [L296] var_82 = var_82 & mask_SORT_1 [L297] SORT_1 bad_83_arg_0 = var_82; [L298] CALL __VERIFIER_assert(!(bad_83_arg_0)) [L21] COND FALSE !(!(cond)) [L298] RET __VERIFIER_assert(!(bad_83_arg_0)) [L300] SORT_96 var_121_arg_0 = state_100; [L301] SORT_96 var_121_arg_1 = var_120; [L302] SORT_1 var_121 = var_121_arg_0 == var_121_arg_1; [L303] SORT_72 var_114_arg_0 = var_113; [L304] var_114_arg_0 = var_114_arg_0 & mask_SORT_72 [L305] SORT_96 var_114 = var_114_arg_0; [L306] SORT_96 var_115_arg_0 = var_114; [L307] SORT_96 var_115_arg_1 = state_97; [L308] SORT_1 var_115 = var_115_arg_0 <= var_115_arg_1; [L309] SORT_72 var_117_arg_0 = var_116; [L310] var_117_arg_0 = var_117_arg_0 & mask_SORT_72 [L311] SORT_96 var_117 = var_117_arg_0; [L312] SORT_96 var_118_arg_0 = state_97; [L313] SORT_96 var_118_arg_1 = var_117; [L314] SORT_1 var_118 = var_118_arg_0 <= var_118_arg_1; [L315] SORT_1 var_119_arg_0 = var_115; [L316] SORT_1 var_119_arg_1 = var_118; [L317] SORT_1 var_119 = var_119_arg_0 & var_119_arg_1; [L318] SORT_1 var_122_arg_0 = var_121; [L319] SORT_1 var_122_arg_1 = var_119; [L320] SORT_1 var_122_arg_2 = var_8; [L321] SORT_1 var_122 = var_122_arg_0 ? var_122_arg_1 : var_122_arg_2; [L322] SORT_1 var_123_arg_0 = input_4; [L323] SORT_1 var_123_arg_1 = var_8; [L324] SORT_1 var_123_arg_2 = var_122; [L325] SORT_1 var_123 = var_123_arg_0 ? var_123_arg_1 : var_123_arg_2; [L326] SORT_1 next_124_arg_1 = var_123; [L327] SORT_1 var_127_arg_0 = var_8; [L328] var_127_arg_0 = var_127_arg_0 & mask_SORT_1 [L329] SORT_11 var_127 = var_127_arg_0; [L330] SORT_11 var_128_arg_0 = state_17; [L331] SORT_11 var_128_arg_1 = var_127; [L332] SORT_11 var_128 = var_128_arg_0 + var_128_arg_1; [L333] SORT_1 var_125_arg_0 = var_8; [L334] var_125_arg_0 = var_125_arg_0 & mask_SORT_1 [L335] SORT_11 var_125 = var_125_arg_0; [L336] SORT_11 var_126_arg_0 = state_17; [L337] SORT_11 var_126_arg_1 = var_125; [L338] SORT_11 var_126 = var_126_arg_0 - var_126_arg_1; [L339] SORT_1 var_129_arg_0 = var_68; [L340] SORT_11 var_129_arg_1 = var_128; [L341] SORT_11 var_129_arg_2 = var_126; [L342] SORT_11 var_129 = var_129_arg_0 ? var_129_arg_1 : var_129_arg_2; [L343] SORT_1 var_130_arg_0 = input_4; [L344] SORT_11 var_130_arg_1 = var_75; [L345] SORT_11 var_130_arg_2 = var_129; [L346] SORT_11 var_130 = var_130_arg_0 ? var_130_arg_1 : var_130_arg_2; [L347] SORT_11 next_131_arg_1 = var_130; [L348] SORT_1 var_132_arg_0 = var_8; [L349] var_132_arg_0 = var_132_arg_0 & mask_SORT_1 [L350] SORT_11 var_132 = var_132_arg_0; [L351] SORT_11 var_133_arg_0 = state_76; [L352] SORT_11 var_133_arg_1 = var_132; [L353] SORT_11 var_133 = var_133_arg_0 + var_133_arg_1; [L354] var_133 = var_133 & mask_SORT_11 [L355] SORT_11 next_134_arg_1 = var_133; [L356] SORT_72 var_138_arg_0 = var_137; [L357] SORT_1 var_138_arg_1 = input_3; [L358] SORT_96 var_138 = ((SORT_96)var_138_arg_0 << 1) | var_138_arg_1; [L359] SORT_1 var_135_arg_0 = input_3; [L360] var_135_arg_0 = var_135_arg_0 & mask_SORT_1 [L361] SORT_96 var_135 = var_135_arg_0; [L362] SORT_96 var_136_arg_0 = state_97; [L363] SORT_96 var_136_arg_1 = var_135; [L364] SORT_96 var_136 = var_136_arg_0 + var_136_arg_1; [L365] SORT_1 var_139_arg_0 = var_121; [L366] SORT_96 var_139_arg_1 = var_138; [L367] SORT_96 var_139_arg_2 = var_136; [L368] SORT_96 var_139 = var_139_arg_0 ? var_139_arg_1 : var_139_arg_2; [L369] SORT_1 var_141_arg_0 = input_4; [L370] SORT_96 var_141_arg_1 = var_140; [L371] SORT_96 var_141_arg_2 = var_139; [L372] SORT_96 var_141 = var_141_arg_0 ? var_141_arg_1 : var_141_arg_2; [L373] var_141 = var_141 & mask_SORT_96 [L374] SORT_96 next_142_arg_1 = var_141; [L375] SORT_1 var_143_arg_0 = var_8; [L376] var_143_arg_0 = var_143_arg_0 & mask_SORT_1 [L377] SORT_96 var_143 = var_143_arg_0; [L378] SORT_96 var_144_arg_0 = state_100; [L379] SORT_96 var_144_arg_1 = var_143; [L380] SORT_96 var_144 = var_144_arg_0 + var_144_arg_1; [L381] SORT_1 var_145_arg_0 = var_121; [L382] SORT_96 var_145_arg_1 = var_140; [L383] SORT_96 var_145_arg_2 = var_144; [L384] SORT_96 var_145 = var_145_arg_0 ? var_145_arg_1 : var_145_arg_2; [L385] SORT_1 var_146_arg_0 = input_4; [L386] SORT_96 var_146_arg_1 = var_140; [L387] SORT_96 var_146_arg_2 = var_145; [L388] SORT_96 var_146 = var_146_arg_0 ? var_146_arg_1 : var_146_arg_2; [L389] var_146 = var_146 & mask_SORT_96 [L390] SORT_96 next_147_arg_1 = var_146; [L392] state_5 = next_124_arg_1 [L393] state_17 = next_131_arg_1 [L394] state_76 = next_134_arg_1 [L395] state_97 = next_142_arg_1 [L396] state_100 = next_147_arg_1 [L120] input_2 = __VERIFIER_nondet_uchar() [L121] input_3 = __VERIFIER_nondet_uchar() [L122] input_3 = input_3 & mask_SORT_1 [L123] input_4 = __VERIFIER_nondet_uchar() [L124] input_4 = input_4 & mask_SORT_1 [L126] SORT_1 var_84_arg_0 = state_5; [L127] SORT_1 var_84 = ~var_84_arg_0; [L128] SORT_1 var_85_arg_0 = var_84; [L129] SORT_1 var_85 = ~var_85_arg_0; [L130] SORT_1 var_86_arg_0 = state_5; [L131] SORT_1 var_86_arg_1 = var_85; [L132] SORT_1 var_86 = var_86_arg_0 | var_86_arg_1; [L133] var_86 = var_86 & mask_SORT_1 [L134] SORT_1 constr_87_arg_0 = var_86; VAL [constr_87_arg_0=1, input_3=0, input_4=0, mask_SORT_11=-1, mask_SORT_12=-1, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=2, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=-56, var_73=5, var_75=0, var_7=0, var_8=1] [L135] CALL assume_abort_if_not(constr_87_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L135] RET assume_abort_if_not(constr_87_arg_0) VAL [constr_87_arg_0=1, input_3=0, input_4=0, mask_SORT_11=-1, mask_SORT_12=-1, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=2, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=-56, var_73=5, var_75=0, var_7=0, var_8=1] [L136] SORT_1 var_88_arg_0 = var_8; [L137] var_88_arg_0 = var_88_arg_0 & mask_SORT_1 [L138] SORT_11 var_88 = var_88_arg_0; [L139] SORT_11 var_89_arg_0 = state_76; [L140] SORT_11 var_89_arg_1 = var_88; [L141] SORT_1 var_89 = var_89_arg_0 <= var_89_arg_1; [L142] SORT_1 var_90_arg_0 = input_4; [L143] SORT_1 var_90_arg_1 = var_89; [L144] SORT_1 var_90 = var_90_arg_0 ^ var_90_arg_1; [L145] SORT_1 var_91_arg_0 = var_90; [L146] SORT_1 var_91 = ~var_91_arg_0; [L147] SORT_1 var_92_arg_0 = var_90; [L148] SORT_1 var_92 = ~var_92_arg_0; [L149] SORT_1 var_93_arg_0 = var_91; [L150] SORT_1 var_93_arg_1 = var_92; [L151] SORT_1 var_93 = var_93_arg_0 | var_93_arg_1; [L152] var_93 = var_93 & mask_SORT_1 [L153] SORT_1 constr_94_arg_0 = var_93; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=-1, mask_SORT_12=-1, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=2, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=-56, var_73=5, var_75=0, var_7=0, var_8=1] [L154] CALL assume_abort_if_not(constr_94_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L154] RET assume_abort_if_not(constr_94_arg_0) VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=-1, mask_SORT_12=-1, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=0, state_17=0, state_76=2, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=-56, var_73=5, var_75=0, var_7=0, var_8=1] [L156] SORT_72 var_74_arg_0 = var_73; [L157] var_74_arg_0 = var_74_arg_0 & mask_SORT_72 [L158] SORT_11 var_74 = var_74_arg_0; [L159] SORT_11 var_78_arg_0 = var_74; [L160] SORT_11 var_78_arg_1 = state_76; [L161] SORT_1 var_78 = var_78_arg_0 < var_78_arg_1; [L162] SORT_1 var_15_arg_0 = input_3; [L163] SORT_12 var_15_arg_1 = var_14; [L164] SORT_12 var_15_arg_2 = var_13; [L165] SORT_12 var_15 = var_15_arg_0 ? var_15_arg_1 : var_15_arg_2; [L166] var_15 = var_15 & mask_SORT_12 [L167] SORT_12 var_16_arg_0 = var_13; [L168] SORT_12 var_16_arg_1 = var_15; [L169] SORT_11 var_16 = ((SORT_11)var_16_arg_0 << 8) | var_16_arg_1; [L170] SORT_11 var_18_arg_0 = var_16; [L171] SORT_11 var_18_arg_1 = state_17; [L172] SORT_11 var_18 = var_18_arg_0 - var_18_arg_1; [L173] var_18 = var_18 & mask_SORT_11 [L174] SORT_11 var_19_arg_0 = var_18; [L175] SORT_1 var_19 = var_19_arg_0 >> 15; [L176] SORT_1 var_21_arg_0 = var_19; [L177] SORT_9 var_21_arg_1 = var_10; [L178] SORT_20 var_21 = ((SORT_20)var_21_arg_0 << 31) | var_21_arg_1; [L179] var_21 = var_21 & mask_SORT_20 [L180] SORT_11 var_64_arg_0 = var_18; [L181] SORT_1 var_64 = var_64_arg_0 >> 15; [L182] SORT_11 var_61_arg_0 = var_18; [L183] SORT_1 var_61 = var_61_arg_0 >> 15; [L184] SORT_11 var_58_arg_0 = var_18; [L185] SORT_1 var_58 = var_58_arg_0 >> 15; [L186] SORT_11 var_55_arg_0 = var_18; [L187] SORT_1 var_55 = var_55_arg_0 >> 15; [L188] SORT_11 var_52_arg_0 = var_18; [L189] SORT_1 var_52 = var_52_arg_0 >> 15; [L190] SORT_11 var_49_arg_0 = var_18; [L191] SORT_1 var_49 = var_49_arg_0 >> 15; [L192] SORT_11 var_46_arg_0 = var_18; [L193] SORT_1 var_46 = var_46_arg_0 >> 15; [L194] SORT_11 var_43_arg_0 = var_18; [L195] SORT_1 var_43 = var_43_arg_0 >> 15; [L196] SORT_11 var_40_arg_0 = var_18; [L197] SORT_1 var_40 = var_40_arg_0 >> 15; [L198] SORT_11 var_37_arg_0 = var_18; [L199] SORT_1 var_37 = var_37_arg_0 >> 15; [L200] SORT_11 var_34_arg_0 = var_18; [L201] SORT_1 var_34 = var_34_arg_0 >> 15; [L202] SORT_11 var_31_arg_0 = var_18; [L203] SORT_1 var_31 = var_31_arg_0 >> 15; [L204] SORT_11 var_28_arg_0 = var_18; [L205] SORT_1 var_28 = var_28_arg_0 >> 15; [L206] SORT_11 var_25_arg_0 = var_18; [L207] SORT_1 var_25 = var_25_arg_0 >> 15; [L208] SORT_11 var_22_arg_0 = var_18; [L209] SORT_1 var_22 = var_22_arg_0 >> 15; [L210] SORT_1 var_24_arg_0 = var_22; [L211] SORT_11 var_24_arg_1 = var_18; [L212] SORT_23 var_24 = ((SORT_23)var_24_arg_0 << 16) | var_24_arg_1; [L213] var_24 = var_24 & mask_SORT_23 [L214] SORT_1 var_27_arg_0 = var_25; [L215] SORT_23 var_27_arg_1 = var_24; [L216] SORT_26 var_27 = ((SORT_26)var_27_arg_0 << 17) | var_27_arg_1; [L217] var_27 = var_27 & mask_SORT_26 [L218] SORT_1 var_30_arg_0 = var_28; [L219] SORT_26 var_30_arg_1 = var_27; [L220] SORT_29 var_30 = ((SORT_29)var_30_arg_0 << 18) | var_30_arg_1; [L221] var_30 = var_30 & mask_SORT_29 [L222] SORT_1 var_33_arg_0 = var_31; [L223] SORT_29 var_33_arg_1 = var_30; [L224] SORT_32 var_33 = ((SORT_32)var_33_arg_0 << 19) | var_33_arg_1; [L225] var_33 = var_33 & mask_SORT_32 [L226] SORT_1 var_36_arg_0 = var_34; [L227] SORT_32 var_36_arg_1 = var_33; [L228] SORT_35 var_36 = ((SORT_35)var_36_arg_0 << 20) | var_36_arg_1; [L229] var_36 = var_36 & mask_SORT_35 [L230] SORT_1 var_39_arg_0 = var_37; [L231] SORT_35 var_39_arg_1 = var_36; [L232] SORT_38 var_39 = ((SORT_38)var_39_arg_0 << 21) | var_39_arg_1; [L233] var_39 = var_39 & mask_SORT_38 [L234] SORT_1 var_42_arg_0 = var_40; [L235] SORT_38 var_42_arg_1 = var_39; [L236] SORT_41 var_42 = ((SORT_41)var_42_arg_0 << 22) | var_42_arg_1; [L237] var_42 = var_42 & mask_SORT_41 [L238] SORT_1 var_45_arg_0 = var_43; [L239] SORT_41 var_45_arg_1 = var_42; [L240] SORT_44 var_45 = ((SORT_44)var_45_arg_0 << 23) | var_45_arg_1; [L241] var_45 = var_45 & mask_SORT_44 [L242] SORT_1 var_48_arg_0 = var_46; [L243] SORT_44 var_48_arg_1 = var_45; [L244] SORT_47 var_48 = ((SORT_47)var_48_arg_0 << 24) | var_48_arg_1; [L245] var_48 = var_48 & mask_SORT_47 [L246] SORT_1 var_51_arg_0 = var_49; [L247] SORT_47 var_51_arg_1 = var_48; [L248] SORT_50 var_51 = ((SORT_50)var_51_arg_0 << 25) | var_51_arg_1; [L249] var_51 = var_51 & mask_SORT_50 [L250] SORT_1 var_54_arg_0 = var_52; [L251] SORT_50 var_54_arg_1 = var_51; [L252] SORT_53 var_54 = ((SORT_53)var_54_arg_0 << 26) | var_54_arg_1; [L253] var_54 = var_54 & mask_SORT_53 [L254] SORT_1 var_57_arg_0 = var_55; [L255] SORT_53 var_57_arg_1 = var_54; [L256] SORT_56 var_57 = ((SORT_56)var_57_arg_0 << 27) | var_57_arg_1; [L257] var_57 = var_57 & mask_SORT_56 [L258] SORT_1 var_60_arg_0 = var_58; [L259] SORT_56 var_60_arg_1 = var_57; [L260] SORT_59 var_60 = ((SORT_59)var_60_arg_0 << 28) | var_60_arg_1; [L261] var_60 = var_60 & mask_SORT_59 [L262] SORT_1 var_63_arg_0 = var_61; [L263] SORT_59 var_63_arg_1 = var_60; [L264] SORT_62 var_63 = ((SORT_62)var_63_arg_0 << 29) | var_63_arg_1; [L265] var_63 = var_63 & mask_SORT_62 [L266] SORT_1 var_65_arg_0 = var_64; [L267] SORT_62 var_65_arg_1 = var_63; [L268] SORT_9 var_65 = ((SORT_9)var_65_arg_0 << 30) | var_65_arg_1; [L269] SORT_9 var_66_arg_0 = var_65; [L270] var_66_arg_0 = var_66_arg_0 & mask_SORT_9 [L271] SORT_20 var_66 = var_66_arg_0; [L272] SORT_20 var_67_arg_0 = var_21; [L273] SORT_20 var_67_arg_1 = var_66; [L274] SORT_1 var_67 = var_67_arg_0 <= var_67_arg_1; [L275] SORT_1 var_68_arg_0 = var_67; [L276] SORT_1 var_68_arg_1 = var_8; [L277] SORT_1 var_68_arg_2 = var_7; [L278] SORT_1 var_68 = var_68_arg_0 ? var_68_arg_1 : var_68_arg_2; [L279] var_68 = var_68 & mask_SORT_1 [L280] SORT_1 var_69_arg_0 = input_3; [L281] SORT_1 var_69_arg_1 = var_68; [L282] SORT_1 var_69 = var_69_arg_0 ^ var_69_arg_1; [L283] SORT_1 var_70_arg_0 = var_69; [L284] SORT_1 var_70 = ~var_70_arg_0; [L285] SORT_1 var_79_arg_0 = var_78; [L286] SORT_1 var_79_arg_1 = var_70; [L287] SORT_1 var_79_arg_2 = var_8; [L288] SORT_1 var_79 = var_79_arg_0 ? var_79_arg_1 : var_79_arg_2; [L289] SORT_1 var_80_arg_0 = var_79; [L290] SORT_1 var_80 = ~var_80_arg_0; [L291] SORT_1 var_81_arg_0 = var_79; [L292] SORT_1 var_81 = ~var_81_arg_0; [L293] SORT_1 var_82_arg_0 = var_80; [L294] SORT_1 var_82_arg_1 = var_81; [L295] SORT_1 var_82 = var_82_arg_0 & var_82_arg_1; [L296] var_82 = var_82 & mask_SORT_1 [L297] SORT_1 bad_83_arg_0 = var_82; [L298] CALL __VERIFIER_assert(!(bad_83_arg_0)) [L21] COND FALSE !(!(cond)) [L298] RET __VERIFIER_assert(!(bad_83_arg_0)) [L300] SORT_96 var_121_arg_0 = state_100; [L301] SORT_96 var_121_arg_1 = var_120; [L302] SORT_1 var_121 = var_121_arg_0 == var_121_arg_1; [L303] SORT_72 var_114_arg_0 = var_113; [L304] var_114_arg_0 = var_114_arg_0 & mask_SORT_72 [L305] SORT_96 var_114 = var_114_arg_0; [L306] SORT_96 var_115_arg_0 = var_114; [L307] SORT_96 var_115_arg_1 = state_97; [L308] SORT_1 var_115 = var_115_arg_0 <= var_115_arg_1; [L309] SORT_72 var_117_arg_0 = var_116; [L310] var_117_arg_0 = var_117_arg_0 & mask_SORT_72 [L311] SORT_96 var_117 = var_117_arg_0; [L312] SORT_96 var_118_arg_0 = state_97; [L313] SORT_96 var_118_arg_1 = var_117; [L314] SORT_1 var_118 = var_118_arg_0 <= var_118_arg_1; [L315] SORT_1 var_119_arg_0 = var_115; [L316] SORT_1 var_119_arg_1 = var_118; [L317] SORT_1 var_119 = var_119_arg_0 & var_119_arg_1; [L318] SORT_1 var_122_arg_0 = var_121; [L319] SORT_1 var_122_arg_1 = var_119; [L320] SORT_1 var_122_arg_2 = var_8; [L321] SORT_1 var_122 = var_122_arg_0 ? var_122_arg_1 : var_122_arg_2; [L322] SORT_1 var_123_arg_0 = input_4; [L323] SORT_1 var_123_arg_1 = var_8; [L324] SORT_1 var_123_arg_2 = var_122; [L325] SORT_1 var_123 = var_123_arg_0 ? var_123_arg_1 : var_123_arg_2; [L326] SORT_1 next_124_arg_1 = var_123; [L327] SORT_1 var_127_arg_0 = var_8; [L328] var_127_arg_0 = var_127_arg_0 & mask_SORT_1 [L329] SORT_11 var_127 = var_127_arg_0; [L330] SORT_11 var_128_arg_0 = state_17; [L331] SORT_11 var_128_arg_1 = var_127; [L332] SORT_11 var_128 = var_128_arg_0 + var_128_arg_1; [L333] SORT_1 var_125_arg_0 = var_8; [L334] var_125_arg_0 = var_125_arg_0 & mask_SORT_1 [L335] SORT_11 var_125 = var_125_arg_0; [L336] SORT_11 var_126_arg_0 = state_17; [L337] SORT_11 var_126_arg_1 = var_125; [L338] SORT_11 var_126 = var_126_arg_0 - var_126_arg_1; [L339] SORT_1 var_129_arg_0 = var_68; [L340] SORT_11 var_129_arg_1 = var_128; [L341] SORT_11 var_129_arg_2 = var_126; [L342] SORT_11 var_129 = var_129_arg_0 ? var_129_arg_1 : var_129_arg_2; [L343] SORT_1 var_130_arg_0 = input_4; [L344] SORT_11 var_130_arg_1 = var_75; [L345] SORT_11 var_130_arg_2 = var_129; [L346] SORT_11 var_130 = var_130_arg_0 ? var_130_arg_1 : var_130_arg_2; [L347] SORT_11 next_131_arg_1 = var_130; [L348] SORT_1 var_132_arg_0 = var_8; [L349] var_132_arg_0 = var_132_arg_0 & mask_SORT_1 [L350] SORT_11 var_132 = var_132_arg_0; [L351] SORT_11 var_133_arg_0 = state_76; [L352] SORT_11 var_133_arg_1 = var_132; [L353] SORT_11 var_133 = var_133_arg_0 + var_133_arg_1; [L354] var_133 = var_133 & mask_SORT_11 [L355] SORT_11 next_134_arg_1 = var_133; [L356] SORT_72 var_138_arg_0 = var_137; [L357] SORT_1 var_138_arg_1 = input_3; [L358] SORT_96 var_138 = ((SORT_96)var_138_arg_0 << 1) | var_138_arg_1; [L359] SORT_1 var_135_arg_0 = input_3; [L360] var_135_arg_0 = var_135_arg_0 & mask_SORT_1 [L361] SORT_96 var_135 = var_135_arg_0; [L362] SORT_96 var_136_arg_0 = state_97; [L363] SORT_96 var_136_arg_1 = var_135; [L364] SORT_96 var_136 = var_136_arg_0 + var_136_arg_1; [L365] SORT_1 var_139_arg_0 = var_121; [L366] SORT_96 var_139_arg_1 = var_138; [L367] SORT_96 var_139_arg_2 = var_136; [L368] SORT_96 var_139 = var_139_arg_0 ? var_139_arg_1 : var_139_arg_2; [L369] SORT_1 var_141_arg_0 = input_4; [L370] SORT_96 var_141_arg_1 = var_140; [L371] SORT_96 var_141_arg_2 = var_139; [L372] SORT_96 var_141 = var_141_arg_0 ? var_141_arg_1 : var_141_arg_2; [L373] var_141 = var_141 & mask_SORT_96 [L374] SORT_96 next_142_arg_1 = var_141; [L375] SORT_1 var_143_arg_0 = var_8; [L376] var_143_arg_0 = var_143_arg_0 & mask_SORT_1 [L377] SORT_96 var_143 = var_143_arg_0; [L378] SORT_96 var_144_arg_0 = state_100; [L379] SORT_96 var_144_arg_1 = var_143; [L380] SORT_96 var_144 = var_144_arg_0 + var_144_arg_1; [L381] SORT_1 var_145_arg_0 = var_121; [L382] SORT_96 var_145_arg_1 = var_140; [L383] SORT_96 var_145_arg_2 = var_144; [L384] SORT_96 var_145 = var_145_arg_0 ? var_145_arg_1 : var_145_arg_2; [L385] SORT_1 var_146_arg_0 = input_4; [L386] SORT_96 var_146_arg_1 = var_140; [L387] SORT_96 var_146_arg_2 = var_145; [L388] SORT_96 var_146 = var_146_arg_0 ? var_146_arg_1 : var_146_arg_2; [L389] var_146 = var_146 & mask_SORT_96 [L390] SORT_96 next_147_arg_1 = var_146; [L392] state_5 = next_124_arg_1 [L393] state_17 = next_131_arg_1 [L394] state_76 = next_134_arg_1 [L395] state_97 = next_142_arg_1 [L396] state_100 = next_147_arg_1 [L120] input_2 = __VERIFIER_nondet_uchar() [L121] input_3 = __VERIFIER_nondet_uchar() [L122] input_3 = input_3 & mask_SORT_1 [L123] input_4 = __VERIFIER_nondet_uchar() [L124] input_4 = input_4 & mask_SORT_1 [L126] SORT_1 var_84_arg_0 = state_5; [L127] SORT_1 var_84 = ~var_84_arg_0; [L128] SORT_1 var_85_arg_0 = var_84; [L129] SORT_1 var_85 = ~var_85_arg_0; [L130] SORT_1 var_86_arg_0 = state_5; [L131] SORT_1 var_86_arg_1 = var_85; [L132] SORT_1 var_86 = var_86_arg_0 | var_86_arg_1; [L133] var_86 = var_86 & mask_SORT_1 [L134] SORT_1 constr_87_arg_0 = var_86; VAL [constr_87_arg_0=1, input_3=1, input_4=0, mask_SORT_11=-1, mask_SORT_12=-1, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=1, state_17=1, state_76=3, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=-56, var_73=5, var_75=0, var_7=0, var_8=1] [L135] CALL assume_abort_if_not(constr_87_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L135] RET assume_abort_if_not(constr_87_arg_0) VAL [constr_87_arg_0=1, input_3=1, input_4=0, mask_SORT_11=-1, mask_SORT_12=-1, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=1, state_17=1, state_76=3, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=-56, var_73=5, var_75=0, var_7=0, var_8=1] [L136] SORT_1 var_88_arg_0 = var_8; [L137] var_88_arg_0 = var_88_arg_0 & mask_SORT_1 [L138] SORT_11 var_88 = var_88_arg_0; [L139] SORT_11 var_89_arg_0 = state_76; [L140] SORT_11 var_89_arg_1 = var_88; [L141] SORT_1 var_89 = var_89_arg_0 <= var_89_arg_1; [L142] SORT_1 var_90_arg_0 = input_4; [L143] SORT_1 var_90_arg_1 = var_89; [L144] SORT_1 var_90 = var_90_arg_0 ^ var_90_arg_1; [L145] SORT_1 var_91_arg_0 = var_90; [L146] SORT_1 var_91 = ~var_91_arg_0; [L147] SORT_1 var_92_arg_0 = var_90; [L148] SORT_1 var_92 = ~var_92_arg_0; [L149] SORT_1 var_93_arg_0 = var_91; [L150] SORT_1 var_93_arg_1 = var_92; [L151] SORT_1 var_93 = var_93_arg_0 | var_93_arg_1; [L152] var_93 = var_93 & mask_SORT_1 [L153] SORT_1 constr_94_arg_0 = var_93; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=1, input_4=0, mask_SORT_11=-1, mask_SORT_12=-1, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=1, state_17=1, state_76=3, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=-56, var_73=5, var_75=0, var_7=0, var_8=1] [L154] CALL assume_abort_if_not(constr_94_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L154] RET assume_abort_if_not(constr_94_arg_0) VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=1, input_4=0, mask_SORT_11=-1, mask_SORT_12=-1, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=1, state_17=1, state_76=3, state_97=0, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=-56, var_73=5, var_75=0, var_7=0, var_8=1] [L156] SORT_72 var_74_arg_0 = var_73; [L157] var_74_arg_0 = var_74_arg_0 & mask_SORT_72 [L158] SORT_11 var_74 = var_74_arg_0; [L159] SORT_11 var_78_arg_0 = var_74; [L160] SORT_11 var_78_arg_1 = state_76; [L161] SORT_1 var_78 = var_78_arg_0 < var_78_arg_1; [L162] SORT_1 var_15_arg_0 = input_3; [L163] SORT_12 var_15_arg_1 = var_14; [L164] SORT_12 var_15_arg_2 = var_13; [L165] SORT_12 var_15 = var_15_arg_0 ? var_15_arg_1 : var_15_arg_2; [L166] var_15 = var_15 & mask_SORT_12 [L167] SORT_12 var_16_arg_0 = var_13; [L168] SORT_12 var_16_arg_1 = var_15; [L169] SORT_11 var_16 = ((SORT_11)var_16_arg_0 << 8) | var_16_arg_1; [L170] SORT_11 var_18_arg_0 = var_16; [L171] SORT_11 var_18_arg_1 = state_17; [L172] SORT_11 var_18 = var_18_arg_0 - var_18_arg_1; [L173] var_18 = var_18 & mask_SORT_11 [L174] SORT_11 var_19_arg_0 = var_18; [L175] SORT_1 var_19 = var_19_arg_0 >> 15; [L176] SORT_1 var_21_arg_0 = var_19; [L177] SORT_9 var_21_arg_1 = var_10; [L178] SORT_20 var_21 = ((SORT_20)var_21_arg_0 << 31) | var_21_arg_1; [L179] var_21 = var_21 & mask_SORT_20 [L180] SORT_11 var_64_arg_0 = var_18; [L181] SORT_1 var_64 = var_64_arg_0 >> 15; [L182] SORT_11 var_61_arg_0 = var_18; [L183] SORT_1 var_61 = var_61_arg_0 >> 15; [L184] SORT_11 var_58_arg_0 = var_18; [L185] SORT_1 var_58 = var_58_arg_0 >> 15; [L186] SORT_11 var_55_arg_0 = var_18; [L187] SORT_1 var_55 = var_55_arg_0 >> 15; [L188] SORT_11 var_52_arg_0 = var_18; [L189] SORT_1 var_52 = var_52_arg_0 >> 15; [L190] SORT_11 var_49_arg_0 = var_18; [L191] SORT_1 var_49 = var_49_arg_0 >> 15; [L192] SORT_11 var_46_arg_0 = var_18; [L193] SORT_1 var_46 = var_46_arg_0 >> 15; [L194] SORT_11 var_43_arg_0 = var_18; [L195] SORT_1 var_43 = var_43_arg_0 >> 15; [L196] SORT_11 var_40_arg_0 = var_18; [L197] SORT_1 var_40 = var_40_arg_0 >> 15; [L198] SORT_11 var_37_arg_0 = var_18; [L199] SORT_1 var_37 = var_37_arg_0 >> 15; [L200] SORT_11 var_34_arg_0 = var_18; [L201] SORT_1 var_34 = var_34_arg_0 >> 15; [L202] SORT_11 var_31_arg_0 = var_18; [L203] SORT_1 var_31 = var_31_arg_0 >> 15; [L204] SORT_11 var_28_arg_0 = var_18; [L205] SORT_1 var_28 = var_28_arg_0 >> 15; [L206] SORT_11 var_25_arg_0 = var_18; [L207] SORT_1 var_25 = var_25_arg_0 >> 15; [L208] SORT_11 var_22_arg_0 = var_18; [L209] SORT_1 var_22 = var_22_arg_0 >> 15; [L210] SORT_1 var_24_arg_0 = var_22; [L211] SORT_11 var_24_arg_1 = var_18; [L212] SORT_23 var_24 = ((SORT_23)var_24_arg_0 << 16) | var_24_arg_1; [L213] var_24 = var_24 & mask_SORT_23 [L214] SORT_1 var_27_arg_0 = var_25; [L215] SORT_23 var_27_arg_1 = var_24; [L216] SORT_26 var_27 = ((SORT_26)var_27_arg_0 << 17) | var_27_arg_1; [L217] var_27 = var_27 & mask_SORT_26 [L218] SORT_1 var_30_arg_0 = var_28; [L219] SORT_26 var_30_arg_1 = var_27; [L220] SORT_29 var_30 = ((SORT_29)var_30_arg_0 << 18) | var_30_arg_1; [L221] var_30 = var_30 & mask_SORT_29 [L222] SORT_1 var_33_arg_0 = var_31; [L223] SORT_29 var_33_arg_1 = var_30; [L224] SORT_32 var_33 = ((SORT_32)var_33_arg_0 << 19) | var_33_arg_1; [L225] var_33 = var_33 & mask_SORT_32 [L226] SORT_1 var_36_arg_0 = var_34; [L227] SORT_32 var_36_arg_1 = var_33; [L228] SORT_35 var_36 = ((SORT_35)var_36_arg_0 << 20) | var_36_arg_1; [L229] var_36 = var_36 & mask_SORT_35 [L230] SORT_1 var_39_arg_0 = var_37; [L231] SORT_35 var_39_arg_1 = var_36; [L232] SORT_38 var_39 = ((SORT_38)var_39_arg_0 << 21) | var_39_arg_1; [L233] var_39 = var_39 & mask_SORT_38 [L234] SORT_1 var_42_arg_0 = var_40; [L235] SORT_38 var_42_arg_1 = var_39; [L236] SORT_41 var_42 = ((SORT_41)var_42_arg_0 << 22) | var_42_arg_1; [L237] var_42 = var_42 & mask_SORT_41 [L238] SORT_1 var_45_arg_0 = var_43; [L239] SORT_41 var_45_arg_1 = var_42; [L240] SORT_44 var_45 = ((SORT_44)var_45_arg_0 << 23) | var_45_arg_1; [L241] var_45 = var_45 & mask_SORT_44 [L242] SORT_1 var_48_arg_0 = var_46; [L243] SORT_44 var_48_arg_1 = var_45; [L244] SORT_47 var_48 = ((SORT_47)var_48_arg_0 << 24) | var_48_arg_1; [L245] var_48 = var_48 & mask_SORT_47 [L246] SORT_1 var_51_arg_0 = var_49; [L247] SORT_47 var_51_arg_1 = var_48; [L248] SORT_50 var_51 = ((SORT_50)var_51_arg_0 << 25) | var_51_arg_1; [L249] var_51 = var_51 & mask_SORT_50 [L250] SORT_1 var_54_arg_0 = var_52; [L251] SORT_50 var_54_arg_1 = var_51; [L252] SORT_53 var_54 = ((SORT_53)var_54_arg_0 << 26) | var_54_arg_1; [L253] var_54 = var_54 & mask_SORT_53 [L254] SORT_1 var_57_arg_0 = var_55; [L255] SORT_53 var_57_arg_1 = var_54; [L256] SORT_56 var_57 = ((SORT_56)var_57_arg_0 << 27) | var_57_arg_1; [L257] var_57 = var_57 & mask_SORT_56 [L258] SORT_1 var_60_arg_0 = var_58; [L259] SORT_56 var_60_arg_1 = var_57; [L260] SORT_59 var_60 = ((SORT_59)var_60_arg_0 << 28) | var_60_arg_1; [L261] var_60 = var_60 & mask_SORT_59 [L262] SORT_1 var_63_arg_0 = var_61; [L263] SORT_59 var_63_arg_1 = var_60; [L264] SORT_62 var_63 = ((SORT_62)var_63_arg_0 << 29) | var_63_arg_1; [L265] var_63 = var_63 & mask_SORT_62 [L266] SORT_1 var_65_arg_0 = var_64; [L267] SORT_62 var_65_arg_1 = var_63; [L268] SORT_9 var_65 = ((SORT_9)var_65_arg_0 << 30) | var_65_arg_1; [L269] SORT_9 var_66_arg_0 = var_65; [L270] var_66_arg_0 = var_66_arg_0 & mask_SORT_9 [L271] SORT_20 var_66 = var_66_arg_0; [L272] SORT_20 var_67_arg_0 = var_21; [L273] SORT_20 var_67_arg_1 = var_66; [L274] SORT_1 var_67 = var_67_arg_0 <= var_67_arg_1; [L275] SORT_1 var_68_arg_0 = var_67; [L276] SORT_1 var_68_arg_1 = var_8; [L277] SORT_1 var_68_arg_2 = var_7; [L278] SORT_1 var_68 = var_68_arg_0 ? var_68_arg_1 : var_68_arg_2; [L279] var_68 = var_68 & mask_SORT_1 [L280] SORT_1 var_69_arg_0 = input_3; [L281] SORT_1 var_69_arg_1 = var_68; [L282] SORT_1 var_69 = var_69_arg_0 ^ var_69_arg_1; [L283] SORT_1 var_70_arg_0 = var_69; [L284] SORT_1 var_70 = ~var_70_arg_0; [L285] SORT_1 var_79_arg_0 = var_78; [L286] SORT_1 var_79_arg_1 = var_70; [L287] SORT_1 var_79_arg_2 = var_8; [L288] SORT_1 var_79 = var_79_arg_0 ? var_79_arg_1 : var_79_arg_2; [L289] SORT_1 var_80_arg_0 = var_79; [L290] SORT_1 var_80 = ~var_80_arg_0; [L291] SORT_1 var_81_arg_0 = var_79; [L292] SORT_1 var_81 = ~var_81_arg_0; [L293] SORT_1 var_82_arg_0 = var_80; [L294] SORT_1 var_82_arg_1 = var_81; [L295] SORT_1 var_82 = var_82_arg_0 & var_82_arg_1; [L296] var_82 = var_82 & mask_SORT_1 [L297] SORT_1 bad_83_arg_0 = var_82; [L298] CALL __VERIFIER_assert(!(bad_83_arg_0)) [L21] COND FALSE !(!(cond)) [L298] RET __VERIFIER_assert(!(bad_83_arg_0)) [L300] SORT_96 var_121_arg_0 = state_100; [L301] SORT_96 var_121_arg_1 = var_120; [L302] SORT_1 var_121 = var_121_arg_0 == var_121_arg_1; [L303] SORT_72 var_114_arg_0 = var_113; [L304] var_114_arg_0 = var_114_arg_0 & mask_SORT_72 [L305] SORT_96 var_114 = var_114_arg_0; [L306] SORT_96 var_115_arg_0 = var_114; [L307] SORT_96 var_115_arg_1 = state_97; [L308] SORT_1 var_115 = var_115_arg_0 <= var_115_arg_1; [L309] SORT_72 var_117_arg_0 = var_116; [L310] var_117_arg_0 = var_117_arg_0 & mask_SORT_72 [L311] SORT_96 var_117 = var_117_arg_0; [L312] SORT_96 var_118_arg_0 = state_97; [L313] SORT_96 var_118_arg_1 = var_117; [L314] SORT_1 var_118 = var_118_arg_0 <= var_118_arg_1; [L315] SORT_1 var_119_arg_0 = var_115; [L316] SORT_1 var_119_arg_1 = var_118; [L317] SORT_1 var_119 = var_119_arg_0 & var_119_arg_1; [L318] SORT_1 var_122_arg_0 = var_121; [L319] SORT_1 var_122_arg_1 = var_119; [L320] SORT_1 var_122_arg_2 = var_8; [L321] SORT_1 var_122 = var_122_arg_0 ? var_122_arg_1 : var_122_arg_2; [L322] SORT_1 var_123_arg_0 = input_4; [L323] SORT_1 var_123_arg_1 = var_8; [L324] SORT_1 var_123_arg_2 = var_122; [L325] SORT_1 var_123 = var_123_arg_0 ? var_123_arg_1 : var_123_arg_2; [L326] SORT_1 next_124_arg_1 = var_123; [L327] SORT_1 var_127_arg_0 = var_8; [L328] var_127_arg_0 = var_127_arg_0 & mask_SORT_1 [L329] SORT_11 var_127 = var_127_arg_0; [L330] SORT_11 var_128_arg_0 = state_17; [L331] SORT_11 var_128_arg_1 = var_127; [L332] SORT_11 var_128 = var_128_arg_0 + var_128_arg_1; [L333] SORT_1 var_125_arg_0 = var_8; [L334] var_125_arg_0 = var_125_arg_0 & mask_SORT_1 [L335] SORT_11 var_125 = var_125_arg_0; [L336] SORT_11 var_126_arg_0 = state_17; [L337] SORT_11 var_126_arg_1 = var_125; [L338] SORT_11 var_126 = var_126_arg_0 - var_126_arg_1; [L339] SORT_1 var_129_arg_0 = var_68; [L340] SORT_11 var_129_arg_1 = var_128; [L341] SORT_11 var_129_arg_2 = var_126; [L342] SORT_11 var_129 = var_129_arg_0 ? var_129_arg_1 : var_129_arg_2; [L343] SORT_1 var_130_arg_0 = input_4; [L344] SORT_11 var_130_arg_1 = var_75; [L345] SORT_11 var_130_arg_2 = var_129; [L346] SORT_11 var_130 = var_130_arg_0 ? var_130_arg_1 : var_130_arg_2; [L347] SORT_11 next_131_arg_1 = var_130; [L348] SORT_1 var_132_arg_0 = var_8; [L349] var_132_arg_0 = var_132_arg_0 & mask_SORT_1 [L350] SORT_11 var_132 = var_132_arg_0; [L351] SORT_11 var_133_arg_0 = state_76; [L352] SORT_11 var_133_arg_1 = var_132; [L353] SORT_11 var_133 = var_133_arg_0 + var_133_arg_1; [L354] var_133 = var_133 & mask_SORT_11 [L355] SORT_11 next_134_arg_1 = var_133; [L356] SORT_72 var_138_arg_0 = var_137; [L357] SORT_1 var_138_arg_1 = input_3; [L358] SORT_96 var_138 = ((SORT_96)var_138_arg_0 << 1) | var_138_arg_1; [L359] SORT_1 var_135_arg_0 = input_3; [L360] var_135_arg_0 = var_135_arg_0 & mask_SORT_1 [L361] SORT_96 var_135 = var_135_arg_0; [L362] SORT_96 var_136_arg_0 = state_97; [L363] SORT_96 var_136_arg_1 = var_135; [L364] SORT_96 var_136 = var_136_arg_0 + var_136_arg_1; [L365] SORT_1 var_139_arg_0 = var_121; [L366] SORT_96 var_139_arg_1 = var_138; [L367] SORT_96 var_139_arg_2 = var_136; [L368] SORT_96 var_139 = var_139_arg_0 ? var_139_arg_1 : var_139_arg_2; [L369] SORT_1 var_141_arg_0 = input_4; [L370] SORT_96 var_141_arg_1 = var_140; [L371] SORT_96 var_141_arg_2 = var_139; [L372] SORT_96 var_141 = var_141_arg_0 ? var_141_arg_1 : var_141_arg_2; [L373] var_141 = var_141 & mask_SORT_96 [L374] SORT_96 next_142_arg_1 = var_141; [L375] SORT_1 var_143_arg_0 = var_8; [L376] var_143_arg_0 = var_143_arg_0 & mask_SORT_1 [L377] SORT_96 var_143 = var_143_arg_0; [L378] SORT_96 var_144_arg_0 = state_100; [L379] SORT_96 var_144_arg_1 = var_143; [L380] SORT_96 var_144 = var_144_arg_0 + var_144_arg_1; [L381] SORT_1 var_145_arg_0 = var_121; [L382] SORT_96 var_145_arg_1 = var_140; [L383] SORT_96 var_145_arg_2 = var_144; [L384] SORT_96 var_145 = var_145_arg_0 ? var_145_arg_1 : var_145_arg_2; [L385] SORT_1 var_146_arg_0 = input_4; [L386] SORT_96 var_146_arg_1 = var_140; [L387] SORT_96 var_146_arg_2 = var_145; [L388] SORT_96 var_146 = var_146_arg_0 ? var_146_arg_1 : var_146_arg_2; [L389] var_146 = var_146 & mask_SORT_96 [L390] SORT_96 next_147_arg_1 = var_146; [L392] state_5 = next_124_arg_1 [L393] state_17 = next_131_arg_1 [L394] state_76 = next_134_arg_1 [L395] state_97 = next_142_arg_1 [L396] state_100 = next_147_arg_1 [L120] input_2 = __VERIFIER_nondet_uchar() [L121] input_3 = __VERIFIER_nondet_uchar() [L122] input_3 = input_3 & mask_SORT_1 [L123] input_4 = __VERIFIER_nondet_uchar() [L124] input_4 = input_4 & mask_SORT_1 [L126] SORT_1 var_84_arg_0 = state_5; [L127] SORT_1 var_84 = ~var_84_arg_0; [L128] SORT_1 var_85_arg_0 = var_84; [L129] SORT_1 var_85 = ~var_85_arg_0; [L130] SORT_1 var_86_arg_0 = state_5; [L131] SORT_1 var_86_arg_1 = var_85; [L132] SORT_1 var_86 = var_86_arg_0 | var_86_arg_1; [L133] var_86 = var_86 & mask_SORT_1 [L134] SORT_1 constr_87_arg_0 = var_86; VAL [constr_87_arg_0=1, input_3=0, input_4=0, mask_SORT_11=-1, mask_SORT_12=-1, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=2, state_17=2, state_76=4, state_97=1, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=-56, var_73=5, var_75=0, var_7=0, var_8=1] [L135] CALL assume_abort_if_not(constr_87_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L135] RET assume_abort_if_not(constr_87_arg_0) VAL [constr_87_arg_0=1, input_3=0, input_4=0, mask_SORT_11=-1, mask_SORT_12=-1, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=2, state_17=2, state_76=4, state_97=1, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=-56, var_73=5, var_75=0, var_7=0, var_8=1] [L136] SORT_1 var_88_arg_0 = var_8; [L137] var_88_arg_0 = var_88_arg_0 & mask_SORT_1 [L138] SORT_11 var_88 = var_88_arg_0; [L139] SORT_11 var_89_arg_0 = state_76; [L140] SORT_11 var_89_arg_1 = var_88; [L141] SORT_1 var_89 = var_89_arg_0 <= var_89_arg_1; [L142] SORT_1 var_90_arg_0 = input_4; [L143] SORT_1 var_90_arg_1 = var_89; [L144] SORT_1 var_90 = var_90_arg_0 ^ var_90_arg_1; [L145] SORT_1 var_91_arg_0 = var_90; [L146] SORT_1 var_91 = ~var_91_arg_0; [L147] SORT_1 var_92_arg_0 = var_90; [L148] SORT_1 var_92 = ~var_92_arg_0; [L149] SORT_1 var_93_arg_0 = var_91; [L150] SORT_1 var_93_arg_1 = var_92; [L151] SORT_1 var_93 = var_93_arg_0 | var_93_arg_1; [L152] var_93 = var_93 & mask_SORT_1 [L153] SORT_1 constr_94_arg_0 = var_93; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=-1, mask_SORT_12=-1, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=2, state_17=2, state_76=4, state_97=1, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=-56, var_73=5, var_75=0, var_7=0, var_8=1] [L154] CALL assume_abort_if_not(constr_94_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L154] RET assume_abort_if_not(constr_94_arg_0) VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=-1, mask_SORT_12=-1, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=2, state_17=2, state_76=4, state_97=1, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=-56, var_73=5, var_75=0, var_7=0, var_8=1] [L156] SORT_72 var_74_arg_0 = var_73; [L157] var_74_arg_0 = var_74_arg_0 & mask_SORT_72 [L158] SORT_11 var_74 = var_74_arg_0; [L159] SORT_11 var_78_arg_0 = var_74; [L160] SORT_11 var_78_arg_1 = state_76; [L161] SORT_1 var_78 = var_78_arg_0 < var_78_arg_1; [L162] SORT_1 var_15_arg_0 = input_3; [L163] SORT_12 var_15_arg_1 = var_14; [L164] SORT_12 var_15_arg_2 = var_13; [L165] SORT_12 var_15 = var_15_arg_0 ? var_15_arg_1 : var_15_arg_2; [L166] var_15 = var_15 & mask_SORT_12 [L167] SORT_12 var_16_arg_0 = var_13; [L168] SORT_12 var_16_arg_1 = var_15; [L169] SORT_11 var_16 = ((SORT_11)var_16_arg_0 << 8) | var_16_arg_1; [L170] SORT_11 var_18_arg_0 = var_16; [L171] SORT_11 var_18_arg_1 = state_17; [L172] SORT_11 var_18 = var_18_arg_0 - var_18_arg_1; [L173] var_18 = var_18 & mask_SORT_11 [L174] SORT_11 var_19_arg_0 = var_18; [L175] SORT_1 var_19 = var_19_arg_0 >> 15; [L176] SORT_1 var_21_arg_0 = var_19; [L177] SORT_9 var_21_arg_1 = var_10; [L178] SORT_20 var_21 = ((SORT_20)var_21_arg_0 << 31) | var_21_arg_1; [L179] var_21 = var_21 & mask_SORT_20 [L180] SORT_11 var_64_arg_0 = var_18; [L181] SORT_1 var_64 = var_64_arg_0 >> 15; [L182] SORT_11 var_61_arg_0 = var_18; [L183] SORT_1 var_61 = var_61_arg_0 >> 15; [L184] SORT_11 var_58_arg_0 = var_18; [L185] SORT_1 var_58 = var_58_arg_0 >> 15; [L186] SORT_11 var_55_arg_0 = var_18; [L187] SORT_1 var_55 = var_55_arg_0 >> 15; [L188] SORT_11 var_52_arg_0 = var_18; [L189] SORT_1 var_52 = var_52_arg_0 >> 15; [L190] SORT_11 var_49_arg_0 = var_18; [L191] SORT_1 var_49 = var_49_arg_0 >> 15; [L192] SORT_11 var_46_arg_0 = var_18; [L193] SORT_1 var_46 = var_46_arg_0 >> 15; [L194] SORT_11 var_43_arg_0 = var_18; [L195] SORT_1 var_43 = var_43_arg_0 >> 15; [L196] SORT_11 var_40_arg_0 = var_18; [L197] SORT_1 var_40 = var_40_arg_0 >> 15; [L198] SORT_11 var_37_arg_0 = var_18; [L199] SORT_1 var_37 = var_37_arg_0 >> 15; [L200] SORT_11 var_34_arg_0 = var_18; [L201] SORT_1 var_34 = var_34_arg_0 >> 15; [L202] SORT_11 var_31_arg_0 = var_18; [L203] SORT_1 var_31 = var_31_arg_0 >> 15; [L204] SORT_11 var_28_arg_0 = var_18; [L205] SORT_1 var_28 = var_28_arg_0 >> 15; [L206] SORT_11 var_25_arg_0 = var_18; [L207] SORT_1 var_25 = var_25_arg_0 >> 15; [L208] SORT_11 var_22_arg_0 = var_18; [L209] SORT_1 var_22 = var_22_arg_0 >> 15; [L210] SORT_1 var_24_arg_0 = var_22; [L211] SORT_11 var_24_arg_1 = var_18; [L212] SORT_23 var_24 = ((SORT_23)var_24_arg_0 << 16) | var_24_arg_1; [L213] var_24 = var_24 & mask_SORT_23 [L214] SORT_1 var_27_arg_0 = var_25; [L215] SORT_23 var_27_arg_1 = var_24; [L216] SORT_26 var_27 = ((SORT_26)var_27_arg_0 << 17) | var_27_arg_1; [L217] var_27 = var_27 & mask_SORT_26 [L218] SORT_1 var_30_arg_0 = var_28; [L219] SORT_26 var_30_arg_1 = var_27; [L220] SORT_29 var_30 = ((SORT_29)var_30_arg_0 << 18) | var_30_arg_1; [L221] var_30 = var_30 & mask_SORT_29 [L222] SORT_1 var_33_arg_0 = var_31; [L223] SORT_29 var_33_arg_1 = var_30; [L224] SORT_32 var_33 = ((SORT_32)var_33_arg_0 << 19) | var_33_arg_1; [L225] var_33 = var_33 & mask_SORT_32 [L226] SORT_1 var_36_arg_0 = var_34; [L227] SORT_32 var_36_arg_1 = var_33; [L228] SORT_35 var_36 = ((SORT_35)var_36_arg_0 << 20) | var_36_arg_1; [L229] var_36 = var_36 & mask_SORT_35 [L230] SORT_1 var_39_arg_0 = var_37; [L231] SORT_35 var_39_arg_1 = var_36; [L232] SORT_38 var_39 = ((SORT_38)var_39_arg_0 << 21) | var_39_arg_1; [L233] var_39 = var_39 & mask_SORT_38 [L234] SORT_1 var_42_arg_0 = var_40; [L235] SORT_38 var_42_arg_1 = var_39; [L236] SORT_41 var_42 = ((SORT_41)var_42_arg_0 << 22) | var_42_arg_1; [L237] var_42 = var_42 & mask_SORT_41 [L238] SORT_1 var_45_arg_0 = var_43; [L239] SORT_41 var_45_arg_1 = var_42; [L240] SORT_44 var_45 = ((SORT_44)var_45_arg_0 << 23) | var_45_arg_1; [L241] var_45 = var_45 & mask_SORT_44 [L242] SORT_1 var_48_arg_0 = var_46; [L243] SORT_44 var_48_arg_1 = var_45; [L244] SORT_47 var_48 = ((SORT_47)var_48_arg_0 << 24) | var_48_arg_1; [L245] var_48 = var_48 & mask_SORT_47 [L246] SORT_1 var_51_arg_0 = var_49; [L247] SORT_47 var_51_arg_1 = var_48; [L248] SORT_50 var_51 = ((SORT_50)var_51_arg_0 << 25) | var_51_arg_1; [L249] var_51 = var_51 & mask_SORT_50 [L250] SORT_1 var_54_arg_0 = var_52; [L251] SORT_50 var_54_arg_1 = var_51; [L252] SORT_53 var_54 = ((SORT_53)var_54_arg_0 << 26) | var_54_arg_1; [L253] var_54 = var_54 & mask_SORT_53 [L254] SORT_1 var_57_arg_0 = var_55; [L255] SORT_53 var_57_arg_1 = var_54; [L256] SORT_56 var_57 = ((SORT_56)var_57_arg_0 << 27) | var_57_arg_1; [L257] var_57 = var_57 & mask_SORT_56 [L258] SORT_1 var_60_arg_0 = var_58; [L259] SORT_56 var_60_arg_1 = var_57; [L260] SORT_59 var_60 = ((SORT_59)var_60_arg_0 << 28) | var_60_arg_1; [L261] var_60 = var_60 & mask_SORT_59 [L262] SORT_1 var_63_arg_0 = var_61; [L263] SORT_59 var_63_arg_1 = var_60; [L264] SORT_62 var_63 = ((SORT_62)var_63_arg_0 << 29) | var_63_arg_1; [L265] var_63 = var_63 & mask_SORT_62 [L266] SORT_1 var_65_arg_0 = var_64; [L267] SORT_62 var_65_arg_1 = var_63; [L268] SORT_9 var_65 = ((SORT_9)var_65_arg_0 << 30) | var_65_arg_1; [L269] SORT_9 var_66_arg_0 = var_65; [L270] var_66_arg_0 = var_66_arg_0 & mask_SORT_9 [L271] SORT_20 var_66 = var_66_arg_0; [L272] SORT_20 var_67_arg_0 = var_21; [L273] SORT_20 var_67_arg_1 = var_66; [L274] SORT_1 var_67 = var_67_arg_0 <= var_67_arg_1; [L275] SORT_1 var_68_arg_0 = var_67; [L276] SORT_1 var_68_arg_1 = var_8; [L277] SORT_1 var_68_arg_2 = var_7; [L278] SORT_1 var_68 = var_68_arg_0 ? var_68_arg_1 : var_68_arg_2; [L279] var_68 = var_68 & mask_SORT_1 [L280] SORT_1 var_69_arg_0 = input_3; [L281] SORT_1 var_69_arg_1 = var_68; [L282] SORT_1 var_69 = var_69_arg_0 ^ var_69_arg_1; [L283] SORT_1 var_70_arg_0 = var_69; [L284] SORT_1 var_70 = ~var_70_arg_0; [L285] SORT_1 var_79_arg_0 = var_78; [L286] SORT_1 var_79_arg_1 = var_70; [L287] SORT_1 var_79_arg_2 = var_8; [L288] SORT_1 var_79 = var_79_arg_0 ? var_79_arg_1 : var_79_arg_2; [L289] SORT_1 var_80_arg_0 = var_79; [L290] SORT_1 var_80 = ~var_80_arg_0; [L291] SORT_1 var_81_arg_0 = var_79; [L292] SORT_1 var_81 = ~var_81_arg_0; [L293] SORT_1 var_82_arg_0 = var_80; [L294] SORT_1 var_82_arg_1 = var_81; [L295] SORT_1 var_82 = var_82_arg_0 & var_82_arg_1; [L296] var_82 = var_82 & mask_SORT_1 [L297] SORT_1 bad_83_arg_0 = var_82; [L298] CALL __VERIFIER_assert(!(bad_83_arg_0)) [L21] COND FALSE !(!(cond)) [L298] RET __VERIFIER_assert(!(bad_83_arg_0)) [L300] SORT_96 var_121_arg_0 = state_100; [L301] SORT_96 var_121_arg_1 = var_120; [L302] SORT_1 var_121 = var_121_arg_0 == var_121_arg_1; [L303] SORT_72 var_114_arg_0 = var_113; [L304] var_114_arg_0 = var_114_arg_0 & mask_SORT_72 [L305] SORT_96 var_114 = var_114_arg_0; [L306] SORT_96 var_115_arg_0 = var_114; [L307] SORT_96 var_115_arg_1 = state_97; [L308] SORT_1 var_115 = var_115_arg_0 <= var_115_arg_1; [L309] SORT_72 var_117_arg_0 = var_116; [L310] var_117_arg_0 = var_117_arg_0 & mask_SORT_72 [L311] SORT_96 var_117 = var_117_arg_0; [L312] SORT_96 var_118_arg_0 = state_97; [L313] SORT_96 var_118_arg_1 = var_117; [L314] SORT_1 var_118 = var_118_arg_0 <= var_118_arg_1; [L315] SORT_1 var_119_arg_0 = var_115; [L316] SORT_1 var_119_arg_1 = var_118; [L317] SORT_1 var_119 = var_119_arg_0 & var_119_arg_1; [L318] SORT_1 var_122_arg_0 = var_121; [L319] SORT_1 var_122_arg_1 = var_119; [L320] SORT_1 var_122_arg_2 = var_8; [L321] SORT_1 var_122 = var_122_arg_0 ? var_122_arg_1 : var_122_arg_2; [L322] SORT_1 var_123_arg_0 = input_4; [L323] SORT_1 var_123_arg_1 = var_8; [L324] SORT_1 var_123_arg_2 = var_122; [L325] SORT_1 var_123 = var_123_arg_0 ? var_123_arg_1 : var_123_arg_2; [L326] SORT_1 next_124_arg_1 = var_123; [L327] SORT_1 var_127_arg_0 = var_8; [L328] var_127_arg_0 = var_127_arg_0 & mask_SORT_1 [L329] SORT_11 var_127 = var_127_arg_0; [L330] SORT_11 var_128_arg_0 = state_17; [L331] SORT_11 var_128_arg_1 = var_127; [L332] SORT_11 var_128 = var_128_arg_0 + var_128_arg_1; [L333] SORT_1 var_125_arg_0 = var_8; [L334] var_125_arg_0 = var_125_arg_0 & mask_SORT_1 [L335] SORT_11 var_125 = var_125_arg_0; [L336] SORT_11 var_126_arg_0 = state_17; [L337] SORT_11 var_126_arg_1 = var_125; [L338] SORT_11 var_126 = var_126_arg_0 - var_126_arg_1; [L339] SORT_1 var_129_arg_0 = var_68; [L340] SORT_11 var_129_arg_1 = var_128; [L341] SORT_11 var_129_arg_2 = var_126; [L342] SORT_11 var_129 = var_129_arg_0 ? var_129_arg_1 : var_129_arg_2; [L343] SORT_1 var_130_arg_0 = input_4; [L344] SORT_11 var_130_arg_1 = var_75; [L345] SORT_11 var_130_arg_2 = var_129; [L346] SORT_11 var_130 = var_130_arg_0 ? var_130_arg_1 : var_130_arg_2; [L347] SORT_11 next_131_arg_1 = var_130; [L348] SORT_1 var_132_arg_0 = var_8; [L349] var_132_arg_0 = var_132_arg_0 & mask_SORT_1 [L350] SORT_11 var_132 = var_132_arg_0; [L351] SORT_11 var_133_arg_0 = state_76; [L352] SORT_11 var_133_arg_1 = var_132; [L353] SORT_11 var_133 = var_133_arg_0 + var_133_arg_1; [L354] var_133 = var_133 & mask_SORT_11 [L355] SORT_11 next_134_arg_1 = var_133; [L356] SORT_72 var_138_arg_0 = var_137; [L357] SORT_1 var_138_arg_1 = input_3; [L358] SORT_96 var_138 = ((SORT_96)var_138_arg_0 << 1) | var_138_arg_1; [L359] SORT_1 var_135_arg_0 = input_3; [L360] var_135_arg_0 = var_135_arg_0 & mask_SORT_1 [L361] SORT_96 var_135 = var_135_arg_0; [L362] SORT_96 var_136_arg_0 = state_97; [L363] SORT_96 var_136_arg_1 = var_135; [L364] SORT_96 var_136 = var_136_arg_0 + var_136_arg_1; [L365] SORT_1 var_139_arg_0 = var_121; [L366] SORT_96 var_139_arg_1 = var_138; [L367] SORT_96 var_139_arg_2 = var_136; [L368] SORT_96 var_139 = var_139_arg_0 ? var_139_arg_1 : var_139_arg_2; [L369] SORT_1 var_141_arg_0 = input_4; [L370] SORT_96 var_141_arg_1 = var_140; [L371] SORT_96 var_141_arg_2 = var_139; [L372] SORT_96 var_141 = var_141_arg_0 ? var_141_arg_1 : var_141_arg_2; [L373] var_141 = var_141 & mask_SORT_96 [L374] SORT_96 next_142_arg_1 = var_141; [L375] SORT_1 var_143_arg_0 = var_8; [L376] var_143_arg_0 = var_143_arg_0 & mask_SORT_1 [L377] SORT_96 var_143 = var_143_arg_0; [L378] SORT_96 var_144_arg_0 = state_100; [L379] SORT_96 var_144_arg_1 = var_143; [L380] SORT_96 var_144 = var_144_arg_0 + var_144_arg_1; [L381] SORT_1 var_145_arg_0 = var_121; [L382] SORT_96 var_145_arg_1 = var_140; [L383] SORT_96 var_145_arg_2 = var_144; [L384] SORT_96 var_145 = var_145_arg_0 ? var_145_arg_1 : var_145_arg_2; [L385] SORT_1 var_146_arg_0 = input_4; [L386] SORT_96 var_146_arg_1 = var_140; [L387] SORT_96 var_146_arg_2 = var_145; [L388] SORT_96 var_146 = var_146_arg_0 ? var_146_arg_1 : var_146_arg_2; [L389] var_146 = var_146 & mask_SORT_96 [L390] SORT_96 next_147_arg_1 = var_146; [L392] state_5 = next_124_arg_1 [L393] state_17 = next_131_arg_1 [L394] state_76 = next_134_arg_1 [L395] state_97 = next_142_arg_1 [L396] state_100 = next_147_arg_1 [L120] input_2 = __VERIFIER_nondet_uchar() [L121] input_3 = __VERIFIER_nondet_uchar() [L122] input_3 = input_3 & mask_SORT_1 [L123] input_4 = __VERIFIER_nondet_uchar() [L124] input_4 = input_4 & mask_SORT_1 [L126] SORT_1 var_84_arg_0 = state_5; [L127] SORT_1 var_84 = ~var_84_arg_0; [L128] SORT_1 var_85_arg_0 = var_84; [L129] SORT_1 var_85 = ~var_85_arg_0; [L130] SORT_1 var_86_arg_0 = state_5; [L131] SORT_1 var_86_arg_1 = var_85; [L132] SORT_1 var_86 = var_86_arg_0 | var_86_arg_1; [L133] var_86 = var_86 & mask_SORT_1 [L134] SORT_1 constr_87_arg_0 = var_86; VAL [constr_87_arg_0=1, input_3=0, input_4=0, mask_SORT_11=-1, mask_SORT_12=-1, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=3, state_17=1, state_76=5, state_97=1, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=-56, var_73=5, var_75=0, var_7=0, var_8=1] [L135] CALL assume_abort_if_not(constr_87_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L135] RET assume_abort_if_not(constr_87_arg_0) VAL [constr_87_arg_0=1, input_3=0, input_4=0, mask_SORT_11=-1, mask_SORT_12=-1, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=3, state_17=1, state_76=5, state_97=1, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=-56, var_73=5, var_75=0, var_7=0, var_8=1] [L136] SORT_1 var_88_arg_0 = var_8; [L137] var_88_arg_0 = var_88_arg_0 & mask_SORT_1 [L138] SORT_11 var_88 = var_88_arg_0; [L139] SORT_11 var_89_arg_0 = state_76; [L140] SORT_11 var_89_arg_1 = var_88; [L141] SORT_1 var_89 = var_89_arg_0 <= var_89_arg_1; [L142] SORT_1 var_90_arg_0 = input_4; [L143] SORT_1 var_90_arg_1 = var_89; [L144] SORT_1 var_90 = var_90_arg_0 ^ var_90_arg_1; [L145] SORT_1 var_91_arg_0 = var_90; [L146] SORT_1 var_91 = ~var_91_arg_0; [L147] SORT_1 var_92_arg_0 = var_90; [L148] SORT_1 var_92 = ~var_92_arg_0; [L149] SORT_1 var_93_arg_0 = var_91; [L150] SORT_1 var_93_arg_1 = var_92; [L151] SORT_1 var_93 = var_93_arg_0 | var_93_arg_1; [L152] var_93 = var_93 & mask_SORT_1 [L153] SORT_1 constr_94_arg_0 = var_93; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=-1, mask_SORT_12=-1, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=3, state_17=1, state_76=5, state_97=1, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=-56, var_73=5, var_75=0, var_7=0, var_8=1] [L154] CALL assume_abort_if_not(constr_94_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L154] RET assume_abort_if_not(constr_94_arg_0) VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=-1, mask_SORT_12=-1, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=3, state_17=1, state_76=5, state_97=1, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=-56, var_73=5, var_75=0, var_7=0, var_8=1] [L156] SORT_72 var_74_arg_0 = var_73; [L157] var_74_arg_0 = var_74_arg_0 & mask_SORT_72 [L158] SORT_11 var_74 = var_74_arg_0; [L159] SORT_11 var_78_arg_0 = var_74; [L160] SORT_11 var_78_arg_1 = state_76; [L161] SORT_1 var_78 = var_78_arg_0 < var_78_arg_1; [L162] SORT_1 var_15_arg_0 = input_3; [L163] SORT_12 var_15_arg_1 = var_14; [L164] SORT_12 var_15_arg_2 = var_13; [L165] SORT_12 var_15 = var_15_arg_0 ? var_15_arg_1 : var_15_arg_2; [L166] var_15 = var_15 & mask_SORT_12 [L167] SORT_12 var_16_arg_0 = var_13; [L168] SORT_12 var_16_arg_1 = var_15; [L169] SORT_11 var_16 = ((SORT_11)var_16_arg_0 << 8) | var_16_arg_1; [L170] SORT_11 var_18_arg_0 = var_16; [L171] SORT_11 var_18_arg_1 = state_17; [L172] SORT_11 var_18 = var_18_arg_0 - var_18_arg_1; [L173] var_18 = var_18 & mask_SORT_11 [L174] SORT_11 var_19_arg_0 = var_18; [L175] SORT_1 var_19 = var_19_arg_0 >> 15; [L176] SORT_1 var_21_arg_0 = var_19; [L177] SORT_9 var_21_arg_1 = var_10; [L178] SORT_20 var_21 = ((SORT_20)var_21_arg_0 << 31) | var_21_arg_1; [L179] var_21 = var_21 & mask_SORT_20 [L180] SORT_11 var_64_arg_0 = var_18; [L181] SORT_1 var_64 = var_64_arg_0 >> 15; [L182] SORT_11 var_61_arg_0 = var_18; [L183] SORT_1 var_61 = var_61_arg_0 >> 15; [L184] SORT_11 var_58_arg_0 = var_18; [L185] SORT_1 var_58 = var_58_arg_0 >> 15; [L186] SORT_11 var_55_arg_0 = var_18; [L187] SORT_1 var_55 = var_55_arg_0 >> 15; [L188] SORT_11 var_52_arg_0 = var_18; [L189] SORT_1 var_52 = var_52_arg_0 >> 15; [L190] SORT_11 var_49_arg_0 = var_18; [L191] SORT_1 var_49 = var_49_arg_0 >> 15; [L192] SORT_11 var_46_arg_0 = var_18; [L193] SORT_1 var_46 = var_46_arg_0 >> 15; [L194] SORT_11 var_43_arg_0 = var_18; [L195] SORT_1 var_43 = var_43_arg_0 >> 15; [L196] SORT_11 var_40_arg_0 = var_18; [L197] SORT_1 var_40 = var_40_arg_0 >> 15; [L198] SORT_11 var_37_arg_0 = var_18; [L199] SORT_1 var_37 = var_37_arg_0 >> 15; [L200] SORT_11 var_34_arg_0 = var_18; [L201] SORT_1 var_34 = var_34_arg_0 >> 15; [L202] SORT_11 var_31_arg_0 = var_18; [L203] SORT_1 var_31 = var_31_arg_0 >> 15; [L204] SORT_11 var_28_arg_0 = var_18; [L205] SORT_1 var_28 = var_28_arg_0 >> 15; [L206] SORT_11 var_25_arg_0 = var_18; [L207] SORT_1 var_25 = var_25_arg_0 >> 15; [L208] SORT_11 var_22_arg_0 = var_18; [L209] SORT_1 var_22 = var_22_arg_0 >> 15; [L210] SORT_1 var_24_arg_0 = var_22; [L211] SORT_11 var_24_arg_1 = var_18; [L212] SORT_23 var_24 = ((SORT_23)var_24_arg_0 << 16) | var_24_arg_1; [L213] var_24 = var_24 & mask_SORT_23 [L214] SORT_1 var_27_arg_0 = var_25; [L215] SORT_23 var_27_arg_1 = var_24; [L216] SORT_26 var_27 = ((SORT_26)var_27_arg_0 << 17) | var_27_arg_1; [L217] var_27 = var_27 & mask_SORT_26 [L218] SORT_1 var_30_arg_0 = var_28; [L219] SORT_26 var_30_arg_1 = var_27; [L220] SORT_29 var_30 = ((SORT_29)var_30_arg_0 << 18) | var_30_arg_1; [L221] var_30 = var_30 & mask_SORT_29 [L222] SORT_1 var_33_arg_0 = var_31; [L223] SORT_29 var_33_arg_1 = var_30; [L224] SORT_32 var_33 = ((SORT_32)var_33_arg_0 << 19) | var_33_arg_1; [L225] var_33 = var_33 & mask_SORT_32 [L226] SORT_1 var_36_arg_0 = var_34; [L227] SORT_32 var_36_arg_1 = var_33; [L228] SORT_35 var_36 = ((SORT_35)var_36_arg_0 << 20) | var_36_arg_1; [L229] var_36 = var_36 & mask_SORT_35 [L230] SORT_1 var_39_arg_0 = var_37; [L231] SORT_35 var_39_arg_1 = var_36; [L232] SORT_38 var_39 = ((SORT_38)var_39_arg_0 << 21) | var_39_arg_1; [L233] var_39 = var_39 & mask_SORT_38 [L234] SORT_1 var_42_arg_0 = var_40; [L235] SORT_38 var_42_arg_1 = var_39; [L236] SORT_41 var_42 = ((SORT_41)var_42_arg_0 << 22) | var_42_arg_1; [L237] var_42 = var_42 & mask_SORT_41 [L238] SORT_1 var_45_arg_0 = var_43; [L239] SORT_41 var_45_arg_1 = var_42; [L240] SORT_44 var_45 = ((SORT_44)var_45_arg_0 << 23) | var_45_arg_1; [L241] var_45 = var_45 & mask_SORT_44 [L242] SORT_1 var_48_arg_0 = var_46; [L243] SORT_44 var_48_arg_1 = var_45; [L244] SORT_47 var_48 = ((SORT_47)var_48_arg_0 << 24) | var_48_arg_1; [L245] var_48 = var_48 & mask_SORT_47 [L246] SORT_1 var_51_arg_0 = var_49; [L247] SORT_47 var_51_arg_1 = var_48; [L248] SORT_50 var_51 = ((SORT_50)var_51_arg_0 << 25) | var_51_arg_1; [L249] var_51 = var_51 & mask_SORT_50 [L250] SORT_1 var_54_arg_0 = var_52; [L251] SORT_50 var_54_arg_1 = var_51; [L252] SORT_53 var_54 = ((SORT_53)var_54_arg_0 << 26) | var_54_arg_1; [L253] var_54 = var_54 & mask_SORT_53 [L254] SORT_1 var_57_arg_0 = var_55; [L255] SORT_53 var_57_arg_1 = var_54; [L256] SORT_56 var_57 = ((SORT_56)var_57_arg_0 << 27) | var_57_arg_1; [L257] var_57 = var_57 & mask_SORT_56 [L258] SORT_1 var_60_arg_0 = var_58; [L259] SORT_56 var_60_arg_1 = var_57; [L260] SORT_59 var_60 = ((SORT_59)var_60_arg_0 << 28) | var_60_arg_1; [L261] var_60 = var_60 & mask_SORT_59 [L262] SORT_1 var_63_arg_0 = var_61; [L263] SORT_59 var_63_arg_1 = var_60; [L264] SORT_62 var_63 = ((SORT_62)var_63_arg_0 << 29) | var_63_arg_1; [L265] var_63 = var_63 & mask_SORT_62 [L266] SORT_1 var_65_arg_0 = var_64; [L267] SORT_62 var_65_arg_1 = var_63; [L268] SORT_9 var_65 = ((SORT_9)var_65_arg_0 << 30) | var_65_arg_1; [L269] SORT_9 var_66_arg_0 = var_65; [L270] var_66_arg_0 = var_66_arg_0 & mask_SORT_9 [L271] SORT_20 var_66 = var_66_arg_0; [L272] SORT_20 var_67_arg_0 = var_21; [L273] SORT_20 var_67_arg_1 = var_66; [L274] SORT_1 var_67 = var_67_arg_0 <= var_67_arg_1; [L275] SORT_1 var_68_arg_0 = var_67; [L276] SORT_1 var_68_arg_1 = var_8; [L277] SORT_1 var_68_arg_2 = var_7; [L278] SORT_1 var_68 = var_68_arg_0 ? var_68_arg_1 : var_68_arg_2; [L279] var_68 = var_68 & mask_SORT_1 [L280] SORT_1 var_69_arg_0 = input_3; [L281] SORT_1 var_69_arg_1 = var_68; [L282] SORT_1 var_69 = var_69_arg_0 ^ var_69_arg_1; [L283] SORT_1 var_70_arg_0 = var_69; [L284] SORT_1 var_70 = ~var_70_arg_0; [L285] SORT_1 var_79_arg_0 = var_78; [L286] SORT_1 var_79_arg_1 = var_70; [L287] SORT_1 var_79_arg_2 = var_8; [L288] SORT_1 var_79 = var_79_arg_0 ? var_79_arg_1 : var_79_arg_2; [L289] SORT_1 var_80_arg_0 = var_79; [L290] SORT_1 var_80 = ~var_80_arg_0; [L291] SORT_1 var_81_arg_0 = var_79; [L292] SORT_1 var_81 = ~var_81_arg_0; [L293] SORT_1 var_82_arg_0 = var_80; [L294] SORT_1 var_82_arg_1 = var_81; [L295] SORT_1 var_82 = var_82_arg_0 & var_82_arg_1; [L296] var_82 = var_82 & mask_SORT_1 [L297] SORT_1 bad_83_arg_0 = var_82; [L298] CALL __VERIFIER_assert(!(bad_83_arg_0)) [L21] COND FALSE !(!(cond)) [L298] RET __VERIFIER_assert(!(bad_83_arg_0)) [L300] SORT_96 var_121_arg_0 = state_100; [L301] SORT_96 var_121_arg_1 = var_120; [L302] SORT_1 var_121 = var_121_arg_0 == var_121_arg_1; [L303] SORT_72 var_114_arg_0 = var_113; [L304] var_114_arg_0 = var_114_arg_0 & mask_SORT_72 [L305] SORT_96 var_114 = var_114_arg_0; [L306] SORT_96 var_115_arg_0 = var_114; [L307] SORT_96 var_115_arg_1 = state_97; [L308] SORT_1 var_115 = var_115_arg_0 <= var_115_arg_1; [L309] SORT_72 var_117_arg_0 = var_116; [L310] var_117_arg_0 = var_117_arg_0 & mask_SORT_72 [L311] SORT_96 var_117 = var_117_arg_0; [L312] SORT_96 var_118_arg_0 = state_97; [L313] SORT_96 var_118_arg_1 = var_117; [L314] SORT_1 var_118 = var_118_arg_0 <= var_118_arg_1; [L315] SORT_1 var_119_arg_0 = var_115; [L316] SORT_1 var_119_arg_1 = var_118; [L317] SORT_1 var_119 = var_119_arg_0 & var_119_arg_1; [L318] SORT_1 var_122_arg_0 = var_121; [L319] SORT_1 var_122_arg_1 = var_119; [L320] SORT_1 var_122_arg_2 = var_8; [L321] SORT_1 var_122 = var_122_arg_0 ? var_122_arg_1 : var_122_arg_2; [L322] SORT_1 var_123_arg_0 = input_4; [L323] SORT_1 var_123_arg_1 = var_8; [L324] SORT_1 var_123_arg_2 = var_122; [L325] SORT_1 var_123 = var_123_arg_0 ? var_123_arg_1 : var_123_arg_2; [L326] SORT_1 next_124_arg_1 = var_123; [L327] SORT_1 var_127_arg_0 = var_8; [L328] var_127_arg_0 = var_127_arg_0 & mask_SORT_1 [L329] SORT_11 var_127 = var_127_arg_0; [L330] SORT_11 var_128_arg_0 = state_17; [L331] SORT_11 var_128_arg_1 = var_127; [L332] SORT_11 var_128 = var_128_arg_0 + var_128_arg_1; [L333] SORT_1 var_125_arg_0 = var_8; [L334] var_125_arg_0 = var_125_arg_0 & mask_SORT_1 [L335] SORT_11 var_125 = var_125_arg_0; [L336] SORT_11 var_126_arg_0 = state_17; [L337] SORT_11 var_126_arg_1 = var_125; [L338] SORT_11 var_126 = var_126_arg_0 - var_126_arg_1; [L339] SORT_1 var_129_arg_0 = var_68; [L340] SORT_11 var_129_arg_1 = var_128; [L341] SORT_11 var_129_arg_2 = var_126; [L342] SORT_11 var_129 = var_129_arg_0 ? var_129_arg_1 : var_129_arg_2; [L343] SORT_1 var_130_arg_0 = input_4; [L344] SORT_11 var_130_arg_1 = var_75; [L345] SORT_11 var_130_arg_2 = var_129; [L346] SORT_11 var_130 = var_130_arg_0 ? var_130_arg_1 : var_130_arg_2; [L347] SORT_11 next_131_arg_1 = var_130; [L348] SORT_1 var_132_arg_0 = var_8; [L349] var_132_arg_0 = var_132_arg_0 & mask_SORT_1 [L350] SORT_11 var_132 = var_132_arg_0; [L351] SORT_11 var_133_arg_0 = state_76; [L352] SORT_11 var_133_arg_1 = var_132; [L353] SORT_11 var_133 = var_133_arg_0 + var_133_arg_1; [L354] var_133 = var_133 & mask_SORT_11 [L355] SORT_11 next_134_arg_1 = var_133; [L356] SORT_72 var_138_arg_0 = var_137; [L357] SORT_1 var_138_arg_1 = input_3; [L358] SORT_96 var_138 = ((SORT_96)var_138_arg_0 << 1) | var_138_arg_1; [L359] SORT_1 var_135_arg_0 = input_3; [L360] var_135_arg_0 = var_135_arg_0 & mask_SORT_1 [L361] SORT_96 var_135 = var_135_arg_0; [L362] SORT_96 var_136_arg_0 = state_97; [L363] SORT_96 var_136_arg_1 = var_135; [L364] SORT_96 var_136 = var_136_arg_0 + var_136_arg_1; [L365] SORT_1 var_139_arg_0 = var_121; [L366] SORT_96 var_139_arg_1 = var_138; [L367] SORT_96 var_139_arg_2 = var_136; [L368] SORT_96 var_139 = var_139_arg_0 ? var_139_arg_1 : var_139_arg_2; [L369] SORT_1 var_141_arg_0 = input_4; [L370] SORT_96 var_141_arg_1 = var_140; [L371] SORT_96 var_141_arg_2 = var_139; [L372] SORT_96 var_141 = var_141_arg_0 ? var_141_arg_1 : var_141_arg_2; [L373] var_141 = var_141 & mask_SORT_96 [L374] SORT_96 next_142_arg_1 = var_141; [L375] SORT_1 var_143_arg_0 = var_8; [L376] var_143_arg_0 = var_143_arg_0 & mask_SORT_1 [L377] SORT_96 var_143 = var_143_arg_0; [L378] SORT_96 var_144_arg_0 = state_100; [L379] SORT_96 var_144_arg_1 = var_143; [L380] SORT_96 var_144 = var_144_arg_0 + var_144_arg_1; [L381] SORT_1 var_145_arg_0 = var_121; [L382] SORT_96 var_145_arg_1 = var_140; [L383] SORT_96 var_145_arg_2 = var_144; [L384] SORT_96 var_145 = var_145_arg_0 ? var_145_arg_1 : var_145_arg_2; [L385] SORT_1 var_146_arg_0 = input_4; [L386] SORT_96 var_146_arg_1 = var_140; [L387] SORT_96 var_146_arg_2 = var_145; [L388] SORT_96 var_146 = var_146_arg_0 ? var_146_arg_1 : var_146_arg_2; [L389] var_146 = var_146 & mask_SORT_96 [L390] SORT_96 next_147_arg_1 = var_146; [L392] state_5 = next_124_arg_1 [L393] state_17 = next_131_arg_1 [L394] state_76 = next_134_arg_1 [L395] state_97 = next_142_arg_1 [L396] state_100 = next_147_arg_1 [L120] input_2 = __VERIFIER_nondet_uchar() [L121] input_3 = __VERIFIER_nondet_uchar() [L122] input_3 = input_3 & mask_SORT_1 [L123] input_4 = __VERIFIER_nondet_uchar() [L124] input_4 = input_4 & mask_SORT_1 [L126] SORT_1 var_84_arg_0 = state_5; [L127] SORT_1 var_84 = ~var_84_arg_0; [L128] SORT_1 var_85_arg_0 = var_84; [L129] SORT_1 var_85 = ~var_85_arg_0; [L130] SORT_1 var_86_arg_0 = state_5; [L131] SORT_1 var_86_arg_1 = var_85; [L132] SORT_1 var_86 = var_86_arg_0 | var_86_arg_1; [L133] var_86 = var_86 & mask_SORT_1 [L134] SORT_1 constr_87_arg_0 = var_86; VAL [constr_87_arg_0=1, input_3=0, input_4=0, mask_SORT_11=-1, mask_SORT_12=-1, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=4, state_17=0, state_76=6, state_97=1, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=-56, var_73=5, var_75=0, var_7=0, var_8=1] [L135] CALL assume_abort_if_not(constr_87_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L135] RET assume_abort_if_not(constr_87_arg_0) VAL [constr_87_arg_0=1, input_3=0, input_4=0, mask_SORT_11=-1, mask_SORT_12=-1, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=4, state_17=0, state_76=6, state_97=1, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=-56, var_73=5, var_75=0, var_7=0, var_8=1] [L136] SORT_1 var_88_arg_0 = var_8; [L137] var_88_arg_0 = var_88_arg_0 & mask_SORT_1 [L138] SORT_11 var_88 = var_88_arg_0; [L139] SORT_11 var_89_arg_0 = state_76; [L140] SORT_11 var_89_arg_1 = var_88; [L141] SORT_1 var_89 = var_89_arg_0 <= var_89_arg_1; [L142] SORT_1 var_90_arg_0 = input_4; [L143] SORT_1 var_90_arg_1 = var_89; [L144] SORT_1 var_90 = var_90_arg_0 ^ var_90_arg_1; [L145] SORT_1 var_91_arg_0 = var_90; [L146] SORT_1 var_91 = ~var_91_arg_0; [L147] SORT_1 var_92_arg_0 = var_90; [L148] SORT_1 var_92 = ~var_92_arg_0; [L149] SORT_1 var_93_arg_0 = var_91; [L150] SORT_1 var_93_arg_1 = var_92; [L151] SORT_1 var_93 = var_93_arg_0 | var_93_arg_1; [L152] var_93 = var_93 & mask_SORT_1 [L153] SORT_1 constr_94_arg_0 = var_93; VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=-1, mask_SORT_12=-1, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=4, state_17=0, state_76=6, state_97=1, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=-56, var_73=5, var_75=0, var_7=0, var_8=1] [L154] CALL assume_abort_if_not(constr_94_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L154] RET assume_abort_if_not(constr_94_arg_0) VAL [constr_87_arg_0=1, constr_94_arg_0=1, input_3=0, input_4=0, mask_SORT_11=-1, mask_SORT_12=-1, mask_SORT_1=1, mask_SORT_20=-1, mask_SORT_23=131071, mask_SORT_26=262143, mask_SORT_29=524287, mask_SORT_32=1048575, mask_SORT_35=2097151, mask_SORT_38=4194303, mask_SORT_41=8388607, mask_SORT_44=16777215, mask_SORT_47=33554431, mask_SORT_50=67108863, mask_SORT_53=134217727, mask_SORT_56=268435455, mask_SORT_59=536870911, mask_SORT_62=1073741823, mask_SORT_72=7, mask_SORT_96=15, mask_SORT_9=2147483647, state_100=4, state_17=0, state_76=6, state_97=1, var_10=0, var_113=4, var_116=6, var_120=9, var_137=0, var_13=0, var_140=0, var_14=-56, var_73=5, var_75=0, var_7=0, var_8=1] [L156] SORT_72 var_74_arg_0 = var_73; [L157] var_74_arg_0 = var_74_arg_0 & mask_SORT_72 [L158] SORT_11 var_74 = var_74_arg_0; [L159] SORT_11 var_78_arg_0 = var_74; [L160] SORT_11 var_78_arg_1 = state_76; [L161] SORT_1 var_78 = var_78_arg_0 < var_78_arg_1; [L162] SORT_1 var_15_arg_0 = input_3; [L163] SORT_12 var_15_arg_1 = var_14; [L164] SORT_12 var_15_arg_2 = var_13; [L165] SORT_12 var_15 = var_15_arg_0 ? var_15_arg_1 : var_15_arg_2; [L166] var_15 = var_15 & mask_SORT_12 [L167] SORT_12 var_16_arg_0 = var_13; [L168] SORT_12 var_16_arg_1 = var_15; [L169] SORT_11 var_16 = ((SORT_11)var_16_arg_0 << 8) | var_16_arg_1; [L170] SORT_11 var_18_arg_0 = var_16; [L171] SORT_11 var_18_arg_1 = state_17; [L172] SORT_11 var_18 = var_18_arg_0 - var_18_arg_1; [L173] var_18 = var_18 & mask_SORT_11 [L174] SORT_11 var_19_arg_0 = var_18; [L175] SORT_1 var_19 = var_19_arg_0 >> 15; [L176] SORT_1 var_21_arg_0 = var_19; [L177] SORT_9 var_21_arg_1 = var_10; [L178] SORT_20 var_21 = ((SORT_20)var_21_arg_0 << 31) | var_21_arg_1; [L179] var_21 = var_21 & mask_SORT_20 [L180] SORT_11 var_64_arg_0 = var_18; [L181] SORT_1 var_64 = var_64_arg_0 >> 15; [L182] SORT_11 var_61_arg_0 = var_18; [L183] SORT_1 var_61 = var_61_arg_0 >> 15; [L184] SORT_11 var_58_arg_0 = var_18; [L185] SORT_1 var_58 = var_58_arg_0 >> 15; [L186] SORT_11 var_55_arg_0 = var_18; [L187] SORT_1 var_55 = var_55_arg_0 >> 15; [L188] SORT_11 var_52_arg_0 = var_18; [L189] SORT_1 var_52 = var_52_arg_0 >> 15; [L190] SORT_11 var_49_arg_0 = var_18; [L191] SORT_1 var_49 = var_49_arg_0 >> 15; [L192] SORT_11 var_46_arg_0 = var_18; [L193] SORT_1 var_46 = var_46_arg_0 >> 15; [L194] SORT_11 var_43_arg_0 = var_18; [L195] SORT_1 var_43 = var_43_arg_0 >> 15; [L196] SORT_11 var_40_arg_0 = var_18; [L197] SORT_1 var_40 = var_40_arg_0 >> 15; [L198] SORT_11 var_37_arg_0 = var_18; [L199] SORT_1 var_37 = var_37_arg_0 >> 15; [L200] SORT_11 var_34_arg_0 = var_18; [L201] SORT_1 var_34 = var_34_arg_0 >> 15; [L202] SORT_11 var_31_arg_0 = var_18; [L203] SORT_1 var_31 = var_31_arg_0 >> 15; [L204] SORT_11 var_28_arg_0 = var_18; [L205] SORT_1 var_28 = var_28_arg_0 >> 15; [L206] SORT_11 var_25_arg_0 = var_18; [L207] SORT_1 var_25 = var_25_arg_0 >> 15; [L208] SORT_11 var_22_arg_0 = var_18; [L209] SORT_1 var_22 = var_22_arg_0 >> 15; [L210] SORT_1 var_24_arg_0 = var_22; [L211] SORT_11 var_24_arg_1 = var_18; [L212] SORT_23 var_24 = ((SORT_23)var_24_arg_0 << 16) | var_24_arg_1; [L213] var_24 = var_24 & mask_SORT_23 [L214] SORT_1 var_27_arg_0 = var_25; [L215] SORT_23 var_27_arg_1 = var_24; [L216] SORT_26 var_27 = ((SORT_26)var_27_arg_0 << 17) | var_27_arg_1; [L217] var_27 = var_27 & mask_SORT_26 [L218] SORT_1 var_30_arg_0 = var_28; [L219] SORT_26 var_30_arg_1 = var_27; [L220] SORT_29 var_30 = ((SORT_29)var_30_arg_0 << 18) | var_30_arg_1; [L221] var_30 = var_30 & mask_SORT_29 [L222] SORT_1 var_33_arg_0 = var_31; [L223] SORT_29 var_33_arg_1 = var_30; [L224] SORT_32 var_33 = ((SORT_32)var_33_arg_0 << 19) | var_33_arg_1; [L225] var_33 = var_33 & mask_SORT_32 [L226] SORT_1 var_36_arg_0 = var_34; [L227] SORT_32 var_36_arg_1 = var_33; [L228] SORT_35 var_36 = ((SORT_35)var_36_arg_0 << 20) | var_36_arg_1; [L229] var_36 = var_36 & mask_SORT_35 [L230] SORT_1 var_39_arg_0 = var_37; [L231] SORT_35 var_39_arg_1 = var_36; [L232] SORT_38 var_39 = ((SORT_38)var_39_arg_0 << 21) | var_39_arg_1; [L233] var_39 = var_39 & mask_SORT_38 [L234] SORT_1 var_42_arg_0 = var_40; [L235] SORT_38 var_42_arg_1 = var_39; [L236] SORT_41 var_42 = ((SORT_41)var_42_arg_0 << 22) | var_42_arg_1; [L237] var_42 = var_42 & mask_SORT_41 [L238] SORT_1 var_45_arg_0 = var_43; [L239] SORT_41 var_45_arg_1 = var_42; [L240] SORT_44 var_45 = ((SORT_44)var_45_arg_0 << 23) | var_45_arg_1; [L241] var_45 = var_45 & mask_SORT_44 [L242] SORT_1 var_48_arg_0 = var_46; [L243] SORT_44 var_48_arg_1 = var_45; [L244] SORT_47 var_48 = ((SORT_47)var_48_arg_0 << 24) | var_48_arg_1; [L245] var_48 = var_48 & mask_SORT_47 [L246] SORT_1 var_51_arg_0 = var_49; [L247] SORT_47 var_51_arg_1 = var_48; [L248] SORT_50 var_51 = ((SORT_50)var_51_arg_0 << 25) | var_51_arg_1; [L249] var_51 = var_51 & mask_SORT_50 [L250] SORT_1 var_54_arg_0 = var_52; [L251] SORT_50 var_54_arg_1 = var_51; [L252] SORT_53 var_54 = ((SORT_53)var_54_arg_0 << 26) | var_54_arg_1; [L253] var_54 = var_54 & mask_SORT_53 [L254] SORT_1 var_57_arg_0 = var_55; [L255] SORT_53 var_57_arg_1 = var_54; [L256] SORT_56 var_57 = ((SORT_56)var_57_arg_0 << 27) | var_57_arg_1; [L257] var_57 = var_57 & mask_SORT_56 [L258] SORT_1 var_60_arg_0 = var_58; [L259] SORT_56 var_60_arg_1 = var_57; [L260] SORT_59 var_60 = ((SORT_59)var_60_arg_0 << 28) | var_60_arg_1; [L261] var_60 = var_60 & mask_SORT_59 [L262] SORT_1 var_63_arg_0 = var_61; [L263] SORT_59 var_63_arg_1 = var_60; [L264] SORT_62 var_63 = ((SORT_62)var_63_arg_0 << 29) | var_63_arg_1; [L265] var_63 = var_63 & mask_SORT_62 [L266] SORT_1 var_65_arg_0 = var_64; [L267] SORT_62 var_65_arg_1 = var_63; [L268] SORT_9 var_65 = ((SORT_9)var_65_arg_0 << 30) | var_65_arg_1; [L269] SORT_9 var_66_arg_0 = var_65; [L270] var_66_arg_0 = var_66_arg_0 & mask_SORT_9 [L271] SORT_20 var_66 = var_66_arg_0; [L272] SORT_20 var_67_arg_0 = var_21; [L273] SORT_20 var_67_arg_1 = var_66; [L274] SORT_1 var_67 = var_67_arg_0 <= var_67_arg_1; [L275] SORT_1 var_68_arg_0 = var_67; [L276] SORT_1 var_68_arg_1 = var_8; [L277] SORT_1 var_68_arg_2 = var_7; [L278] SORT_1 var_68 = var_68_arg_0 ? var_68_arg_1 : var_68_arg_2; [L279] var_68 = var_68 & mask_SORT_1 [L280] SORT_1 var_69_arg_0 = input_3; [L281] SORT_1 var_69_arg_1 = var_68; [L282] SORT_1 var_69 = var_69_arg_0 ^ var_69_arg_1; [L283] SORT_1 var_70_arg_0 = var_69; [L284] SORT_1 var_70 = ~var_70_arg_0; [L285] SORT_1 var_79_arg_0 = var_78; [L286] SORT_1 var_79_arg_1 = var_70; [L287] SORT_1 var_79_arg_2 = var_8; [L288] SORT_1 var_79 = var_79_arg_0 ? var_79_arg_1 : var_79_arg_2; [L289] SORT_1 var_80_arg_0 = var_79; [L290] SORT_1 var_80 = ~var_80_arg_0; [L291] SORT_1 var_81_arg_0 = var_79; [L292] SORT_1 var_81 = ~var_81_arg_0; [L293] SORT_1 var_82_arg_0 = var_80; [L294] SORT_1 var_82_arg_1 = var_81; [L295] SORT_1 var_82 = var_82_arg_0 & var_82_arg_1; [L296] var_82 = var_82 & mask_SORT_1 [L297] SORT_1 bad_83_arg_0 = var_82; [L298] CALL __VERIFIER_assert(!(bad_83_arg_0)) [L21] COND TRUE !(cond) [L21] reach_error() - StatisticsResult: Ultimate Automizer benchmark data CFG has 2 procedures, 19 locations, 1 error locations. Started 1 CEGAR loops. OverallTime: 33.7s, OverallIterations: 8, TraceHistogramMax: 14, PathProgramHistogramMax: 6, EmptinessCheckTime: 0.0s, AutomataDifference: 3.1s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, InitialAbstractionConstructionTime: 0.0s, HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 12 SdHoareTripleChecker+Valid, 2.1s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 12 mSDsluCounter, 555 SdHoareTripleChecker+Invalid, 1.9s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 421 mSDsCounter, 13 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 718 IncrementalHoareTripleChecker+Invalid, 731 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 13 mSolverCounterUnsat, 134 mSDtfsCounter, 718 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown, PredicateUnifierStatistics: 0 DeclaredPredicates, 723 GetRequests, 652 SyntacticMatches, 5 SemanticMatches, 66 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 92 ImplicationChecksByTransitivity, 2.1s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=56occurred in iteration=7, InterpolantAutomatonStates: 56, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 0.1s AutomataMinimizationTime, 7 MinimizatonAttempts, 6 StatesRemovedByMinimization, 6 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 2.4s SsaConstructionTime, 5.7s SatisfiabilityAnalysisTime, 12.3s InterpolantComputationTime, 778 NumberOfCodeBlocks, 766 NumberOfCodeBlocksAsserted, 51 NumberOfCheckSat, 658 ConstructedInterpolants, 21 QuantifiedInterpolants, 5800 SizeOfPredicates, 81 NumberOfNonLiveVariables, 8144 ConjunctsInSsa, 342 ConjunctsInUnsatCore, 13 InterpolantComputations, 2 PerfectInterpolantSequences, 1289/1752 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, ACCELERATED_INTERPOLATION: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! [2024-11-08 17:01:56,202 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_4d779130-2c8e-4256-9199-4b9f27d7008b/bin/uautomizer-verify-jihMAELWvX/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE