./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.03.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 4f9af400 extending candidate: java ['java'] extending candidate: /usr/bin/java ['java', '/usr/bin/java'] extending candidate: /opt/oracle-jdk-bin-*/bin/java ['java', '/usr/bin/java'] extending candidate: /opt/openjdk-*/bin/java ['java', '/usr/bin/java'] extending candidate: /usr/lib/jvm/java-*-openjdk-amd64/bin/java ['java', '/usr/bin/java', '/usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java', '/usr/lib/jvm/java-17-openjdk-amd64/bin/java', '/usr/lib/jvm/java-11-openjdk-amd64/bin/java', '/usr/lib/jvm/java-1.17.0-openjdk-amd64/bin/java'] ['/root/.sdkman/candidates/java/21.0.5-tem/bin/java', '-Dosgi.configuration.area=/storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/config', '-Xmx15G', '-Xms4m', '-jar', '/storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar', '-data', '@noDefault', '-ultimatedata', '/storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data', '-tc', '/storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml', '-i', '../sv-benchmarks/c/systemc/token_ring.03.cil-2.c', '-s', '/storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf', '--cacsl2boogietranslator.entry.function', 'main', '--witnessprinter.witness.directory', '/storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux', '--witnessprinter.witness.filename', 'witness', '--witnessprinter.write.witness.besides.input.file', 'false', '--witnessprinter.graph.data.specification', 'CHECK( init(main()), LTL(F end) )\n\n', '--witnessprinter.graph.data.producer', 'Automizer', '--witnessprinter.graph.data.architecture', '32bit', '--witnessprinter.graph.data.programhash', '4996a252ab084c920e1b9a19c3119ce328d4cb97d6d45029062c9dac50449e19'] Calling Ultimate with: /root/.sdkman/candidates/java/21.0.5-tem/bin/java -Dosgi.configuration.area=/storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.03.cil-2.c -s /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 4996a252ab084c920e1b9a19c3119ce328d4cb97d6d45029062c9dac50449e19 --- Real Ultimate output --- This is Ultimate 0.3.0-?-4f9af40 [2024-11-08 00:34:43,259 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-08 00:34:43,398 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-11-08 00:34:43,409 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-08 00:34:43,409 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-08 00:34:43,450 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-08 00:34:43,451 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-08 00:34:43,451 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-08 00:34:43,451 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-08 00:34:43,451 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-08 00:34:43,451 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-08 00:34:43,452 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-08 00:34:43,452 INFO L153 SettingsManager]: * Use SBE=true [2024-11-08 00:34:43,452 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-11-08 00:34:43,452 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-11-08 00:34:43,452 INFO L153 SettingsManager]: * Use old map elimination=false [2024-11-08 00:34:43,452 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-11-08 00:34:43,452 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-11-08 00:34:43,452 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-11-08 00:34:43,452 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-08 00:34:43,454 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-11-08 00:34:43,454 INFO L153 SettingsManager]: * sizeof long=4 [2024-11-08 00:34:43,454 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-08 00:34:43,454 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-11-08 00:34:43,454 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-08 00:34:43,455 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-11-08 00:34:43,455 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-11-08 00:34:43,455 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-11-08 00:34:43,455 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-11-08 00:34:43,455 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-11-08 00:34:43,455 INFO L153 SettingsManager]: * sizeof long double=12 [2024-11-08 00:34:43,455 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-08 00:34:43,455 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-11-08 00:34:43,455 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-08 00:34:43,456 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-11-08 00:34:43,456 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-08 00:34:43,456 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-08 00:34:43,456 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-11-08 00:34:43,456 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-11-08 00:34:43,456 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 4996a252ab084c920e1b9a19c3119ce328d4cb97d6d45029062c9dac50449e19 [2024-11-08 00:34:43,699 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-08 00:34:43,707 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-08 00:34:43,709 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-08 00:34:43,710 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-08 00:34:43,710 INFO L274 PluginConnector]: CDTParser initialized [2024-11-08 00:34:43,712 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.03.cil-2.c [2024-11-08 00:34:44,935 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-11-08 00:34:45,168 INFO L384 CDTParser]: Found 1 translation units. [2024-11-08 00:34:45,169 INFO L180 CDTParser]: Scanning /storage/repos/ultimate-jdk21/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.03.cil-2.c [2024-11-08 00:34:45,179 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/549c19f4c/df6b00060f3d4cd4a0e0b04bff71fafc/FLAG324e9fd32 [2024-11-08 00:34:45,196 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/549c19f4c/df6b00060f3d4cd4a0e0b04bff71fafc [2024-11-08 00:34:45,198 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-08 00:34:45,199 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-08 00:34:45,200 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-08 00:34:45,200 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-08 00:34:45,203 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-08 00:34:45,204 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 08.11 12:34:45" (1/1) ... [2024-11-08 00:34:45,206 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@2bb56ef3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 12:34:45, skipping insertion in model container [2024-11-08 00:34:45,206 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 08.11 12:34:45" (1/1) ... [2024-11-08 00:34:45,227 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-08 00:34:45,370 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-08 00:34:45,383 INFO L200 MainTranslator]: Completed pre-run [2024-11-08 00:34:45,422 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-08 00:34:45,437 INFO L204 MainTranslator]: Completed translation [2024-11-08 00:34:45,438 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 12:34:45 WrapperNode [2024-11-08 00:34:45,439 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-08 00:34:45,439 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-08 00:34:45,439 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-08 00:34:45,439 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-08 00:34:45,445 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 12:34:45" (1/1) ... [2024-11-08 00:34:45,452 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 12:34:45" (1/1) ... [2024-11-08 00:34:45,483 INFO L138 Inliner]: procedures = 34, calls = 41, calls flagged for inlining = 36, calls inlined = 63, statements flattened = 822 [2024-11-08 00:34:45,484 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-08 00:34:45,487 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-08 00:34:45,487 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-08 00:34:45,487 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-08 00:34:45,500 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 12:34:45" (1/1) ... [2024-11-08 00:34:45,500 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 12:34:45" (1/1) ... [2024-11-08 00:34:45,503 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 12:34:45" (1/1) ... [2024-11-08 00:34:45,527 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-11-08 00:34:45,527 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 12:34:45" (1/1) ... [2024-11-08 00:34:45,527 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 12:34:45" (1/1) ... [2024-11-08 00:34:45,538 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 12:34:45" (1/1) ... [2024-11-08 00:34:45,553 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 12:34:45" (1/1) ... [2024-11-08 00:34:45,555 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 12:34:45" (1/1) ... [2024-11-08 00:34:45,561 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 12:34:45" (1/1) ... [2024-11-08 00:34:45,563 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-08 00:34:45,564 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-11-08 00:34:45,564 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-11-08 00:34:45,564 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-11-08 00:34:45,565 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 12:34:45" (1/1) ... [2024-11-08 00:34:45,569 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 00:34:45,578 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2024-11-08 00:34:45,599 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 00:34:45,604 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-11-08 00:34:45,617 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-08 00:34:45,618 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-11-08 00:34:45,618 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-08 00:34:45,618 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-08 00:34:45,674 INFO L238 CfgBuilder]: Building ICFG [2024-11-08 00:34:45,676 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-08 00:34:46,270 INFO L? ?]: Removed 144 outVars from TransFormulas that were not future-live. [2024-11-08 00:34:46,270 INFO L287 CfgBuilder]: Performing block encoding [2024-11-08 00:34:46,281 INFO L311 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-08 00:34:46,282 INFO L316 CfgBuilder]: Removed 6 assume(true) statements. [2024-11-08 00:34:46,282 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 08.11 12:34:46 BoogieIcfgContainer [2024-11-08 00:34:46,282 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-11-08 00:34:46,283 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-11-08 00:34:46,283 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-11-08 00:34:46,286 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-11-08 00:34:46,287 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-08 00:34:46,287 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 08.11 12:34:45" (1/3) ... [2024-11-08 00:34:46,288 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@15bebf9b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 08.11 12:34:46, skipping insertion in model container [2024-11-08 00:34:46,288 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-08 00:34:46,288 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 12:34:45" (2/3) ... [2024-11-08 00:34:46,288 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@15bebf9b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 08.11 12:34:46, skipping insertion in model container [2024-11-08 00:34:46,288 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-08 00:34:46,288 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 08.11 12:34:46" (3/3) ... [2024-11-08 00:34:46,289 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.03.cil-2.c [2024-11-08 00:34:46,323 INFO L300 stractBuchiCegarLoop]: Interprodecural is true [2024-11-08 00:34:46,323 INFO L301 stractBuchiCegarLoop]: Hoare is None [2024-11-08 00:34:46,323 INFO L302 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-11-08 00:34:46,323 INFO L303 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-11-08 00:34:46,323 INFO L304 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-11-08 00:34:46,324 INFO L305 stractBuchiCegarLoop]: Difference is false [2024-11-08 00:34:46,324 INFO L306 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-11-08 00:34:46,324 INFO L310 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-11-08 00:34:46,328 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 329 states, 328 states have (on average 1.5274390243902438) internal successors, (501), 328 states have internal predecessors, (501), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:34:46,350 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 270 [2024-11-08 00:34:46,351 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:34:46,351 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:34:46,360 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:46,360 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:46,360 INFO L332 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-11-08 00:34:46,361 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 329 states, 328 states have (on average 1.5274390243902438) internal successors, (501), 328 states have internal predecessors, (501), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:34:46,368 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 270 [2024-11-08 00:34:46,368 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:34:46,368 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:34:46,369 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:46,369 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:46,375 INFO L745 eck$LassoCheckResult]: Stem: 205#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 222#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 326#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 217#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 114#L292true assume !(1 == ~m_i~0);~m_st~0 := 2; 229#L292-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 207#L297-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 190#L302-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 198#L307-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 261#L429true assume !(0 == ~M_E~0); 56#L429-2true assume !(0 == ~T1_E~0); 150#L434-1true assume 0 == ~T2_E~0;~T2_E~0 := 1; 230#L439-1true assume !(0 == ~T3_E~0); 174#L444-1true assume !(0 == ~E_M~0); 278#L449-1true assume !(0 == ~E_1~0); 58#L454-1true assume !(0 == ~E_2~0); 304#L459-1true assume !(0 == ~E_3~0); 36#L464-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 297#L208true assume 1 == ~m_pc~0; 302#L209true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 329#L219true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 176#is_master_triggered_returnLabel#1true activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 50#L531true assume !(0 != activate_threads_~tmp~1#1); 137#L531-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 121#L227true assume !(1 == ~t1_pc~0); 49#L227-2true is_transmit1_triggered_~__retres1~1#1 := 0; 199#L238true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 43#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 57#L539true assume !(0 != activate_threads_~tmp___0~0#1); 145#L539-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 74#L246true assume 1 == ~t2_pc~0; 134#L247true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 156#L257true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 327#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 211#L547true assume !(0 != activate_threads_~tmp___1~0#1); 239#L547-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 81#L265true assume !(1 == ~t3_pc~0); 311#L265-2true is_transmit3_triggered_~__retres1~3#1 := 0; 3#L276true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 325#L555true assume !(0 != activate_threads_~tmp___2~0#1); 63#L555-2true havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 202#L477true assume !(1 == ~M_E~0); 267#L477-2true assume !(1 == ~T1_E~0); 223#L482-1true assume 1 == ~T2_E~0;~T2_E~0 := 2; 172#L487-1true assume !(1 == ~T3_E~0); 257#L492-1true assume !(1 == ~E_M~0); 40#L497-1true assume !(1 == ~E_1~0); 144#L502-1true assume !(1 == ~E_2~0); 30#L507-1true assume !(1 == ~E_3~0); 118#L512-1true assume { :end_inline_reset_delta_events } true; 194#L678-2true [2024-11-08 00:34:46,376 INFO L747 eck$LassoCheckResult]: Loop: 194#L678-2true assume !false; 286#L679true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 308#L404-1true assume !true; 106#eval_returnLabel#1true havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 146#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 269#L429-3true assume 0 == ~M_E~0;~M_E~0 := 1; 330#L429-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 192#L434-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 236#L439-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 61#L444-3true assume 0 == ~E_M~0;~E_M~0 := 1; 68#L449-3true assume 0 == ~E_1~0;~E_1~0 := 1; 92#L454-3true assume !(0 == ~E_2~0); 241#L459-3true assume 0 == ~E_3~0;~E_3~0 := 1; 59#L464-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 252#L208-15true assume 1 == ~m_pc~0; 281#L209-5true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 250#L219-5true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 96#is_master_triggered_returnLabel#6true activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 158#L531-15true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 69#L531-17true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 290#L227-15true assume 1 == ~t1_pc~0; 318#L228-5true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 242#L238-5true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 75#is_transmit1_triggered_returnLabel#6true activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 208#L539-15true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 189#L539-17true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 175#L246-15true assume 1 == ~t2_pc~0; 9#L247-5true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 254#L257-5true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 279#is_transmit2_triggered_returnLabel#6true activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 313#L547-15true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 55#L547-17true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 203#L265-15true assume !(1 == ~t3_pc~0); 271#L265-17true is_transmit3_triggered_~__retres1~3#1 := 0; 130#L276-5true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 247#is_transmit3_triggered_returnLabel#6true activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 86#L555-15true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 218#L555-17true havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 260#L477-3true assume 1 == ~M_E~0;~M_E~0 := 2; 180#L477-5true assume !(1 == ~T1_E~0); 266#L482-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 93#L487-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 54#L492-3true assume 1 == ~E_M~0;~E_M~0 := 2; 289#L497-3true assume 1 == ~E_1~0;~E_1~0 := 2; 142#L502-3true assume 1 == ~E_2~0;~E_2~0 := 2; 185#L507-3true assume 1 == ~E_3~0;~E_3~0 := 2; 109#L512-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 32#L320-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 13#L342-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 282#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 210#L697true assume !(0 == start_simulation_~tmp~3#1); 2#L697-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 258#L320-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 79#L342-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 41#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1; 328#L652true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 200#L659true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 162#stop_simulation_returnLabel#1true start_simulation_#t~ret16#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 80#L710true assume !(0 != start_simulation_~tmp___0~1#1); 194#L678-2true [2024-11-08 00:34:46,379 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:34:46,380 INFO L85 PathProgramCache]: Analyzing trace with hash 1917692997, now seen corresponding path program 1 times [2024-11-08 00:34:46,384 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:34:46,385 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1134831593] [2024-11-08 00:34:46,385 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:34:46,385 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:34:46,448 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:34:46,541 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:34:46,542 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:34:46,542 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1134831593] [2024-11-08 00:34:46,543 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1134831593] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:34:46,543 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:34:46,543 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:34:46,546 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1651373387] [2024-11-08 00:34:46,546 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:34:46,549 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:34:46,551 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:34:46,551 INFO L85 PathProgramCache]: Analyzing trace with hash 1122762879, now seen corresponding path program 1 times [2024-11-08 00:34:46,551 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:34:46,551 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1260790666] [2024-11-08 00:34:46,552 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:34:46,552 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:34:46,563 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:34:46,603 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:34:46,603 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:34:46,603 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1260790666] [2024-11-08 00:34:46,603 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1260790666] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:34:46,603 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:34:46,603 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-08 00:34:46,603 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [236588642] [2024-11-08 00:34:46,603 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:34:46,604 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:34:46,605 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:34:46,628 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:34:46,629 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:34:46,631 INFO L87 Difference]: Start difference. First operand has 329 states, 328 states have (on average 1.5274390243902438) internal successors, (501), 328 states have internal predecessors, (501), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:34:46,676 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:34:46,681 INFO L93 Difference]: Finished difference Result 327 states and 485 transitions. [2024-11-08 00:34:46,682 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 327 states and 485 transitions. [2024-11-08 00:34:46,689 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 267 [2024-11-08 00:34:46,699 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 327 states to 322 states and 480 transitions. [2024-11-08 00:34:46,700 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 322 [2024-11-08 00:34:46,702 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 322 [2024-11-08 00:34:46,703 INFO L73 IsDeterministic]: Start isDeterministic. Operand 322 states and 480 transitions. [2024-11-08 00:34:46,704 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:34:46,705 INFO L218 hiAutomatonCegarLoop]: Abstraction has 322 states and 480 transitions. [2024-11-08 00:34:46,716 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 322 states and 480 transitions. [2024-11-08 00:34:46,782 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 322 to 322. [2024-11-08 00:34:46,785 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 322 states, 322 states have (on average 1.4906832298136645) internal successors, (480), 321 states have internal predecessors, (480), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:34:46,786 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 322 states to 322 states and 480 transitions. [2024-11-08 00:34:46,787 INFO L240 hiAutomatonCegarLoop]: Abstraction has 322 states and 480 transitions. [2024-11-08 00:34:46,788 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:34:46,790 INFO L425 stractBuchiCegarLoop]: Abstraction has 322 states and 480 transitions. [2024-11-08 00:34:46,790 INFO L332 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-11-08 00:34:46,790 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 322 states and 480 transitions. [2024-11-08 00:34:46,794 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 267 [2024-11-08 00:34:46,794 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:34:46,795 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:34:46,796 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:46,797 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:46,798 INFO L745 eck$LassoCheckResult]: Stem: 949#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 950#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 962#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 960#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 867#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 868#L292-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 951#L297-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 937#L302-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 938#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 945#L429 assume !(0 == ~M_E~0); 771#L429-2 assume !(0 == ~T1_E~0); 772#L434-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 899#L439-1 assume !(0 == ~T3_E~0); 920#L444-1 assume !(0 == ~E_M~0); 921#L449-1 assume !(0 == ~E_1~0); 774#L454-1 assume !(0 == ~E_2~0); 775#L459-1 assume !(0 == ~E_3~0); 732#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 733#L208 assume 1 == ~m_pc~0; 984#L209 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 986#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 923#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 759#L531 assume !(0 != activate_threads_~tmp~1#1); 760#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 872#L227 assume !(1 == ~t1_pc~0); 757#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 758#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 745#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 746#L539 assume !(0 != activate_threads_~tmp___0~0#1); 773#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 806#L246 assume 1 == ~t2_pc~0; 807#L247 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 888#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 903#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 954#L547 assume !(0 != activate_threads_~tmp___1~0#1); 955#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 820#L265 assume !(1 == ~t3_pc~0); 694#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 667#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 668#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 695#L555 assume !(0 != activate_threads_~tmp___2~0#1); 788#L555-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 789#L477 assume !(1 == ~M_E~0); 948#L477-2 assume !(1 == ~T1_E~0); 963#L482-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 916#L487-1 assume !(1 == ~T3_E~0); 917#L492-1 assume !(1 == ~E_M~0); 743#L497-1 assume !(1 == ~E_1~0); 744#L502-1 assume !(1 == ~E_2~0); 722#L507-1 assume !(1 == ~E_3~0); 723#L512-1 assume { :end_inline_reset_delta_events } true; 817#L678-2 [2024-11-08 00:34:46,800 INFO L747 eck$LassoCheckResult]: Loop: 817#L678-2 assume !false; 943#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 956#L404-1 assume !false; 871#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 852#L320 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 707#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 696#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 697#L357 assume !(0 != eval_~tmp~0#1); 795#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 858#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 897#L429-3 assume 0 == ~M_E~0;~M_E~0 := 1; 977#L429-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 939#L434-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 940#L439-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 781#L444-3 assume 0 == ~E_M~0;~E_M~0 := 1; 782#L449-3 assume 0 == ~E_1~0;~E_1~0 := 1; 796#L454-3 assume !(0 == ~E_2~0); 835#L459-3 assume 0 == ~E_3~0;~E_3~0 := 1; 776#L464-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 777#L208-15 assume !(1 == ~m_pc~0); 925#L208-17 is_master_triggered_~__retres1~0#1 := 0; 926#L219-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 842#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 843#L531-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 797#L531-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 798#L227-15 assume !(1 == ~t1_pc~0); 979#L227-17 is_transmit1_triggered_~__retres1~1#1 := 0; 969#L238-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 804#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 805#L539-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 936#L539-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 922#L246-15 assume 1 == ~t2_pc~0; 675#L247-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 676#L257-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 974#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 981#L547-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 769#L547-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 770#L265-15 assume !(1 == ~t3_pc~0); 849#L265-17 is_transmit3_triggered_~__retres1~3#1 := 0; 848#L276-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 880#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 825#L555-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 826#L555-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 959#L477-3 assume 1 == ~M_E~0;~M_E~0 := 2; 927#L477-5 assume !(1 == ~T1_E~0); 928#L482-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 834#L487-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 765#L492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 766#L497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 893#L502-3 assume 1 == ~E_2~0;~E_2~0 := 2; 894#L507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 860#L512-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 726#L320-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 686#L342-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 687#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 952#L697 assume !(0 == start_simulation_~tmp~3#1); 665#L697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 666#L320-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 815#L342-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 738#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1; 739#L652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 946#L659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 905#stop_simulation_returnLabel#1 start_simulation_#t~ret16#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 816#L710 assume !(0 != start_simulation_~tmp___0~1#1); 817#L678-2 [2024-11-08 00:34:46,801 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:34:46,801 INFO L85 PathProgramCache]: Analyzing trace with hash -2024185917, now seen corresponding path program 1 times [2024-11-08 00:34:46,801 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:34:46,801 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [475387000] [2024-11-08 00:34:46,801 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:34:46,801 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:34:46,821 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:34:46,873 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:34:46,873 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:34:46,874 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [475387000] [2024-11-08 00:34:46,874 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [475387000] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:34:46,874 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:34:46,874 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:34:46,874 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [196147005] [2024-11-08 00:34:46,874 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:34:46,874 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:34:46,874 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:34:46,874 INFO L85 PathProgramCache]: Analyzing trace with hash 1981164799, now seen corresponding path program 1 times [2024-11-08 00:34:46,874 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:34:46,875 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [850436326] [2024-11-08 00:34:46,875 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:34:46,875 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:34:46,901 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:34:46,978 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:34:46,979 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:34:46,979 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [850436326] [2024-11-08 00:34:46,979 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [850436326] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:34:46,979 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:34:46,979 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:34:46,979 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [810592801] [2024-11-08 00:34:46,979 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:34:46,980 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:34:46,980 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:34:46,980 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:34:46,984 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:34:46,985 INFO L87 Difference]: Start difference. First operand 322 states and 480 transitions. cyclomatic complexity: 159 Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:34:47,008 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:34:47,011 INFO L93 Difference]: Finished difference Result 322 states and 479 transitions. [2024-11-08 00:34:47,011 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 322 states and 479 transitions. [2024-11-08 00:34:47,013 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 267 [2024-11-08 00:34:47,016 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 322 states to 322 states and 479 transitions. [2024-11-08 00:34:47,019 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 322 [2024-11-08 00:34:47,019 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 322 [2024-11-08 00:34:47,019 INFO L73 IsDeterministic]: Start isDeterministic. Operand 322 states and 479 transitions. [2024-11-08 00:34:47,020 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:34:47,020 INFO L218 hiAutomatonCegarLoop]: Abstraction has 322 states and 479 transitions. [2024-11-08 00:34:47,021 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 322 states and 479 transitions. [2024-11-08 00:34:47,029 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 322 to 322. [2024-11-08 00:34:47,033 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 322 states, 322 states have (on average 1.4875776397515528) internal successors, (479), 321 states have internal predecessors, (479), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:34:47,034 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 322 states to 322 states and 479 transitions. [2024-11-08 00:34:47,034 INFO L240 hiAutomatonCegarLoop]: Abstraction has 322 states and 479 transitions. [2024-11-08 00:34:47,035 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:34:47,035 INFO L425 stractBuchiCegarLoop]: Abstraction has 322 states and 479 transitions. [2024-11-08 00:34:47,036 INFO L332 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-11-08 00:34:47,036 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 322 states and 479 transitions. [2024-11-08 00:34:47,038 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 267 [2024-11-08 00:34:47,039 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:34:47,039 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:34:47,041 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:47,041 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:47,042 INFO L745 eck$LassoCheckResult]: Stem: 1600#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 1601#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 1614#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1611#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1520#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 1521#L292-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1602#L297-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1588#L302-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1589#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1596#L429 assume !(0 == ~M_E~0); 1422#L429-2 assume !(0 == ~T1_E~0); 1423#L434-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1550#L439-1 assume !(0 == ~T3_E~0); 1571#L444-1 assume !(0 == ~E_M~0); 1572#L449-1 assume !(0 == ~E_1~0); 1427#L454-1 assume !(0 == ~E_2~0); 1428#L459-1 assume !(0 == ~E_3~0); 1383#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1384#L208 assume 1 == ~m_pc~0; 1635#L209 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1637#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1574#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1410#L531 assume !(0 != activate_threads_~tmp~1#1); 1411#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1524#L227 assume !(1 == ~t1_pc~0); 1408#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1409#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1399#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1400#L539 assume !(0 != activate_threads_~tmp___0~0#1); 1424#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1455#L246 assume 1 == ~t2_pc~0; 1456#L247 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1539#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1554#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1605#L547 assume !(0 != activate_threads_~tmp___1~0#1); 1606#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1469#L265 assume !(1 == ~t3_pc~0); 1345#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1318#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1319#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1346#L555 assume !(0 != activate_threads_~tmp___2~0#1); 1436#L555-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1437#L477 assume !(1 == ~M_E~0); 1599#L477-2 assume !(1 == ~T1_E~0); 1613#L482-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1567#L487-1 assume !(1 == ~T3_E~0); 1568#L492-1 assume !(1 == ~E_M~0); 1389#L497-1 assume !(1 == ~E_1~0); 1390#L502-1 assume !(1 == ~E_2~0); 1373#L507-1 assume !(1 == ~E_3~0); 1374#L512-1 assume { :end_inline_reset_delta_events } true; 1468#L678-2 [2024-11-08 00:34:47,043 INFO L747 eck$LassoCheckResult]: Loop: 1468#L678-2 assume !false; 1592#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1607#L404-1 assume !false; 1522#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 1497#L320 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 1358#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 1347#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1348#L357 assume !(0 != eval_~tmp~0#1); 1444#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1509#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1546#L429-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1628#L429-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1590#L434-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1591#L439-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1432#L444-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1433#L449-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1447#L454-3 assume !(0 == ~E_2~0); 1485#L459-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1425#L464-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1426#L208-15 assume !(1 == ~m_pc~0); 1576#L208-17 is_master_triggered_~__retres1~0#1 := 0; 1577#L219-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1493#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1494#L531-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1448#L531-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1449#L227-15 assume 1 == ~t1_pc~0; 1633#L228-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1620#L238-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1458#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1459#L539-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1587#L539-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1573#L246-15 assume 1 == ~t2_pc~0; 1330#L247-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1331#L257-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1625#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1632#L547-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1420#L547-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1421#L265-15 assume 1 == ~t3_pc~0; 1499#L266-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1500#L276-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1534#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1477#L555-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1478#L555-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1610#L477-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1578#L477-5 assume !(1 == ~T1_E~0); 1579#L482-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1486#L487-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1418#L492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1419#L497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1544#L502-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1545#L507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1511#L512-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 1377#L320-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 1339#L342-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 1340#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 1604#L697 assume !(0 == start_simulation_~tmp~3#1); 1316#L697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 1317#L320-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 1466#L342-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 1391#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1; 1392#L652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1597#L659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1556#stop_simulation_returnLabel#1 start_simulation_#t~ret16#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 1467#L710 assume !(0 != start_simulation_~tmp___0~1#1); 1468#L678-2 [2024-11-08 00:34:47,043 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:34:47,043 INFO L85 PathProgramCache]: Analyzing trace with hash 1377295041, now seen corresponding path program 1 times [2024-11-08 00:34:47,043 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:34:47,043 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1085977486] [2024-11-08 00:34:47,044 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:34:47,044 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:34:47,057 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:34:47,099 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:34:47,099 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:34:47,099 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1085977486] [2024-11-08 00:34:47,099 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1085977486] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:34:47,099 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:34:47,100 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:34:47,100 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1398134374] [2024-11-08 00:34:47,100 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:34:47,100 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:34:47,100 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:34:47,100 INFO L85 PathProgramCache]: Analyzing trace with hash 315643517, now seen corresponding path program 1 times [2024-11-08 00:34:47,100 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:34:47,100 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1506900790] [2024-11-08 00:34:47,100 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:34:47,100 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:34:47,116 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:34:47,159 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:34:47,159 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:34:47,159 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1506900790] [2024-11-08 00:34:47,159 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1506900790] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:34:47,160 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:34:47,160 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:34:47,160 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [701048151] [2024-11-08 00:34:47,160 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:34:47,160 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:34:47,160 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:34:47,160 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:34:47,161 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:34:47,161 INFO L87 Difference]: Start difference. First operand 322 states and 479 transitions. cyclomatic complexity: 158 Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:34:47,174 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:34:47,175 INFO L93 Difference]: Finished difference Result 322 states and 478 transitions. [2024-11-08 00:34:47,175 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 322 states and 478 transitions. [2024-11-08 00:34:47,181 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 267 [2024-11-08 00:34:47,184 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 322 states to 322 states and 478 transitions. [2024-11-08 00:34:47,185 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 322 [2024-11-08 00:34:47,185 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 322 [2024-11-08 00:34:47,186 INFO L73 IsDeterministic]: Start isDeterministic. Operand 322 states and 478 transitions. [2024-11-08 00:34:47,187 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:34:47,187 INFO L218 hiAutomatonCegarLoop]: Abstraction has 322 states and 478 transitions. [2024-11-08 00:34:47,189 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 322 states and 478 transitions. [2024-11-08 00:34:47,197 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 322 to 322. [2024-11-08 00:34:47,201 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 322 states, 322 states have (on average 1.484472049689441) internal successors, (478), 321 states have internal predecessors, (478), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:34:47,202 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 322 states to 322 states and 478 transitions. [2024-11-08 00:34:47,203 INFO L240 hiAutomatonCegarLoop]: Abstraction has 322 states and 478 transitions. [2024-11-08 00:34:47,203 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:34:47,204 INFO L425 stractBuchiCegarLoop]: Abstraction has 322 states and 478 transitions. [2024-11-08 00:34:47,204 INFO L332 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-11-08 00:34:47,204 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 322 states and 478 transitions. [2024-11-08 00:34:47,206 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 267 [2024-11-08 00:34:47,208 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:34:47,208 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:34:47,209 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:47,209 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:47,209 INFO L745 eck$LassoCheckResult]: Stem: 2251#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 2252#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 2264#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2261#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2167#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 2168#L292-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2253#L297-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2239#L302-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2240#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2247#L429 assume !(0 == ~M_E~0); 2073#L429-2 assume !(0 == ~T1_E~0); 2074#L434-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2201#L439-1 assume !(0 == ~T3_E~0); 2222#L444-1 assume !(0 == ~E_M~0); 2223#L449-1 assume !(0 == ~E_1~0); 2076#L454-1 assume !(0 == ~E_2~0); 2077#L459-1 assume !(0 == ~E_3~0); 2034#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2035#L208 assume 1 == ~m_pc~0; 2286#L209 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2288#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2225#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2061#L531 assume !(0 != activate_threads_~tmp~1#1); 2062#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2174#L227 assume !(1 == ~t1_pc~0); 2059#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2060#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2047#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2048#L539 assume !(0 != activate_threads_~tmp___0~0#1); 2075#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2106#L246 assume 1 == ~t2_pc~0; 2107#L247 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2190#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2205#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2256#L547 assume !(0 != activate_threads_~tmp___1~0#1); 2257#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2120#L265 assume !(1 == ~t3_pc~0); 1996#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1969#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1970#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1997#L555 assume !(0 != activate_threads_~tmp___2~0#1); 2087#L555-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2088#L477 assume !(1 == ~M_E~0); 2250#L477-2 assume !(1 == ~T1_E~0); 2265#L482-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2218#L487-1 assume !(1 == ~T3_E~0); 2219#L492-1 assume !(1 == ~E_M~0); 2040#L497-1 assume !(1 == ~E_1~0); 2041#L502-1 assume !(1 == ~E_2~0); 2024#L507-1 assume !(1 == ~E_3~0); 2025#L512-1 assume { :end_inline_reset_delta_events } true; 2119#L678-2 [2024-11-08 00:34:47,210 INFO L747 eck$LassoCheckResult]: Loop: 2119#L678-2 assume !false; 2243#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2258#L404-1 assume !false; 2173#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 2148#L320 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 2009#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 1998#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1999#L357 assume !(0 != eval_~tmp~0#1); 2095#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2160#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2197#L429-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2279#L429-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2241#L434-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2242#L439-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2083#L444-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2084#L449-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2098#L454-3 assume !(0 == ~E_2~0); 2136#L459-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2078#L464-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2079#L208-15 assume !(1 == ~m_pc~0); 2227#L208-17 is_master_triggered_~__retres1~0#1 := 0; 2228#L219-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2144#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2145#L531-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2099#L531-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2100#L227-15 assume !(1 == ~t1_pc~0); 2281#L227-17 is_transmit1_triggered_~__retres1~1#1 := 0; 2271#L238-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2109#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2110#L539-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2238#L539-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2224#L246-15 assume 1 == ~t2_pc~0; 1981#L247-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1982#L257-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2276#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2283#L547-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2071#L547-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2072#L265-15 assume 1 == ~t3_pc~0; 2150#L266-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2151#L276-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2185#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2128#L555-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2129#L555-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2262#L477-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2229#L477-5 assume !(1 == ~T1_E~0); 2230#L482-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2137#L487-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2069#L492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2070#L497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2195#L502-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2196#L507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2163#L512-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 2028#L320-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 1990#L342-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 1991#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 2255#L697 assume !(0 == start_simulation_~tmp~3#1); 1967#L697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 1968#L320-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 2117#L342-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 2042#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1; 2043#L652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2248#L659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2207#stop_simulation_returnLabel#1 start_simulation_#t~ret16#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 2118#L710 assume !(0 != start_simulation_~tmp___0~1#1); 2119#L678-2 [2024-11-08 00:34:47,211 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:34:47,211 INFO L85 PathProgramCache]: Analyzing trace with hash -868284413, now seen corresponding path program 1 times [2024-11-08 00:34:47,211 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:34:47,212 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [967814596] [2024-11-08 00:34:47,212 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:34:47,212 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:34:47,228 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:34:47,285 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:34:47,285 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:34:47,285 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [967814596] [2024-11-08 00:34:47,285 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [967814596] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:34:47,285 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:34:47,286 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:34:47,286 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [957174259] [2024-11-08 00:34:47,286 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:34:47,286 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:34:47,286 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:34:47,286 INFO L85 PathProgramCache]: Analyzing trace with hash -641284866, now seen corresponding path program 1 times [2024-11-08 00:34:47,286 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:34:47,286 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1137461679] [2024-11-08 00:34:47,286 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:34:47,286 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:34:47,295 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:34:47,322 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:34:47,323 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:34:47,323 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1137461679] [2024-11-08 00:34:47,323 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1137461679] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:34:47,323 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:34:47,323 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:34:47,323 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1503362097] [2024-11-08 00:34:47,323 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:34:47,324 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:34:47,324 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:34:47,324 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-08 00:34:47,324 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-08 00:34:47,324 INFO L87 Difference]: Start difference. First operand 322 states and 478 transitions. cyclomatic complexity: 157 Second operand has 4 states, 4 states have (on average 12.75) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:34:47,389 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:34:47,389 INFO L93 Difference]: Finished difference Result 559 states and 824 transitions. [2024-11-08 00:34:47,389 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 559 states and 824 transitions. [2024-11-08 00:34:47,393 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 496 [2024-11-08 00:34:47,395 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 559 states to 559 states and 824 transitions. [2024-11-08 00:34:47,396 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 559 [2024-11-08 00:34:47,396 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 559 [2024-11-08 00:34:47,396 INFO L73 IsDeterministic]: Start isDeterministic. Operand 559 states and 824 transitions. [2024-11-08 00:34:47,397 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:34:47,397 INFO L218 hiAutomatonCegarLoop]: Abstraction has 559 states and 824 transitions. [2024-11-08 00:34:47,398 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 559 states and 824 transitions. [2024-11-08 00:34:47,405 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 559 to 559. [2024-11-08 00:34:47,406 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 559 states, 559 states have (on average 1.4740608228980323) internal successors, (824), 558 states have internal predecessors, (824), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:34:47,407 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 559 states to 559 states and 824 transitions. [2024-11-08 00:34:47,408 INFO L240 hiAutomatonCegarLoop]: Abstraction has 559 states and 824 transitions. [2024-11-08 00:34:47,408 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-08 00:34:47,409 INFO L425 stractBuchiCegarLoop]: Abstraction has 559 states and 824 transitions. [2024-11-08 00:34:47,409 INFO L332 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-11-08 00:34:47,409 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 559 states and 824 transitions. [2024-11-08 00:34:47,411 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 496 [2024-11-08 00:34:47,411 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:34:47,411 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:34:47,412 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:47,412 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:47,412 INFO L745 eck$LassoCheckResult]: Stem: 3157#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 3158#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 3171#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3167#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3063#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 3064#L292-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3159#L297-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3141#L302-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3142#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3151#L429 assume !(0 == ~M_E~0); 2966#L429-2 assume !(0 == ~T1_E~0); 2967#L434-1 assume !(0 == ~T2_E~0); 3102#L439-1 assume !(0 == ~T3_E~0); 3124#L444-1 assume !(0 == ~E_M~0); 3125#L449-1 assume !(0 == ~E_1~0); 2969#L454-1 assume !(0 == ~E_2~0); 2970#L459-1 assume !(0 == ~E_3~0); 2925#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2926#L208 assume 1 == ~m_pc~0; 3199#L209 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3201#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3127#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2954#L531 assume !(0 != activate_threads_~tmp~1#1); 2955#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3071#L227 assume !(1 == ~t1_pc~0); 2952#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2953#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2939#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2940#L539 assume !(0 != activate_threads_~tmp___0~0#1); 2968#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3000#L246 assume 1 == ~t2_pc~0; 3001#L247 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3090#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3106#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3162#L547 assume !(0 != activate_threads_~tmp___1~0#1); 3163#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3014#L265 assume !(1 == ~t3_pc~0); 2887#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2860#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2861#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2888#L555 assume !(0 != activate_threads_~tmp___2~0#1); 2980#L555-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2981#L477 assume 1 == ~M_E~0;~M_E~0 := 2; 3155#L477-2 assume !(1 == ~T1_E~0); 3172#L482-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3120#L487-1 assume !(1 == ~T3_E~0); 3121#L492-1 assume !(1 == ~E_M~0); 2932#L497-1 assume !(1 == ~E_1~0); 2933#L502-1 assume !(1 == ~E_2~0); 2915#L507-1 assume !(1 == ~E_3~0); 2916#L512-1 assume { :end_inline_reset_delta_events } true; 3228#L678-2 [2024-11-08 00:34:47,412 INFO L747 eck$LassoCheckResult]: Loop: 3228#L678-2 assume !false; 3212#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3211#L404-1 assume !false; 3210#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 3208#L320 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 2929#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 2889#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2890#L357 assume !(0 != eval_~tmp~0#1); 3054#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3055#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3202#L429-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3203#L429-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3392#L434-3 assume !(0 == ~T2_E~0); 3391#L439-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3390#L444-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3389#L449-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3388#L454-3 assume !(0 == ~E_2~0); 3387#L459-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3386#L464-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3385#L208-15 assume !(1 == ~m_pc~0); 3383#L208-17 is_master_triggered_~__retres1~0#1 := 0; 3382#L219-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3381#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 3380#L531-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3379#L531-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3378#L227-15 assume 1 == ~t1_pc~0; 3376#L228-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3375#L238-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3374#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3373#L539-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3372#L539-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3371#L246-15 assume !(1 == ~t2_pc~0); 3369#L246-17 is_transmit2_triggered_~__retres1~2#1 := 0; 3368#L257-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3367#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3366#L547-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3365#L547-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3364#L265-15 assume 1 == ~t3_pc~0; 3362#L266-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3361#L276-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3360#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3359#L555-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3358#L555-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3357#L477-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3188#L477-5 assume !(1 == ~T1_E~0); 3356#L482-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3190#L487-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3355#L492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3354#L497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3353#L502-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3352#L507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3351#L512-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 2919#L320-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 2881#L342-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 2882#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 3161#L697 assume !(0 == start_simulation_~tmp~3#1); 2858#L697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 2859#L320-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 3011#L342-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 2934#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1; 2935#L652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3152#L659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3153#stop_simulation_returnLabel#1 start_simulation_#t~ret16#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 3230#L710 assume !(0 != start_simulation_~tmp___0~1#1); 3228#L678-2 [2024-11-08 00:34:47,413 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:34:47,413 INFO L85 PathProgramCache]: Analyzing trace with hash 1374817215, now seen corresponding path program 1 times [2024-11-08 00:34:47,413 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:34:47,413 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [98507023] [2024-11-08 00:34:47,413 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:34:47,413 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:34:47,419 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:34:47,439 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:34:47,440 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:34:47,440 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [98507023] [2024-11-08 00:34:47,440 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [98507023] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:34:47,440 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:34:47,440 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-08 00:34:47,440 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [128949242] [2024-11-08 00:34:47,440 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:34:47,440 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:34:47,441 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:34:47,441 INFO L85 PathProgramCache]: Analyzing trace with hash 277425788, now seen corresponding path program 1 times [2024-11-08 00:34:47,441 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:34:47,441 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2107321778] [2024-11-08 00:34:47,441 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:34:47,441 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:34:47,447 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:34:47,464 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:34:47,465 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:34:47,465 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2107321778] [2024-11-08 00:34:47,465 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2107321778] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:34:47,465 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:34:47,465 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:34:47,465 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1113131354] [2024-11-08 00:34:47,465 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:34:47,465 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:34:47,465 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:34:47,465 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:34:47,465 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:34:47,465 INFO L87 Difference]: Start difference. First operand 559 states and 824 transitions. cyclomatic complexity: 267 Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 2 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:34:47,532 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:34:47,532 INFO L93 Difference]: Finished difference Result 1039 states and 1509 transitions. [2024-11-08 00:34:47,532 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1039 states and 1509 transitions. [2024-11-08 00:34:47,537 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 973 [2024-11-08 00:34:47,542 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1039 states to 1039 states and 1509 transitions. [2024-11-08 00:34:47,542 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1039 [2024-11-08 00:34:47,543 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1039 [2024-11-08 00:34:47,543 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1039 states and 1509 transitions. [2024-11-08 00:34:47,544 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:34:47,544 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1039 states and 1509 transitions. [2024-11-08 00:34:47,546 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1039 states and 1509 transitions. [2024-11-08 00:34:47,564 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1039 to 985. [2024-11-08 00:34:47,566 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 985 states, 985 states have (on average 1.4568527918781726) internal successors, (1435), 984 states have internal predecessors, (1435), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:34:47,568 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 985 states to 985 states and 1435 transitions. [2024-11-08 00:34:47,569 INFO L240 hiAutomatonCegarLoop]: Abstraction has 985 states and 1435 transitions. [2024-11-08 00:34:47,569 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:34:47,570 INFO L425 stractBuchiCegarLoop]: Abstraction has 985 states and 1435 transitions. [2024-11-08 00:34:47,571 INFO L332 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-11-08 00:34:47,571 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 985 states and 1435 transitions. [2024-11-08 00:34:47,575 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 919 [2024-11-08 00:34:47,575 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:34:47,575 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:34:47,576 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:47,576 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:47,576 INFO L745 eck$LassoCheckResult]: Stem: 4787#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 4788#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 4807#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4801#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4679#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 4680#L292-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4789#L297-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4768#L302-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4769#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4781#L429 assume !(0 == ~M_E~0); 4574#L429-2 assume !(0 == ~T1_E~0); 4575#L434-1 assume !(0 == ~T2_E~0); 4719#L439-1 assume !(0 == ~T3_E~0); 4744#L444-1 assume !(0 == ~E_M~0); 4745#L449-1 assume !(0 == ~E_1~0); 4579#L454-1 assume !(0 == ~E_2~0); 4580#L459-1 assume !(0 == ~E_3~0); 4533#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4534#L208 assume !(1 == ~m_pc~0); 4866#L208-2 is_master_triggered_~__retres1~0#1 := 0; 4867#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4747#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 4562#L531 assume !(0 != activate_threads_~tmp~1#1); 4563#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4685#L227 assume !(1 == ~t1_pc~0); 4560#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4561#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4548#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4549#L539 assume !(0 != activate_threads_~tmp___0~0#1); 4576#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4609#L246 assume 1 == ~t2_pc~0; 4610#L247 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4704#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4724#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4794#L547 assume !(0 != activate_threads_~tmp___1~0#1); 4795#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4624#L265 assume !(1 == ~t3_pc~0); 4493#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4465#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4466#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4494#L555 assume !(0 != activate_threads_~tmp___2~0#1); 4593#L555-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4594#L477 assume 1 == ~M_E~0;~M_E~0 := 2; 4784#L477-2 assume !(1 == ~T1_E~0); 4808#L482-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4740#L487-1 assume !(1 == ~T3_E~0); 4741#L492-1 assume !(1 == ~E_M~0); 4546#L497-1 assume !(1 == ~E_1~0); 4547#L502-1 assume !(1 == ~E_2~0); 4521#L507-1 assume !(1 == ~E_3~0); 4522#L512-1 assume { :end_inline_reset_delta_events } true; 5277#L678-2 [2024-11-08 00:34:47,576 INFO L747 eck$LassoCheckResult]: Loop: 5277#L678-2 assume !false; 5274#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5273#L404-1 assume !false; 4683#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 4684#L320 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 4539#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 4540#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 5269#L357 assume !(0 != eval_~tmp~0#1); 4667#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4668#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5267#L429-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5268#L429-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5422#L434-3 assume !(0 == ~T2_E~0); 5421#L439-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5420#L444-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5419#L449-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5418#L454-3 assume !(0 == ~E_2~0); 5417#L459-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5416#L464-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5415#L208-15 assume !(1 == ~m_pc~0); 5414#L208-17 is_master_triggered_~__retres1~0#1 := 0; 5413#L219-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5412#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 5411#L531-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5410#L531-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5409#L227-15 assume 1 == ~t1_pc~0; 4883#L228-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4825#L238-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4607#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4608#L539-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4766#L539-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4767#L246-15 assume !(1 == ~t2_pc~0); 5399#L246-17 is_transmit2_triggered_~__retres1~2#1 := 0; 5397#L257-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4847#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4848#L547-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4572#L547-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4573#L265-15 assume !(1 == ~t3_pc~0); 4657#L265-17 is_transmit3_triggered_~__retres1~3#1 := 0; 4656#L276-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4696#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4828#L555-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5375#L555-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5373#L477-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4835#L477-5 assume !(1 == ~T1_E~0); 5371#L482-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4838#L487-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5370#L492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5369#L497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5368#L502-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5367#L507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5366#L512-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 5006#L320-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 5003#L342-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 4852#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 4853#L697 assume !(0 == start_simulation_~tmp~3#1); 4463#L697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 4464#L320-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 4618#L342-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 4541#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1; 4542#L652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4782#L659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4726#stop_simulation_returnLabel#1 start_simulation_#t~ret16#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 4727#L710 assume !(0 != start_simulation_~tmp___0~1#1); 5277#L678-2 [2024-11-08 00:34:47,579 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:34:47,579 INFO L85 PathProgramCache]: Analyzing trace with hash -201740544, now seen corresponding path program 1 times [2024-11-08 00:34:47,579 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:34:47,579 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1191060398] [2024-11-08 00:34:47,579 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:34:47,579 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:34:47,585 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:34:47,614 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:34:47,615 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:34:47,615 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1191060398] [2024-11-08 00:34:47,615 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1191060398] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:34:47,615 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:34:47,615 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-08 00:34:47,615 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2043692012] [2024-11-08 00:34:47,615 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:34:47,615 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:34:47,615 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:34:47,615 INFO L85 PathProgramCache]: Analyzing trace with hash -1395091843, now seen corresponding path program 1 times [2024-11-08 00:34:47,615 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:34:47,615 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [418987908] [2024-11-08 00:34:47,615 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:34:47,615 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:34:47,622 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:34:47,637 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:34:47,637 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:34:47,638 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [418987908] [2024-11-08 00:34:47,638 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [418987908] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:34:47,638 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:34:47,638 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:34:47,638 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [756205692] [2024-11-08 00:34:47,638 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:34:47,638 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:34:47,638 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:34:47,639 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:34:47,639 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:34:47,639 INFO L87 Difference]: Start difference. First operand 985 states and 1435 transitions. cyclomatic complexity: 454 Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 2 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:34:47,680 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:34:47,681 INFO L93 Difference]: Finished difference Result 1769 states and 2555 transitions. [2024-11-08 00:34:47,681 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1769 states and 2555 transitions. [2024-11-08 00:34:47,689 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1692 [2024-11-08 00:34:47,698 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1769 states to 1769 states and 2555 transitions. [2024-11-08 00:34:47,698 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1769 [2024-11-08 00:34:47,699 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1769 [2024-11-08 00:34:47,699 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1769 states and 2555 transitions. [2024-11-08 00:34:47,701 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:34:47,702 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1769 states and 2555 transitions. [2024-11-08 00:34:47,703 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1769 states and 2555 transitions. [2024-11-08 00:34:47,727 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1769 to 1761. [2024-11-08 00:34:47,730 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1761 states, 1761 states have (on average 1.4463373083475297) internal successors, (2547), 1760 states have internal predecessors, (2547), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:34:47,735 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1761 states to 1761 states and 2547 transitions. [2024-11-08 00:34:47,735 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1761 states and 2547 transitions. [2024-11-08 00:34:47,736 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:34:47,737 INFO L425 stractBuchiCegarLoop]: Abstraction has 1761 states and 2547 transitions. [2024-11-08 00:34:47,739 INFO L332 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-11-08 00:34:47,739 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1761 states and 2547 transitions. [2024-11-08 00:34:47,746 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1684 [2024-11-08 00:34:47,746 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:34:47,746 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:34:47,748 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:47,748 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:47,749 INFO L745 eck$LassoCheckResult]: Stem: 7524#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 7525#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 7546#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7539#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7431#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 7432#L292-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7527#L297-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7510#L302-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7511#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7519#L429 assume !(0 == ~M_E~0); 7331#L429-2 assume !(0 == ~T1_E~0); 7332#L434-1 assume !(0 == ~T2_E~0); 7465#L439-1 assume !(0 == ~T3_E~0); 7490#L444-1 assume !(0 == ~E_M~0); 7491#L449-1 assume !(0 == ~E_1~0); 7334#L454-1 assume !(0 == ~E_2~0); 7335#L459-1 assume !(0 == ~E_3~0); 7292#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7293#L208 assume !(1 == ~m_pc~0); 7594#L208-2 is_master_triggered_~__retres1~0#1 := 0; 7595#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7493#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 7319#L531 assume !(0 != activate_threads_~tmp~1#1); 7320#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7437#L227 assume !(1 == ~t1_pc~0); 7317#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 7318#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7305#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 7306#L539 assume !(0 != activate_threads_~tmp___0~0#1); 7333#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7366#L246 assume !(1 == ~t2_pc~0); 7367#L246-2 is_transmit2_triggered_~__retres1~2#1 := 0; 7471#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7472#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 7532#L547 assume !(0 != activate_threads_~tmp___1~0#1); 7533#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7379#L265 assume !(1 == ~t3_pc~0); 7255#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 7226#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7227#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7256#L555 assume !(0 != activate_threads_~tmp___2~0#1); 7345#L555-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7346#L477 assume 1 == ~M_E~0;~M_E~0 := 2; 7522#L477-2 assume !(1 == ~T1_E~0); 7547#L482-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7548#L487-1 assume !(1 == ~T3_E~0); 8251#L492-1 assume !(1 == ~E_M~0); 7298#L497-1 assume !(1 == ~E_1~0); 7299#L502-1 assume !(1 == ~E_2~0); 8239#L507-1 assume !(1 == ~E_3~0); 8235#L512-1 assume { :end_inline_reset_delta_events } true; 8231#L678-2 [2024-11-08 00:34:47,750 INFO L747 eck$LassoCheckResult]: Loop: 8231#L678-2 assume !false; 8226#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8224#L404-1 assume !false; 8222#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 8219#L320 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 8215#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 8211#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 8208#L357 assume !(0 != eval_~tmp~0#1); 8209#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8378#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8377#L429-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8376#L429-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8375#L434-3 assume !(0 == ~T2_E~0); 8374#L439-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8373#L444-3 assume 0 == ~E_M~0;~E_M~0 := 1; 8372#L449-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8371#L454-3 assume !(0 == ~E_2~0); 8370#L459-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8369#L464-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8368#L208-15 assume !(1 == ~m_pc~0); 8367#L208-17 is_master_triggered_~__retres1~0#1 := 0; 8366#L219-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8365#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 8364#L531-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8363#L531-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8362#L227-15 assume 1 == ~t1_pc~0; 8360#L228-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8358#L238-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8356#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 8354#L539-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8353#L539-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8350#L246-15 assume !(1 == ~t2_pc~0); 8349#L246-17 is_transmit2_triggered_~__retres1~2#1 := 0; 8347#L257-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8345#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 8343#L547-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8341#L547-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8338#L265-15 assume 1 == ~t3_pc~0; 8334#L266-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8331#L276-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8328#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 8325#L555-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 8322#L555-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8318#L477-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7570#L477-5 assume !(1 == ~T1_E~0); 8312#L482-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7573#L487-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8305#L492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8301#L497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8297#L502-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8293#L507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8289#L512-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 8285#L320-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 8277#L342-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 8273#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 8269#L697 assume !(0 == start_simulation_~tmp~3#1); 8264#L697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 8261#L320-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 8255#L342-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 8252#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1; 8248#L652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8243#L659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8240#stop_simulation_returnLabel#1 start_simulation_#t~ret16#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 8236#L710 assume !(0 != start_simulation_~tmp___0~1#1); 8231#L678-2 [2024-11-08 00:34:47,750 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:34:47,750 INFO L85 PathProgramCache]: Analyzing trace with hash -1175229503, now seen corresponding path program 1 times [2024-11-08 00:34:47,750 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:34:47,751 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [768198967] [2024-11-08 00:34:47,751 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:34:47,751 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:34:47,759 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:34:47,781 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:34:47,782 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:34:47,782 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [768198967] [2024-11-08 00:34:47,782 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [768198967] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:34:47,782 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:34:47,782 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-08 00:34:47,782 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1494586] [2024-11-08 00:34:47,782 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:34:47,782 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:34:47,782 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:34:47,783 INFO L85 PathProgramCache]: Analyzing trace with hash 277425788, now seen corresponding path program 2 times [2024-11-08 00:34:47,783 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:34:47,783 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1059166335] [2024-11-08 00:34:47,783 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:34:47,783 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:34:47,788 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:34:47,802 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:34:47,802 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:34:47,803 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1059166335] [2024-11-08 00:34:47,803 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1059166335] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:34:47,803 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:34:47,803 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:34:47,803 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1230112505] [2024-11-08 00:34:47,803 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:34:47,803 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:34:47,803 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:34:47,803 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:34:47,804 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:34:47,804 INFO L87 Difference]: Start difference. First operand 1761 states and 2547 transitions. cyclomatic complexity: 794 Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 2 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:34:47,832 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:34:47,832 INFO L93 Difference]: Finished difference Result 2567 states and 3710 transitions. [2024-11-08 00:34:47,832 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2567 states and 3710 transitions. [2024-11-08 00:34:47,843 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2484 [2024-11-08 00:34:47,854 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2567 states to 2567 states and 3710 transitions. [2024-11-08 00:34:47,854 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2567 [2024-11-08 00:34:47,856 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2567 [2024-11-08 00:34:47,856 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2567 states and 3710 transitions. [2024-11-08 00:34:47,859 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:34:47,859 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2567 states and 3710 transitions. [2024-11-08 00:34:47,860 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2567 states and 3710 transitions. [2024-11-08 00:34:47,906 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2567 to 1785. [2024-11-08 00:34:47,909 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1785 states, 1785 states have (on average 1.4492997198879551) internal successors, (2587), 1784 states have internal predecessors, (2587), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:34:47,913 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1785 states to 1785 states and 2587 transitions. [2024-11-08 00:34:47,914 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1785 states and 2587 transitions. [2024-11-08 00:34:47,914 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:34:47,914 INFO L425 stractBuchiCegarLoop]: Abstraction has 1785 states and 2587 transitions. [2024-11-08 00:34:47,914 INFO L332 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-11-08 00:34:47,914 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1785 states and 2587 transitions. [2024-11-08 00:34:47,920 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1716 [2024-11-08 00:34:47,920 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:34:47,920 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:34:47,921 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:47,921 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:47,921 INFO L745 eck$LassoCheckResult]: Stem: 11857#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 11858#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 11872#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11869#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11764#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 11765#L292-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11860#L297-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11843#L302-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 11844#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11853#L429 assume !(0 == ~M_E~0); 11664#L429-2 assume !(0 == ~T1_E~0); 11665#L434-1 assume !(0 == ~T2_E~0); 11797#L439-1 assume !(0 == ~T3_E~0); 11822#L444-1 assume !(0 == ~E_M~0); 11823#L449-1 assume !(0 == ~E_1~0); 11667#L454-1 assume !(0 == ~E_2~0); 11668#L459-1 assume !(0 == ~E_3~0); 11625#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11626#L208 assume !(1 == ~m_pc~0); 11910#L208-2 is_master_triggered_~__retres1~0#1 := 0; 11911#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11826#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 11652#L531 assume !(0 != activate_threads_~tmp~1#1); 11653#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11772#L227 assume !(1 == ~t1_pc~0); 11650#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 11651#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11638#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 11639#L539 assume !(0 != activate_threads_~tmp___0~0#1); 11666#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11697#L246 assume !(1 == ~t2_pc~0); 11698#L246-2 is_transmit2_triggered_~__retres1~2#1 := 0; 11801#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11802#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 11863#L547 assume !(0 != activate_threads_~tmp___1~0#1); 11864#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11710#L265 assume !(1 == ~t3_pc~0); 11588#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 11561#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11562#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 11589#L555 assume !(0 != activate_threads_~tmp___2~0#1); 11678#L555-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11679#L477 assume !(1 == ~M_E~0); 11856#L477-2 assume !(1 == ~T1_E~0); 11873#L482-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11817#L487-1 assume !(1 == ~T3_E~0); 11818#L492-1 assume !(1 == ~E_M~0); 11631#L497-1 assume !(1 == ~E_1~0); 11632#L502-1 assume !(1 == ~E_2~0); 11616#L507-1 assume !(1 == ~E_3~0); 11617#L512-1 assume { :end_inline_reset_delta_events } true; 11770#L678-2 [2024-11-08 00:34:47,921 INFO L747 eck$LassoCheckResult]: Loop: 11770#L678-2 assume !false; 12693#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12690#L404-1 assume !false; 12688#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 12684#L320 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 12680#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 12678#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 12676#L357 assume !(0 != eval_~tmp~0#1); 11754#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11755#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11793#L429-3 assume !(0 == ~M_E~0); 11897#L429-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11845#L434-3 assume !(0 == ~T2_E~0); 11846#L439-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11674#L444-3 assume 0 == ~E_M~0;~E_M~0 := 1; 11675#L449-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11689#L454-3 assume !(0 == ~E_2~0); 11728#L459-3 assume 0 == ~E_3~0;~E_3~0 := 1; 11669#L464-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11670#L208-15 assume !(1 == ~m_pc~0); 11828#L208-17 is_master_triggered_~__retres1~0#1 := 0; 11829#L219-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11736#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 11737#L531-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 11690#L531-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11691#L227-15 assume 1 == ~t1_pc~0; 11908#L228-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 11885#L238-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11699#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 11700#L539-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11842#L539-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11824#L246-15 assume !(1 == ~t2_pc~0); 11825#L246-17 is_transmit2_triggered_~__retres1~2#1 := 0; 11890#L257-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11891#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 11901#L547-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11662#L547-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11663#L265-15 assume !(1 == ~t3_pc~0); 11745#L265-17 is_transmit3_triggered_~__retres1~3#1 := 0; 11744#L276-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11782#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 11719#L555-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 11720#L555-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11870#L477-3 assume !(1 == ~M_E~0); 11831#L477-5 assume !(1 == ~T1_E~0); 11832#L482-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11729#L487-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11660#L492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 11661#L497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 11791#L502-3 assume 1 == ~E_2~0;~E_2~0 := 2; 11792#L507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 11758#L512-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 11620#L320-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 11582#L342-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 11583#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 11862#L697 assume !(0 == start_simulation_~tmp~3#1); 11559#L697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 11560#L320-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 11712#L342-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 12928#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1; 12925#L652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12921#L659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12918#stop_simulation_returnLabel#1 start_simulation_#t~ret16#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 12913#L710 assume !(0 != start_simulation_~tmp___0~1#1); 11770#L678-2 [2024-11-08 00:34:47,921 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:34:47,922 INFO L85 PathProgramCache]: Analyzing trace with hash -495171133, now seen corresponding path program 1 times [2024-11-08 00:34:47,922 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:34:47,922 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1087149876] [2024-11-08 00:34:47,922 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:34:47,922 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:34:47,927 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:34:47,950 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:34:47,950 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:34:47,950 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1087149876] [2024-11-08 00:34:47,950 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1087149876] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:34:47,950 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:34:47,950 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:34:47,950 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1688642346] [2024-11-08 00:34:47,950 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:34:47,950 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:34:47,950 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:34:47,951 INFO L85 PathProgramCache]: Analyzing trace with hash -96371011, now seen corresponding path program 1 times [2024-11-08 00:34:47,951 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:34:47,951 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2029554999] [2024-11-08 00:34:47,951 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:34:47,951 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:34:47,957 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:34:47,972 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:34:47,972 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:34:47,972 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2029554999] [2024-11-08 00:34:47,973 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2029554999] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:34:47,973 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:34:47,973 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:34:47,973 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1855013023] [2024-11-08 00:34:47,974 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:34:47,974 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:34:47,974 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:34:47,974 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-08 00:34:47,974 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-08 00:34:47,975 INFO L87 Difference]: Start difference. First operand 1785 states and 2587 transitions. cyclomatic complexity: 806 Second operand has 4 states, 4 states have (on average 12.75) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:34:48,016 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:34:48,017 INFO L93 Difference]: Finished difference Result 2561 states and 3678 transitions. [2024-11-08 00:34:48,017 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2561 states and 3678 transitions. [2024-11-08 00:34:48,028 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2484 [2024-11-08 00:34:48,037 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2561 states to 2561 states and 3678 transitions. [2024-11-08 00:34:48,037 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2561 [2024-11-08 00:34:48,040 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2561 [2024-11-08 00:34:48,040 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2561 states and 3678 transitions. [2024-11-08 00:34:48,043 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:34:48,043 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2561 states and 3678 transitions. [2024-11-08 00:34:48,045 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2561 states and 3678 transitions. [2024-11-08 00:34:48,063 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2561 to 1785. [2024-11-08 00:34:48,066 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1785 states, 1785 states have (on average 1.4397759103641457) internal successors, (2570), 1784 states have internal predecessors, (2570), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:34:48,070 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1785 states to 1785 states and 2570 transitions. [2024-11-08 00:34:48,070 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1785 states and 2570 transitions. [2024-11-08 00:34:48,071 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-08 00:34:48,073 INFO L425 stractBuchiCegarLoop]: Abstraction has 1785 states and 2570 transitions. [2024-11-08 00:34:48,073 INFO L332 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-11-08 00:34:48,073 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1785 states and 2570 transitions. [2024-11-08 00:34:48,079 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1716 [2024-11-08 00:34:48,080 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:34:48,080 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:34:48,081 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:48,082 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:48,082 INFO L745 eck$LassoCheckResult]: Stem: 16213#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 16214#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 16229#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16226#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16119#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 16120#L292-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16216#L297-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 16199#L302-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 16200#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16209#L429 assume !(0 == ~M_E~0); 16021#L429-2 assume !(0 == ~T1_E~0); 16022#L434-1 assume !(0 == ~T2_E~0); 16152#L439-1 assume !(0 == ~T3_E~0); 16178#L444-1 assume !(0 == ~E_M~0); 16179#L449-1 assume !(0 == ~E_1~0); 16024#L454-1 assume !(0 == ~E_2~0); 16025#L459-1 assume !(0 == ~E_3~0); 15982#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15983#L208 assume !(1 == ~m_pc~0); 16268#L208-2 is_master_triggered_~__retres1~0#1 := 0; 16269#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16181#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 16009#L531 assume !(0 != activate_threads_~tmp~1#1); 16010#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16127#L227 assume !(1 == ~t1_pc~0); 16007#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 16008#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15995#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 15996#L539 assume !(0 != activate_threads_~tmp___0~0#1); 16023#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16054#L246 assume !(1 == ~t2_pc~0); 16055#L246-2 is_transmit2_triggered_~__retres1~2#1 := 0; 16157#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16158#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 16220#L547 assume !(0 != activate_threads_~tmp___1~0#1); 16221#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16067#L265 assume !(1 == ~t3_pc~0); 15945#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 15917#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15918#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 15946#L555 assume !(0 != activate_threads_~tmp___2~0#1); 16035#L555-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16036#L477 assume !(1 == ~M_E~0); 16212#L477-2 assume !(1 == ~T1_E~0); 16230#L482-1 assume !(1 == ~T2_E~0); 16173#L487-1 assume !(1 == ~T3_E~0); 16174#L492-1 assume !(1 == ~E_M~0); 15988#L497-1 assume !(1 == ~E_1~0); 15989#L502-1 assume !(1 == ~E_2~0); 15973#L507-1 assume !(1 == ~E_3~0); 15974#L512-1 assume { :end_inline_reset_delta_events } true; 16125#L678-2 [2024-11-08 00:34:48,082 INFO L747 eck$LassoCheckResult]: Loop: 16125#L678-2 assume !false; 16994#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16911#L404-1 assume !false; 16910#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 16427#L320 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 16423#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 16421#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 16418#L357 assume !(0 != eval_~tmp~0#1); 16419#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 17187#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 17186#L429-3 assume !(0 == ~M_E~0); 17185#L429-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 17184#L434-3 assume !(0 == ~T2_E~0); 17183#L439-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 17182#L444-3 assume 0 == ~E_M~0;~E_M~0 := 1; 17181#L449-3 assume 0 == ~E_1~0;~E_1~0 := 1; 17180#L454-3 assume !(0 == ~E_2~0); 17179#L459-3 assume 0 == ~E_3~0;~E_3~0 := 1; 17178#L464-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17177#L208-15 assume !(1 == ~m_pc~0); 17176#L208-17 is_master_triggered_~__retres1~0#1 := 0; 17175#L219-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17174#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 17173#L531-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 17172#L531-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17171#L227-15 assume 1 == ~t1_pc~0; 17169#L228-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 17168#L238-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17167#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 17166#L539-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 17165#L539-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17164#L246-15 assume !(1 == ~t2_pc~0); 17163#L246-17 is_transmit2_triggered_~__retres1~2#1 := 0; 17162#L257-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17161#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 17160#L547-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 17159#L547-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17158#L265-15 assume 1 == ~t3_pc~0; 17156#L266-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 17155#L276-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17154#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 17153#L555-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17152#L555-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17151#L477-3 assume !(1 == ~M_E~0); 16848#L477-5 assume !(1 == ~T1_E~0); 17150#L482-3 assume !(1 == ~T2_E~0); 17149#L487-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17148#L492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 17147#L497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 17146#L502-3 assume 1 == ~E_2~0;~E_2~0 := 2; 16193#L507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 16114#L512-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 15977#L320-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 15938#L342-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 15939#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 16218#L697 assume !(0 == start_simulation_~tmp~3#1); 16219#L697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 17014#L320-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 17009#L342-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 17007#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1; 17004#L652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 17002#L659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 17000#stop_simulation_returnLabel#1 start_simulation_#t~ret16#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 16998#L710 assume !(0 != start_simulation_~tmp___0~1#1); 16125#L678-2 [2024-11-08 00:34:48,082 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:34:48,082 INFO L85 PathProgramCache]: Analyzing trace with hash 1279836229, now seen corresponding path program 1 times [2024-11-08 00:34:48,082 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:34:48,083 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1229403051] [2024-11-08 00:34:48,083 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:34:48,083 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:34:48,090 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:34:48,091 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 00:34:48,096 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:34:48,117 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 00:34:48,117 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:34:48,117 INFO L85 PathProgramCache]: Analyzing trace with hash -112797122, now seen corresponding path program 1 times [2024-11-08 00:34:48,118 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:34:48,118 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [15711376] [2024-11-08 00:34:48,118 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:34:48,118 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:34:48,128 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:34:48,146 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:34:48,146 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:34:48,146 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [15711376] [2024-11-08 00:34:48,146 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [15711376] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:34:48,146 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:34:48,146 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:34:48,146 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1325495999] [2024-11-08 00:34:48,146 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:34:48,146 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:34:48,147 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:34:48,147 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:34:48,147 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:34:48,147 INFO L87 Difference]: Start difference. First operand 1785 states and 2570 transitions. cyclomatic complexity: 789 Second operand has 3 states, 3 states have (on average 21.333333333333332) internal successors, (64), 3 states have internal predecessors, (64), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:34:48,171 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:34:48,172 INFO L93 Difference]: Finished difference Result 2108 states and 3030 transitions. [2024-11-08 00:34:48,172 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2108 states and 3030 transitions. [2024-11-08 00:34:48,179 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2004 [2024-11-08 00:34:48,185 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2108 states to 2108 states and 3030 transitions. [2024-11-08 00:34:48,185 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2108 [2024-11-08 00:34:48,186 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2108 [2024-11-08 00:34:48,186 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2108 states and 3030 transitions. [2024-11-08 00:34:48,189 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:34:48,189 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2108 states and 3030 transitions. [2024-11-08 00:34:48,190 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2108 states and 3030 transitions. [2024-11-08 00:34:48,232 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2108 to 2108. [2024-11-08 00:34:48,234 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2108 states, 2108 states have (on average 1.4373814041745732) internal successors, (3030), 2107 states have internal predecessors, (3030), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:34:48,239 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2108 states to 2108 states and 3030 transitions. [2024-11-08 00:34:48,239 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2108 states and 3030 transitions. [2024-11-08 00:34:48,239 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:34:48,239 INFO L425 stractBuchiCegarLoop]: Abstraction has 2108 states and 3030 transitions. [2024-11-08 00:34:48,240 INFO L332 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-11-08 00:34:48,240 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2108 states and 3030 transitions. [2024-11-08 00:34:48,243 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2004 [2024-11-08 00:34:48,244 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:34:48,244 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:34:48,244 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:48,244 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:48,244 INFO L745 eck$LassoCheckResult]: Stem: 20124#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 20125#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 20143#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20139#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 20023#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 20024#L292-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 20127#L297-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 20111#L302-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20112#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20120#L429 assume !(0 == ~M_E~0); 19919#L429-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 19920#L434-1 assume !(0 == ~T2_E~0); 20067#L439-1 assume !(0 == ~T3_E~0); 20092#L444-1 assume !(0 == ~E_M~0); 20093#L449-1 assume !(0 == ~E_1~0); 20216#L454-1 assume !(0 == ~E_2~0); 20181#L459-1 assume !(0 == ~E_3~0); 20182#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20215#L208 assume !(1 == ~m_pc~0); 20178#L208-2 is_master_triggered_~__retres1~0#1 := 0; 20179#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20096#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 19907#L531 assume !(0 != activate_threads_~tmp~1#1); 19908#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20032#L227 assume !(1 == ~t1_pc~0); 19905#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 19906#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19893#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 19894#L539 assume !(0 != activate_threads_~tmp___0~0#1); 19922#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20203#L246 assume !(1 == ~t2_pc~0); 20202#L246-2 is_transmit2_triggered_~__retres1~2#1 := 0; 20201#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20200#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 20199#L547 assume !(0 != activate_threads_~tmp___1~0#1); 20198#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20197#L265 assume !(1 == ~t3_pc~0); 19843#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 19816#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19817#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 19844#L555 assume !(0 != activate_threads_~tmp___2~0#1); 19934#L555-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19935#L477 assume !(1 == ~M_E~0); 20123#L477-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 20144#L482-1 assume !(1 == ~T2_E~0); 20087#L487-1 assume !(1 == ~T3_E~0); 20088#L492-1 assume !(1 == ~E_M~0); 19886#L497-1 assume !(1 == ~E_1~0); 19887#L502-1 assume !(1 == ~E_2~0); 19871#L507-1 assume !(1 == ~E_3~0); 19872#L512-1 assume { :end_inline_reset_delta_events } true; 20030#L678-2 [2024-11-08 00:34:48,245 INFO L747 eck$LassoCheckResult]: Loop: 20030#L678-2 assume !false; 20908#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 20904#L404-1 assume !false; 20900#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 20895#L320 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 20889#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 20883#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 20877#L357 assume !(0 != eval_~tmp~0#1); 20878#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 21197#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 21195#L429-3 assume !(0 == ~M_E~0); 21193#L429-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 21190#L434-3 assume !(0 == ~T2_E~0); 21186#L439-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 21182#L444-3 assume 0 == ~E_M~0;~E_M~0 := 1; 21178#L449-3 assume 0 == ~E_1~0;~E_1~0 := 1; 21174#L454-3 assume !(0 == ~E_2~0); 21170#L459-3 assume 0 == ~E_3~0;~E_3~0 := 1; 21166#L464-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21162#L208-15 assume !(1 == ~m_pc~0); 21158#L208-17 is_master_triggered_~__retres1~0#1 := 0; 21154#L219-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21150#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 21146#L531-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 21142#L531-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21138#L227-15 assume 1 == ~t1_pc~0; 21132#L228-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 21126#L238-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21122#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 21118#L539-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 21113#L539-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21108#L246-15 assume !(1 == ~t2_pc~0); 21103#L246-17 is_transmit2_triggered_~__retres1~2#1 := 0; 21098#L257-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21092#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 21087#L547-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 21082#L547-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21078#L265-15 assume 1 == ~t3_pc~0; 21067#L266-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 21058#L276-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21052#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 21046#L555-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 21040#L555-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21033#L477-3 assume !(1 == ~M_E~0); 21024#L477-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 21020#L482-3 assume !(1 == ~T2_E~0); 21016#L487-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 21011#L492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 21005#L497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 21000#L502-3 assume 1 == ~E_2~0;~E_2~0 := 2; 20995#L507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 20990#L512-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 20985#L320-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 20976#L342-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 20971#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 20966#L697 assume !(0 == start_simulation_~tmp~3#1); 20960#L697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 20956#L320-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 20949#L342-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 20945#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1; 20939#L652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 20932#L659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 20927#stop_simulation_returnLabel#1 start_simulation_#t~ret16#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 20922#L710 assume !(0 != start_simulation_~tmp___0~1#1); 20030#L678-2 [2024-11-08 00:34:48,245 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:34:48,245 INFO L85 PathProgramCache]: Analyzing trace with hash 1665536133, now seen corresponding path program 1 times [2024-11-08 00:34:48,245 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:34:48,245 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [664924254] [2024-11-08 00:34:48,245 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:34:48,245 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:34:48,254 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:34:48,279 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:34:48,279 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:34:48,279 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [664924254] [2024-11-08 00:34:48,279 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [664924254] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:34:48,279 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:34:48,279 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-08 00:34:48,279 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [333543155] [2024-11-08 00:34:48,279 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:34:48,280 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:34:48,280 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:34:48,280 INFO L85 PathProgramCache]: Analyzing trace with hash 704851328, now seen corresponding path program 1 times [2024-11-08 00:34:48,280 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:34:48,280 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1616234228] [2024-11-08 00:34:48,280 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:34:48,280 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:34:48,289 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:34:48,335 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:34:48,335 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:34:48,335 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1616234228] [2024-11-08 00:34:48,335 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1616234228] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:34:48,335 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:34:48,335 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-08 00:34:48,335 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1067285425] [2024-11-08 00:34:48,335 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:34:48,335 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:34:48,335 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:34:48,336 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:34:48,336 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:34:48,336 INFO L87 Difference]: Start difference. First operand 2108 states and 3030 transitions. cyclomatic complexity: 926 Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 2 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:34:48,361 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:34:48,361 INFO L93 Difference]: Finished difference Result 1785 states and 2544 transitions. [2024-11-08 00:34:48,361 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1785 states and 2544 transitions. [2024-11-08 00:34:48,372 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1716 [2024-11-08 00:34:48,381 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1785 states to 1785 states and 2544 transitions. [2024-11-08 00:34:48,381 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1785 [2024-11-08 00:34:48,382 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1785 [2024-11-08 00:34:48,382 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1785 states and 2544 transitions. [2024-11-08 00:34:48,391 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:34:48,391 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1785 states and 2544 transitions. [2024-11-08 00:34:48,392 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1785 states and 2544 transitions. [2024-11-08 00:34:48,415 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1785 to 1785. [2024-11-08 00:34:48,417 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1785 states, 1785 states have (on average 1.4252100840336135) internal successors, (2544), 1784 states have internal predecessors, (2544), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:34:48,421 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1785 states to 1785 states and 2544 transitions. [2024-11-08 00:34:48,421 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1785 states and 2544 transitions. [2024-11-08 00:34:48,421 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:34:48,421 INFO L425 stractBuchiCegarLoop]: Abstraction has 1785 states and 2544 transitions. [2024-11-08 00:34:48,421 INFO L332 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-11-08 00:34:48,421 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1785 states and 2544 transitions. [2024-11-08 00:34:48,424 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1716 [2024-11-08 00:34:48,424 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:34:48,424 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:34:48,425 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:48,425 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:48,425 INFO L745 eck$LassoCheckResult]: Stem: 24015#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 24016#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 24032#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 24029#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 23918#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 23919#L292-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 24020#L297-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 24002#L302-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 24003#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 24010#L429 assume !(0 == ~M_E~0); 23822#L429-2 assume !(0 == ~T1_E~0); 23823#L434-1 assume !(0 == ~T2_E~0); 23958#L439-1 assume !(0 == ~T3_E~0); 23982#L444-1 assume !(0 == ~E_M~0); 23983#L449-1 assume !(0 == ~E_1~0); 23825#L454-1 assume !(0 == ~E_2~0); 23826#L459-1 assume !(0 == ~E_3~0); 23783#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 23784#L208 assume !(1 == ~m_pc~0); 24068#L208-2 is_master_triggered_~__retres1~0#1 := 0; 24069#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 23986#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 23810#L531 assume !(0 != activate_threads_~tmp~1#1); 23811#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23926#L227 assume !(1 == ~t1_pc~0); 23808#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 23809#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23796#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 23797#L539 assume !(0 != activate_threads_~tmp___0~0#1); 23824#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23856#L246 assume !(1 == ~t2_pc~0); 23857#L246-2 is_transmit2_triggered_~__retres1~2#1 := 0; 23962#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23963#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 24023#L547 assume !(0 != activate_threads_~tmp___1~0#1); 24024#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 23869#L265 assume !(1 == ~t3_pc~0); 23745#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 23718#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23719#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 23746#L555 assume !(0 != activate_threads_~tmp___2~0#1); 23836#L555-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 23837#L477 assume !(1 == ~M_E~0); 24013#L477-2 assume !(1 == ~T1_E~0); 24033#L482-1 assume !(1 == ~T2_E~0); 23977#L487-1 assume !(1 == ~T3_E~0); 23978#L492-1 assume !(1 == ~E_M~0); 23789#L497-1 assume !(1 == ~E_1~0); 23790#L502-1 assume !(1 == ~E_2~0); 23773#L507-1 assume !(1 == ~E_3~0); 23774#L512-1 assume { :end_inline_reset_delta_events } true; 23924#L678-2 [2024-11-08 00:34:48,425 INFO L747 eck$LassoCheckResult]: Loop: 23924#L678-2 assume !false; 24796#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 24795#L404-1 assume !false; 24794#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 24792#L320 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 24789#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 24788#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 23843#L357 assume !(0 != eval_~tmp~0#1); 23845#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25499#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25497#L429-3 assume !(0 == ~M_E~0); 25495#L429-5 assume !(0 == ~T1_E~0); 25493#L434-3 assume !(0 == ~T2_E~0); 25491#L439-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25489#L444-3 assume 0 == ~E_M~0;~E_M~0 := 1; 25487#L449-3 assume 0 == ~E_1~0;~E_1~0 := 1; 25485#L454-3 assume !(0 == ~E_2~0); 25483#L459-3 assume 0 == ~E_3~0;~E_3~0 := 1; 25481#L464-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25479#L208-15 assume !(1 == ~m_pc~0); 25477#L208-17 is_master_triggered_~__retres1~0#1 := 0; 25475#L219-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25473#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 25471#L531-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 25469#L531-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25467#L227-15 assume 1 == ~t1_pc~0; 25465#L228-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 24041#L238-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23858#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 23859#L539-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 24001#L539-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23984#L246-15 assume !(1 == ~t2_pc~0); 23985#L246-17 is_transmit2_triggered_~__retres1~2#1 := 0; 25446#L257-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25443#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 25440#L547-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 23820#L547-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 23821#L265-15 assume 1 == ~t3_pc~0; 25429#L266-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 23938#L276-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23939#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 23877#L555-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 23878#L555-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24030#L477-3 assume !(1 == ~M_E~0); 23990#L477-5 assume !(1 == ~T1_E~0); 23991#L482-3 assume !(1 == ~T2_E~0); 23886#L487-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 23818#L492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 23819#L497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 24063#L502-3 assume 1 == ~E_2~0;~E_2~0 := 2; 24828#L507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 24827#L512-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 24825#L320-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 24820#L342-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 24818#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 24817#L697 assume !(0 == start_simulation_~tmp~3#1); 24815#L697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 24814#L320-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 24810#L342-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 24809#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1; 24807#L652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 24805#L659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 24803#stop_simulation_returnLabel#1 start_simulation_#t~ret16#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 24801#L710 assume !(0 != start_simulation_~tmp___0~1#1); 23924#L678-2 [2024-11-08 00:34:48,425 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:34:48,425 INFO L85 PathProgramCache]: Analyzing trace with hash 1279836229, now seen corresponding path program 2 times [2024-11-08 00:34:48,426 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:34:48,426 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1464072915] [2024-11-08 00:34:48,426 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:34:48,426 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:34:48,431 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:34:48,431 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 00:34:48,433 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:34:48,437 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 00:34:48,438 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:34:48,438 INFO L85 PathProgramCache]: Analyzing trace with hash 331103552, now seen corresponding path program 1 times [2024-11-08 00:34:48,438 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:34:48,438 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1075495151] [2024-11-08 00:34:48,438 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:34:48,438 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:34:48,443 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:34:48,472 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:34:48,472 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:34:48,472 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1075495151] [2024-11-08 00:34:48,472 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1075495151] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:34:48,472 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:34:48,472 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-08 00:34:48,472 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2105957751] [2024-11-08 00:34:48,472 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:34:48,472 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:34:48,472 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:34:48,472 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-08 00:34:48,472 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-08 00:34:48,473 INFO L87 Difference]: Start difference. First operand 1785 states and 2544 transitions. cyclomatic complexity: 763 Second operand has 5 states, 5 states have (on average 12.8) internal successors, (64), 5 states have internal predecessors, (64), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:34:48,515 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:34:48,515 INFO L93 Difference]: Finished difference Result 1841 states and 2600 transitions. [2024-11-08 00:34:48,515 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1841 states and 2600 transitions. [2024-11-08 00:34:48,519 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1772 [2024-11-08 00:34:48,524 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1841 states to 1841 states and 2600 transitions. [2024-11-08 00:34:48,524 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1841 [2024-11-08 00:34:48,525 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1841 [2024-11-08 00:34:48,525 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1841 states and 2600 transitions. [2024-11-08 00:34:48,527 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:34:48,527 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1841 states and 2600 transitions. [2024-11-08 00:34:48,528 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1841 states and 2600 transitions. [2024-11-08 00:34:48,563 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1841 to 1809. [2024-11-08 00:34:48,565 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1809 states, 1809 states have (on average 1.4195688225538972) internal successors, (2568), 1808 states have internal predecessors, (2568), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:34:48,569 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1809 states to 1809 states and 2568 transitions. [2024-11-08 00:34:48,569 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1809 states and 2568 transitions. [2024-11-08 00:34:48,569 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-08 00:34:48,570 INFO L425 stractBuchiCegarLoop]: Abstraction has 1809 states and 2568 transitions. [2024-11-08 00:34:48,570 INFO L332 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-11-08 00:34:48,570 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1809 states and 2568 transitions. [2024-11-08 00:34:48,572 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1740 [2024-11-08 00:34:48,573 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:34:48,573 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:34:48,573 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:48,573 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:48,573 INFO L745 eck$LassoCheckResult]: Stem: 27654#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 27655#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 27675#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 27672#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 27559#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 27560#L292-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 27659#L297-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 27641#L302-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 27642#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 27649#L429 assume !(0 == ~M_E~0); 27460#L429-2 assume !(0 == ~T1_E~0); 27461#L434-1 assume !(0 == ~T2_E~0); 27596#L439-1 assume !(0 == ~T3_E~0); 27621#L444-1 assume !(0 == ~E_M~0); 27622#L449-1 assume !(0 == ~E_1~0); 27463#L454-1 assume !(0 == ~E_2~0); 27464#L459-1 assume !(0 == ~E_3~0); 27419#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 27420#L208 assume !(1 == ~m_pc~0); 27718#L208-2 is_master_triggered_~__retres1~0#1 := 0; 27719#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27624#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 27448#L531 assume !(0 != activate_threads_~tmp~1#1); 27449#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 27568#L227 assume !(1 == ~t1_pc~0); 27446#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 27447#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27434#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 27435#L539 assume !(0 != activate_threads_~tmp___0~0#1); 27462#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 27494#L246 assume !(1 == ~t2_pc~0); 27495#L246-2 is_transmit2_triggered_~__retres1~2#1 := 0; 27600#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27601#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 27663#L547 assume !(0 != activate_threads_~tmp___1~0#1); 27664#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 27508#L265 assume !(1 == ~t3_pc~0); 27380#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 27352#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 27353#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 27381#L555 assume !(0 != activate_threads_~tmp___2~0#1); 27474#L555-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27475#L477 assume !(1 == ~M_E~0); 27652#L477-2 assume !(1 == ~T1_E~0); 27676#L482-1 assume !(1 == ~T2_E~0); 27617#L487-1 assume !(1 == ~T3_E~0); 27618#L492-1 assume !(1 == ~E_M~0); 27427#L497-1 assume !(1 == ~E_1~0); 27428#L502-1 assume !(1 == ~E_2~0); 27408#L507-1 assume !(1 == ~E_3~0); 27409#L512-1 assume { :end_inline_reset_delta_events } true; 27565#L678-2 [2024-11-08 00:34:48,573 INFO L747 eck$LassoCheckResult]: Loop: 27565#L678-2 assume !false; 28397#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 28395#L404-1 assume !false; 28393#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 28390#L320 assume !(0 == ~m_st~0); 28391#L324 assume !(0 == ~t1_st~0); 28387#L328 assume !(0 == ~t2_st~0); 28388#L332 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0; 28389#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 28232#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 28233#L357 assume !(0 != eval_~tmp~0#1); 28905#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 28903#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 28901#L429-3 assume !(0 == ~M_E~0); 28899#L429-5 assume !(0 == ~T1_E~0); 28897#L434-3 assume !(0 == ~T2_E~0); 28895#L439-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 28893#L444-3 assume 0 == ~E_M~0;~E_M~0 := 1; 28891#L449-3 assume 0 == ~E_1~0;~E_1~0 := 1; 28889#L454-3 assume !(0 == ~E_2~0); 28887#L459-3 assume 0 == ~E_3~0;~E_3~0 := 1; 28885#L464-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28883#L208-15 assume !(1 == ~m_pc~0); 28881#L208-17 is_master_triggered_~__retres1~0#1 := 0; 28879#L219-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28877#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 28875#L531-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 28873#L531-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28871#L227-15 assume 1 == ~t1_pc~0; 28868#L228-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 28865#L238-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28863#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 28861#L539-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 28859#L539-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28857#L246-15 assume !(1 == ~t2_pc~0); 28855#L246-17 is_transmit2_triggered_~__retres1~2#1 := 0; 28853#L257-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 28851#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 28849#L547-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 28847#L547-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28845#L265-15 assume 1 == ~t3_pc~0; 28842#L266-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 28839#L276-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28837#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 28835#L555-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 28833#L555-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28831#L477-3 assume !(1 == ~M_E~0); 28828#L477-5 assume !(1 == ~T1_E~0); 28826#L482-3 assume !(1 == ~T2_E~0); 28824#L487-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 28822#L492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 28820#L497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 28818#L502-3 assume 1 == ~E_2~0;~E_2~0 := 2; 28816#L507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 28815#L512-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 28814#L320-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 27373#L342-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 27374#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 27661#L697 assume !(0 == start_simulation_~tmp~3#1); 27662#L697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 28503#L320-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 28487#L342-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 28430#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1; 28426#L652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 28420#L659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 28415#stop_simulation_returnLabel#1 start_simulation_#t~ret16#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 28410#L710 assume !(0 != start_simulation_~tmp___0~1#1); 27565#L678-2 [2024-11-08 00:34:48,574 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:34:48,574 INFO L85 PathProgramCache]: Analyzing trace with hash 1279836229, now seen corresponding path program 3 times [2024-11-08 00:34:48,574 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:34:48,574 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1871334935] [2024-11-08 00:34:48,574 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:34:48,574 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:34:48,580 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:34:48,580 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 00:34:48,583 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:34:48,595 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 00:34:48,596 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:34:48,596 INFO L85 PathProgramCache]: Analyzing trace with hash 2001522758, now seen corresponding path program 1 times [2024-11-08 00:34:48,596 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:34:48,596 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1988700712] [2024-11-08 00:34:48,596 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:34:48,596 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:34:48,615 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:34:48,699 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:34:48,699 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:34:48,699 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1988700712] [2024-11-08 00:34:48,699 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1988700712] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:34:48,699 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:34:48,699 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-08 00:34:48,699 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [475376406] [2024-11-08 00:34:48,699 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:34:48,699 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:34:48,699 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:34:48,700 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-08 00:34:48,700 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-08 00:34:48,700 INFO L87 Difference]: Start difference. First operand 1809 states and 2568 transitions. cyclomatic complexity: 763 Second operand has 5 states, 5 states have (on average 13.4) internal successors, (67), 5 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:34:48,833 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:34:48,834 INFO L93 Difference]: Finished difference Result 1869 states and 2611 transitions. [2024-11-08 00:34:48,834 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1869 states and 2611 transitions. [2024-11-08 00:34:48,838 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1800 [2024-11-08 00:34:48,844 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1869 states to 1869 states and 2611 transitions. [2024-11-08 00:34:48,844 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1869 [2024-11-08 00:34:48,845 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1869 [2024-11-08 00:34:48,845 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1869 states and 2611 transitions. [2024-11-08 00:34:48,847 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:34:48,847 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1869 states and 2611 transitions. [2024-11-08 00:34:48,848 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1869 states and 2611 transitions. [2024-11-08 00:34:48,863 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1869 to 1869. [2024-11-08 00:34:48,865 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1869 states, 1869 states have (on average 1.3970037453183521) internal successors, (2611), 1868 states have internal predecessors, (2611), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:34:48,869 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1869 states to 1869 states and 2611 transitions. [2024-11-08 00:34:48,869 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1869 states and 2611 transitions. [2024-11-08 00:34:48,870 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-08 00:34:48,870 INFO L425 stractBuchiCegarLoop]: Abstraction has 1869 states and 2611 transitions. [2024-11-08 00:34:48,870 INFO L332 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-11-08 00:34:48,870 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1869 states and 2611 transitions. [2024-11-08 00:34:48,874 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1800 [2024-11-08 00:34:48,874 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:34:48,874 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:34:48,875 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:48,875 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:48,875 INFO L745 eck$LassoCheckResult]: Stem: 31330#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 31331#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 31349#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 31346#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 31237#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 31238#L292-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 31335#L297-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 31317#L302-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 31318#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 31325#L429 assume !(0 == ~M_E~0); 31142#L429-2 assume !(0 == ~T1_E~0); 31143#L434-1 assume !(0 == ~T2_E~0); 31270#L439-1 assume !(0 == ~T3_E~0); 31297#L444-1 assume !(0 == ~E_M~0); 31298#L449-1 assume !(0 == ~E_1~0); 31145#L454-1 assume !(0 == ~E_2~0); 31146#L459-1 assume !(0 == ~E_3~0); 31102#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 31103#L208 assume !(1 == ~m_pc~0); 31380#L208-2 is_master_triggered_~__retres1~0#1 := 0; 31381#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31300#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 31130#L531 assume !(0 != activate_threads_~tmp~1#1); 31131#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 31245#L227 assume !(1 == ~t1_pc~0); 31128#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 31129#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 31116#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 31117#L539 assume !(0 != activate_threads_~tmp___0~0#1); 31144#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 31175#L246 assume !(1 == ~t2_pc~0); 31176#L246-2 is_transmit2_triggered_~__retres1~2#1 := 0; 31274#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 31275#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 31339#L547 assume !(0 != activate_threads_~tmp___1~0#1); 31340#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 31188#L265 assume !(1 == ~t3_pc~0); 31065#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 31038#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 31039#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 31066#L555 assume !(0 != activate_threads_~tmp___2~0#1); 31156#L555-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 31157#L477 assume !(1 == ~M_E~0); 31329#L477-2 assume !(1 == ~T1_E~0); 31350#L482-1 assume !(1 == ~T2_E~0); 31292#L487-1 assume !(1 == ~T3_E~0); 31293#L492-1 assume !(1 == ~E_M~0); 31109#L497-1 assume !(1 == ~E_1~0); 31110#L502-1 assume !(1 == ~E_2~0); 31093#L507-1 assume !(1 == ~E_3~0); 31094#L512-1 assume { :end_inline_reset_delta_events } true; 31243#L678-2 [2024-11-08 00:34:48,875 INFO L747 eck$LassoCheckResult]: Loop: 31243#L678-2 assume !false; 32514#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 32504#L404-1 assume !false; 32501#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 32499#L320 assume !(0 == ~m_st~0); 32497#L324 assume !(0 == ~t1_st~0); 32495#L328 assume !(0 == ~t2_st~0); 32492#L332 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0; 32480#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 32473#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 32468#L357 assume !(0 != eval_~tmp~0#1); 32463#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 32458#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 32454#L429-3 assume !(0 == ~M_E~0); 32448#L429-5 assume !(0 == ~T1_E~0); 32445#L434-3 assume !(0 == ~T2_E~0); 32443#L439-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 32441#L444-3 assume 0 == ~E_M~0;~E_M~0 := 1; 32439#L449-3 assume 0 == ~E_1~0;~E_1~0 := 1; 32437#L454-3 assume !(0 == ~E_2~0); 32429#L459-3 assume 0 == ~E_3~0;~E_3~0 := 1; 32424#L464-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 32420#L208-15 assume !(1 == ~m_pc~0); 32414#L208-17 is_master_triggered_~__retres1~0#1 := 0; 32410#L219-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 32403#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 32399#L531-15 assume !(0 != activate_threads_~tmp~1#1); 32395#L531-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 32160#L227-15 assume 1 == ~t1_pc~0; 32106#L228-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 32104#L238-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 32102#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 32099#L539-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 32097#L539-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 32095#L246-15 assume !(1 == ~t2_pc~0); 32093#L246-17 is_transmit2_triggered_~__retres1~2#1 := 0; 32091#L257-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32089#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 32086#L547-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 32084#L547-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 32082#L265-15 assume 1 == ~t3_pc~0; 32070#L266-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 32068#L276-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 32045#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 32038#L555-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 32005#L555-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32003#L477-3 assume !(1 == ~M_E~0); 32002#L477-5 assume !(1 == ~T1_E~0); 32316#L482-3 assume !(1 == ~T2_E~0); 32315#L487-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 32314#L492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 32313#L497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 32312#L502-3 assume 1 == ~E_2~0;~E_2~0 := 2; 31984#L507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 31983#L512-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 31979#L320-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 31974#L342-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 31371#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 31337#L697 assume !(0 == start_simulation_~tmp~3#1); 31338#L697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 32594#L320-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 32589#L342-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 32587#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1; 32586#L652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 32582#L659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 32561#stop_simulation_returnLabel#1 start_simulation_#t~ret16#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 32553#L710 assume !(0 != start_simulation_~tmp___0~1#1); 31243#L678-2 [2024-11-08 00:34:48,875 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:34:48,875 INFO L85 PathProgramCache]: Analyzing trace with hash 1279836229, now seen corresponding path program 4 times [2024-11-08 00:34:48,875 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:34:48,875 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [767848936] [2024-11-08 00:34:48,875 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:34:48,875 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:34:48,882 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:34:48,882 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 00:34:48,885 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:34:48,890 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 00:34:48,890 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:34:48,890 INFO L85 PathProgramCache]: Analyzing trace with hash -1869797816, now seen corresponding path program 1 times [2024-11-08 00:34:48,890 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:34:48,890 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [243722396] [2024-11-08 00:34:48,890 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:34:48,890 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:34:48,897 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:34:48,914 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:34:48,914 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:34:48,914 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [243722396] [2024-11-08 00:34:48,914 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [243722396] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:34:48,914 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:34:48,914 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:34:48,914 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [925872488] [2024-11-08 00:34:48,914 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:34:48,914 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:34:48,915 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:34:48,915 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:34:48,915 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:34:48,915 INFO L87 Difference]: Start difference. First operand 1869 states and 2611 transitions. cyclomatic complexity: 746 Second operand has 3 states, 3 states have (on average 22.333333333333332) internal successors, (67), 3 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:34:48,953 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:34:48,953 INFO L93 Difference]: Finished difference Result 2878 states and 3964 transitions. [2024-11-08 00:34:48,953 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2878 states and 3964 transitions. [2024-11-08 00:34:48,960 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 2805 [2024-11-08 00:34:48,969 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2878 states to 2878 states and 3964 transitions. [2024-11-08 00:34:48,970 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2878 [2024-11-08 00:34:48,971 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2878 [2024-11-08 00:34:48,971 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2878 states and 3964 transitions. [2024-11-08 00:34:48,974 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:34:48,974 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2878 states and 3964 transitions. [2024-11-08 00:34:48,976 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2878 states and 3964 transitions. [2024-11-08 00:34:48,998 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2878 to 2788. [2024-11-08 00:34:49,001 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2788 states, 2788 states have (on average 1.3780487804878048) internal successors, (3842), 2787 states have internal predecessors, (3842), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:34:49,008 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2788 states to 2788 states and 3842 transitions. [2024-11-08 00:34:49,008 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2788 states and 3842 transitions. [2024-11-08 00:34:49,008 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:34:49,009 INFO L425 stractBuchiCegarLoop]: Abstraction has 2788 states and 3842 transitions. [2024-11-08 00:34:49,009 INFO L332 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2024-11-08 00:34:49,009 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2788 states and 3842 transitions. [2024-11-08 00:34:49,014 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 2715 [2024-11-08 00:34:49,014 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:34:49,014 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:34:49,015 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:49,015 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:49,015 INFO L745 eck$LassoCheckResult]: Stem: 36100#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 36101#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 36115#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 36111#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 35996#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 35997#L292-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 36103#L297-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 36086#L302-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 36087#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 36095#L429 assume !(0 == ~M_E~0); 35896#L429-2 assume !(0 == ~T1_E~0); 35897#L434-1 assume !(0 == ~T2_E~0); 36038#L439-1 assume !(0 == ~T3_E~0); 36064#L444-1 assume !(0 == ~E_M~0); 36065#L449-1 assume !(0 == ~E_1~0); 35899#L454-1 assume !(0 == ~E_2~0); 35900#L459-1 assume !(0 == ~E_3~0); 35856#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 35857#L208 assume !(1 == ~m_pc~0); 36162#L208-2 is_master_triggered_~__retres1~0#1 := 0; 36163#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36068#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 35884#L531 assume !(0 != activate_threads_~tmp~1#1); 35885#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36005#L227 assume !(1 == ~t1_pc~0); 35882#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 35883#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 35869#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 35870#L539 assume !(0 != activate_threads_~tmp___0~0#1); 35898#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 35929#L246 assume !(1 == ~t2_pc~0); 35930#L246-2 is_transmit2_triggered_~__retres1~2#1 := 0; 36042#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 36043#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 36106#L547 assume !(0 != activate_threads_~tmp___1~0#1); 36107#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 35942#L265 assume !(1 == ~t3_pc~0); 35819#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 35791#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 35792#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 35820#L555 assume !(0 != activate_threads_~tmp___2~0#1); 35910#L555-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 35911#L477 assume !(1 == ~M_E~0); 36099#L477-2 assume !(1 == ~T1_E~0); 36116#L482-1 assume !(1 == ~T2_E~0); 36059#L487-1 assume !(1 == ~T3_E~0); 36060#L492-1 assume !(1 == ~E_M~0); 35862#L497-1 assume !(1 == ~E_1~0); 35863#L502-1 assume !(1 == ~E_2~0); 35847#L507-1 assume !(1 == ~E_3~0); 35848#L512-1 assume { :end_inline_reset_delta_events } true; 36003#L678-2 assume !false; 36822#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 36823#L404-1 [2024-11-08 00:34:49,015 INFO L747 eck$LassoCheckResult]: Loop: 36823#L404-1 assume !false; 36795#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 36796#L320 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 37020#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 37016#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 37011#L357 assume 0 != eval_~tmp~0#1; 37004#L357-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 37000#L365 assume !(0 != eval_~tmp_ndt_1~0#1); 36998#L365-2 havoc eval_~tmp_ndt_1~0#1; 36994#L362-1 assume !(0 == ~t1_st~0); 36989#L376-1 assume !(0 == ~t2_st~0); 36825#L390-1 assume !(0 == ~t3_st~0); 36823#L404-1 [2024-11-08 00:34:49,015 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:34:49,015 INFO L85 PathProgramCache]: Analyzing trace with hash 1561976903, now seen corresponding path program 1 times [2024-11-08 00:34:49,015 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:34:49,015 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2047783320] [2024-11-08 00:34:49,015 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:34:49,015 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:34:49,022 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:34:49,022 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 00:34:49,025 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:34:49,029 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 00:34:49,030 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:34:49,030 INFO L85 PathProgramCache]: Analyzing trace with hash -616621386, now seen corresponding path program 1 times [2024-11-08 00:34:49,030 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:34:49,030 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [488666697] [2024-11-08 00:34:49,030 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:34:49,030 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:34:49,032 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:34:49,032 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 00:34:49,033 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:34:49,034 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 00:34:49,035 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:34:49,035 INFO L85 PathProgramCache]: Analyzing trace with hash 945603068, now seen corresponding path program 1 times [2024-11-08 00:34:49,035 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:34:49,035 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1480841572] [2024-11-08 00:34:49,035 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:34:49,035 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:34:49,041 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:34:49,061 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:34:49,061 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:34:49,062 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1480841572] [2024-11-08 00:34:49,062 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1480841572] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:34:49,062 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:34:49,062 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:34:49,062 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [391439153] [2024-11-08 00:34:49,062 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:34:49,108 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:34:49,108 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:34:49,108 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:34:49,108 INFO L87 Difference]: Start difference. First operand 2788 states and 3842 transitions. cyclomatic complexity: 1060 Second operand has 3 states, 3 states have (on average 21.666666666666668) internal successors, (65), 3 states have internal predecessors, (65), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:34:49,153 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:34:49,153 INFO L93 Difference]: Finished difference Result 5000 states and 6813 transitions. [2024-11-08 00:34:49,153 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5000 states and 6813 transitions. [2024-11-08 00:34:49,166 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 4860 [2024-11-08 00:34:49,183 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5000 states to 5000 states and 6813 transitions. [2024-11-08 00:34:49,183 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5000 [2024-11-08 00:34:49,186 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5000 [2024-11-08 00:34:49,186 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5000 states and 6813 transitions. [2024-11-08 00:34:49,191 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:34:49,191 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5000 states and 6813 transitions. [2024-11-08 00:34:49,194 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5000 states and 6813 transitions. [2024-11-08 00:34:49,261 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5000 to 4755. [2024-11-08 00:34:49,267 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4755 states, 4755 states have (on average 1.3665615141955836) internal successors, (6498), 4754 states have internal predecessors, (6498), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:34:49,276 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4755 states to 4755 states and 6498 transitions. [2024-11-08 00:34:49,276 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4755 states and 6498 transitions. [2024-11-08 00:34:49,277 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:34:49,277 INFO L425 stractBuchiCegarLoop]: Abstraction has 4755 states and 6498 transitions. [2024-11-08 00:34:49,277 INFO L332 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2024-11-08 00:34:49,277 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4755 states and 6498 transitions. [2024-11-08 00:34:49,287 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 4615 [2024-11-08 00:34:49,287 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:34:49,287 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:34:49,287 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:49,287 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:49,287 INFO L745 eck$LassoCheckResult]: Stem: 43919#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 43920#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 43939#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 43937#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 43805#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 43806#L292-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 43947#L297-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 43902#L302-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 43903#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 43966#L429 assume !(0 == ~M_E~0); 43967#L429-2 assume !(0 == ~T1_E~0); 43852#L434-1 assume !(0 == ~T2_E~0); 43853#L439-1 assume !(0 == ~T3_E~0); 43880#L444-1 assume !(0 == ~E_M~0); 43881#L449-1 assume !(0 == ~E_1~0); 43702#L454-1 assume !(0 == ~E_2~0); 43703#L459-1 assume !(0 == ~E_3~0); 43654#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 43655#L208 assume !(1 == ~m_pc~0); 43998#L208-2 is_master_triggered_~__retres1~0#1 := 0; 43999#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 43883#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 43884#L531 assume !(0 != activate_threads_~tmp~1#1); 43836#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 43837#L227 assume !(1 == ~t1_pc~0); 43682#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 43683#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 43672#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 43673#L539 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 43699#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 43734#L246 assume !(1 == ~t2_pc~0); 43735#L246-2 is_transmit2_triggered_~__retres1~2#1 := 0; 43859#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 43860#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 43930#L547 assume !(0 != activate_threads_~tmp___1~0#1); 43931#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 43748#L265 assume !(1 == ~t3_pc~0); 43749#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 43587#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 43588#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 44010#L555 assume !(0 != activate_threads_~tmp___2~0#1); 44011#L555-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 43917#L477 assume !(1 == ~M_E~0); 43918#L477-2 assume !(1 == ~T1_E~0); 43940#L482-1 assume !(1 == ~T2_E~0); 43941#L487-1 assume !(1 == ~T3_E~0); 43962#L492-1 assume !(1 == ~E_M~0); 43963#L497-1 assume !(1 == ~E_1~0); 43842#L502-1 assume !(1 == ~E_2~0); 43843#L507-1 assume !(1 == ~E_3~0); 43807#L512-1 assume { :end_inline_reset_delta_events } true; 43808#L678-2 assume !false; 45396#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 45392#L404-1 [2024-11-08 00:34:49,288 INFO L747 eck$LassoCheckResult]: Loop: 45392#L404-1 assume !false; 45391#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 45389#L320 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 45388#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 45386#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 45384#L357 assume 0 != eval_~tmp~0#1; 45381#L357-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 45378#L365 assume !(0 != eval_~tmp_ndt_1~0#1); 45376#L365-2 havoc eval_~tmp_ndt_1~0#1; 45374#L362-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 45292#L379 assume !(0 != eval_~tmp_ndt_2~0#1); 45369#L379-2 havoc eval_~tmp_ndt_2~0#1; 45366#L376-1 assume !(0 == ~t2_st~0); 45367#L390-1 assume !(0 == ~t3_st~0); 45392#L404-1 [2024-11-08 00:34:49,288 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:34:49,288 INFO L85 PathProgramCache]: Analyzing trace with hash -934376957, now seen corresponding path program 1 times [2024-11-08 00:34:49,288 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:34:49,288 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [990476722] [2024-11-08 00:34:49,288 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:34:49,288 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:34:49,294 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:34:49,306 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:34:49,306 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:34:49,306 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [990476722] [2024-11-08 00:34:49,306 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [990476722] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:34:49,306 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:34:49,306 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:34:49,306 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1674552735] [2024-11-08 00:34:49,306 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:34:49,306 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:34:49,307 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:34:49,307 INFO L85 PathProgramCache]: Analyzing trace with hash 6018452, now seen corresponding path program 1 times [2024-11-08 00:34:49,307 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:34:49,307 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1240502478] [2024-11-08 00:34:49,307 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:34:49,307 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:34:49,309 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:34:49,309 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 00:34:49,310 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:34:49,311 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 00:34:49,358 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:34:49,358 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:34:49,358 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:34:49,358 INFO L87 Difference]: Start difference. First operand 4755 states and 6498 transitions. cyclomatic complexity: 1749 Second operand has 3 states, 3 states have (on average 17.666666666666668) internal successors, (53), 3 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:34:49,372 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:34:49,372 INFO L93 Difference]: Finished difference Result 4706 states and 6431 transitions. [2024-11-08 00:34:49,372 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4706 states and 6431 transitions. [2024-11-08 00:34:49,383 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 4615 [2024-11-08 00:34:49,393 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4706 states to 4706 states and 6431 transitions. [2024-11-08 00:34:49,393 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4706 [2024-11-08 00:34:49,395 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4706 [2024-11-08 00:34:49,395 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4706 states and 6431 transitions. [2024-11-08 00:34:49,399 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:34:49,400 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4706 states and 6431 transitions. [2024-11-08 00:34:49,402 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4706 states and 6431 transitions. [2024-11-08 00:34:49,430 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4706 to 4706. [2024-11-08 00:34:49,435 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4706 states, 4706 states have (on average 1.3665533361665958) internal successors, (6431), 4705 states have internal predecessors, (6431), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:34:49,442 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4706 states to 4706 states and 6431 transitions. [2024-11-08 00:34:49,442 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4706 states and 6431 transitions. [2024-11-08 00:34:49,442 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:34:49,443 INFO L425 stractBuchiCegarLoop]: Abstraction has 4706 states and 6431 transitions. [2024-11-08 00:34:49,443 INFO L332 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2024-11-08 00:34:49,443 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4706 states and 6431 transitions. [2024-11-08 00:34:49,450 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 4615 [2024-11-08 00:34:49,450 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:34:49,450 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:34:49,451 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:49,451 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:49,451 INFO L745 eck$LassoCheckResult]: Stem: 53362#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 53363#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 53382#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 53380#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 53259#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 53260#L292-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 53369#L297-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 53346#L302-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 53347#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 53356#L429 assume !(0 == ~M_E~0); 53159#L429-2 assume !(0 == ~T1_E~0); 53160#L434-1 assume !(0 == ~T2_E~0); 53296#L439-1 assume !(0 == ~T3_E~0); 53325#L444-1 assume !(0 == ~E_M~0); 53326#L449-1 assume !(0 == ~E_1~0); 53164#L454-1 assume !(0 == ~E_2~0); 53165#L459-1 assume !(0 == ~E_3~0); 53117#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 53118#L208 assume !(1 == ~m_pc~0); 53428#L208-2 is_master_triggered_~__retres1~0#1 := 0; 53429#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 53329#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 53147#L531 assume !(0 != activate_threads_~tmp~1#1); 53148#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 53264#L227 assume !(1 == ~t1_pc~0); 53145#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 53146#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 53135#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 53136#L539 assume !(0 != activate_threads_~tmp___0~0#1); 53161#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 53194#L246 assume !(1 == ~t2_pc~0); 53195#L246-2 is_transmit2_triggered_~__retres1~2#1 := 0; 53301#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 53302#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 53373#L547 assume !(0 != activate_threads_~tmp___1~0#1); 53374#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 53208#L265 assume !(1 == ~t3_pc~0); 53081#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 53054#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 53055#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 53084#L555 assume !(0 != activate_threads_~tmp___2~0#1); 53178#L555-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 53179#L477 assume !(1 == ~M_E~0); 53361#L477-2 assume !(1 == ~T1_E~0); 53383#L482-1 assume !(1 == ~T2_E~0); 53323#L487-1 assume !(1 == ~T3_E~0); 53324#L492-1 assume !(1 == ~E_M~0); 53130#L497-1 assume !(1 == ~E_1~0); 53131#L502-1 assume !(1 == ~E_2~0); 53110#L507-1 assume !(1 == ~E_3~0); 53111#L512-1 assume { :end_inline_reset_delta_events } true; 53261#L678-2 assume !false; 54518#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 54516#L404-1 [2024-11-08 00:34:49,451 INFO L747 eck$LassoCheckResult]: Loop: 54516#L404-1 assume !false; 54514#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 54512#L320 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 54509#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 54507#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 54505#L357 assume 0 != eval_~tmp~0#1; 54504#L357-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 54503#L365 assume !(0 != eval_~tmp_ndt_1~0#1); 53304#L365-2 havoc eval_~tmp_ndt_1~0#1; 53305#L362-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 54527#L379 assume !(0 != eval_~tmp_ndt_2~0#1); 54525#L379-2 havoc eval_~tmp_ndt_2~0#1; 54523#L376-1 assume !(0 == ~t2_st~0); 54520#L390-1 assume !(0 == ~t3_st~0); 54516#L404-1 [2024-11-08 00:34:49,451 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:34:49,451 INFO L85 PathProgramCache]: Analyzing trace with hash 1561976903, now seen corresponding path program 2 times [2024-11-08 00:34:49,451 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:34:49,451 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [403006073] [2024-11-08 00:34:49,451 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:34:49,452 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:34:49,457 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:34:49,457 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 00:34:49,460 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:34:49,462 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 00:34:49,463 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:34:49,463 INFO L85 PathProgramCache]: Analyzing trace with hash 6018452, now seen corresponding path program 2 times [2024-11-08 00:34:49,463 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:34:49,463 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1271089482] [2024-11-08 00:34:49,463 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:34:49,463 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:34:49,465 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:34:49,465 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 00:34:49,466 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:34:49,467 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 00:34:49,467 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:34:49,467 INFO L85 PathProgramCache]: Analyzing trace with hash -1934834854, now seen corresponding path program 1 times [2024-11-08 00:34:49,467 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:34:49,467 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2069663008] [2024-11-08 00:34:49,467 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:34:49,467 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:34:49,472 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:34:49,488 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:34:49,488 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:34:49,488 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2069663008] [2024-11-08 00:34:49,488 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2069663008] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:34:49,488 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:34:49,488 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:34:49,488 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [121237932] [2024-11-08 00:34:49,488 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:34:49,522 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:34:49,522 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:34:49,522 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:34:49,522 INFO L87 Difference]: Start difference. First operand 4706 states and 6431 transitions. cyclomatic complexity: 1731 Second operand has 3 states, 3 states have (on average 22.333333333333332) internal successors, (67), 3 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:34:49,563 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:34:49,563 INFO L93 Difference]: Finished difference Result 5299 states and 7206 transitions. [2024-11-08 00:34:49,563 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5299 states and 7206 transitions. [2024-11-08 00:34:49,574 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 5216 [2024-11-08 00:34:49,583 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5299 states to 5299 states and 7206 transitions. [2024-11-08 00:34:49,583 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5299 [2024-11-08 00:34:49,586 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5299 [2024-11-08 00:34:49,586 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5299 states and 7206 transitions. [2024-11-08 00:34:49,590 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:34:49,590 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5299 states and 7206 transitions. [2024-11-08 00:34:49,593 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5299 states and 7206 transitions. [2024-11-08 00:34:49,664 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5299 to 5145. [2024-11-08 00:34:49,670 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5145 states, 5145 states have (on average 1.3624878522837707) internal successors, (7010), 5144 states have internal predecessors, (7010), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:34:49,678 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5145 states to 5145 states and 7010 transitions. [2024-11-08 00:34:49,678 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5145 states and 7010 transitions. [2024-11-08 00:34:49,679 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:34:49,679 INFO L425 stractBuchiCegarLoop]: Abstraction has 5145 states and 7010 transitions. [2024-11-08 00:34:49,679 INFO L332 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2024-11-08 00:34:49,679 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5145 states and 7010 transitions. [2024-11-08 00:34:49,687 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 5062 [2024-11-08 00:34:49,687 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:34:49,687 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:34:49,687 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:49,687 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:49,688 INFO L745 eck$LassoCheckResult]: Stem: 63377#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 63378#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 63395#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 63391#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 63273#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 63274#L292-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 63380#L297-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 63362#L302-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 63363#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 63371#L429 assume !(0 == ~M_E~0); 63173#L429-2 assume !(0 == ~T1_E~0); 63174#L434-1 assume !(0 == ~T2_E~0); 63318#L439-1 assume !(0 == ~T3_E~0); 63344#L444-1 assume !(0 == ~E_M~0); 63345#L449-1 assume !(0 == ~E_1~0); 63176#L454-1 assume !(0 == ~E_2~0); 63177#L459-1 assume !(0 == ~E_3~0); 63131#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 63132#L208 assume !(1 == ~m_pc~0); 63437#L208-2 is_master_triggered_~__retres1~0#1 := 0; 63438#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 63347#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 63161#L531 assume !(0 != activate_threads_~tmp~1#1); 63162#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 63283#L227 assume !(1 == ~t1_pc~0); 63159#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 63160#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 63146#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 63147#L539 assume !(0 != activate_threads_~tmp___0~0#1); 63175#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 63206#L246 assume !(1 == ~t2_pc~0); 63207#L246-2 is_transmit2_triggered_~__retres1~2#1 := 0; 63323#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 63324#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 63385#L547 assume !(0 != activate_threads_~tmp___1~0#1); 63386#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 63218#L265 assume !(1 == ~t3_pc~0); 63095#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 63067#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 63068#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 63096#L555 assume !(0 != activate_threads_~tmp___2~0#1); 63187#L555-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 63188#L477 assume !(1 == ~M_E~0); 63376#L477-2 assume !(1 == ~T1_E~0); 63396#L482-1 assume !(1 == ~T2_E~0); 63340#L487-1 assume !(1 == ~T3_E~0); 63341#L492-1 assume !(1 == ~E_M~0); 63139#L497-1 assume !(1 == ~E_1~0); 63140#L502-1 assume !(1 == ~E_2~0); 63122#L507-1 assume !(1 == ~E_3~0); 63123#L512-1 assume { :end_inline_reset_delta_events } true; 63280#L678-2 assume !false; 65199#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 65194#L404-1 [2024-11-08 00:34:49,688 INFO L747 eck$LassoCheckResult]: Loop: 65194#L404-1 assume !false; 65189#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 65182#L320 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 65177#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 65172#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 65164#L357 assume 0 != eval_~tmp~0#1; 65159#L357-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 65154#L365 assume !(0 != eval_~tmp_ndt_1~0#1); 65149#L365-2 havoc eval_~tmp_ndt_1~0#1; 65143#L362-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 64929#L379 assume !(0 != eval_~tmp_ndt_2~0#1); 65138#L379-2 havoc eval_~tmp_ndt_2~0#1; 65262#L376-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 65259#L393 assume !(0 != eval_~tmp_ndt_3~0#1); 65211#L393-2 havoc eval_~tmp_ndt_3~0#1; 65201#L390-1 assume !(0 == ~t3_st~0); 65194#L404-1 [2024-11-08 00:34:49,688 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:34:49,688 INFO L85 PathProgramCache]: Analyzing trace with hash 1561976903, now seen corresponding path program 3 times [2024-11-08 00:34:49,688 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:34:49,688 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1629528371] [2024-11-08 00:34:49,688 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:34:49,688 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:34:49,693 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:34:49,693 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 00:34:49,696 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:34:49,699 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 00:34:49,699 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:34:49,699 INFO L85 PathProgramCache]: Analyzing trace with hash 1484720438, now seen corresponding path program 1 times [2024-11-08 00:34:49,699 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:34:49,699 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [728666948] [2024-11-08 00:34:49,699 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:34:49,699 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:34:49,702 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:34:49,702 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 00:34:49,703 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:34:49,704 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 00:34:49,704 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:34:49,704 INFO L85 PathProgramCache]: Analyzing trace with hash 340499836, now seen corresponding path program 1 times [2024-11-08 00:34:49,704 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:34:49,704 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [132099948] [2024-11-08 00:34:49,704 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:34:49,704 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:34:49,709 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:34:49,725 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:34:49,725 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:34:49,725 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [132099948] [2024-11-08 00:34:49,725 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [132099948] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:34:49,725 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:34:49,725 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-08 00:34:49,725 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [955392735] [2024-11-08 00:34:49,725 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:34:49,764 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:34:49,765 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:34:49,765 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:34:49,765 INFO L87 Difference]: Start difference. First operand 5145 states and 7010 transitions. cyclomatic complexity: 1871 Second operand has 3 states, 2 states have (on average 34.5) internal successors, (69), 3 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:34:49,813 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:34:49,813 INFO L93 Difference]: Finished difference Result 8657 states and 11688 transitions. [2024-11-08 00:34:49,813 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8657 states and 11688 transitions. [2024-11-08 00:34:49,835 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 8546 [2024-11-08 00:34:49,854 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8657 states to 8657 states and 11688 transitions. [2024-11-08 00:34:49,854 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8657 [2024-11-08 00:34:49,860 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8657 [2024-11-08 00:34:49,860 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8657 states and 11688 transitions. [2024-11-08 00:34:49,868 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:34:49,869 INFO L218 hiAutomatonCegarLoop]: Abstraction has 8657 states and 11688 transitions. [2024-11-08 00:34:49,874 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8657 states and 11688 transitions. [2024-11-08 00:34:49,923 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8657 to 8513. [2024-11-08 00:34:49,933 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8513 states, 8513 states have (on average 1.35604369787384) internal successors, (11544), 8512 states have internal predecessors, (11544), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:34:49,947 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8513 states to 8513 states and 11544 transitions. [2024-11-08 00:34:49,947 INFO L240 hiAutomatonCegarLoop]: Abstraction has 8513 states and 11544 transitions. [2024-11-08 00:34:49,947 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:34:49,948 INFO L425 stractBuchiCegarLoop]: Abstraction has 8513 states and 11544 transitions. [2024-11-08 00:34:49,948 INFO L332 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2024-11-08 00:34:49,948 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8513 states and 11544 transitions. [2024-11-08 00:34:49,965 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 8402 [2024-11-08 00:34:49,966 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:34:49,966 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:34:49,966 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:49,966 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:49,966 INFO L745 eck$LassoCheckResult]: Stem: 77186#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 77187#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 77203#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 77200#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 77083#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 77084#L292-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 77189#L297-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 77171#L302-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 77172#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 77181#L429 assume !(0 == ~M_E~0); 76981#L429-2 assume !(0 == ~T1_E~0); 76982#L434-1 assume !(0 == ~T2_E~0); 77122#L439-1 assume !(0 == ~T3_E~0); 77152#L444-1 assume !(0 == ~E_M~0); 77153#L449-1 assume !(0 == ~E_1~0); 76984#L454-1 assume !(0 == ~E_2~0); 76985#L459-1 assume !(0 == ~E_3~0); 76940#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 76941#L208 assume !(1 == ~m_pc~0); 77245#L208-2 is_master_triggered_~__retres1~0#1 := 0; 77246#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 77155#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 76969#L531 assume !(0 != activate_threads_~tmp~1#1); 76970#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 77091#L227 assume !(1 == ~t1_pc~0); 76967#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 76968#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 76954#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 76955#L539 assume !(0 != activate_threads_~tmp___0~0#1); 76983#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 77015#L246 assume !(1 == ~t2_pc~0); 77016#L246-2 is_transmit2_triggered_~__retres1~2#1 := 0; 77127#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 77128#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 77194#L547 assume !(0 != activate_threads_~tmp___1~0#1); 77195#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 77027#L265 assume !(1 == ~t3_pc~0); 76904#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 76877#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 76878#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 76905#L555 assume !(0 != activate_threads_~tmp___2~0#1); 76995#L555-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 76996#L477 assume !(1 == ~M_E~0); 77185#L477-2 assume !(1 == ~T1_E~0); 77204#L482-1 assume !(1 == ~T2_E~0); 77148#L487-1 assume !(1 == ~T3_E~0); 77149#L492-1 assume !(1 == ~E_M~0); 76947#L497-1 assume !(1 == ~E_1~0); 76948#L502-1 assume !(1 == ~E_2~0); 76931#L507-1 assume !(1 == ~E_3~0); 76932#L512-1 assume { :end_inline_reset_delta_events } true; 77089#L678-2 assume !false; 81992#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 81990#L404-1 [2024-11-08 00:34:49,968 INFO L747 eck$LassoCheckResult]: Loop: 81990#L404-1 assume !false; 81988#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 81985#L320 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 81943#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 81944#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 81904#L357 assume 0 != eval_~tmp~0#1; 81905#L357-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 81976#L365 assume !(0 != eval_~tmp_ndt_1~0#1); 81974#L365-2 havoc eval_~tmp_ndt_1~0#1; 81972#L362-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 81960#L379 assume !(0 != eval_~tmp_ndt_2~0#1); 81971#L379-2 havoc eval_~tmp_ndt_2~0#1; 82038#L376-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 82034#L393 assume !(0 != eval_~tmp_ndt_3~0#1); 82035#L393-2 havoc eval_~tmp_ndt_3~0#1; 81998#L390-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 81995#L407 assume !(0 != eval_~tmp_ndt_4~0#1); 81993#L407-2 havoc eval_~tmp_ndt_4~0#1; 81990#L404-1 [2024-11-08 00:34:49,968 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:34:49,968 INFO L85 PathProgramCache]: Analyzing trace with hash 1561976903, now seen corresponding path program 4 times [2024-11-08 00:34:49,968 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:34:49,968 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [282292579] [2024-11-08 00:34:49,968 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:34:49,968 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:34:49,976 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:34:49,976 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 00:34:49,979 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:34:49,983 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 00:34:49,984 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:34:49,984 INFO L85 PathProgramCache]: Analyzing trace with hash 887098260, now seen corresponding path program 1 times [2024-11-08 00:34:49,984 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:34:49,984 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [431402062] [2024-11-08 00:34:49,985 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:34:49,985 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:34:49,987 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:34:49,988 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 00:34:49,990 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:34:49,991 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 00:34:49,992 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:34:49,992 INFO L85 PathProgramCache]: Analyzing trace with hash 802727514, now seen corresponding path program 1 times [2024-11-08 00:34:49,992 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:34:49,992 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [992519800] [2024-11-08 00:34:49,992 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:34:49,992 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:34:50,002 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:34:50,002 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 00:34:50,006 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:34:50,051 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 00:34:50,718 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:34:50,718 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 00:34:50,731 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:34:50,833 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 08.11 12:34:50 BoogieIcfgContainer [2024-11-08 00:34:50,833 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2024-11-08 00:34:50,833 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2024-11-08 00:34:50,833 INFO L270 PluginConnector]: Initializing Witness Printer... [2024-11-08 00:34:50,833 INFO L274 PluginConnector]: Witness Printer initialized [2024-11-08 00:34:50,834 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 08.11 12:34:46" (3/4) ... [2024-11-08 00:34:50,839 INFO L139 WitnessPrinter]: Generating witness for non-termination counterexample [2024-11-08 00:34:50,916 INFO L149 WitnessManager]: Wrote witness to /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/witness.graphml [2024-11-08 00:34:50,919 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2024-11-08 00:34:50,920 INFO L158 Benchmark]: Toolchain (without parser) took 5721.03ms. Allocated memory was 117.4MB in the beginning and 285.2MB in the end (delta: 167.8MB). Free memory was 91.5MB in the beginning and 88.4MB in the end (delta: 3.1MB). Peak memory consumption was 169.0MB. Max. memory is 16.1GB. [2024-11-08 00:34:50,920 INFO L158 Benchmark]: CDTParser took 0.22ms. Allocated memory is still 117.4MB. Free memory is still 81.5MB. There was no memory consumed. Max. memory is 16.1GB. [2024-11-08 00:34:50,920 INFO L158 Benchmark]: CACSL2BoogieTranslator took 238.84ms. Allocated memory is still 117.4MB. Free memory was 91.4MB in the beginning and 77.1MB in the end (delta: 14.3MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. [2024-11-08 00:34:50,921 INFO L158 Benchmark]: Boogie Procedure Inliner took 44.47ms. Allocated memory is still 117.4MB. Free memory was 77.1MB in the beginning and 73.8MB in the end (delta: 3.3MB). There was no memory consumed. Max. memory is 16.1GB. [2024-11-08 00:34:50,921 INFO L158 Benchmark]: Boogie Preprocessor took 76.06ms. Allocated memory is still 117.4MB. Free memory was 73.8MB in the beginning and 70.0MB in the end (delta: 3.8MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2024-11-08 00:34:50,921 INFO L158 Benchmark]: RCFGBuilder took 718.39ms. Allocated memory is still 117.4MB. Free memory was 70.0MB in the beginning and 70.9MB in the end (delta: -877.3kB). Peak memory consumption was 31.0MB. Max. memory is 16.1GB. [2024-11-08 00:34:50,921 INFO L158 Benchmark]: BuchiAutomizer took 4549.94ms. Allocated memory was 117.4MB in the beginning and 285.2MB in the end (delta: 167.8MB). Free memory was 70.9MB in the beginning and 96.8MB in the end (delta: -26.0MB). Peak memory consumption was 138.1MB. Max. memory is 16.1GB. [2024-11-08 00:34:50,921 INFO L158 Benchmark]: Witness Printer took 86.20ms. Allocated memory is still 285.2MB. Free memory was 96.8MB in the beginning and 88.4MB in the end (delta: 8.4MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2024-11-08 00:34:50,922 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.22ms. Allocated memory is still 117.4MB. Free memory is still 81.5MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 238.84ms. Allocated memory is still 117.4MB. Free memory was 91.4MB in the beginning and 77.1MB in the end (delta: 14.3MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 44.47ms. Allocated memory is still 117.4MB. Free memory was 77.1MB in the beginning and 73.8MB in the end (delta: 3.3MB). There was no memory consumed. Max. memory is 16.1GB. * Boogie Preprocessor took 76.06ms. Allocated memory is still 117.4MB. Free memory was 73.8MB in the beginning and 70.0MB in the end (delta: 3.8MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * RCFGBuilder took 718.39ms. Allocated memory is still 117.4MB. Free memory was 70.0MB in the beginning and 70.9MB in the end (delta: -877.3kB). Peak memory consumption was 31.0MB. Max. memory is 16.1GB. * BuchiAutomizer took 4549.94ms. Allocated memory was 117.4MB in the beginning and 285.2MB in the end (delta: 167.8MB). Free memory was 70.9MB in the beginning and 96.8MB in the end (delta: -26.0MB). Peak memory consumption was 138.1MB. Max. memory is 16.1GB. * Witness Printer took 86.20ms. Allocated memory is still 285.2MB. Free memory was 96.8MB in the beginning and 88.4MB in the end (delta: 8.4MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 17 terminating modules (17 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.17 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 8513 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 4.4s and 18 iterations. TraceHistogramMax:1. Analysis of lassos took 2.3s. Construction of modules took 0.3s. Büchi inclusion checks took 1.5s. Highest rank in rank-based complementation 0. Minimization of det autom 17. Minimization of nondet autom 0. Automata minimization 0.7s AutomataMinimizationTime, 17 MinimizatonAttempts, 2285 StatesRemovedByMinimization, 9 NontrivialMinimizations. Non-live state removal took 0.2s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 6836 SdHoareTripleChecker+Valid, 0.5s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 6836 mSDsluCounter, 14889 SdHoareTripleChecker+Invalid, 0.4s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 6526 mSDsCounter, 137 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 354 IncrementalHoareTripleChecker+Invalid, 491 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 137 mSolverCounterUnsat, 8363 mSDtfsCounter, 354 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI4 SFLT0 conc3 concLT0 SILN1 SILU0 SILI9 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 352]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int t2_pc = 0; [L27] int t3_pc = 0; [L28] int m_st ; [L29] int t1_st ; [L30] int t2_st ; [L31] int t3_st ; [L32] int m_i ; [L33] int t1_i ; [L34] int t2_i ; [L35] int t3_i ; [L36] int M_E = 2; [L37] int T1_E = 2; [L38] int T2_E = 2; [L39] int T3_E = 2; [L40] int E_M = 2; [L41] int E_1 = 2; [L42] int E_2 = 2; [L43] int E_3 = 2; [L49] int token ; [L51] int local ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0, token=0] [L723] int __retres1 ; [L727] CALL init_model() [L636] m_i = 1 [L637] t1_i = 1 [L638] t2_i = 1 [L639] t3_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L727] RET init_model() [L728] CALL start_simulation() [L664] int kernel_st ; [L665] int tmp ; [L666] int tmp___0 ; [L670] kernel_st = 0 [L671] FCALL update_channels() [L672] CALL init_threads() [L292] COND TRUE m_i == 1 [L293] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L297] COND TRUE t1_i == 1 [L298] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L302] COND TRUE t2_i == 1 [L303] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L307] COND TRUE t3_i == 1 [L308] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L672] RET init_threads() [L673] CALL fire_delta_events() [L429] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L434] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L439] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L444] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L449] COND FALSE !(E_M == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L454] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L459] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L464] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L673] RET fire_delta_events() [L674] CALL activate_threads() [L522] int tmp ; [L523] int tmp___0 ; [L524] int tmp___1 ; [L525] int tmp___2 ; [L529] CALL, EXPR is_master_triggered() [L205] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L208] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L218] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L220] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L529] RET, EXPR is_master_triggered() [L529] tmp = is_master_triggered() [L531] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L537] CALL, EXPR is_transmit1_triggered() [L224] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L227] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L237] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L239] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L537] RET, EXPR is_transmit1_triggered() [L537] tmp___0 = is_transmit1_triggered() [L539] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L545] CALL, EXPR is_transmit2_triggered() [L243] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L246] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L256] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L258] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L545] RET, EXPR is_transmit2_triggered() [L545] tmp___1 = is_transmit2_triggered() [L547] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L553] CALL, EXPR is_transmit3_triggered() [L262] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L265] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L275] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L277] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L553] RET, EXPR is_transmit3_triggered() [L553] tmp___2 = is_transmit3_triggered() [L555] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L674] RET activate_threads() [L675] CALL reset_delta_events() [L477] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L482] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L487] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L492] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L497] COND FALSE !(E_M == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L502] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L507] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L512] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L675] RET reset_delta_events() [L678] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L681] kernel_st = 1 [L682] CALL eval() [L348] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] Loop: [L352] COND TRUE 1 [L355] CALL, EXPR exists_runnable_thread() [L317] int __retres1 ; [L320] COND TRUE m_st == 0 [L321] __retres1 = 1 [L343] return (__retres1); [L355] RET, EXPR exists_runnable_thread() [L355] tmp = exists_runnable_thread() [L357] COND TRUE \read(tmp) [L362] COND TRUE m_st == 0 [L363] int tmp_ndt_1; [L364] tmp_ndt_1 = __VERIFIER_nondet_int() [L365] COND FALSE !(\read(tmp_ndt_1)) [L376] COND TRUE t1_st == 0 [L377] int tmp_ndt_2; [L378] tmp_ndt_2 = __VERIFIER_nondet_int() [L379] COND FALSE !(\read(tmp_ndt_2)) [L390] COND TRUE t2_st == 0 [L391] int tmp_ndt_3; [L392] tmp_ndt_3 = __VERIFIER_nondet_int() [L393] COND FALSE !(\read(tmp_ndt_3)) [L404] COND TRUE t3_st == 0 [L405] int tmp_ndt_4; [L406] tmp_ndt_4 = __VERIFIER_nondet_int() [L407] COND FALSE !(\read(tmp_ndt_4)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 352]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int t2_pc = 0; [L27] int t3_pc = 0; [L28] int m_st ; [L29] int t1_st ; [L30] int t2_st ; [L31] int t3_st ; [L32] int m_i ; [L33] int t1_i ; [L34] int t2_i ; [L35] int t3_i ; [L36] int M_E = 2; [L37] int T1_E = 2; [L38] int T2_E = 2; [L39] int T3_E = 2; [L40] int E_M = 2; [L41] int E_1 = 2; [L42] int E_2 = 2; [L43] int E_3 = 2; [L49] int token ; [L51] int local ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0, token=0] [L723] int __retres1 ; [L727] CALL init_model() [L636] m_i = 1 [L637] t1_i = 1 [L638] t2_i = 1 [L639] t3_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L727] RET init_model() [L728] CALL start_simulation() [L664] int kernel_st ; [L665] int tmp ; [L666] int tmp___0 ; [L670] kernel_st = 0 [L671] FCALL update_channels() [L672] CALL init_threads() [L292] COND TRUE m_i == 1 [L293] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L297] COND TRUE t1_i == 1 [L298] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L302] COND TRUE t2_i == 1 [L303] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L307] COND TRUE t3_i == 1 [L308] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L672] RET init_threads() [L673] CALL fire_delta_events() [L429] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L434] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L439] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L444] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L449] COND FALSE !(E_M == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L454] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L459] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L464] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L673] RET fire_delta_events() [L674] CALL activate_threads() [L522] int tmp ; [L523] int tmp___0 ; [L524] int tmp___1 ; [L525] int tmp___2 ; [L529] CALL, EXPR is_master_triggered() [L205] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L208] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L218] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L220] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L529] RET, EXPR is_master_triggered() [L529] tmp = is_master_triggered() [L531] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L537] CALL, EXPR is_transmit1_triggered() [L224] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L227] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L237] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L239] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L537] RET, EXPR is_transmit1_triggered() [L537] tmp___0 = is_transmit1_triggered() [L539] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L545] CALL, EXPR is_transmit2_triggered() [L243] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L246] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L256] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L258] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L545] RET, EXPR is_transmit2_triggered() [L545] tmp___1 = is_transmit2_triggered() [L547] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L553] CALL, EXPR is_transmit3_triggered() [L262] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L265] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L275] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L277] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L553] RET, EXPR is_transmit3_triggered() [L553] tmp___2 = is_transmit3_triggered() [L555] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L674] RET activate_threads() [L675] CALL reset_delta_events() [L477] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L482] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L487] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L492] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L497] COND FALSE !(E_M == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L502] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L507] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L512] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L675] RET reset_delta_events() [L678] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L681] kernel_st = 1 [L682] CALL eval() [L348] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] Loop: [L352] COND TRUE 1 [L355] CALL, EXPR exists_runnable_thread() [L317] int __retres1 ; [L320] COND TRUE m_st == 0 [L321] __retres1 = 1 [L343] return (__retres1); [L355] RET, EXPR exists_runnable_thread() [L355] tmp = exists_runnable_thread() [L357] COND TRUE \read(tmp) [L362] COND TRUE m_st == 0 [L363] int tmp_ndt_1; [L364] tmp_ndt_1 = __VERIFIER_nondet_int() [L365] COND FALSE !(\read(tmp_ndt_1)) [L376] COND TRUE t1_st == 0 [L377] int tmp_ndt_2; [L378] tmp_ndt_2 = __VERIFIER_nondet_int() [L379] COND FALSE !(\read(tmp_ndt_2)) [L390] COND TRUE t2_st == 0 [L391] int tmp_ndt_3; [L392] tmp_ndt_3 = __VERIFIER_nondet_int() [L393] COND FALSE !(\read(tmp_ndt_3)) [L404] COND TRUE t3_st == 0 [L405] int tmp_ndt_4; [L406] tmp_ndt_4 = __VERIFIER_nondet_int() [L407] COND FALSE !(\read(tmp_ndt_4)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2024-11-08 00:34:50,967 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)