./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.05.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 4f9af400 extending candidate: java ['java'] extending candidate: /usr/bin/java ['java', '/usr/bin/java'] extending candidate: /opt/oracle-jdk-bin-*/bin/java ['java', '/usr/bin/java'] extending candidate: /opt/openjdk-*/bin/java ['java', '/usr/bin/java'] extending candidate: /usr/lib/jvm/java-*-openjdk-amd64/bin/java ['java', '/usr/bin/java', '/usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java', '/usr/lib/jvm/java-17-openjdk-amd64/bin/java', '/usr/lib/jvm/java-11-openjdk-amd64/bin/java', '/usr/lib/jvm/java-1.17.0-openjdk-amd64/bin/java'] ['/root/.sdkman/candidates/java/21.0.5-tem/bin/java', '-Dosgi.configuration.area=/storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/config', '-Xmx15G', '-Xms4m', '-jar', '/storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar', '-data', '@noDefault', '-ultimatedata', '/storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data', '-tc', '/storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml', '-i', '../sv-benchmarks/c/systemc/token_ring.05.cil-2.c', '-s', '/storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf', '--cacsl2boogietranslator.entry.function', 'main', '--witnessprinter.witness.directory', '/storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux', '--witnessprinter.witness.filename', 'witness', '--witnessprinter.write.witness.besides.input.file', 'false', '--witnessprinter.graph.data.specification', 'CHECK( init(main()), LTL(F end) )\n\n', '--witnessprinter.graph.data.producer', 'Automizer', '--witnessprinter.graph.data.architecture', '32bit', '--witnessprinter.graph.data.programhash', '16e147b68a860b93a665f8bd36a316225675cf186d50a72fc3242bc6ec552f78'] Calling Ultimate with: /root/.sdkman/candidates/java/21.0.5-tem/bin/java -Dosgi.configuration.area=/storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.05.cil-2.c -s /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 16e147b68a860b93a665f8bd36a316225675cf186d50a72fc3242bc6ec552f78 --- Real Ultimate output --- This is Ultimate 0.3.0-?-4f9af40 [2024-11-08 00:34:50,008 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-08 00:34:50,112 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-11-08 00:34:50,119 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-08 00:34:50,121 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-08 00:34:50,150 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-08 00:34:50,151 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-08 00:34:50,152 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-08 00:34:50,152 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-08 00:34:50,153 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-08 00:34:50,153 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-08 00:34:50,154 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-08 00:34:50,154 INFO L153 SettingsManager]: * Use SBE=true [2024-11-08 00:34:50,154 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-11-08 00:34:50,154 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-11-08 00:34:50,154 INFO L153 SettingsManager]: * Use old map elimination=false [2024-11-08 00:34:50,154 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-11-08 00:34:50,154 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-11-08 00:34:50,154 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-11-08 00:34:50,154 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-08 00:34:50,154 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-11-08 00:34:50,154 INFO L153 SettingsManager]: * sizeof long=4 [2024-11-08 00:34:50,155 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-08 00:34:50,155 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-11-08 00:34:50,155 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-08 00:34:50,155 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-11-08 00:34:50,155 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-11-08 00:34:50,155 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-11-08 00:34:50,155 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-11-08 00:34:50,155 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-11-08 00:34:50,155 INFO L153 SettingsManager]: * sizeof long double=12 [2024-11-08 00:34:50,156 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-08 00:34:50,156 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-11-08 00:34:50,156 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-08 00:34:50,156 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-11-08 00:34:50,156 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-08 00:34:50,156 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-08 00:34:50,156 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-11-08 00:34:50,156 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-11-08 00:34:50,156 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 16e147b68a860b93a665f8bd36a316225675cf186d50a72fc3242bc6ec552f78 [2024-11-08 00:34:50,433 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-08 00:34:50,440 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-08 00:34:50,442 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-08 00:34:50,444 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-08 00:34:50,444 INFO L274 PluginConnector]: CDTParser initialized [2024-11-08 00:34:50,446 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.05.cil-2.c [2024-11-08 00:34:51,755 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-11-08 00:34:52,015 INFO L384 CDTParser]: Found 1 translation units. [2024-11-08 00:34:52,016 INFO L180 CDTParser]: Scanning /storage/repos/ultimate-jdk21/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.05.cil-2.c [2024-11-08 00:34:52,028 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/3d9e76fdd/0a8bbcfbf9af42ddb83c9a80847c9e3d/FLAGdd56a7458 [2024-11-08 00:34:52,041 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/3d9e76fdd/0a8bbcfbf9af42ddb83c9a80847c9e3d [2024-11-08 00:34:52,043 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-08 00:34:52,045 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-08 00:34:52,045 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-08 00:34:52,045 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-08 00:34:52,048 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-08 00:34:52,049 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 08.11 12:34:52" (1/1) ... [2024-11-08 00:34:52,050 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@b7877e6 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 12:34:52, skipping insertion in model container [2024-11-08 00:34:52,050 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 08.11 12:34:52" (1/1) ... [2024-11-08 00:34:52,081 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-08 00:34:52,273 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-08 00:34:52,284 INFO L200 MainTranslator]: Completed pre-run [2024-11-08 00:34:52,327 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-08 00:34:52,344 INFO L204 MainTranslator]: Completed translation [2024-11-08 00:34:52,344 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 12:34:52 WrapperNode [2024-11-08 00:34:52,345 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-08 00:34:52,346 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-08 00:34:52,346 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-08 00:34:52,346 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-08 00:34:52,351 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 12:34:52" (1/1) ... [2024-11-08 00:34:52,361 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 12:34:52" (1/1) ... [2024-11-08 00:34:52,426 INFO L138 Inliner]: procedures = 38, calls = 48, calls flagged for inlining = 43, calls inlined = 97, statements flattened = 1368 [2024-11-08 00:34:52,431 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-08 00:34:52,432 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-08 00:34:52,432 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-08 00:34:52,432 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-08 00:34:52,440 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 12:34:52" (1/1) ... [2024-11-08 00:34:52,440 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 12:34:52" (1/1) ... [2024-11-08 00:34:52,450 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 12:34:52" (1/1) ... [2024-11-08 00:34:52,486 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-11-08 00:34:52,493 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 12:34:52" (1/1) ... [2024-11-08 00:34:52,493 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 12:34:52" (1/1) ... [2024-11-08 00:34:52,507 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 12:34:52" (1/1) ... [2024-11-08 00:34:52,521 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 12:34:52" (1/1) ... [2024-11-08 00:34:52,524 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 12:34:52" (1/1) ... [2024-11-08 00:34:52,527 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 12:34:52" (1/1) ... [2024-11-08 00:34:52,533 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-08 00:34:52,534 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-11-08 00:34:52,534 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-11-08 00:34:52,534 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-11-08 00:34:52,535 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 12:34:52" (1/1) ... [2024-11-08 00:34:52,540 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 00:34:52,562 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2024-11-08 00:34:52,576 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 00:34:52,579 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-11-08 00:34:52,604 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-08 00:34:52,604 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-11-08 00:34:52,604 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-08 00:34:52,604 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-08 00:34:52,709 INFO L238 CfgBuilder]: Building ICFG [2024-11-08 00:34:52,711 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-08 00:34:53,995 INFO L? ?]: Removed 256 outVars from TransFormulas that were not future-live. [2024-11-08 00:34:53,996 INFO L287 CfgBuilder]: Performing block encoding [2024-11-08 00:34:54,026 INFO L311 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-08 00:34:54,028 INFO L316 CfgBuilder]: Removed 8 assume(true) statements. [2024-11-08 00:34:54,029 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 08.11 12:34:54 BoogieIcfgContainer [2024-11-08 00:34:54,029 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-11-08 00:34:54,029 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-11-08 00:34:54,030 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-11-08 00:34:54,036 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-11-08 00:34:54,037 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-08 00:34:54,037 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 08.11 12:34:52" (1/3) ... [2024-11-08 00:34:54,038 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@4c60eba3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 08.11 12:34:54, skipping insertion in model container [2024-11-08 00:34:54,038 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-08 00:34:54,038 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 12:34:52" (2/3) ... [2024-11-08 00:34:54,039 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@4c60eba3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 08.11 12:34:54, skipping insertion in model container [2024-11-08 00:34:54,039 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-08 00:34:54,039 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 08.11 12:34:54" (3/3) ... [2024-11-08 00:34:54,041 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.05.cil-2.c [2024-11-08 00:34:54,101 INFO L300 stractBuchiCegarLoop]: Interprodecural is true [2024-11-08 00:34:54,101 INFO L301 stractBuchiCegarLoop]: Hoare is None [2024-11-08 00:34:54,101 INFO L302 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-11-08 00:34:54,102 INFO L303 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-11-08 00:34:54,102 INFO L304 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-11-08 00:34:54,102 INFO L305 stractBuchiCegarLoop]: Difference is false [2024-11-08 00:34:54,102 INFO L306 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-11-08 00:34:54,102 INFO L310 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-11-08 00:34:54,111 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 567 states, 566 states have (on average 1.5229681978798586) internal successors, (862), 566 states have internal predecessors, (862), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:34:54,148 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 484 [2024-11-08 00:34:54,149 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:34:54,149 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:34:54,158 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:54,158 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:54,158 INFO L332 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-11-08 00:34:54,159 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 567 states, 566 states have (on average 1.5229681978798586) internal successors, (862), 566 states have internal predecessors, (862), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:34:54,168 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 484 [2024-11-08 00:34:54,169 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:34:54,169 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:34:54,171 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:54,171 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:54,183 INFO L745 eck$LassoCheckResult]: Stem: 192#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 472#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 279#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 469#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 265#L426true assume !(1 == ~m_i~0);~m_st~0 := 2; 328#L426-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 153#L431-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 323#L436-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 138#L441-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 507#L446-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 364#L451-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 209#L611true assume 0 == ~M_E~0;~M_E~0 := 1; 385#L611-2true assume !(0 == ~T1_E~0); 382#L616-1true assume !(0 == ~T2_E~0); 390#L621-1true assume !(0 == ~T3_E~0); 65#L626-1true assume !(0 == ~T4_E~0); 354#L631-1true assume !(0 == ~T5_E~0); 177#L636-1true assume !(0 == ~E_M~0); 91#L641-1true assume !(0 == ~E_1~0); 188#L646-1true assume 0 == ~E_2~0;~E_2~0 := 1; 498#L651-1true assume !(0 == ~E_3~0); 444#L656-1true assume !(0 == ~E_4~0); 362#L661-1true assume !(0 == ~E_5~0); 407#L666-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 530#L304true assume !(1 == ~m_pc~0); 104#L304-2true is_master_triggered_~__retres1~0#1 := 0; 52#L315true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 156#is_master_triggered_returnLabel#1true activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 27#L755true assume !(0 != activate_threads_~tmp~1#1); 553#L755-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6#L323true assume 1 == ~t1_pc~0; 309#L324true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 35#L334true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 43#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 499#L763true assume !(0 != activate_threads_~tmp___0~0#1); 510#L763-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 37#L342true assume 1 == ~t2_pc~0; 524#L343true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 110#L353true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 281#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 532#L771true assume !(0 != activate_threads_~tmp___1~0#1); 355#L771-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 238#L361true assume !(1 == ~t3_pc~0); 256#L361-2true is_transmit3_triggered_~__retres1~3#1 := 0; 463#L372true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 435#L779true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 45#L779-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 237#L380true assume 1 == ~t4_pc~0; 77#L381true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 375#L391true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 88#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 270#L787true assume !(0 != activate_threads_~tmp___3~0#1); 522#L787-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 78#L399true assume !(1 == ~t5_pc~0); 159#L399-2true is_transmit5_triggered_~__retres1~5#1 := 0; 387#L410true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 164#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 154#L795true assume !(0 != activate_threads_~tmp___4~0#1); 458#L795-2true havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 533#L679true assume !(1 == ~M_E~0); 206#L679-2true assume !(1 == ~T1_E~0); 117#L684-1true assume !(1 == ~T2_E~0); 244#L689-1true assume !(1 == ~T3_E~0); 544#L694-1true assume !(1 == ~T4_E~0); 243#L699-1true assume !(1 == ~T5_E~0); 363#L704-1true assume !(1 == ~E_M~0); 224#L709-1true assume 1 == ~E_1~0;~E_1~0 := 2; 180#L714-1true assume !(1 == ~E_2~0); 344#L719-1true assume !(1 == ~E_3~0); 483#L724-1true assume !(1 == ~E_4~0); 59#L729-1true assume !(1 == ~E_5~0); 465#L734-1true assume { :end_inline_reset_delta_events } true; 333#L940-2true [2024-11-08 00:34:54,185 INFO L747 eck$LassoCheckResult]: Loop: 333#L940-2true assume !false; 402#L941true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 447#L586-1true assume false; 96#eval_returnLabel#1true havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 412#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 303#L611-3true assume 0 == ~M_E~0;~M_E~0 := 1; 60#L611-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 319#L616-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 57#L621-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 30#L626-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 563#L631-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 31#L636-3true assume 0 == ~E_M~0;~E_M~0 := 1; 66#L641-3true assume !(0 == ~E_1~0); 240#L646-3true assume 0 == ~E_2~0;~E_2~0 := 1; 72#L651-3true assume 0 == ~E_3~0;~E_3~0 := 1; 218#L656-3true assume 0 == ~E_4~0;~E_4~0 := 1; 500#L661-3true assume 0 == ~E_5~0;~E_5~0 := 1; 512#L666-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 157#L304-21true assume 1 == ~m_pc~0; 519#L305-7true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 267#L315-7true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 114#is_master_triggered_returnLabel#8true activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 197#L755-21true assume !(0 != activate_threads_~tmp~1#1); 220#L755-23true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 495#L323-21true assume !(1 == ~t1_pc~0); 372#L323-23true is_transmit1_triggered_~__retres1~1#1 := 0; 408#L334-7true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 82#is_transmit1_triggered_returnLabel#8true activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 403#L763-21true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 423#L763-23true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 560#L342-21true assume 1 == ~t2_pc~0; 25#L343-7true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 261#L353-7true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 205#is_transmit2_triggered_returnLabel#8true activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 357#L771-21true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 79#L771-23true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 478#L361-21true assume !(1 == ~t3_pc~0); 460#L361-23true is_transmit3_triggered_~__retres1~3#1 := 0; 482#L372-7true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 484#is_transmit3_triggered_returnLabel#8true activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 178#L779-21true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 29#L779-23true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 518#L380-21true assume 1 == ~t4_pc~0; 432#L381-7true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 99#L391-7true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 454#is_transmit4_triggered_returnLabel#8true activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 343#L787-21true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 271#L787-23true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 144#L399-21true assume 1 == ~t5_pc~0; 129#L400-7true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 286#L410-7true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 255#is_transmit5_triggered_returnLabel#8true activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 505#L795-21true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 451#L795-23true havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26#L679-3true assume 1 == ~M_E~0;~M_E~0 := 2; 185#L679-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 230#L684-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 2#L689-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 168#L694-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 21#L699-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 307#L704-3true assume !(1 == ~E_M~0); 400#L709-3true assume 1 == ~E_1~0;~E_1~0 := 2; 291#L714-3true assume 1 == ~E_2~0;~E_2~0 := 2; 162#L719-3true assume 1 == ~E_3~0;~E_3~0 := 2; 20#L724-3true assume 1 == ~E_4~0;~E_4~0 := 2; 276#L729-3true assume 1 == ~E_5~0;~E_5~0 := 2; 326#L734-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 34#L464-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 219#L496-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 250#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 253#L959true assume !(0 == start_simulation_~tmp~3#1); 517#L959-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 182#L464-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 384#L496-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 42#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 373#L914true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 128#L921true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 422#stop_simulation_returnLabel#1true start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 308#L972true assume !(0 != start_simulation_~tmp___0~1#1); 333#L940-2true [2024-11-08 00:34:54,194 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:34:54,194 INFO L85 PathProgramCache]: Analyzing trace with hash 907431560, now seen corresponding path program 1 times [2024-11-08 00:34:54,199 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:34:54,200 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [210086468] [2024-11-08 00:34:54,200 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:34:54,200 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:34:54,286 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:34:54,446 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:34:54,446 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:34:54,446 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [210086468] [2024-11-08 00:34:54,448 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [210086468] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:34:54,448 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:34:54,449 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:34:54,451 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1754060100] [2024-11-08 00:34:54,452 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:34:54,455 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:34:54,456 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:34:54,456 INFO L85 PathProgramCache]: Analyzing trace with hash -2069699191, now seen corresponding path program 1 times [2024-11-08 00:34:54,456 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:34:54,456 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [904047456] [2024-11-08 00:34:54,456 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:34:54,457 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:34:54,470 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:34:54,513 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:34:54,513 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:34:54,513 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [904047456] [2024-11-08 00:34:54,513 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [904047456] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:34:54,513 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:34:54,513 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-08 00:34:54,513 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [9672768] [2024-11-08 00:34:54,514 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:34:54,515 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:34:54,515 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:34:54,544 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:34:54,546 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:34:54,549 INFO L87 Difference]: Start difference. First operand has 567 states, 566 states have (on average 1.5229681978798586) internal successors, (862), 566 states have internal predecessors, (862), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:34:54,613 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:34:54,614 INFO L93 Difference]: Finished difference Result 563 states and 839 transitions. [2024-11-08 00:34:54,615 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 563 states and 839 transitions. [2024-11-08 00:34:54,621 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 478 [2024-11-08 00:34:54,636 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 563 states to 557 states and 833 transitions. [2024-11-08 00:34:54,637 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 557 [2024-11-08 00:34:54,638 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 557 [2024-11-08 00:34:54,639 INFO L73 IsDeterministic]: Start isDeterministic. Operand 557 states and 833 transitions. [2024-11-08 00:34:54,642 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:34:54,642 INFO L218 hiAutomatonCegarLoop]: Abstraction has 557 states and 833 transitions. [2024-11-08 00:34:54,655 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 557 states and 833 transitions. [2024-11-08 00:34:54,684 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 557 to 557. [2024-11-08 00:34:54,686 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 557 states, 557 states have (on average 1.4955116696588868) internal successors, (833), 556 states have internal predecessors, (833), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:34:54,688 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 557 states to 557 states and 833 transitions. [2024-11-08 00:34:54,690 INFO L240 hiAutomatonCegarLoop]: Abstraction has 557 states and 833 transitions. [2024-11-08 00:34:54,691 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:34:54,694 INFO L425 stractBuchiCegarLoop]: Abstraction has 557 states and 833 transitions. [2024-11-08 00:34:54,694 INFO L332 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-11-08 00:34:54,694 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 557 states and 833 transitions. [2024-11-08 00:34:54,699 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 478 [2024-11-08 00:34:54,700 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:34:54,700 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:34:54,702 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:54,702 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:54,703 INFO L745 eck$LassoCheckResult]: Stem: 1478#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 1479#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 1578#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1579#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1564#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 1565#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1421#L431-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1422#L436-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1399#L441-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1400#L446-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1630#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1502#L611 assume 0 == ~M_E~0;~M_E~0 := 1; 1503#L611-2 assume !(0 == ~T1_E~0); 1642#L616-1 assume !(0 == ~T2_E~0); 1643#L621-1 assume !(0 == ~T3_E~0); 1267#L626-1 assume !(0 == ~T4_E~0); 1268#L631-1 assume !(0 == ~T5_E~0); 1459#L636-1 assume !(0 == ~E_M~0); 1319#L641-1 assume !(0 == ~E_1~0); 1320#L646-1 assume 0 == ~E_2~0;~E_2~0 := 1; 1476#L651-1 assume !(0 == ~E_3~0); 1671#L656-1 assume !(0 == ~E_4~0); 1628#L661-1 assume !(0 == ~E_5~0); 1629#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1655#L304 assume !(1 == ~m_pc~0); 1345#L304-2 is_master_triggered_~__retres1~0#1 := 0; 1242#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1243#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1193#L755 assume !(0 != activate_threads_~tmp~1#1); 1194#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1149#L323 assume 1 == ~t1_pc~0; 1150#L324 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1212#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1213#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1228#L763 assume !(0 != activate_threads_~tmp___0~0#1); 1691#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1215#L342 assume 1 == ~t2_pc~0; 1216#L343 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1351#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1352#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1580#L771 assume !(0 != activate_threads_~tmp___1~0#1); 1625#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1535#L361 assume !(1 == ~t3_pc~0); 1536#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1560#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1165#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1166#L779 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1233#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1234#L380 assume 1 == ~t4_pc~0; 1289#L381 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1290#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1314#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1315#L787 assume !(0 != activate_threads_~tmp___3~0#1); 1567#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1292#L399 assume !(1 == ~t5_pc~0); 1293#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1431#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1436#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1423#L795 assume !(0 != activate_threads_~tmp___4~0#1); 1424#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1680#L679 assume !(1 == ~M_E~0); 1500#L679-2 assume !(1 == ~T1_E~0); 1364#L684-1 assume !(1 == ~T2_E~0); 1365#L689-1 assume !(1 == ~T3_E~0); 1543#L694-1 assume !(1 == ~T4_E~0); 1541#L699-1 assume !(1 == ~T5_E~0); 1542#L704-1 assume !(1 == ~E_M~0); 1525#L709-1 assume 1 == ~E_1~0;~E_1~0 := 2; 1466#L714-1 assume !(1 == ~E_2~0); 1467#L719-1 assume !(1 == ~E_3~0); 1621#L724-1 assume !(1 == ~E_4~0); 1253#L729-1 assume !(1 == ~E_5~0); 1254#L734-1 assume { :end_inline_reset_delta_events } true; 1597#L940-2 [2024-11-08 00:34:54,704 INFO L747 eck$LassoCheckResult]: Loop: 1597#L940-2 assume !false; 1611#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1327#L586-1 assume !false; 1674#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1677#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1538#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1539#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1534#L511 assume !(0 != eval_~tmp~0#1); 1330#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1331#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1591#L611-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1255#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1256#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1251#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1200#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1201#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1202#L636-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1203#L641-3 assume !(0 == ~E_1~0); 1269#L646-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1279#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1280#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1519#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1692#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1428#L304-21 assume !(1 == ~m_pc~0); 1282#L304-23 is_master_triggered_~__retres1~0#1 := 0; 1283#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1358#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1359#L755-21 assume !(0 != activate_threads_~tmp~1#1); 1487#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1521#L323-21 assume 1 == ~t1_pc~0; 1162#L324-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1163#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1301#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1302#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1653#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1664#L342-21 assume 1 == ~t2_pc~0; 1188#L343-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1189#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1498#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1499#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1295#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1296#L361-21 assume !(1 == ~t3_pc~0); 1681#L361-23 is_transmit3_triggered_~__retres1~3#1 := 0; 1682#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1686#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1462#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1198#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1199#L380-21 assume 1 == ~t4_pc~0; 1670#L381-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1262#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1337#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1618#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1568#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1409#L399-21 assume !(1 == ~t5_pc~0); 1265#L399-23 is_transmit5_triggered_~__retres1~5#1 := 0; 1266#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1558#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1559#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1676#L795-23 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1191#L679-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1192#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1472#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1139#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1140#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1180#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1181#L704-3 assume !(1 == ~E_M~0); 1595#L709-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1586#L714-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1433#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1178#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1179#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1574#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1209#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1210#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1520#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 1553#L959 assume !(0 == start_simulation_~tmp~3#1); 1557#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1463#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1464#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1224#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 1225#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1383#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1384#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 1596#L972 assume !(0 != start_simulation_~tmp___0~1#1); 1597#L940-2 [2024-11-08 00:34:54,705 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:34:54,705 INFO L85 PathProgramCache]: Analyzing trace with hash 1400057734, now seen corresponding path program 1 times [2024-11-08 00:34:54,705 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:34:54,705 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1307633287] [2024-11-08 00:34:54,705 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:34:54,705 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:34:54,731 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:34:54,782 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:34:54,782 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:34:54,782 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1307633287] [2024-11-08 00:34:54,783 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1307633287] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:34:54,783 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:34:54,783 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:34:54,783 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2100461365] [2024-11-08 00:34:54,783 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:34:54,783 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:34:54,783 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:34:54,784 INFO L85 PathProgramCache]: Analyzing trace with hash -803035657, now seen corresponding path program 1 times [2024-11-08 00:34:54,784 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:34:54,784 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [881268720] [2024-11-08 00:34:54,784 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:34:54,784 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:34:54,823 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:34:54,912 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:34:54,914 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:34:54,915 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [881268720] [2024-11-08 00:34:54,915 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [881268720] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:34:54,915 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:34:54,915 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:34:54,915 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1554443578] [2024-11-08 00:34:54,915 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:34:54,915 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:34:54,915 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:34:54,916 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:34:54,916 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:34:54,916 INFO L87 Difference]: Start difference. First operand 557 states and 833 transitions. cyclomatic complexity: 277 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:34:54,942 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:34:54,942 INFO L93 Difference]: Finished difference Result 557 states and 832 transitions. [2024-11-08 00:34:54,942 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 557 states and 832 transitions. [2024-11-08 00:34:54,948 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 478 [2024-11-08 00:34:54,952 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 557 states to 557 states and 832 transitions. [2024-11-08 00:34:54,953 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 557 [2024-11-08 00:34:54,954 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 557 [2024-11-08 00:34:54,954 INFO L73 IsDeterministic]: Start isDeterministic. Operand 557 states and 832 transitions. [2024-11-08 00:34:54,959 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:34:54,959 INFO L218 hiAutomatonCegarLoop]: Abstraction has 557 states and 832 transitions. [2024-11-08 00:34:54,960 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 557 states and 832 transitions. [2024-11-08 00:34:54,974 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 557 to 557. [2024-11-08 00:34:54,975 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 557 states, 557 states have (on average 1.4937163375224416) internal successors, (832), 556 states have internal predecessors, (832), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:34:54,978 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 557 states to 557 states and 832 transitions. [2024-11-08 00:34:54,978 INFO L240 hiAutomatonCegarLoop]: Abstraction has 557 states and 832 transitions. [2024-11-08 00:34:54,978 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:34:54,979 INFO L425 stractBuchiCegarLoop]: Abstraction has 557 states and 832 transitions. [2024-11-08 00:34:54,979 INFO L332 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-11-08 00:34:54,979 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 557 states and 832 transitions. [2024-11-08 00:34:54,982 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 478 [2024-11-08 00:34:54,982 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:34:54,982 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:34:54,984 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:54,985 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:54,985 INFO L745 eck$LassoCheckResult]: Stem: 2599#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 2600#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 2699#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2700#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2685#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 2686#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2542#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2543#L436-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2520#L441-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2521#L446-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2751#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2623#L611 assume 0 == ~M_E~0;~M_E~0 := 1; 2624#L611-2 assume !(0 == ~T1_E~0); 2763#L616-1 assume !(0 == ~T2_E~0); 2764#L621-1 assume !(0 == ~T3_E~0); 2388#L626-1 assume !(0 == ~T4_E~0); 2389#L631-1 assume !(0 == ~T5_E~0); 2583#L636-1 assume !(0 == ~E_M~0); 2440#L641-1 assume !(0 == ~E_1~0); 2441#L646-1 assume 0 == ~E_2~0;~E_2~0 := 1; 2597#L651-1 assume !(0 == ~E_3~0); 2792#L656-1 assume !(0 == ~E_4~0); 2749#L661-1 assume !(0 == ~E_5~0); 2750#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2776#L304 assume !(1 == ~m_pc~0); 2467#L304-2 is_master_triggered_~__retres1~0#1 := 0; 2363#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2364#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2316#L755 assume !(0 != activate_threads_~tmp~1#1); 2317#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2270#L323 assume 1 == ~t1_pc~0; 2271#L324 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2333#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2334#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2349#L763 assume !(0 != activate_threads_~tmp___0~0#1); 2812#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2340#L342 assume 1 == ~t2_pc~0; 2341#L343 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2472#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2473#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2701#L771 assume !(0 != activate_threads_~tmp___1~0#1); 2746#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2656#L361 assume !(1 == ~t3_pc~0); 2657#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2681#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2286#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2287#L779 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2354#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2355#L380 assume 1 == ~t4_pc~0; 2410#L381 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2411#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2436#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2437#L787 assume !(0 != activate_threads_~tmp___3~0#1); 2688#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2413#L399 assume !(1 == ~t5_pc~0); 2414#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2552#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2557#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2544#L795 assume !(0 != activate_threads_~tmp___4~0#1); 2545#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2801#L679 assume !(1 == ~M_E~0); 2621#L679-2 assume !(1 == ~T1_E~0); 2485#L684-1 assume !(1 == ~T2_E~0); 2486#L689-1 assume !(1 == ~T3_E~0); 2664#L694-1 assume !(1 == ~T4_E~0); 2662#L699-1 assume !(1 == ~T5_E~0); 2663#L704-1 assume !(1 == ~E_M~0); 2646#L709-1 assume 1 == ~E_1~0;~E_1~0 := 2; 2587#L714-1 assume !(1 == ~E_2~0); 2588#L719-1 assume !(1 == ~E_3~0); 2742#L724-1 assume !(1 == ~E_4~0); 2374#L729-1 assume !(1 == ~E_5~0); 2375#L734-1 assume { :end_inline_reset_delta_events } true; 2718#L940-2 [2024-11-08 00:34:54,985 INFO L747 eck$LassoCheckResult]: Loop: 2718#L940-2 assume !false; 2732#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2448#L586-1 assume !false; 2795#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 2798#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 2659#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 2660#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 2655#L511 assume !(0 != eval_~tmp~0#1); 2451#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2452#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2712#L611-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2376#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2377#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2373#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2321#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2322#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2323#L636-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2324#L641-3 assume !(0 == ~E_1~0); 2390#L646-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2400#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2401#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2640#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2813#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2549#L304-21 assume !(1 == ~m_pc~0); 2403#L304-23 is_master_triggered_~__retres1~0#1 := 0; 2404#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2479#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2480#L755-21 assume !(0 != activate_threads_~tmp~1#1); 2608#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2642#L323-21 assume 1 == ~t1_pc~0; 2283#L324-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2284#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2422#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2423#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2774#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2785#L342-21 assume 1 == ~t2_pc~0; 2309#L343-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2310#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2617#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2618#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2416#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2417#L361-21 assume !(1 == ~t3_pc~0); 2802#L361-23 is_transmit3_triggered_~__retres1~3#1 := 0; 2803#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2807#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2582#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2314#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2315#L380-21 assume 1 == ~t4_pc~0; 2791#L381-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2381#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2456#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2739#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2689#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2530#L399-21 assume !(1 == ~t5_pc~0); 2386#L399-23 is_transmit5_triggered_~__retres1~5#1 := 0; 2387#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2679#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2680#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2797#L795-23 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2312#L679-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2313#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2593#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2260#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2261#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2301#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2302#L704-3 assume !(1 == ~E_M~0); 2716#L709-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2707#L714-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2554#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2299#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2300#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2695#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 2330#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 2331#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 2641#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 2674#L959 assume !(0 == start_simulation_~tmp~3#1); 2678#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 2584#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 2585#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 2345#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 2346#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2504#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2505#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 2717#L972 assume !(0 != start_simulation_~tmp___0~1#1); 2718#L940-2 [2024-11-08 00:34:54,986 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:34:54,988 INFO L85 PathProgramCache]: Analyzing trace with hash -1678755836, now seen corresponding path program 1 times [2024-11-08 00:34:54,988 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:34:54,989 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [570803182] [2024-11-08 00:34:54,989 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:34:54,989 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:34:55,004 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:34:55,059 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:34:55,059 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:34:55,059 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [570803182] [2024-11-08 00:34:55,059 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [570803182] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:34:55,059 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:34:55,059 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:34:55,060 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [356438606] [2024-11-08 00:34:55,060 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:34:55,060 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:34:55,060 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:34:55,060 INFO L85 PathProgramCache]: Analyzing trace with hash -803035657, now seen corresponding path program 2 times [2024-11-08 00:34:55,060 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:34:55,061 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1743593890] [2024-11-08 00:34:55,061 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:34:55,061 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:34:55,076 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:34:55,158 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:34:55,158 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:34:55,158 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1743593890] [2024-11-08 00:34:55,158 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1743593890] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:34:55,158 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:34:55,158 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:34:55,158 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [782687730] [2024-11-08 00:34:55,158 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:34:55,159 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:34:55,159 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:34:55,159 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:34:55,159 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:34:55,159 INFO L87 Difference]: Start difference. First operand 557 states and 832 transitions. cyclomatic complexity: 276 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:34:55,178 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:34:55,178 INFO L93 Difference]: Finished difference Result 557 states and 831 transitions. [2024-11-08 00:34:55,178 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 557 states and 831 transitions. [2024-11-08 00:34:55,182 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 478 [2024-11-08 00:34:55,185 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 557 states to 557 states and 831 transitions. [2024-11-08 00:34:55,186 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 557 [2024-11-08 00:34:55,186 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 557 [2024-11-08 00:34:55,187 INFO L73 IsDeterministic]: Start isDeterministic. Operand 557 states and 831 transitions. [2024-11-08 00:34:55,187 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:34:55,188 INFO L218 hiAutomatonCegarLoop]: Abstraction has 557 states and 831 transitions. [2024-11-08 00:34:55,189 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 557 states and 831 transitions. [2024-11-08 00:34:55,196 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 557 to 557. [2024-11-08 00:34:55,197 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 557 states, 557 states have (on average 1.4919210053859964) internal successors, (831), 556 states have internal predecessors, (831), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:34:55,199 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 557 states to 557 states and 831 transitions. [2024-11-08 00:34:55,199 INFO L240 hiAutomatonCegarLoop]: Abstraction has 557 states and 831 transitions. [2024-11-08 00:34:55,200 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:34:55,201 INFO L425 stractBuchiCegarLoop]: Abstraction has 557 states and 831 transitions. [2024-11-08 00:34:55,202 INFO L332 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-11-08 00:34:55,202 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 557 states and 831 transitions. [2024-11-08 00:34:55,205 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 478 [2024-11-08 00:34:55,205 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:34:55,205 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:34:55,206 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:55,207 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:55,207 INFO L745 eck$LassoCheckResult]: Stem: 3720#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 3721#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 3820#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3821#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3806#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 3807#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3663#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3664#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3641#L441-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3642#L446-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3872#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3744#L611 assume 0 == ~M_E~0;~M_E~0 := 1; 3745#L611-2 assume !(0 == ~T1_E~0); 3885#L616-1 assume !(0 == ~T2_E~0); 3886#L621-1 assume !(0 == ~T3_E~0); 3509#L626-1 assume !(0 == ~T4_E~0); 3510#L631-1 assume !(0 == ~T5_E~0); 3704#L636-1 assume !(0 == ~E_M~0); 3561#L641-1 assume !(0 == ~E_1~0); 3562#L646-1 assume 0 == ~E_2~0;~E_2~0 := 1; 3718#L651-1 assume !(0 == ~E_3~0); 3913#L656-1 assume !(0 == ~E_4~0); 3870#L661-1 assume !(0 == ~E_5~0); 3871#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3897#L304 assume !(1 == ~m_pc~0); 3590#L304-2 is_master_triggered_~__retres1~0#1 := 0; 3484#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3485#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3437#L755 assume !(0 != activate_threads_~tmp~1#1); 3438#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3391#L323 assume 1 == ~t1_pc~0; 3392#L324 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3454#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3455#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3470#L763 assume !(0 != activate_threads_~tmp___0~0#1); 3933#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3461#L342 assume 1 == ~t2_pc~0; 3462#L343 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3593#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3594#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3822#L771 assume !(0 != activate_threads_~tmp___1~0#1); 3867#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3777#L361 assume !(1 == ~t3_pc~0); 3778#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3802#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3407#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3408#L779 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3475#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3476#L380 assume 1 == ~t4_pc~0; 3531#L381 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3532#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3557#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3558#L787 assume !(0 != activate_threads_~tmp___3~0#1); 3809#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3534#L399 assume !(1 == ~t5_pc~0); 3535#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3674#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3678#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3665#L795 assume !(0 != activate_threads_~tmp___4~0#1); 3666#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3922#L679 assume !(1 == ~M_E~0); 3743#L679-2 assume !(1 == ~T1_E~0); 3606#L684-1 assume !(1 == ~T2_E~0); 3607#L689-1 assume !(1 == ~T3_E~0); 3785#L694-1 assume !(1 == ~T4_E~0); 3783#L699-1 assume !(1 == ~T5_E~0); 3784#L704-1 assume !(1 == ~E_M~0); 3767#L709-1 assume 1 == ~E_1~0;~E_1~0 := 2; 3708#L714-1 assume !(1 == ~E_2~0); 3709#L719-1 assume !(1 == ~E_3~0); 3863#L724-1 assume !(1 == ~E_4~0); 3495#L729-1 assume !(1 == ~E_5~0); 3496#L734-1 assume { :end_inline_reset_delta_events } true; 3839#L940-2 [2024-11-08 00:34:55,207 INFO L747 eck$LassoCheckResult]: Loop: 3839#L940-2 assume !false; 3853#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3569#L586-1 assume !false; 3916#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 3919#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 3780#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 3781#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 3776#L511 assume !(0 != eval_~tmp~0#1); 3572#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3573#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3833#L611-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3497#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3498#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3494#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3442#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3443#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3444#L636-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3445#L641-3 assume !(0 == ~E_1~0); 3511#L646-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3521#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3522#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3761#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3934#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3670#L304-21 assume !(1 == ~m_pc~0); 3524#L304-23 is_master_triggered_~__retres1~0#1 := 0; 3525#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3600#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3601#L755-21 assume !(0 != activate_threads_~tmp~1#1); 3729#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3763#L323-21 assume 1 == ~t1_pc~0; 3404#L324-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3405#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3543#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3544#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3895#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3906#L342-21 assume 1 == ~t2_pc~0; 3430#L343-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3431#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3738#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3739#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3537#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3538#L361-21 assume !(1 == ~t3_pc~0); 3923#L361-23 is_transmit3_triggered_~__retres1~3#1 := 0; 3924#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3928#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3703#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3435#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3436#L380-21 assume 1 == ~t4_pc~0; 3912#L381-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3504#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3577#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3861#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3810#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3651#L399-21 assume !(1 == ~t5_pc~0); 3507#L399-23 is_transmit5_triggered_~__retres1~5#1 := 0; 3508#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3800#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3801#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3918#L795-23 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3433#L679-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3434#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3714#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3381#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3382#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3422#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3423#L704-3 assume !(1 == ~E_M~0); 3837#L709-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3828#L714-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3675#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3420#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3421#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3818#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 3451#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 3452#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 3762#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 3795#L959 assume !(0 == start_simulation_~tmp~3#1); 3799#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 3705#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 3706#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 3466#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 3467#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3625#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3626#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 3838#L972 assume !(0 != start_simulation_~tmp___0~1#1); 3839#L940-2 [2024-11-08 00:34:55,210 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:34:55,210 INFO L85 PathProgramCache]: Analyzing trace with hash -946788410, now seen corresponding path program 1 times [2024-11-08 00:34:55,210 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:34:55,210 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [443518224] [2024-11-08 00:34:55,210 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:34:55,210 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:34:55,230 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:34:55,271 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:34:55,272 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:34:55,272 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [443518224] [2024-11-08 00:34:55,272 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [443518224] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:34:55,272 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:34:55,272 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:34:55,272 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1917662407] [2024-11-08 00:34:55,272 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:34:55,273 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:34:55,273 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:34:55,273 INFO L85 PathProgramCache]: Analyzing trace with hash -803035657, now seen corresponding path program 3 times [2024-11-08 00:34:55,273 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:34:55,273 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1408235706] [2024-11-08 00:34:55,274 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:34:55,274 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:34:55,286 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:34:55,330 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:34:55,330 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:34:55,331 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1408235706] [2024-11-08 00:34:55,331 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1408235706] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:34:55,331 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:34:55,331 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:34:55,331 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [809009054] [2024-11-08 00:34:55,331 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:34:55,331 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:34:55,332 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:34:55,332 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:34:55,332 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:34:55,332 INFO L87 Difference]: Start difference. First operand 557 states and 831 transitions. cyclomatic complexity: 275 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:34:55,352 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:34:55,353 INFO L93 Difference]: Finished difference Result 557 states and 830 transitions. [2024-11-08 00:34:55,353 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 557 states and 830 transitions. [2024-11-08 00:34:55,357 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 478 [2024-11-08 00:34:55,361 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 557 states to 557 states and 830 transitions. [2024-11-08 00:34:55,361 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 557 [2024-11-08 00:34:55,362 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 557 [2024-11-08 00:34:55,362 INFO L73 IsDeterministic]: Start isDeterministic. Operand 557 states and 830 transitions. [2024-11-08 00:34:55,362 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:34:55,363 INFO L218 hiAutomatonCegarLoop]: Abstraction has 557 states and 830 transitions. [2024-11-08 00:34:55,363 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 557 states and 830 transitions. [2024-11-08 00:34:55,370 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 557 to 557. [2024-11-08 00:34:55,373 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 557 states, 557 states have (on average 1.4901256732495511) internal successors, (830), 556 states have internal predecessors, (830), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:34:55,375 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 557 states to 557 states and 830 transitions. [2024-11-08 00:34:55,377 INFO L240 hiAutomatonCegarLoop]: Abstraction has 557 states and 830 transitions. [2024-11-08 00:34:55,377 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:34:55,379 INFO L425 stractBuchiCegarLoop]: Abstraction has 557 states and 830 transitions. [2024-11-08 00:34:55,379 INFO L332 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-11-08 00:34:55,379 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 557 states and 830 transitions. [2024-11-08 00:34:55,382 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 478 [2024-11-08 00:34:55,382 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:34:55,382 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:34:55,384 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:55,386 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:55,387 INFO L745 eck$LassoCheckResult]: Stem: 4841#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 4842#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 4941#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4942#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4927#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 4928#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4784#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4785#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4762#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4763#L446-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4993#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4865#L611 assume 0 == ~M_E~0;~M_E~0 := 1; 4866#L611-2 assume !(0 == ~T1_E~0); 5006#L616-1 assume !(0 == ~T2_E~0); 5007#L621-1 assume !(0 == ~T3_E~0); 4634#L626-1 assume !(0 == ~T4_E~0); 4635#L631-1 assume !(0 == ~T5_E~0); 4825#L636-1 assume !(0 == ~E_M~0); 4685#L641-1 assume !(0 == ~E_1~0); 4686#L646-1 assume 0 == ~E_2~0;~E_2~0 := 1; 4839#L651-1 assume !(0 == ~E_3~0); 5034#L656-1 assume !(0 == ~E_4~0); 4991#L661-1 assume !(0 == ~E_5~0); 4992#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5018#L304 assume !(1 == ~m_pc~0); 4712#L304-2 is_master_triggered_~__retres1~0#1 := 0; 4605#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4606#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4558#L755 assume !(0 != activate_threads_~tmp~1#1); 4559#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4514#L323 assume 1 == ~t1_pc~0; 4515#L324 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4575#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4576#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4591#L763 assume !(0 != activate_threads_~tmp___0~0#1); 5054#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4584#L342 assume 1 == ~t2_pc~0; 4585#L343 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4714#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4715#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4943#L771 assume !(0 != activate_threads_~tmp___1~0#1); 4988#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4898#L361 assume !(1 == ~t3_pc~0); 4899#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4923#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4528#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4529#L779 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4596#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4597#L380 assume 1 == ~t4_pc~0; 4652#L381 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4653#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4680#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4681#L787 assume !(0 != activate_threads_~tmp___3~0#1); 4930#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4655#L399 assume !(1 == ~t5_pc~0); 4656#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4795#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4799#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4786#L795 assume !(0 != activate_threads_~tmp___4~0#1); 4787#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5043#L679 assume !(1 == ~M_E~0); 4864#L679-2 assume !(1 == ~T1_E~0); 4727#L684-1 assume !(1 == ~T2_E~0); 4728#L689-1 assume !(1 == ~T3_E~0); 4906#L694-1 assume !(1 == ~T4_E~0); 4904#L699-1 assume !(1 == ~T5_E~0); 4905#L704-1 assume !(1 == ~E_M~0); 4888#L709-1 assume 1 == ~E_1~0;~E_1~0 := 2; 4830#L714-1 assume !(1 == ~E_2~0); 4831#L719-1 assume !(1 == ~E_3~0); 4984#L724-1 assume !(1 == ~E_4~0); 4616#L729-1 assume !(1 == ~E_5~0); 4617#L734-1 assume { :end_inline_reset_delta_events } true; 4961#L940-2 [2024-11-08 00:34:55,387 INFO L747 eck$LassoCheckResult]: Loop: 4961#L940-2 assume !false; 4974#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4690#L586-1 assume !false; 5037#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 5040#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 4901#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 4902#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 4897#L511 assume !(0 != eval_~tmp~0#1); 4693#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4694#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4954#L611-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4618#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4619#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4615#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4563#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4564#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4565#L636-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4566#L641-3 assume !(0 == ~E_1~0); 4628#L646-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4642#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4643#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4881#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5055#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4791#L304-21 assume !(1 == ~m_pc~0); 4645#L304-23 is_master_triggered_~__retres1~0#1 := 0; 4646#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4721#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4722#L755-21 assume !(0 != activate_threads_~tmp~1#1); 4850#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4884#L323-21 assume 1 == ~t1_pc~0; 4525#L324-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4526#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4664#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4665#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5016#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5027#L342-21 assume 1 == ~t2_pc~0; 4551#L343-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4552#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4861#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4862#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4658#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4659#L361-21 assume !(1 == ~t3_pc~0); 5044#L361-23 is_transmit3_triggered_~__retres1~3#1 := 0; 5045#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5049#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4824#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4556#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4557#L380-21 assume !(1 == ~t4_pc~0); 4624#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 4625#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4698#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4982#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4931#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4772#L399-21 assume !(1 == ~t5_pc~0); 4632#L399-23 is_transmit5_triggered_~__retres1~5#1 := 0; 4633#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4921#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4922#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5039#L795-23 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4554#L679-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4555#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4835#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4502#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4503#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4543#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4544#L704-3 assume !(1 == ~E_M~0); 4959#L709-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4949#L714-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4796#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4541#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4542#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4939#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 4572#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 4573#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 4883#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 4916#L959 assume !(0 == start_simulation_~tmp~3#1); 4920#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 4827#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 4828#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 4589#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 4590#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4746#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4747#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 4960#L972 assume !(0 != start_simulation_~tmp___0~1#1); 4961#L940-2 [2024-11-08 00:34:55,388 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:34:55,388 INFO L85 PathProgramCache]: Analyzing trace with hash 739391428, now seen corresponding path program 1 times [2024-11-08 00:34:55,388 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:34:55,388 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1595428564] [2024-11-08 00:34:55,388 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:34:55,388 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:34:55,402 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:34:55,438 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:34:55,439 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:34:55,439 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1595428564] [2024-11-08 00:34:55,439 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1595428564] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:34:55,439 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:34:55,439 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:34:55,439 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [985359356] [2024-11-08 00:34:55,440 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:34:55,440 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:34:55,441 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:34:55,441 INFO L85 PathProgramCache]: Analyzing trace with hash 322224312, now seen corresponding path program 1 times [2024-11-08 00:34:55,442 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:34:55,442 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2065234951] [2024-11-08 00:34:55,442 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:34:55,442 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:34:55,456 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:34:55,496 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:34:55,496 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:34:55,496 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2065234951] [2024-11-08 00:34:55,496 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2065234951] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:34:55,496 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:34:55,496 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:34:55,497 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [568347332] [2024-11-08 00:34:55,497 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:34:55,497 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:34:55,497 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:34:55,497 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:34:55,497 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:34:55,498 INFO L87 Difference]: Start difference. First operand 557 states and 830 transitions. cyclomatic complexity: 274 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:34:55,514 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:34:55,514 INFO L93 Difference]: Finished difference Result 557 states and 829 transitions. [2024-11-08 00:34:55,515 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 557 states and 829 transitions. [2024-11-08 00:34:55,519 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 478 [2024-11-08 00:34:55,522 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 557 states to 557 states and 829 transitions. [2024-11-08 00:34:55,523 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 557 [2024-11-08 00:34:55,523 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 557 [2024-11-08 00:34:55,523 INFO L73 IsDeterministic]: Start isDeterministic. Operand 557 states and 829 transitions. [2024-11-08 00:34:55,527 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:34:55,527 INFO L218 hiAutomatonCegarLoop]: Abstraction has 557 states and 829 transitions. [2024-11-08 00:34:55,528 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 557 states and 829 transitions. [2024-11-08 00:34:55,540 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 557 to 557. [2024-11-08 00:34:55,541 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 557 states, 557 states have (on average 1.488330341113106) internal successors, (829), 556 states have internal predecessors, (829), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:34:55,547 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 557 states to 557 states and 829 transitions. [2024-11-08 00:34:55,547 INFO L240 hiAutomatonCegarLoop]: Abstraction has 557 states and 829 transitions. [2024-11-08 00:34:55,548 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:34:55,549 INFO L425 stractBuchiCegarLoop]: Abstraction has 557 states and 829 transitions. [2024-11-08 00:34:55,549 INFO L332 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-11-08 00:34:55,549 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 557 states and 829 transitions. [2024-11-08 00:34:55,552 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 478 [2024-11-08 00:34:55,553 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:34:55,553 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:34:55,555 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:55,555 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:55,555 INFO L745 eck$LassoCheckResult]: Stem: 5962#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 5963#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 6062#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6063#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6048#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 6049#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5905#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5906#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5883#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5884#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 6114#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5986#L611 assume 0 == ~M_E~0;~M_E~0 := 1; 5987#L611-2 assume !(0 == ~T1_E~0); 6127#L616-1 assume !(0 == ~T2_E~0); 6128#L621-1 assume !(0 == ~T3_E~0); 5755#L626-1 assume !(0 == ~T4_E~0); 5756#L631-1 assume !(0 == ~T5_E~0); 5946#L636-1 assume !(0 == ~E_M~0); 5806#L641-1 assume !(0 == ~E_1~0); 5807#L646-1 assume 0 == ~E_2~0;~E_2~0 := 1; 5960#L651-1 assume !(0 == ~E_3~0); 6155#L656-1 assume !(0 == ~E_4~0); 6112#L661-1 assume !(0 == ~E_5~0); 6113#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6139#L304 assume !(1 == ~m_pc~0); 5833#L304-2 is_master_triggered_~__retres1~0#1 := 0; 5726#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5727#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5682#L755 assume !(0 != activate_threads_~tmp~1#1); 5683#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5635#L323 assume 1 == ~t1_pc~0; 5636#L324 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5696#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5697#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5712#L763 assume !(0 != activate_threads_~tmp___0~0#1); 6175#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5705#L342 assume 1 == ~t2_pc~0; 5706#L343 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5835#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5836#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6064#L771 assume !(0 != activate_threads_~tmp___1~0#1); 6109#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6019#L361 assume !(1 == ~t3_pc~0); 6020#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 6044#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5649#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5650#L779 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5717#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5718#L380 assume 1 == ~t4_pc~0; 5776#L381 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5777#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5798#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5799#L787 assume !(0 != activate_threads_~tmp___3~0#1); 6051#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5773#L399 assume !(1 == ~t5_pc~0); 5774#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 5915#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5920#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5907#L795 assume !(0 != activate_threads_~tmp___4~0#1); 5908#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6164#L679 assume !(1 == ~M_E~0); 5984#L679-2 assume !(1 == ~T1_E~0); 5848#L684-1 assume !(1 == ~T2_E~0); 5849#L689-1 assume !(1 == ~T3_E~0); 6027#L694-1 assume !(1 == ~T4_E~0); 6025#L699-1 assume !(1 == ~T5_E~0); 6026#L704-1 assume !(1 == ~E_M~0); 6009#L709-1 assume 1 == ~E_1~0;~E_1~0 := 2; 5947#L714-1 assume !(1 == ~E_2~0); 5948#L719-1 assume !(1 == ~E_3~0); 6105#L724-1 assume !(1 == ~E_4~0); 5737#L729-1 assume !(1 == ~E_5~0); 5738#L734-1 assume { :end_inline_reset_delta_events } true; 6082#L940-2 [2024-11-08 00:34:55,555 INFO L747 eck$LassoCheckResult]: Loop: 6082#L940-2 assume !false; 6095#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5811#L586-1 assume !false; 6157#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 6161#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 6022#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 6023#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 6018#L511 assume !(0 != eval_~tmp~0#1); 5814#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5815#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6075#L611-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5739#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5740#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5735#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5684#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5685#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5686#L636-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5687#L641-3 assume !(0 == ~E_1~0); 5749#L646-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5763#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5764#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6003#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6176#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5912#L304-21 assume !(1 == ~m_pc~0); 5766#L304-23 is_master_triggered_~__retres1~0#1 := 0; 5767#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5842#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5843#L755-21 assume !(0 != activate_threads_~tmp~1#1); 5971#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6005#L323-21 assume !(1 == ~t1_pc~0); 5648#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 5647#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5785#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5786#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6137#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6148#L342-21 assume 1 == ~t2_pc~0; 5672#L343-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5673#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5982#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5983#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5779#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5780#L361-21 assume !(1 == ~t3_pc~0); 6165#L361-23 is_transmit3_triggered_~__retres1~3#1 := 0; 6166#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6170#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5945#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5680#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5681#L380-21 assume !(1 == ~t4_pc~0); 5745#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 5746#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5819#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6104#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6052#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5893#L399-21 assume !(1 == ~t5_pc~0); 5753#L399-23 is_transmit5_triggered_~__retres1~5#1 := 0; 5754#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6042#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6043#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6160#L795-23 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5675#L679-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5676#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5956#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5623#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5624#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5664#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5665#L704-3 assume !(1 == ~E_M~0); 6080#L709-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6070#L714-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5917#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5662#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5663#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6060#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 5693#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 5694#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 6004#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 6037#L959 assume !(0 == start_simulation_~tmp~3#1); 6041#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 5950#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 5951#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 5710#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 5711#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5867#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5868#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 6081#L972 assume !(0 != start_simulation_~tmp___0~1#1); 6082#L940-2 [2024-11-08 00:34:55,556 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:34:55,556 INFO L85 PathProgramCache]: Analyzing trace with hash 793784326, now seen corresponding path program 1 times [2024-11-08 00:34:55,556 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:34:55,557 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [5320682] [2024-11-08 00:34:55,557 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:34:55,557 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:34:55,585 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:34:55,636 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:34:55,636 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:34:55,636 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [5320682] [2024-11-08 00:34:55,636 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [5320682] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:34:55,636 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:34:55,636 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-08 00:34:55,636 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1863436828] [2024-11-08 00:34:55,636 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:34:55,636 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:34:55,637 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:34:55,637 INFO L85 PathProgramCache]: Analyzing trace with hash -785904327, now seen corresponding path program 1 times [2024-11-08 00:34:55,637 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:34:55,640 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1186350889] [2024-11-08 00:34:55,640 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:34:55,640 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:34:55,657 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:34:55,696 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:34:55,696 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:34:55,696 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1186350889] [2024-11-08 00:34:55,696 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1186350889] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:34:55,696 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:34:55,696 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:34:55,696 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1360133539] [2024-11-08 00:34:55,697 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:34:55,697 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:34:55,697 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:34:55,697 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:34:55,697 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:34:55,697 INFO L87 Difference]: Start difference. First operand 557 states and 829 transitions. cyclomatic complexity: 273 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 2 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:34:55,750 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:34:55,750 INFO L93 Difference]: Finished difference Result 991 states and 1469 transitions. [2024-11-08 00:34:55,750 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 991 states and 1469 transitions. [2024-11-08 00:34:55,757 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 912 [2024-11-08 00:34:55,763 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 991 states to 991 states and 1469 transitions. [2024-11-08 00:34:55,763 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 991 [2024-11-08 00:34:55,764 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 991 [2024-11-08 00:34:55,764 INFO L73 IsDeterministic]: Start isDeterministic. Operand 991 states and 1469 transitions. [2024-11-08 00:34:55,766 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:34:55,766 INFO L218 hiAutomatonCegarLoop]: Abstraction has 991 states and 1469 transitions. [2024-11-08 00:34:55,768 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 991 states and 1469 transitions. [2024-11-08 00:34:55,782 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 991 to 991. [2024-11-08 00:34:55,784 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 991 states, 991 states have (on average 1.4823410696266397) internal successors, (1469), 990 states have internal predecessors, (1469), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:34:55,787 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 991 states to 991 states and 1469 transitions. [2024-11-08 00:34:55,788 INFO L240 hiAutomatonCegarLoop]: Abstraction has 991 states and 1469 transitions. [2024-11-08 00:34:55,789 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:34:55,790 INFO L425 stractBuchiCegarLoop]: Abstraction has 991 states and 1469 transitions. [2024-11-08 00:34:55,791 INFO L332 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-11-08 00:34:55,792 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 991 states and 1469 transitions. [2024-11-08 00:34:55,796 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 912 [2024-11-08 00:34:55,797 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:34:55,797 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:34:55,798 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:55,798 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:55,801 INFO L745 eck$LassoCheckResult]: Stem: 7520#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 7521#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 7623#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7624#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7609#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 7610#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7461#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7462#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7439#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7440#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 7688#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7544#L611 assume !(0 == ~M_E~0); 7545#L611-2 assume !(0 == ~T1_E~0); 7701#L616-1 assume !(0 == ~T2_E~0); 7702#L621-1 assume !(0 == ~T3_E~0); 7304#L626-1 assume !(0 == ~T4_E~0); 7305#L631-1 assume !(0 == ~T5_E~0); 7500#L636-1 assume !(0 == ~E_M~0); 7359#L641-1 assume !(0 == ~E_1~0); 7360#L646-1 assume 0 == ~E_2~0;~E_2~0 := 1; 7518#L651-1 assume !(0 == ~E_3~0); 7739#L656-1 assume !(0 == ~E_4~0); 7686#L661-1 assume !(0 == ~E_5~0); 7687#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7718#L304 assume !(1 == ~m_pc~0); 7385#L304-2 is_master_triggered_~__retres1~0#1 := 0; 7281#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7282#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7232#L755 assume !(0 != activate_threads_~tmp~1#1); 7233#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7186#L323 assume 1 == ~t1_pc~0; 7187#L324 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7251#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7252#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7267#L763 assume !(0 != activate_threads_~tmp___0~0#1); 7766#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7254#L342 assume 1 == ~t2_pc~0; 7255#L343 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7391#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7392#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7625#L771 assume !(0 != activate_threads_~tmp___1~0#1); 7681#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7579#L361 assume !(1 == ~t3_pc~0); 7580#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 7604#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7204#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7205#L779 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7270#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7271#L380 assume 1 == ~t4_pc~0; 7328#L381 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7329#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7354#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7355#L787 assume !(0 != activate_threads_~tmp___3~0#1); 7612#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7331#L399 assume !(1 == ~t5_pc~0); 7332#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 7471#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7476#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7463#L795 assume !(0 != activate_threads_~tmp___4~0#1); 7464#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7751#L679 assume !(1 == ~M_E~0); 7542#L679-2 assume !(1 == ~T1_E~0); 7404#L684-1 assume !(1 == ~T2_E~0); 7405#L689-1 assume !(1 == ~T3_E~0); 7587#L694-1 assume !(1 == ~T4_E~0); 7585#L699-1 assume !(1 == ~T5_E~0); 7586#L704-1 assume !(1 == ~E_M~0); 7568#L709-1 assume 1 == ~E_1~0;~E_1~0 := 2; 7504#L714-1 assume !(1 == ~E_2~0); 7505#L719-1 assume !(1 == ~E_3~0); 7676#L724-1 assume !(1 == ~E_4~0); 7292#L729-1 assume !(1 == ~E_5~0); 7293#L734-1 assume { :end_inline_reset_delta_events } true; 7647#L940-2 [2024-11-08 00:34:55,802 INFO L747 eck$LassoCheckResult]: Loop: 7647#L940-2 assume !false; 7715#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7367#L586-1 assume !false; 7784#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 7780#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 7777#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 7638#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 7577#L511 assume !(0 != eval_~tmp~0#1); 7370#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7371#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7640#L611-3 assume !(0 == ~M_E~0); 7294#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7295#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7290#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7239#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7240#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7241#L636-3 assume 0 == ~E_M~0;~E_M~0 := 1; 7242#L641-3 assume !(0 == ~E_1~0); 7306#L646-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7318#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7319#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7562#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7767#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7468#L304-21 assume !(1 == ~m_pc~0); 7321#L304-23 is_master_triggered_~__retres1~0#1 := 0; 7322#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7398#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7399#L755-21 assume !(0 != activate_threads_~tmp~1#1); 7529#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7564#L323-21 assume 1 == ~t1_pc~0; 7201#L324-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7202#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7341#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7342#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7716#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7731#L342-21 assume 1 == ~t2_pc~0; 7227#L343-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7228#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7540#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7541#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7334#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7335#L361-21 assume !(1 == ~t3_pc~0); 7752#L361-23 is_transmit3_triggered_~__retres1~3#1 := 0; 7753#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7760#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7503#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7237#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7238#L380-21 assume !(1 == ~t4_pc~0); 7300#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 7301#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7375#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7675#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7613#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7449#L399-21 assume 1 == ~t5_pc~0; 7425#L400-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7311#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7602#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7603#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7745#L795-23 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7230#L679-3 assume !(1 == ~M_E~0); 7231#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8141#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8140#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8139#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8138#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8137#L704-3 assume !(1 == ~E_M~0); 8136#L709-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8135#L714-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8134#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8133#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8132#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8131#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 8118#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 8114#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 8113#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 8112#L959 assume !(0 == start_simulation_~tmp~3#1); 8110#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 8106#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 8103#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 7265#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 7266#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7423#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7424#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 7646#L972 assume !(0 != start_simulation_~tmp___0~1#1); 7647#L940-2 [2024-11-08 00:34:55,802 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:34:55,802 INFO L85 PathProgramCache]: Analyzing trace with hash 1473056580, now seen corresponding path program 1 times [2024-11-08 00:34:55,802 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:34:55,803 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [713065545] [2024-11-08 00:34:55,803 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:34:55,803 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:34:55,813 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:34:55,878 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:34:55,878 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:34:55,878 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [713065545] [2024-11-08 00:34:55,878 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [713065545] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:34:55,878 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:34:55,878 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-08 00:34:55,878 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [802257687] [2024-11-08 00:34:55,878 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:34:55,879 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:34:55,879 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:34:55,879 INFO L85 PathProgramCache]: Analyzing trace with hash -1173500553, now seen corresponding path program 1 times [2024-11-08 00:34:55,879 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:34:55,879 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [735125368] [2024-11-08 00:34:55,879 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:34:55,879 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:34:55,892 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:34:55,919 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:34:55,920 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:34:55,920 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [735125368] [2024-11-08 00:34:55,920 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [735125368] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:34:55,920 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:34:55,920 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:34:55,920 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1116186401] [2024-11-08 00:34:55,920 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:34:55,920 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:34:55,921 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:34:55,921 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:34:55,921 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:34:55,921 INFO L87 Difference]: Start difference. First operand 991 states and 1469 transitions. cyclomatic complexity: 479 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 2 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:34:55,969 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:34:55,969 INFO L93 Difference]: Finished difference Result 991 states and 1447 transitions. [2024-11-08 00:34:55,969 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 991 states and 1447 transitions. [2024-11-08 00:34:55,976 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 912 [2024-11-08 00:34:55,981 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 991 states to 991 states and 1447 transitions. [2024-11-08 00:34:55,981 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 991 [2024-11-08 00:34:55,982 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 991 [2024-11-08 00:34:55,982 INFO L73 IsDeterministic]: Start isDeterministic. Operand 991 states and 1447 transitions. [2024-11-08 00:34:55,984 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:34:55,984 INFO L218 hiAutomatonCegarLoop]: Abstraction has 991 states and 1447 transitions. [2024-11-08 00:34:55,985 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 991 states and 1447 transitions. [2024-11-08 00:34:55,999 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 991 to 991. [2024-11-08 00:34:56,001 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 991 states, 991 states have (on average 1.4601412714429869) internal successors, (1447), 990 states have internal predecessors, (1447), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:34:56,005 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 991 states to 991 states and 1447 transitions. [2024-11-08 00:34:56,005 INFO L240 hiAutomatonCegarLoop]: Abstraction has 991 states and 1447 transitions. [2024-11-08 00:34:56,005 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:34:56,007 INFO L425 stractBuchiCegarLoop]: Abstraction has 991 states and 1447 transitions. [2024-11-08 00:34:56,007 INFO L332 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-11-08 00:34:56,007 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 991 states and 1447 transitions. [2024-11-08 00:34:56,012 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 912 [2024-11-08 00:34:56,013 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:34:56,013 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:34:56,014 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:56,014 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:56,015 INFO L745 eck$LassoCheckResult]: Stem: 9508#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 9509#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 9612#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9613#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9598#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 9599#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9449#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9450#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9427#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9428#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 9677#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9532#L611 assume !(0 == ~M_E~0); 9533#L611-2 assume !(0 == ~T1_E~0); 9691#L616-1 assume !(0 == ~T2_E~0); 9692#L621-1 assume !(0 == ~T3_E~0); 9298#L626-1 assume !(0 == ~T4_E~0); 9299#L631-1 assume !(0 == ~T5_E~0); 9488#L636-1 assume !(0 == ~E_M~0); 9347#L641-1 assume !(0 == ~E_1~0); 9348#L646-1 assume !(0 == ~E_2~0); 9506#L651-1 assume !(0 == ~E_3~0); 9730#L656-1 assume !(0 == ~E_4~0); 9675#L661-1 assume !(0 == ~E_5~0); 9676#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9709#L304 assume !(1 == ~m_pc~0); 9373#L304-2 is_master_triggered_~__retres1~0#1 := 0; 9269#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9270#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 9220#L755 assume !(0 != activate_threads_~tmp~1#1); 9221#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9175#L323 assume 1 == ~t1_pc~0; 9176#L324 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9239#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9240#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9255#L763 assume !(0 != activate_threads_~tmp___0~0#1); 9756#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9242#L342 assume !(1 == ~t2_pc~0); 9244#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 9379#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9380#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9614#L771 assume !(0 != activate_threads_~tmp___1~0#1); 9671#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9567#L361 assume !(1 == ~t3_pc~0); 9568#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 9592#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9193#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9194#L779 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9258#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9259#L380 assume 1 == ~t4_pc~0; 9316#L381 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9317#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9342#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9343#L787 assume !(0 != activate_threads_~tmp___3~0#1); 9601#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9319#L399 assume !(1 == ~t5_pc~0); 9320#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 9459#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9464#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9451#L795 assume !(0 != activate_threads_~tmp___4~0#1); 9452#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9741#L679 assume !(1 == ~M_E~0); 9530#L679-2 assume !(1 == ~T1_E~0); 9392#L684-1 assume !(1 == ~T2_E~0); 9393#L689-1 assume !(1 == ~T3_E~0); 9575#L694-1 assume !(1 == ~T4_E~0); 9573#L699-1 assume !(1 == ~T5_E~0); 9574#L704-1 assume !(1 == ~E_M~0); 9556#L709-1 assume 1 == ~E_1~0;~E_1~0 := 2; 9492#L714-1 assume !(1 == ~E_2~0); 9493#L719-1 assume !(1 == ~E_3~0); 9665#L724-1 assume !(1 == ~E_4~0); 9280#L729-1 assume !(1 == ~E_5~0); 9281#L734-1 assume { :end_inline_reset_delta_events } true; 9635#L940-2 [2024-11-08 00:34:56,015 INFO L747 eck$LassoCheckResult]: Loop: 9635#L940-2 assume !false; 9704#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9355#L586-1 assume !false; 9732#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 9736#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 9570#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 9571#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 9766#L511 assume !(0 != eval_~tmp~0#1); 9358#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9359#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9628#L611-3 assume !(0 == ~M_E~0); 9282#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9283#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9278#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9227#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9228#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9229#L636-3 assume 0 == ~E_M~0;~E_M~0 := 1; 9230#L641-3 assume !(0 == ~E_1~0); 9292#L646-3 assume !(0 == ~E_2~0); 9306#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9307#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 9550#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9757#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9456#L304-21 assume 1 == ~m_pc~0; 9457#L305-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 9310#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9386#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 9387#L755-21 assume !(0 != activate_threads_~tmp~1#1); 9517#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9552#L323-21 assume 1 == ~t1_pc~0; 9190#L324-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9191#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9329#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9330#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 9705#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9722#L342-21 assume !(1 == ~t2_pc~0); 9217#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 9596#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9528#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9529#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9322#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9323#L361-21 assume 1 == ~t3_pc~0; 9748#L362-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9743#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9749#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9491#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9225#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9226#L380-21 assume 1 == ~t4_pc~0; 9728#L381-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9289#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9363#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9664#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9602#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9437#L399-21 assume !(1 == ~t5_pc~0); 9296#L399-23 is_transmit5_triggered_~__retres1~5#1 := 0; 9297#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9618#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10041#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 9735#L795-23 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9218#L679-3 assume !(1 == ~M_E~0); 9219#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10080#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 10079#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10078#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10077#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 10076#L704-3 assume !(1 == ~E_M~0); 10075#L709-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10074#L714-3 assume !(1 == ~E_2~0); 10073#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10072#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10071#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 10070#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 10057#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 10053#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 10052#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 10051#L959 assume !(0 == start_simulation_~tmp~3#1); 10049#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 10045#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 10042#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 9253#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 9254#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9411#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9412#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 9634#L972 assume !(0 != start_simulation_~tmp___0~1#1); 9635#L940-2 [2024-11-08 00:34:56,015 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:34:56,015 INFO L85 PathProgramCache]: Analyzing trace with hash -820631741, now seen corresponding path program 1 times [2024-11-08 00:34:56,016 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:34:56,016 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1592417162] [2024-11-08 00:34:56,016 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:34:56,016 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:34:56,026 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:34:56,081 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:34:56,082 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:34:56,082 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1592417162] [2024-11-08 00:34:56,082 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1592417162] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:34:56,082 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:34:56,082 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-08 00:34:56,082 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2073089198] [2024-11-08 00:34:56,082 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:34:56,083 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:34:56,083 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:34:56,083 INFO L85 PathProgramCache]: Analyzing trace with hash 740528630, now seen corresponding path program 1 times [2024-11-08 00:34:56,083 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:34:56,083 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1473978791] [2024-11-08 00:34:56,083 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:34:56,083 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:34:56,096 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:34:56,129 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:34:56,130 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:34:56,130 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1473978791] [2024-11-08 00:34:56,130 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1473978791] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:34:56,130 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:34:56,132 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:34:56,132 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2143926027] [2024-11-08 00:34:56,132 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:34:56,132 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:34:56,132 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:34:56,133 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:34:56,133 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:34:56,133 INFO L87 Difference]: Start difference. First operand 991 states and 1447 transitions. cyclomatic complexity: 457 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 2 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:34:56,198 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:34:56,199 INFO L93 Difference]: Finished difference Result 1799 states and 2607 transitions. [2024-11-08 00:34:56,199 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1799 states and 2607 transitions. [2024-11-08 00:34:56,210 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1717 [2024-11-08 00:34:56,220 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1799 states to 1799 states and 2607 transitions. [2024-11-08 00:34:56,220 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1799 [2024-11-08 00:34:56,222 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1799 [2024-11-08 00:34:56,222 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1799 states and 2607 transitions. [2024-11-08 00:34:56,225 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:34:56,226 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1799 states and 2607 transitions. [2024-11-08 00:34:56,229 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1799 states and 2607 transitions. [2024-11-08 00:34:56,253 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1799 to 1795. [2024-11-08 00:34:56,256 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1795 states, 1795 states have (on average 1.4501392757660168) internal successors, (2603), 1794 states have internal predecessors, (2603), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:34:56,262 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1795 states to 1795 states and 2603 transitions. [2024-11-08 00:34:56,263 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1795 states and 2603 transitions. [2024-11-08 00:34:56,263 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:34:56,266 INFO L425 stractBuchiCegarLoop]: Abstraction has 1795 states and 2603 transitions. [2024-11-08 00:34:56,266 INFO L332 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-11-08 00:34:56,266 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1795 states and 2603 transitions. [2024-11-08 00:34:56,275 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1713 [2024-11-08 00:34:56,276 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:34:56,276 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:34:56,277 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:56,277 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:56,277 INFO L745 eck$LassoCheckResult]: Stem: 12314#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 12315#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 12424#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12425#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12410#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 12411#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12253#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12254#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12230#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 12231#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 12501#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12341#L611 assume !(0 == ~M_E~0); 12342#L611-2 assume !(0 == ~T1_E~0); 12519#L616-1 assume !(0 == ~T2_E~0); 12520#L621-1 assume !(0 == ~T3_E~0); 12090#L626-1 assume !(0 == ~T4_E~0); 12091#L631-1 assume !(0 == ~T5_E~0); 12293#L636-1 assume !(0 == ~E_M~0); 12145#L641-1 assume !(0 == ~E_1~0); 12146#L646-1 assume !(0 == ~E_2~0); 12311#L651-1 assume !(0 == ~E_3~0); 12568#L656-1 assume !(0 == ~E_4~0); 12499#L661-1 assume !(0 == ~E_5~0); 12500#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12541#L304 assume !(1 == ~m_pc~0); 12172#L304-2 is_master_triggered_~__retres1~0#1 := 0; 12066#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12067#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 12016#L755 assume !(0 != activate_threads_~tmp~1#1); 12017#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11972#L323 assume !(1 == ~t1_pc~0); 11973#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 12035#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12036#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 12051#L763 assume !(0 != activate_threads_~tmp___0~0#1); 12606#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12038#L342 assume !(1 == ~t2_pc~0); 12040#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 12178#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12179#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 12427#L771 assume !(0 != activate_threads_~tmp___1~0#1); 12492#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12377#L361 assume !(1 == ~t3_pc~0); 12378#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 12404#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11989#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 11990#L779 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12054#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12055#L380 assume 1 == ~t4_pc~0; 12114#L381 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12115#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12140#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12141#L787 assume !(0 != activate_threads_~tmp___3~0#1); 12413#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12117#L399 assume !(1 == ~t5_pc~0); 12118#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 12263#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12269#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12255#L795 assume !(0 != activate_threads_~tmp___4~0#1); 12256#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12580#L679 assume !(1 == ~M_E~0); 12339#L679-2 assume !(1 == ~T1_E~0); 12191#L684-1 assume !(1 == ~T2_E~0); 12192#L689-1 assume !(1 == ~T3_E~0); 12385#L694-1 assume !(1 == ~T4_E~0); 12383#L699-1 assume !(1 == ~T5_E~0); 12384#L704-1 assume !(1 == ~E_M~0); 12365#L709-1 assume 1 == ~E_1~0;~E_1~0 := 2; 12297#L714-1 assume !(1 == ~E_2~0); 12298#L719-1 assume !(1 == ~E_3~0); 12487#L724-1 assume !(1 == ~E_4~0); 12078#L729-1 assume !(1 == ~E_5~0); 12079#L734-1 assume { :end_inline_reset_delta_events } true; 12585#L940-2 [2024-11-08 00:34:56,277 INFO L747 eck$LassoCheckResult]: Loop: 12585#L940-2 assume !false; 12876#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12682#L586-1 assume !false; 12683#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 12669#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 12667#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 12661#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 12662#L511 assume !(0 != eval_~tmp~0#1); 13373#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12546#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12448#L611-3 assume !(0 == ~M_E~0); 12080#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12081#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 12075#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 12023#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 12024#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 12025#L636-3 assume 0 == ~E_M~0;~E_M~0 := 1; 12026#L641-3 assume !(0 == ~E_1~0); 12092#L646-3 assume !(0 == ~E_2~0); 12104#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12105#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12358#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 12608#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12260#L304-21 assume 1 == ~m_pc~0; 12261#L305-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 12108#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12185#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 12186#L755-21 assume !(0 != activate_threads_~tmp~1#1); 12323#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12361#L323-21 assume !(1 == ~t1_pc~0); 12508#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 12509#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12127#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 12128#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12538#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12553#L342-21 assume !(1 == ~t2_pc~0); 12013#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 12408#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12337#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 12338#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12120#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12121#L361-21 assume 1 == ~t3_pc~0; 12593#L362-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12582#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12595#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12296#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12021#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12022#L380-21 assume 1 == ~t4_pc~0; 12560#L381-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12087#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12162#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12486#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12414#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12240#L399-21 assume !(1 == ~t5_pc~0); 12096#L399-23 is_transmit5_triggered_~__retres1~5#1 := 0; 12097#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12402#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12403#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 12573#L795-23 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12014#L679-3 assume !(1 == ~M_E~0); 12015#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13564#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 13563#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 13562#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 13561#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 13560#L704-3 assume !(1 == ~E_M~0); 13559#L709-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13558#L714-3 assume !(1 == ~E_2~0); 13557#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 13556#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 13555#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 13554#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 13550#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 13547#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 13546#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 13545#L959 assume !(0 == start_simulation_~tmp~3#1); 13543#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 12898#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 12894#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 12892#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 12890#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12885#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12881#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 12882#L972 assume !(0 != start_simulation_~tmp___0~1#1); 12585#L940-2 [2024-11-08 00:34:56,278 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:34:56,278 INFO L85 PathProgramCache]: Analyzing trace with hash 1077898564, now seen corresponding path program 1 times [2024-11-08 00:34:56,278 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:34:56,278 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [991358368] [2024-11-08 00:34:56,278 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:34:56,278 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:34:56,288 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:34:56,342 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:34:56,343 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:34:56,343 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [991358368] [2024-11-08 00:34:56,343 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [991358368] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:34:56,343 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:34:56,343 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-08 00:34:56,343 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1118337301] [2024-11-08 00:34:56,343 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:34:56,344 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:34:56,344 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:34:56,344 INFO L85 PathProgramCache]: Analyzing trace with hash -367600009, now seen corresponding path program 1 times [2024-11-08 00:34:56,345 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:34:56,345 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1842162879] [2024-11-08 00:34:56,345 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:34:56,345 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:34:56,360 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:34:56,385 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:34:56,385 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:34:56,385 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1842162879] [2024-11-08 00:34:56,385 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1842162879] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:34:56,385 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:34:56,385 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:34:56,385 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [171370707] [2024-11-08 00:34:56,385 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:34:56,386 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:34:56,386 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:34:56,386 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-08 00:34:56,386 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-08 00:34:56,387 INFO L87 Difference]: Start difference. First operand 1795 states and 2603 transitions. cyclomatic complexity: 810 Second operand has 5 states, 5 states have (on average 14.6) internal successors, (73), 5 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:34:56,576 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:34:56,576 INFO L93 Difference]: Finished difference Result 1882 states and 2690 transitions. [2024-11-08 00:34:56,576 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1882 states and 2690 transitions. [2024-11-08 00:34:56,625 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1797 [2024-11-08 00:34:56,635 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1882 states to 1882 states and 2690 transitions. [2024-11-08 00:34:56,636 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1882 [2024-11-08 00:34:56,637 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1882 [2024-11-08 00:34:56,637 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1882 states and 2690 transitions. [2024-11-08 00:34:56,640 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:34:56,640 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1882 states and 2690 transitions. [2024-11-08 00:34:56,642 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1882 states and 2690 transitions. [2024-11-08 00:34:56,671 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1882 to 1882. [2024-11-08 00:34:56,674 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1882 states, 1882 states have (on average 1.4293304994686504) internal successors, (2690), 1881 states have internal predecessors, (2690), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:34:56,681 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1882 states to 1882 states and 2690 transitions. [2024-11-08 00:34:56,681 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1882 states and 2690 transitions. [2024-11-08 00:34:56,682 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-08 00:34:56,682 INFO L425 stractBuchiCegarLoop]: Abstraction has 1882 states and 2690 transitions. [2024-11-08 00:34:56,682 INFO L332 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-11-08 00:34:56,682 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1882 states and 2690 transitions. [2024-11-08 00:34:56,694 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1797 [2024-11-08 00:34:56,694 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:34:56,694 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:34:56,695 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:56,695 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:56,696 INFO L745 eck$LassoCheckResult]: Stem: 16009#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 16010#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 16128#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16129#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16114#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 16115#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 15941#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15942#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15919#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 15920#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 16200#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16034#L611 assume !(0 == ~M_E~0); 16035#L611-2 assume !(0 == ~T1_E~0); 16216#L616-1 assume !(0 == ~T2_E~0); 16217#L621-1 assume !(0 == ~T3_E~0); 15779#L626-1 assume !(0 == ~T4_E~0); 15780#L631-1 assume !(0 == ~T5_E~0); 15985#L636-1 assume !(0 == ~E_M~0); 15836#L641-1 assume !(0 == ~E_1~0); 15837#L646-1 assume !(0 == ~E_2~0); 16004#L651-1 assume !(0 == ~E_3~0); 16267#L656-1 assume !(0 == ~E_4~0); 16198#L661-1 assume !(0 == ~E_5~0); 16199#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16238#L304 assume !(1 == ~m_pc~0); 15862#L304-2 is_master_triggered_~__retres1~0#1 := 0; 15756#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15757#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 15702#L755 assume !(0 != activate_threads_~tmp~1#1); 15703#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15658#L323 assume !(1 == ~t1_pc~0); 15659#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 15721#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15722#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 15738#L763 assume !(0 != activate_threads_~tmp___0~0#1); 16308#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15725#L342 assume !(1 == ~t2_pc~0); 15727#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 15868#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15869#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 16131#L771 assume !(0 != activate_threads_~tmp___1~0#1); 16191#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16074#L361 assume !(1 == ~t3_pc~0); 16075#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 16105#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15675#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 15676#L779 assume !(0 != activate_threads_~tmp___2~0#1); 15741#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15742#L380 assume 1 == ~t4_pc~0; 15804#L381 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 15805#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15831#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15832#L787 assume !(0 != activate_threads_~tmp___3~0#1); 16117#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15807#L399 assume !(1 == ~t5_pc~0); 15808#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 15951#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15961#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 15943#L795 assume !(0 != activate_threads_~tmp___4~0#1); 15944#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16279#L679 assume !(1 == ~M_E~0); 16032#L679-2 assume !(1 == ~T1_E~0); 15882#L684-1 assume !(1 == ~T2_E~0); 15883#L689-1 assume !(1 == ~T3_E~0); 16084#L694-1 assume !(1 == ~T4_E~0); 16082#L699-1 assume !(1 == ~T5_E~0); 16083#L704-1 assume !(1 == ~E_M~0); 16060#L709-1 assume 1 == ~E_1~0;~E_1~0 := 2; 15990#L714-1 assume !(1 == ~E_2~0); 15991#L719-1 assume !(1 == ~E_3~0); 16183#L724-1 assume !(1 == ~E_4~0); 15767#L729-1 assume !(1 == ~E_5~0); 15768#L734-1 assume { :end_inline_reset_delta_events } true; 16284#L940-2 [2024-11-08 00:34:56,696 INFO L747 eck$LassoCheckResult]: Loop: 16284#L940-2 assume !false; 16829#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16828#L586-1 assume !false; 16827#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 16430#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 16428#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 16370#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 16371#L511 assume !(0 != eval_~tmp~0#1); 16812#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 16811#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 16145#L611-3 assume !(0 == ~M_E~0); 15769#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 15770#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 15765#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 15709#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 15710#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 15711#L636-3 assume 0 == ~E_M~0;~E_M~0 := 1; 15712#L641-3 assume !(0 == ~E_1~0); 17525#L646-3 assume !(0 == ~E_2~0); 17524#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 17523#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 17513#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 16411#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16406#L304-21 assume 1 == ~m_pc~0; 16400#L305-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 16395#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16390#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 16386#L755-21 assume !(0 != activate_threads_~tmp~1#1); 16054#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16055#L323-21 assume !(1 == ~t1_pc~0); 16207#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 16208#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15817#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 15818#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 16253#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16254#L342-21 assume !(1 == ~t2_pc~0); 15699#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 16109#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16030#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 16031#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 15810#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15811#L361-21 assume 1 == ~t3_pc~0; 16295#L362-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 16317#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17490#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 17489#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 15707#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15708#L380-21 assume 1 == ~t4_pc~0; 16261#L381-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 15776#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15852#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 16182#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 16118#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15928#L399-21 assume 1 == ~t5_pc~0; 15904#L400-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15787#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16103#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 16104#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 16273#L795-23 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15700#L679-3 assume !(1 == ~M_E~0); 15701#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15999#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15650#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15651#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15690#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 15691#L704-3 assume !(1 == ~E_M~0); 16150#L709-3 assume 1 == ~E_1~0;~E_1~0 := 2; 16138#L714-3 assume !(1 == ~E_2~0); 15956#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 15957#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 16125#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 16126#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 15718#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 15719#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 16053#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 16359#L959 assume !(0 == start_simulation_~tmp~3#1); 17366#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 17349#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 17346#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 17345#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 17344#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 17343#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 17342#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 17341#L972 assume !(0 != start_simulation_~tmp___0~1#1); 16284#L940-2 [2024-11-08 00:34:56,696 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:34:56,697 INFO L85 PathProgramCache]: Analyzing trace with hash -1293840698, now seen corresponding path program 1 times [2024-11-08 00:34:56,697 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:34:56,697 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [581811273] [2024-11-08 00:34:56,697 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:34:56,697 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:34:56,706 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:34:56,745 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:34:56,746 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:34:56,746 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [581811273] [2024-11-08 00:34:56,746 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [581811273] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:34:56,746 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:34:56,746 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-08 00:34:56,746 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2101444340] [2024-11-08 00:34:56,746 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:34:56,747 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:34:56,747 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:34:56,748 INFO L85 PathProgramCache]: Analyzing trace with hash 1403870966, now seen corresponding path program 1 times [2024-11-08 00:34:56,748 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:34:56,748 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [611256885] [2024-11-08 00:34:56,748 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:34:56,748 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:34:56,757 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:34:56,783 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:34:56,783 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:34:56,783 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [611256885] [2024-11-08 00:34:56,783 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [611256885] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:34:56,783 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:34:56,783 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:34:56,784 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [361737017] [2024-11-08 00:34:56,784 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:34:56,784 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:34:56,784 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:34:56,785 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:34:56,785 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:34:56,785 INFO L87 Difference]: Start difference. First operand 1882 states and 2690 transitions. cyclomatic complexity: 810 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 2 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:34:56,875 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:34:56,875 INFO L93 Difference]: Finished difference Result 3468 states and 4930 transitions. [2024-11-08 00:34:56,875 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3468 states and 4930 transitions. [2024-11-08 00:34:56,902 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3372 [2024-11-08 00:34:56,921 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3468 states to 3468 states and 4930 transitions. [2024-11-08 00:34:56,922 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3468 [2024-11-08 00:34:56,925 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3468 [2024-11-08 00:34:56,926 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3468 states and 4930 transitions. [2024-11-08 00:34:56,932 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:34:56,932 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3468 states and 4930 transitions. [2024-11-08 00:34:56,935 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3468 states and 4930 transitions. [2024-11-08 00:34:57,034 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3468 to 3460. [2024-11-08 00:34:57,040 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3460 states, 3460 states have (on average 1.4225433526011562) internal successors, (4922), 3459 states have internal predecessors, (4922), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:34:57,054 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3460 states to 3460 states and 4922 transitions. [2024-11-08 00:34:57,054 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3460 states and 4922 transitions. [2024-11-08 00:34:57,055 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:34:57,055 INFO L425 stractBuchiCegarLoop]: Abstraction has 3460 states and 4922 transitions. [2024-11-08 00:34:57,055 INFO L332 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-11-08 00:34:57,055 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3460 states and 4922 transitions. [2024-11-08 00:34:57,074 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3364 [2024-11-08 00:34:57,074 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:34:57,074 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:34:57,076 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:57,077 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:57,077 INFO L745 eck$LassoCheckResult]: Stem: 21352#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 21353#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 21459#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 21460#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21446#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 21447#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21287#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21288#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21265#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 21266#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 21527#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 21376#L611 assume !(0 == ~M_E~0); 21377#L611-2 assume !(0 == ~T1_E~0); 21542#L616-1 assume !(0 == ~T2_E~0); 21543#L621-1 assume !(0 == ~T3_E~0); 21131#L626-1 assume !(0 == ~T4_E~0); 21132#L631-1 assume !(0 == ~T5_E~0); 21328#L636-1 assume !(0 == ~E_M~0); 21184#L641-1 assume !(0 == ~E_1~0); 21185#L646-1 assume !(0 == ~E_2~0); 21348#L651-1 assume !(0 == ~E_3~0); 21588#L656-1 assume !(0 == ~E_4~0); 21525#L661-1 assume !(0 == ~E_5~0); 21526#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21559#L304 assume !(1 == ~m_pc~0); 21210#L304-2 is_master_triggered_~__retres1~0#1 := 0; 21108#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21109#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 21059#L755 assume !(0 != activate_threads_~tmp~1#1); 21060#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21015#L323 assume !(1 == ~t1_pc~0); 21016#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 21077#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21078#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 21094#L763 assume !(0 != activate_threads_~tmp___0~0#1); 21620#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21081#L342 assume !(1 == ~t2_pc~0); 21083#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 21216#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21217#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 21462#L771 assume !(0 != activate_threads_~tmp___1~0#1); 21521#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21413#L361 assume !(1 == ~t3_pc~0); 21414#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 21439#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21032#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 21033#L779 assume !(0 != activate_threads_~tmp___2~0#1); 21097#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21098#L380 assume !(1 == ~t4_pc~0); 21412#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 21535#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21177#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 21178#L787 assume !(0 != activate_threads_~tmp___3~0#1); 21448#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 21155#L399 assume !(1 == ~t5_pc~0); 21156#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 21297#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21303#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 21289#L795 assume !(0 != activate_threads_~tmp___4~0#1); 21290#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21598#L679 assume !(1 == ~M_E~0); 21374#L679-2 assume !(1 == ~T1_E~0); 21229#L684-1 assume !(1 == ~T2_E~0); 21230#L689-1 assume !(1 == ~T3_E~0); 21421#L694-1 assume !(1 == ~T4_E~0); 21419#L699-1 assume !(1 == ~T5_E~0); 21420#L704-1 assume !(1 == ~E_M~0); 21401#L709-1 assume 1 == ~E_1~0;~E_1~0 := 2; 21333#L714-1 assume !(1 == ~E_2~0); 21334#L719-1 assume !(1 == ~E_3~0); 21517#L724-1 assume !(1 == ~E_4~0); 21119#L729-1 assume !(1 == ~E_5~0); 21120#L734-1 assume { :end_inline_reset_delta_events } true; 21602#L940-2 [2024-11-08 00:34:57,077 INFO L747 eck$LassoCheckResult]: Loop: 21602#L940-2 assume !false; 23355#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 23353#L586-1 assume !false; 23351#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 23333#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 23326#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 23321#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 23313#L511 assume !(0 != eval_~tmp~0#1); 23314#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 23796#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 23794#L611-3 assume !(0 == ~M_E~0); 23791#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 23789#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 23787#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 23785#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 23783#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 23779#L636-3 assume 0 == ~E_M~0;~E_M~0 := 1; 23777#L641-3 assume !(0 == ~E_1~0); 23775#L646-3 assume !(0 == ~E_2~0); 23774#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 23773#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 23755#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 23747#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 23740#L304-21 assume 1 == ~m_pc~0; 23732#L305-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 23727#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 23725#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 23723#L755-21 assume !(0 != activate_threads_~tmp~1#1); 23716#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23714#L323-21 assume !(1 == ~t1_pc~0); 23712#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 23709#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23707#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 23705#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 23703#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23701#L342-21 assume !(1 == ~t2_pc~0); 23698#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 23696#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23693#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 23691#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 23689#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 23687#L361-21 assume 1 == ~t3_pc~0; 23684#L362-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 23681#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23678#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 23675#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 23673#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23671#L380-21 assume !(1 == ~t4_pc~0); 23668#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 23666#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 23664#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 23661#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 23658#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 23655#L399-21 assume 1 == ~t5_pc~0; 23651#L400-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 23591#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 23587#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 23585#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 23583#L795-23 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 23581#L679-3 assume !(1 == ~M_E~0); 23577#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 23575#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 23573#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 23571#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 23569#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 23560#L704-3 assume !(1 == ~E_M~0); 23557#L709-3 assume 1 == ~E_1~0;~E_1~0 := 2; 23553#L714-3 assume !(1 == ~E_2~0); 23549#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 23543#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 23539#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 23537#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 23501#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 23494#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 23489#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 23482#L959 assume !(0 == start_simulation_~tmp~3#1); 23477#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 23426#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 23418#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 23412#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 23406#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 23400#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 23394#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 23390#L972 assume !(0 != start_simulation_~tmp___0~1#1); 21602#L940-2 [2024-11-08 00:34:57,078 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:34:57,078 INFO L85 PathProgramCache]: Analyzing trace with hash 943522567, now seen corresponding path program 1 times [2024-11-08 00:34:57,078 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:34:57,078 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1661802488] [2024-11-08 00:34:57,078 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:34:57,078 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:34:57,090 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:34:57,155 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:34:57,155 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:34:57,155 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1661802488] [2024-11-08 00:34:57,156 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1661802488] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:34:57,156 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:34:57,156 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:34:57,156 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1289221269] [2024-11-08 00:34:57,156 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:34:57,156 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:34:57,156 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:34:57,157 INFO L85 PathProgramCache]: Analyzing trace with hash -1765836361, now seen corresponding path program 1 times [2024-11-08 00:34:57,157 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:34:57,157 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [77646617] [2024-11-08 00:34:57,157 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:34:57,157 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:34:57,169 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:34:57,201 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:34:57,202 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:34:57,202 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [77646617] [2024-11-08 00:34:57,202 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [77646617] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:34:57,202 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:34:57,202 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:34:57,202 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1760264055] [2024-11-08 00:34:57,202 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:34:57,203 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:34:57,203 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:34:57,204 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-08 00:34:57,205 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-08 00:34:57,205 INFO L87 Difference]: Start difference. First operand 3460 states and 4922 transitions. cyclomatic complexity: 1466 Second operand has 4 states, 4 states have (on average 18.25) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:34:57,377 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:34:57,378 INFO L93 Difference]: Finished difference Result 5489 states and 7747 transitions. [2024-11-08 00:34:57,378 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5489 states and 7747 transitions. [2024-11-08 00:34:57,418 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5284 [2024-11-08 00:34:57,453 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5489 states to 5489 states and 7747 transitions. [2024-11-08 00:34:57,453 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5489 [2024-11-08 00:34:57,459 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5489 [2024-11-08 00:34:57,459 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5489 states and 7747 transitions. [2024-11-08 00:34:57,469 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:34:57,469 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5489 states and 7747 transitions. [2024-11-08 00:34:57,474 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5489 states and 7747 transitions. [2024-11-08 00:34:57,531 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5489 to 3972. [2024-11-08 00:34:57,539 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3972 states, 3972 states have (on average 1.4149043303121853) internal successors, (5620), 3971 states have internal predecessors, (5620), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:34:57,554 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3972 states to 3972 states and 5620 transitions. [2024-11-08 00:34:57,554 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3972 states and 5620 transitions. [2024-11-08 00:34:57,555 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-08 00:34:57,555 INFO L425 stractBuchiCegarLoop]: Abstraction has 3972 states and 5620 transitions. [2024-11-08 00:34:57,555 INFO L332 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-11-08 00:34:57,555 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3972 states and 5620 transitions. [2024-11-08 00:34:57,573 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3820 [2024-11-08 00:34:57,573 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:34:57,573 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:34:57,575 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:57,575 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:57,575 INFO L745 eck$LassoCheckResult]: Stem: 30312#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 30313#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 30423#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 30424#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 30408#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 30409#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 30249#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 30250#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 30227#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 30228#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 30490#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 30336#L611 assume !(0 == ~M_E~0); 30337#L611-2 assume !(0 == ~T1_E~0); 30508#L616-1 assume !(0 == ~T2_E~0); 30509#L621-1 assume !(0 == ~T3_E~0); 30098#L626-1 assume !(0 == ~T4_E~0); 30099#L631-1 assume !(0 == ~T5_E~0); 30294#L636-1 assume !(0 == ~E_M~0); 30146#L641-1 assume 0 == ~E_1~0;~E_1~0 := 1; 30147#L646-1 assume !(0 == ~E_2~0); 30583#L651-1 assume !(0 == ~E_3~0); 30584#L656-1 assume !(0 == ~E_4~0); 30664#L661-1 assume !(0 == ~E_5~0); 30663#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30598#L304 assume !(1 == ~m_pc~0); 30174#L304-2 is_master_triggered_~__retres1~0#1 := 0; 30067#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30068#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 30659#L755 assume !(0 != activate_threads_~tmp~1#1); 30614#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30615#L323 assume !(1 == ~t1_pc~0); 30658#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 30036#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30037#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 30051#L763 assume !(0 != activate_threads_~tmp___0~0#1); 30585#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30589#L342 assume !(1 == ~t2_pc~0); 30487#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 30176#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 30177#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 30599#L771 assume !(0 != activate_threads_~tmp___1~0#1); 30600#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30652#L361 assume !(1 == ~t3_pc~0); 30650#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 30648#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30645#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 30638#L779 assume !(0 != activate_threads_~tmp___2~0#1); 30637#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30636#L380 assume !(1 == ~t4_pc~0); 30604#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 30500#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30141#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 30142#L787 assume !(0 != activate_threads_~tmp___3~0#1); 30633#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 30116#L399 assume !(1 == ~t5_pc~0); 30117#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 30632#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30266#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 30267#L795 assume !(0 != activate_threads_~tmp___4~0#1); 30631#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30601#L679 assume !(1 == ~M_E~0); 30333#L679-2 assume !(1 == ~T1_E~0); 30189#L684-1 assume !(1 == ~T2_E~0); 30190#L689-1 assume !(1 == ~T3_E~0); 30383#L694-1 assume !(1 == ~T4_E~0); 30627#L699-1 assume !(1 == ~T5_E~0); 30626#L704-1 assume !(1 == ~E_M~0); 30625#L709-1 assume 1 == ~E_1~0;~E_1~0 := 2; 30295#L714-1 assume !(1 == ~E_2~0); 30296#L719-1 assume !(1 == ~E_3~0); 30476#L724-1 assume !(1 == ~E_4~0); 30078#L729-1 assume !(1 == ~E_5~0); 30079#L734-1 assume { :end_inline_reset_delta_events } true; 30568#L940-2 [2024-11-08 00:34:57,576 INFO L747 eck$LassoCheckResult]: Loop: 30568#L940-2 assume !false; 32034#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 32033#L586-1 assume !false; 32032#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 32028#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 32025#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 32019#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 32016#L511 assume !(0 != eval_~tmp~0#1); 32017#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 33055#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 33052#L611-3 assume !(0 == ~M_E~0); 33049#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 33047#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 33043#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 33040#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 33037#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 33034#L636-3 assume 0 == ~E_M~0;~E_M~0 := 1; 33030#L641-3 assume 0 == ~E_1~0;~E_1~0 := 1; 33029#L646-3 assume !(0 == ~E_2~0); 33028#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 33027#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 33026#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 33025#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33024#L304-21 assume 1 == ~m_pc~0; 33022#L305-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 33021#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33020#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 33019#L755-21 assume !(0 != activate_threads_~tmp~1#1); 33018#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33017#L323-21 assume !(1 == ~t1_pc~0); 33016#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 33015#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33014#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 33013#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 33012#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33011#L342-21 assume !(1 == ~t2_pc~0); 33009#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 33008#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33007#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 33006#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 33005#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33004#L361-21 assume 1 == ~t3_pc~0; 33002#L362-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 33000#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 32998#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 32996#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 32995#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 32994#L380-21 assume !(1 == ~t4_pc~0); 32993#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 32992#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 32991#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 32990#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 32989#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 32988#L399-21 assume 1 == ~t5_pc~0; 32986#L400-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 32985#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 32984#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 32983#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 32982#L795-23 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32981#L679-3 assume !(1 == ~M_E~0); 31446#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 32980#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 32979#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 32978#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 32977#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 32976#L704-3 assume !(1 == ~E_M~0); 32974#L709-3 assume 1 == ~E_1~0;~E_1~0 := 2; 32972#L714-3 assume !(1 == ~E_2~0); 32970#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 32967#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 32964#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 32804#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 30033#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 30034#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 30354#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 30395#L959 assume !(0 == start_simulation_~tmp~3#1); 30399#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 32171#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 32167#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 32165#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 32163#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 32161#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 32159#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 32157#L972 assume !(0 != start_simulation_~tmp___0~1#1); 30568#L940-2 [2024-11-08 00:34:57,576 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:34:57,576 INFO L85 PathProgramCache]: Analyzing trace with hash -443262843, now seen corresponding path program 1 times [2024-11-08 00:34:57,576 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:34:57,576 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2100750153] [2024-11-08 00:34:57,577 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:34:57,577 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:34:57,585 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:34:57,640 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:34:57,640 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:34:57,641 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2100750153] [2024-11-08 00:34:57,641 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2100750153] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:34:57,641 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:34:57,641 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:34:57,641 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [71214633] [2024-11-08 00:34:57,641 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:34:57,641 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:34:57,642 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:34:57,642 INFO L85 PathProgramCache]: Analyzing trace with hash -549682635, now seen corresponding path program 1 times [2024-11-08 00:34:57,642 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:34:57,642 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1921744705] [2024-11-08 00:34:57,642 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:34:57,642 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:34:57,653 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:34:57,677 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:34:57,678 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:34:57,678 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1921744705] [2024-11-08 00:34:57,678 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1921744705] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:34:57,678 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:34:57,678 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:34:57,678 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1695189172] [2024-11-08 00:34:57,678 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:34:57,678 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:34:57,679 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:34:57,679 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-08 00:34:57,679 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-08 00:34:57,679 INFO L87 Difference]: Start difference. First operand 3972 states and 5620 transitions. cyclomatic complexity: 1652 Second operand has 4 states, 4 states have (on average 18.25) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:34:57,773 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:34:57,773 INFO L93 Difference]: Finished difference Result 4826 states and 6797 transitions. [2024-11-08 00:34:57,773 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4826 states and 6797 transitions. [2024-11-08 00:34:57,795 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4682 [2024-11-08 00:34:57,823 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4826 states to 4826 states and 6797 transitions. [2024-11-08 00:34:57,824 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4826 [2024-11-08 00:34:57,829 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4826 [2024-11-08 00:34:57,829 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4826 states and 6797 transitions. [2024-11-08 00:34:57,837 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:34:57,837 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4826 states and 6797 transitions. [2024-11-08 00:34:57,842 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4826 states and 6797 transitions. [2024-11-08 00:34:57,887 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4826 to 3460. [2024-11-08 00:34:57,893 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3460 states, 3460 states have (on average 1.408092485549133) internal successors, (4872), 3459 states have internal predecessors, (4872), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:34:57,903 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3460 states to 3460 states and 4872 transitions. [2024-11-08 00:34:57,904 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3460 states and 4872 transitions. [2024-11-08 00:34:57,904 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-08 00:34:57,906 INFO L425 stractBuchiCegarLoop]: Abstraction has 3460 states and 4872 transitions. [2024-11-08 00:34:57,906 INFO L332 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-11-08 00:34:57,906 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3460 states and 4872 transitions. [2024-11-08 00:34:57,918 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3364 [2024-11-08 00:34:57,919 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:34:57,919 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:34:57,920 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:57,920 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:57,921 INFO L745 eck$LassoCheckResult]: Stem: 39116#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 39117#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 39223#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 39224#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 39211#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 39212#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 39056#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 39057#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 39032#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 39033#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 39285#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 39140#L611 assume !(0 == ~M_E~0); 39141#L611-2 assume !(0 == ~T1_E~0); 39299#L616-1 assume !(0 == ~T2_E~0); 39300#L621-1 assume !(0 == ~T3_E~0); 38898#L626-1 assume !(0 == ~T4_E~0); 38899#L631-1 assume !(0 == ~T5_E~0); 39094#L636-1 assume !(0 == ~E_M~0); 38949#L641-1 assume !(0 == ~E_1~0); 38950#L646-1 assume !(0 == ~E_2~0); 39113#L651-1 assume !(0 == ~E_3~0); 39346#L656-1 assume !(0 == ~E_4~0); 39283#L661-1 assume !(0 == ~E_5~0); 39284#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 39317#L304 assume !(1 == ~m_pc~0); 38975#L304-2 is_master_triggered_~__retres1~0#1 := 0; 38875#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 38876#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 38825#L755 assume !(0 != activate_threads_~tmp~1#1); 38826#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 38782#L323 assume !(1 == ~t1_pc~0); 38783#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 38844#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 38845#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 38861#L763 assume !(0 != activate_threads_~tmp___0~0#1); 39381#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38848#L342 assume !(1 == ~t2_pc~0); 38850#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 38981#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 38982#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 39225#L771 assume !(0 != activate_threads_~tmp___1~0#1); 39279#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 39176#L361 assume !(1 == ~t3_pc~0); 39177#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 39202#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38798#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 38799#L779 assume !(0 != activate_threads_~tmp___2~0#1); 38864#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 38865#L380 assume !(1 == ~t4_pc~0); 39175#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 39292#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 38944#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 38945#L787 assume !(0 != activate_threads_~tmp___3~0#1); 39213#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 38922#L399 assume !(1 == ~t5_pc~0); 38923#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 39066#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 39071#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 39058#L795 assume !(0 != activate_threads_~tmp___4~0#1); 39059#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 39359#L679 assume !(1 == ~M_E~0); 39138#L679-2 assume !(1 == ~T1_E~0); 38994#L684-1 assume !(1 == ~T2_E~0); 38995#L689-1 assume !(1 == ~T3_E~0); 39184#L694-1 assume !(1 == ~T4_E~0); 39182#L699-1 assume !(1 == ~T5_E~0); 39183#L704-1 assume !(1 == ~E_M~0); 39164#L709-1 assume !(1 == ~E_1~0); 39099#L714-1 assume !(1 == ~E_2~0); 39100#L719-1 assume !(1 == ~E_3~0); 39274#L724-1 assume !(1 == ~E_4~0); 38886#L729-1 assume !(1 == ~E_5~0); 38887#L734-1 assume { :end_inline_reset_delta_events } true; 39363#L940-2 [2024-11-08 00:34:57,921 INFO L747 eck$LassoCheckResult]: Loop: 39363#L940-2 assume !false; 40734#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 40732#L586-1 assume !false; 40730#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 40717#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 40713#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 40665#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 40663#L511 assume !(0 != eval_~tmp~0#1); 40664#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 40905#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 40902#L611-3 assume !(0 == ~M_E~0); 40900#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 40898#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 40896#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 40894#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 40892#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 40890#L636-3 assume 0 == ~E_M~0;~E_M~0 := 1; 40887#L641-3 assume !(0 == ~E_1~0); 40885#L646-3 assume !(0 == ~E_2~0); 40883#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 40880#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 40878#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 40876#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 40874#L304-21 assume 1 == ~m_pc~0; 40871#L305-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 40869#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 40867#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 40865#L755-21 assume !(0 != activate_threads_~tmp~1#1); 40863#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 40860#L323-21 assume !(1 == ~t1_pc~0); 40858#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 40856#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 40854#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 40852#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 40851#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 40850#L342-21 assume !(1 == ~t2_pc~0); 40845#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 40843#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 40841#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 40840#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 40839#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 40572#L361-21 assume !(1 == ~t3_pc~0); 40569#L361-23 is_transmit3_triggered_~__retres1~3#1 := 0; 40565#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 40563#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 40561#L779-21 assume !(0 != activate_threads_~tmp___2~0#1); 40559#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 40558#L380-21 assume !(1 == ~t4_pc~0); 40557#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 40517#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 40509#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 40501#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 40498#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 40497#L399-21 assume !(1 == ~t5_pc~0); 40496#L399-23 is_transmit5_triggered_~__retres1~5#1 := 0; 40494#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 40493#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 40491#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 40489#L795-23 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40487#L679-3 assume !(1 == ~M_E~0); 40300#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 40483#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 40481#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 40479#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 40477#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 40475#L704-3 assume !(1 == ~E_M~0); 40474#L709-3 assume !(1 == ~E_1~0); 40470#L714-3 assume !(1 == ~E_2~0); 40468#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 40466#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 40465#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 40462#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 40449#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 40400#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 40399#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 39445#L959 assume !(0 == start_simulation_~tmp~3#1); 39447#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 40823#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 40818#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 40816#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 40814#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 40812#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 40810#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 40808#L972 assume !(0 != start_simulation_~tmp___0~1#1); 39363#L940-2 [2024-11-08 00:34:57,921 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:34:57,922 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 1 times [2024-11-08 00:34:57,922 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:34:57,922 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [536446525] [2024-11-08 00:34:57,922 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:34:57,922 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:34:57,931 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:34:57,932 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 00:34:57,939 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:34:57,977 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 00:34:57,978 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:34:57,979 INFO L85 PathProgramCache]: Analyzing trace with hash -1183321607, now seen corresponding path program 1 times [2024-11-08 00:34:57,979 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:34:57,979 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2106605337] [2024-11-08 00:34:57,979 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:34:57,979 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:34:57,993 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:34:58,015 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:34:58,016 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:34:58,016 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2106605337] [2024-11-08 00:34:58,016 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2106605337] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:34:58,016 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:34:58,016 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:34:58,016 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1427665980] [2024-11-08 00:34:58,016 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:34:58,016 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:34:58,016 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:34:58,017 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:34:58,017 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:34:58,017 INFO L87 Difference]: Start difference. First operand 3460 states and 4872 transitions. cyclomatic complexity: 1416 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:34:58,107 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:34:58,107 INFO L93 Difference]: Finished difference Result 6232 states and 8688 transitions. [2024-11-08 00:34:58,108 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6232 states and 8688 transitions. [2024-11-08 00:34:58,166 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6064 [2024-11-08 00:34:58,190 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6232 states to 6232 states and 8688 transitions. [2024-11-08 00:34:58,191 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6232 [2024-11-08 00:34:58,196 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6232 [2024-11-08 00:34:58,197 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6232 states and 8688 transitions. [2024-11-08 00:34:58,208 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:34:58,208 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6232 states and 8688 transitions. [2024-11-08 00:34:58,214 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6232 states and 8688 transitions. [2024-11-08 00:34:58,297 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6232 to 6224. [2024-11-08 00:34:58,306 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6224 states, 6224 states have (on average 1.3946015424164524) internal successors, (8680), 6223 states have internal predecessors, (8680), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:34:58,328 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6224 states to 6224 states and 8680 transitions. [2024-11-08 00:34:58,328 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6224 states and 8680 transitions. [2024-11-08 00:34:58,328 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:34:58,329 INFO L425 stractBuchiCegarLoop]: Abstraction has 6224 states and 8680 transitions. [2024-11-08 00:34:58,329 INFO L332 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2024-11-08 00:34:58,329 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6224 states and 8680 transitions. [2024-11-08 00:34:58,353 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6056 [2024-11-08 00:34:58,354 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:34:58,354 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:34:58,355 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:58,355 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:58,355 INFO L745 eck$LassoCheckResult]: Stem: 48824#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 48825#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 48935#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 48936#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 48919#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 48920#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 48759#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 48760#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 48738#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 48739#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 48998#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 48849#L611 assume !(0 == ~M_E~0); 48850#L611-2 assume !(0 == ~T1_E~0); 49012#L616-1 assume !(0 == ~T2_E~0); 49013#L621-1 assume !(0 == ~T3_E~0); 48597#L626-1 assume !(0 == ~T4_E~0); 48598#L631-1 assume !(0 == ~T5_E~0); 48799#L636-1 assume 0 == ~E_M~0;~E_M~0 := 1; 48800#L641-1 assume !(0 == ~E_1~0); 48820#L646-1 assume !(0 == ~E_2~0); 48821#L651-1 assume !(0 == ~E_3~0); 49053#L656-1 assume !(0 == ~E_4~0); 49054#L661-1 assume !(0 == ~E_5~0); 49029#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 49030#L304 assume !(1 == ~m_pc~0); 48676#L304-2 is_master_triggered_~__retres1~0#1 := 0; 48677#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 48766#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 48523#L755 assume !(0 != activate_threads_~tmp~1#1); 48524#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 49153#L323 assume !(1 == ~t1_pc~0); 49152#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 48541#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 48542#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 49151#L763 assume !(0 != activate_threads_~tmp___0~0#1); 49149#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 48545#L342 assume !(1 == ~t2_pc~0); 48547#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 49146#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 48937#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 48938#L771 assume !(0 != activate_threads_~tmp___1~0#1); 48992#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 48885#L361 assume !(1 == ~t3_pc~0); 48886#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 48911#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 48496#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 48497#L779 assume !(0 != activate_threads_~tmp___2~0#1); 48563#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 48564#L380 assume !(1 == ~t4_pc~0); 48884#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 49134#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 49133#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 48922#L787 assume !(0 != activate_threads_~tmp___3~0#1); 48923#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 48621#L399 assume !(1 == ~t5_pc~0); 48622#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 48770#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 48775#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 48761#L795 assume !(0 != activate_threads_~tmp___4~0#1); 48762#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 49067#L679 assume !(1 == ~M_E~0); 49124#L679-2 assume !(1 == ~T1_E~0); 49123#L684-1 assume !(1 == ~T2_E~0); 49122#L689-1 assume !(1 == ~T3_E~0); 49107#L694-1 assume !(1 == ~T4_E~0); 48892#L699-1 assume !(1 == ~T5_E~0); 48893#L704-1 assume 1 == ~E_M~0;~E_M~0 := 2; 48872#L709-1 assume !(1 == ~E_1~0); 48805#L714-1 assume !(1 == ~E_2~0); 48806#L719-1 assume !(1 == ~E_3~0); 48987#L724-1 assume !(1 == ~E_4~0); 48585#L729-1 assume !(1 == ~E_5~0); 48586#L734-1 assume { :end_inline_reset_delta_events } true; 48960#L940-2 [2024-11-08 00:34:58,356 INFO L747 eck$LassoCheckResult]: Loop: 48960#L940-2 assume !false; 48977#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 48658#L586-1 assume !false; 49058#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 49062#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 48888#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 48889#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 48882#L511 assume !(0 != eval_~tmp~0#1); 48883#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 54687#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 54686#L611-3 assume !(0 == ~M_E~0); 54685#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 54684#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 54683#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 54606#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 54578#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 54576#L636-3 assume !(0 == ~E_M~0); 54577#L641-3 assume !(0 == ~E_1~0); 54588#L646-3 assume !(0 == ~E_2~0); 54587#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 54586#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 54585#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 54584#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 54583#L304-21 assume 1 == ~m_pc~0; 54560#L305-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 49095#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 54554#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 54552#L755-21 assume !(0 != activate_threads_~tmp~1#1); 54551#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 54550#L323-21 assume !(1 == ~t1_pc~0); 54549#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 54548#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 54547#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 54546#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 54545#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 54544#L342-21 assume !(1 == ~t2_pc~0); 54542#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 54541#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 54540#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 54539#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 54536#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 54535#L361-21 assume 1 == ~t3_pc~0; 54533#L362-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 54531#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 54529#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 54492#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 54491#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 54490#L380-21 assume !(1 == ~t4_pc~0); 54488#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 54487#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 49063#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 48986#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 48924#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 48747#L399-21 assume 1 == ~t5_pc~0; 48722#L400-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 48604#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 48909#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 48910#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 49061#L795-23 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 48521#L679-3 assume !(1 == ~M_E~0); 48522#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 48814#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 48472#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 48473#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 48511#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 48512#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 48958#L709-3 assume !(1 == ~E_1~0); 48944#L714-3 assume !(1 == ~E_2~0); 48772#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 48509#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 48510#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 48932#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 48538#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 48539#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 48866#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 48904#L959 assume !(0 == start_simulation_~tmp~3#1); 48908#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 48808#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 48809#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 48557#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 48558#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 48720#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 48721#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 48959#L972 assume !(0 != start_simulation_~tmp___0~1#1); 48960#L940-2 [2024-11-08 00:34:58,357 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:34:58,357 INFO L85 PathProgramCache]: Analyzing trace with hash -814901243, now seen corresponding path program 1 times [2024-11-08 00:34:58,357 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:34:58,357 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1995645219] [2024-11-08 00:34:58,357 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:34:58,357 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:34:58,372 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:34:58,413 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:34:58,414 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:34:58,414 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1995645219] [2024-11-08 00:34:58,414 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1995645219] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:34:58,414 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:34:58,414 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:34:58,414 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [34474547] [2024-11-08 00:34:58,414 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:34:58,415 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:34:58,415 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:34:58,415 INFO L85 PathProgramCache]: Analyzing trace with hash -1117097167, now seen corresponding path program 1 times [2024-11-08 00:34:58,415 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:34:58,415 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1526533670] [2024-11-08 00:34:58,415 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:34:58,416 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:34:58,427 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:34:58,476 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:34:58,476 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:34:58,477 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1526533670] [2024-11-08 00:34:58,479 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1526533670] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:34:58,479 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:34:58,479 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-08 00:34:58,479 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [192254880] [2024-11-08 00:34:58,479 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:34:58,479 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:34:58,479 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:34:58,480 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-08 00:34:58,480 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-08 00:34:58,480 INFO L87 Difference]: Start difference. First operand 6224 states and 8680 transitions. cyclomatic complexity: 2460 Second operand has 4 states, 4 states have (on average 18.25) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:34:58,611 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:34:58,611 INFO L93 Difference]: Finished difference Result 8837 states and 12305 transitions. [2024-11-08 00:34:58,611 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8837 states and 12305 transitions. [2024-11-08 00:34:58,696 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 8388 [2024-11-08 00:34:58,726 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8837 states to 8837 states and 12305 transitions. [2024-11-08 00:34:58,727 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8837 [2024-11-08 00:34:58,736 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8837 [2024-11-08 00:34:58,736 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8837 states and 12305 transitions. [2024-11-08 00:34:58,750 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:34:58,750 INFO L218 hiAutomatonCegarLoop]: Abstraction has 8837 states and 12305 transitions. [2024-11-08 00:34:58,759 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8837 states and 12305 transitions. [2024-11-08 00:34:58,822 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8837 to 6215. [2024-11-08 00:34:58,836 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6215 states, 6215 states have (on average 1.3930812550281577) internal successors, (8658), 6214 states have internal predecessors, (8658), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:34:58,862 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6215 states to 6215 states and 8658 transitions. [2024-11-08 00:34:58,862 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6215 states and 8658 transitions. [2024-11-08 00:34:58,862 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-08 00:34:58,863 INFO L425 stractBuchiCegarLoop]: Abstraction has 6215 states and 8658 transitions. [2024-11-08 00:34:58,863 INFO L332 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2024-11-08 00:34:58,863 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6215 states and 8658 transitions. [2024-11-08 00:34:58,883 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6056 [2024-11-08 00:34:58,883 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:34:58,883 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:34:58,885 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:58,885 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:58,885 INFO L745 eck$LassoCheckResult]: Stem: 63896#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 63897#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 64013#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 64014#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 63996#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 63997#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 63830#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 63831#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 63806#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 63807#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 64082#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 63922#L611 assume !(0 == ~M_E~0); 63923#L611-2 assume !(0 == ~T1_E~0); 64103#L616-1 assume !(0 == ~T2_E~0); 64104#L621-1 assume !(0 == ~T3_E~0); 63670#L626-1 assume !(0 == ~T4_E~0); 63671#L631-1 assume !(0 == ~T5_E~0); 63874#L636-1 assume !(0 == ~E_M~0); 63722#L641-1 assume !(0 == ~E_1~0); 63723#L646-1 assume !(0 == ~E_2~0); 63893#L651-1 assume !(0 == ~E_3~0); 64154#L656-1 assume !(0 == ~E_4~0); 64079#L661-1 assume !(0 == ~E_5~0); 64080#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 64121#L304 assume !(1 == ~m_pc~0); 63748#L304-2 is_master_triggered_~__retres1~0#1 := 0; 63647#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 63648#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 63596#L755 assume !(0 != activate_threads_~tmp~1#1); 63597#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 63553#L323 assume !(1 == ~t1_pc~0); 63554#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 63614#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 63615#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 64199#L763 assume !(0 != activate_threads_~tmp___0~0#1); 64200#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 63618#L342 assume !(1 == ~t2_pc~0); 63620#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 63756#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 63757#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 64215#L771 assume !(0 != activate_threads_~tmp___1~0#1); 64216#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 63962#L361 assume !(1 == ~t3_pc~0); 63963#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 64248#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 64249#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 64144#L779 assume !(0 != activate_threads_~tmp___2~0#1); 64145#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 63960#L380 assume !(1 == ~t4_pc~0); 63961#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 64093#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 64094#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 63999#L787 assume !(0 != activate_threads_~tmp___3~0#1); 64000#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 64212#L399 assume !(1 == ~t5_pc~0); 63842#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 63843#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 63848#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 63849#L795 assume !(0 != activate_threads_~tmp___4~0#1); 64168#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 64169#L679 assume !(1 == ~M_E~0); 63919#L679-2 assume !(1 == ~T1_E~0); 63920#L684-1 assume !(1 == ~T2_E~0); 64247#L689-1 assume !(1 == ~T3_E~0); 64226#L694-1 assume !(1 == ~T4_E~0); 63968#L699-1 assume !(1 == ~T5_E~0); 63969#L704-1 assume !(1 == ~E_M~0); 63946#L709-1 assume !(1 == ~E_1~0); 63879#L714-1 assume !(1 == ~E_2~0); 63880#L719-1 assume !(1 == ~E_3~0); 64065#L724-1 assume !(1 == ~E_4~0); 63658#L729-1 assume !(1 == ~E_5~0); 63659#L734-1 assume { :end_inline_reset_delta_events } true; 64179#L940-2 [2024-11-08 00:34:58,886 INFO L747 eck$LassoCheckResult]: Loop: 64179#L940-2 assume !false; 66430#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 66428#L586-1 assume !false; 66425#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 65895#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 65891#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 65889#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 65886#L511 assume !(0 != eval_~tmp~0#1); 65884#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 65882#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 65880#L611-3 assume !(0 == ~M_E~0); 65878#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 65876#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 65874#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 65872#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 65870#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 65868#L636-3 assume !(0 == ~E_M~0); 65865#L641-3 assume !(0 == ~E_1~0); 65864#L646-3 assume !(0 == ~E_2~0); 65862#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 65860#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 65858#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 65856#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 65847#L304-21 assume !(1 == ~m_pc~0); 65843#L304-23 is_master_triggered_~__retres1~0#1 := 0; 65841#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 65839#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 65836#L755-21 assume !(0 != activate_threads_~tmp~1#1); 65834#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 65832#L323-21 assume !(1 == ~t1_pc~0); 65830#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 65828#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 65826#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 65824#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 65821#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 65819#L342-21 assume !(1 == ~t2_pc~0); 65816#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 65815#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 65812#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 65810#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 65808#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 65806#L361-21 assume !(1 == ~t3_pc~0); 65802#L361-23 is_transmit3_triggered_~__retres1~3#1 := 0; 65796#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 65793#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 65791#L779-21 assume !(0 != activate_threads_~tmp___2~0#1); 65788#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 65786#L380-21 assume !(1 == ~t4_pc~0); 65784#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 65783#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 65780#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 65778#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 65776#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 65775#L399-21 assume 1 == ~t5_pc~0; 65773#L400-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 65770#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 65769#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 65113#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 65106#L795-23 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 64426#L679-3 assume !(1 == ~M_E~0); 64418#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 64412#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 64406#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 64400#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 64394#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 64390#L704-3 assume !(1 == ~E_M~0); 64387#L709-3 assume !(1 == ~E_1~0); 64384#L714-3 assume !(1 == ~E_2~0); 64381#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 64378#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 64376#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 64375#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 64364#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 64354#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 64352#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 64295#L959 assume !(0 == start_simulation_~tmp~3#1); 64297#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 66487#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 66482#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 66480#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 66478#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 66476#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 66474#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 66472#L972 assume !(0 != start_simulation_~tmp___0~1#1); 64179#L940-2 [2024-11-08 00:34:58,886 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:34:58,886 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 2 times [2024-11-08 00:34:58,887 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:34:58,887 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1260411340] [2024-11-08 00:34:58,887 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:34:58,887 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:34:58,896 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:34:58,897 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 00:34:58,905 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:34:58,915 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 00:34:58,916 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:34:58,916 INFO L85 PathProgramCache]: Analyzing trace with hash -1724345609, now seen corresponding path program 1 times [2024-11-08 00:34:58,916 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:34:58,916 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1340719148] [2024-11-08 00:34:58,917 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:34:58,917 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:34:58,926 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:34:58,972 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:34:58,972 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:34:58,972 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1340719148] [2024-11-08 00:34:58,972 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1340719148] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:34:58,972 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:34:58,972 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-08 00:34:58,972 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [316857507] [2024-11-08 00:34:58,973 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:34:58,973 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:34:58,973 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:34:58,973 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-08 00:34:58,973 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-08 00:34:58,974 INFO L87 Difference]: Start difference. First operand 6215 states and 8658 transitions. cyclomatic complexity: 2447 Second operand has 5 states, 5 states have (on average 16.8) internal successors, (84), 5 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:34:59,087 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:34:59,088 INFO L93 Difference]: Finished difference Result 6295 states and 8738 transitions. [2024-11-08 00:34:59,088 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6295 states and 8738 transitions. [2024-11-08 00:34:59,115 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6136 [2024-11-08 00:34:59,140 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6295 states to 6295 states and 8738 transitions. [2024-11-08 00:34:59,141 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6295 [2024-11-08 00:34:59,147 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6295 [2024-11-08 00:34:59,147 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6295 states and 8738 transitions. [2024-11-08 00:34:59,157 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:34:59,157 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6295 states and 8738 transitions. [2024-11-08 00:34:59,164 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6295 states and 8738 transitions. [2024-11-08 00:34:59,248 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6295 to 6263. [2024-11-08 00:34:59,258 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6263 states, 6263 states have (on average 1.3900686571930385) internal successors, (8706), 6262 states have internal predecessors, (8706), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:34:59,278 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6263 states to 6263 states and 8706 transitions. [2024-11-08 00:34:59,279 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6263 states and 8706 transitions. [2024-11-08 00:34:59,279 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-08 00:34:59,280 INFO L425 stractBuchiCegarLoop]: Abstraction has 6263 states and 8706 transitions. [2024-11-08 00:34:59,281 INFO L332 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2024-11-08 00:34:59,281 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6263 states and 8706 transitions. [2024-11-08 00:34:59,303 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6104 [2024-11-08 00:34:59,303 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:34:59,303 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:34:59,305 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:59,305 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:59,305 INFO L745 eck$LassoCheckResult]: Stem: 76427#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 76428#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 76558#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 76559#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 76541#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 76542#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 76359#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 76360#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 76335#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 76336#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 76663#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 76455#L611 assume !(0 == ~M_E~0); 76456#L611-2 assume !(0 == ~T1_E~0); 76684#L616-1 assume !(0 == ~T2_E~0); 76685#L621-1 assume !(0 == ~T3_E~0); 76191#L626-1 assume !(0 == ~T4_E~0); 76192#L631-1 assume !(0 == ~T5_E~0); 76401#L636-1 assume !(0 == ~E_M~0); 76245#L641-1 assume !(0 == ~E_1~0); 76246#L646-1 assume !(0 == ~E_2~0); 76421#L651-1 assume !(0 == ~E_3~0); 76753#L656-1 assume !(0 == ~E_4~0); 76661#L661-1 assume !(0 == ~E_5~0); 76662#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 76710#L304 assume !(1 == ~m_pc~0); 76272#L304-2 is_master_triggered_~__retres1~0#1 := 0; 76167#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 76168#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 76114#L755 assume !(0 != activate_threads_~tmp~1#1); 76115#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 76071#L323 assume !(1 == ~t1_pc~0); 76072#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 76132#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 76133#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 76813#L763 assume !(0 != activate_threads_~tmp___0~0#1); 76814#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 76136#L342 assume !(1 == ~t2_pc~0); 76138#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 76281#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 76282#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 76841#L771 assume !(0 != activate_threads_~tmp___1~0#1); 76842#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 76496#L361 assume !(1 == ~t3_pc~0); 76497#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 76778#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 76779#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 76744#L779 assume !(0 != activate_threads_~tmp___2~0#1); 76745#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 76494#L380 assume !(1 == ~t4_pc~0); 76495#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 76674#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 76675#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 76544#L787 assume !(0 != activate_threads_~tmp___3~0#1); 76545#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 76891#L399 assume !(1 == ~t5_pc~0); 76889#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 76888#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 76887#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 76886#L795 assume !(0 != activate_threads_~tmp___4~0#1); 76885#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 76843#L679 assume !(1 == ~M_E~0); 76453#L679-2 assume !(1 == ~T1_E~0); 76295#L684-1 assume !(1 == ~T2_E~0); 76296#L689-1 assume !(1 == ~T3_E~0); 76507#L694-1 assume !(1 == ~T4_E~0); 76881#L699-1 assume !(1 == ~T5_E~0); 76880#L704-1 assume !(1 == ~E_M~0); 76480#L709-1 assume !(1 == ~E_1~0); 76405#L714-1 assume !(1 == ~E_2~0); 76406#L719-1 assume !(1 == ~E_3~0); 76637#L724-1 assume !(1 == ~E_4~0); 76179#L729-1 assume !(1 == ~E_5~0); 76180#L734-1 assume { :end_inline_reset_delta_events } true; 76780#L940-2 [2024-11-08 00:34:59,306 INFO L747 eck$LassoCheckResult]: Loop: 76780#L940-2 assume !false; 79461#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 79371#L586-1 assume !false; 79457#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 79458#L464 assume !(0 == ~m_st~0); 81046#L468 assume !(0 == ~t1_st~0); 81048#L472 assume !(0 == ~t2_st~0); 81044#L476 assume !(0 == ~t3_st~0); 81045#L480 assume !(0 == ~t4_st~0); 81047#L484 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 81049#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 82287#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 82285#L511 assume !(0 != eval_~tmp~0#1); 82283#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 82280#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 82279#L611-3 assume !(0 == ~M_E~0); 82277#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 82275#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 82273#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 82271#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 82269#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 82267#L636-3 assume !(0 == ~E_M~0); 82265#L641-3 assume !(0 == ~E_1~0); 82263#L646-3 assume !(0 == ~E_2~0); 82261#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 82258#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 82256#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 82254#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 82252#L304-21 assume !(1 == ~m_pc~0); 82248#L304-23 is_master_triggered_~__retres1~0#1 := 0; 82247#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 82246#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 82245#L755-21 assume !(0 != activate_threads_~tmp~1#1); 82244#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 82243#L323-21 assume !(1 == ~t1_pc~0); 82234#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 82233#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 82231#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 82229#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 82227#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 82225#L342-21 assume !(1 == ~t2_pc~0); 82222#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 82220#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 82202#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 82197#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 82192#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 82187#L361-21 assume !(1 == ~t3_pc~0); 82183#L361-23 is_transmit3_triggered_~__retres1~3#1 := 0; 82178#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 82175#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 82116#L779-21 assume !(0 != activate_threads_~tmp___2~0#1); 82113#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 82111#L380-21 assume !(1 == ~t4_pc~0); 82109#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 82107#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 82105#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 82103#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 82101#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 82099#L399-21 assume !(1 == ~t5_pc~0); 82097#L399-23 is_transmit5_triggered_~__retres1~5#1 := 0; 82090#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 82084#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 82079#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 82074#L795-23 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 82068#L679-3 assume !(1 == ~M_E~0); 82063#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 82059#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 82055#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 82049#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 82044#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 82039#L704-3 assume !(1 == ~E_M~0); 82035#L709-3 assume !(1 == ~E_1~0); 82032#L714-3 assume !(1 == ~E_2~0); 82029#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 82026#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 82022#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 82019#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 82013#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 81838#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 81822#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 81821#L959 assume !(0 == start_simulation_~tmp~3#1); 81819#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 79563#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 79561#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 79553#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 79550#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 79547#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 79543#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 79544#L972 assume !(0 != start_simulation_~tmp___0~1#1); 76780#L940-2 [2024-11-08 00:34:59,306 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:34:59,306 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 3 times [2024-11-08 00:34:59,306 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:34:59,306 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1706137229] [2024-11-08 00:34:59,307 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:34:59,307 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:34:59,322 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:34:59,322 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 00:34:59,331 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:34:59,346 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 00:34:59,347 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:34:59,347 INFO L85 PathProgramCache]: Analyzing trace with hash 690042499, now seen corresponding path program 1 times [2024-11-08 00:34:59,347 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:34:59,347 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [442681372] [2024-11-08 00:34:59,347 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:34:59,347 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:34:59,360 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:34:59,396 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:34:59,397 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:34:59,397 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [442681372] [2024-11-08 00:34:59,397 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [442681372] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:34:59,397 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:34:59,397 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:34:59,397 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [491932772] [2024-11-08 00:34:59,397 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:34:59,398 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:34:59,398 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:34:59,398 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:34:59,398 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:34:59,398 INFO L87 Difference]: Start difference. First operand 6263 states and 8706 transitions. cyclomatic complexity: 2447 Second operand has 3 states, 3 states have (on average 29.666666666666668) internal successors, (89), 3 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:34:59,498 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:34:59,499 INFO L93 Difference]: Finished difference Result 11567 states and 15854 transitions. [2024-11-08 00:34:59,499 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11567 states and 15854 transitions. [2024-11-08 00:34:59,557 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 11376 [2024-11-08 00:34:59,609 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11567 states to 11567 states and 15854 transitions. [2024-11-08 00:34:59,609 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11567 [2024-11-08 00:34:59,624 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11567 [2024-11-08 00:34:59,625 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11567 states and 15854 transitions. [2024-11-08 00:34:59,645 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:34:59,645 INFO L218 hiAutomatonCegarLoop]: Abstraction has 11567 states and 15854 transitions. [2024-11-08 00:34:59,657 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11567 states and 15854 transitions. [2024-11-08 00:34:59,778 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11567 to 10943. [2024-11-08 00:34:59,794 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10943 states, 10943 states have (on average 1.3742118249109019) internal successors, (15038), 10942 states have internal predecessors, (15038), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:34:59,827 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10943 states to 10943 states and 15038 transitions. [2024-11-08 00:34:59,827 INFO L240 hiAutomatonCegarLoop]: Abstraction has 10943 states and 15038 transitions. [2024-11-08 00:34:59,828 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:34:59,828 INFO L425 stractBuchiCegarLoop]: Abstraction has 10943 states and 15038 transitions. [2024-11-08 00:34:59,829 INFO L332 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2024-11-08 00:34:59,829 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10943 states and 15038 transitions. [2024-11-08 00:34:59,895 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 10752 [2024-11-08 00:34:59,895 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:34:59,895 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:34:59,896 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:59,896 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:59,897 INFO L745 eck$LassoCheckResult]: Stem: 94244#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 94245#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 94361#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 94362#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 94346#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 94347#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 94181#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 94182#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 94159#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 94160#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 94437#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 94272#L611 assume !(0 == ~M_E~0); 94273#L611-2 assume !(0 == ~T1_E~0); 94455#L616-1 assume !(0 == ~T2_E~0); 94456#L621-1 assume !(0 == ~T3_E~0); 94024#L626-1 assume !(0 == ~T4_E~0); 94025#L631-1 assume !(0 == ~T5_E~0); 94223#L636-1 assume !(0 == ~E_M~0); 94074#L641-1 assume !(0 == ~E_1~0); 94075#L646-1 assume !(0 == ~E_2~0); 94241#L651-1 assume !(0 == ~E_3~0); 94498#L656-1 assume !(0 == ~E_4~0); 94435#L661-1 assume !(0 == ~E_5~0); 94436#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 94474#L304 assume !(1 == ~m_pc~0); 94100#L304-2 is_master_triggered_~__retres1~0#1 := 0; 94001#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 94002#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 93950#L755 assume !(0 != activate_threads_~tmp~1#1); 93951#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 93907#L323 assume !(1 == ~t1_pc~0); 93908#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 93967#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 93968#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 94538#L763 assume !(0 != activate_threads_~tmp___0~0#1); 94539#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 93971#L342 assume !(1 == ~t2_pc~0); 93973#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 94107#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 94108#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 94560#L771 assume !(0 != activate_threads_~tmp___1~0#1); 94561#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 94310#L361 assume !(1 == ~t3_pc~0); 94311#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 94515#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 94516#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 94493#L779 assume !(0 != activate_threads_~tmp___2~0#1); 94494#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 94308#L380 assume !(1 == ~t4_pc~0); 94309#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 94447#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 94448#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 94349#L787 assume !(0 != activate_threads_~tmp___3~0#1); 94350#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 94595#L399 assume !(1 == ~t5_pc~0); 94593#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 94592#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 94591#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 94590#L795 assume !(0 != activate_threads_~tmp___4~0#1); 94589#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 94562#L679 assume !(1 == ~M_E~0); 94270#L679-2 assume !(1 == ~T1_E~0); 94121#L684-1 assume !(1 == ~T2_E~0); 94122#L689-1 assume !(1 == ~T3_E~0); 94320#L694-1 assume !(1 == ~T4_E~0); 94585#L699-1 assume !(1 == ~T5_E~0); 94584#L704-1 assume !(1 == ~E_M~0); 94295#L709-1 assume !(1 == ~E_1~0); 94227#L714-1 assume !(1 == ~E_2~0); 94228#L719-1 assume !(1 == ~E_3~0); 94425#L724-1 assume !(1 == ~E_4~0); 94012#L729-1 assume !(1 == ~E_5~0); 94013#L734-1 assume { :end_inline_reset_delta_events } true; 94517#L940-2 [2024-11-08 00:34:59,897 INFO L747 eck$LassoCheckResult]: Loop: 94517#L940-2 assume !false; 98816#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 99102#L586-1 assume !false; 98799#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 98800#L464 assume !(0 == ~m_st~0); 98382#L468 assume !(0 == ~t1_st~0); 98381#L472 assume !(0 == ~t2_st~0); 98380#L476 assume !(0 == ~t3_st~0); 98378#L480 assume !(0 == ~t4_st~0); 98375#L484 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 98373#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 98371#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 98363#L511 assume !(0 != eval_~tmp~0#1); 98358#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 98352#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 98347#L611-3 assume !(0 == ~M_E~0); 98343#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 98340#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 98336#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 98332#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 98325#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 98319#L636-3 assume !(0 == ~E_M~0); 98313#L641-3 assume !(0 == ~E_1~0); 98292#L646-3 assume !(0 == ~E_2~0); 98291#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 98290#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 98288#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 98286#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 97437#L304-21 assume !(1 == ~m_pc~0); 97434#L304-23 is_master_triggered_~__retres1~0#1 := 0; 97432#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 97430#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 97427#L755-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 97425#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 97423#L323-21 assume !(1 == ~t1_pc~0); 97421#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 97419#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 97417#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 97415#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 97413#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 97411#L342-21 assume !(1 == ~t2_pc~0); 97408#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 97405#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 97403#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 97401#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 97398#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 97396#L361-21 assume !(1 == ~t3_pc~0); 97392#L361-23 is_transmit3_triggered_~__retres1~3#1 := 0; 97390#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 97388#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 97386#L779-21 assume !(0 != activate_threads_~tmp___2~0#1); 97383#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 97381#L380-21 assume !(1 == ~t4_pc~0); 97378#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 97376#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 97374#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 97372#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 97370#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 97368#L399-21 assume 1 == ~t5_pc~0; 97363#L400-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 97361#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 97359#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 97357#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 97354#L795-23 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 97352#L679-3 assume !(1 == ~M_E~0); 97146#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 97349#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 97347#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 97345#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 97343#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 97293#L704-3 assume !(1 == ~E_M~0); 97292#L709-3 assume !(1 == ~E_1~0); 97289#L714-3 assume !(1 == ~E_2~0); 97284#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 97282#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 97280#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 97278#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 97276#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 97274#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 97272#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 97269#L959 assume !(0 == start_simulation_~tmp~3#1); 97270#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 98868#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 98857#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 98849#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 98843#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 98838#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 98832#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 98825#L972 assume !(0 != start_simulation_~tmp___0~1#1); 94517#L940-2 [2024-11-08 00:34:59,898 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:34:59,898 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 4 times [2024-11-08 00:34:59,898 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:34:59,898 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [96691830] [2024-11-08 00:34:59,898 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:34:59,899 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:34:59,910 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:34:59,912 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 00:34:59,919 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:34:59,927 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 00:34:59,928 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:34:59,928 INFO L85 PathProgramCache]: Analyzing trace with hash 1200596224, now seen corresponding path program 1 times [2024-11-08 00:34:59,928 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:34:59,928 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2034726653] [2024-11-08 00:34:59,928 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:34:59,928 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:34:59,940 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:00,007 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:00,007 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:00,007 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2034726653] [2024-11-08 00:35:00,007 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2034726653] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:00,007 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:00,007 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-08 00:35:00,007 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [543709228] [2024-11-08 00:35:00,007 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:00,008 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:35:00,008 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:35:00,008 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-08 00:35:00,008 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-08 00:35:00,008 INFO L87 Difference]: Start difference. First operand 10943 states and 15038 transitions. cyclomatic complexity: 4099 Second operand has 5 states, 5 states have (on average 17.8) internal successors, (89), 5 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:00,214 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:35:00,214 INFO L93 Difference]: Finished difference Result 10823 states and 14701 transitions. [2024-11-08 00:35:00,214 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10823 states and 14701 transitions. [2024-11-08 00:35:00,265 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 10632 [2024-11-08 00:35:00,309 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10823 states to 10823 states and 14701 transitions. [2024-11-08 00:35:00,309 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10823 [2024-11-08 00:35:00,329 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10823 [2024-11-08 00:35:00,329 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10823 states and 14701 transitions. [2024-11-08 00:35:00,344 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:35:00,344 INFO L218 hiAutomatonCegarLoop]: Abstraction has 10823 states and 14701 transitions. [2024-11-08 00:35:00,354 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10823 states and 14701 transitions. [2024-11-08 00:35:00,450 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10823 to 10823. [2024-11-08 00:35:00,466 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10823 states, 10823 states have (on average 1.3583110043426037) internal successors, (14701), 10822 states have internal predecessors, (14701), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:00,502 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10823 states to 10823 states and 14701 transitions. [2024-11-08 00:35:00,503 INFO L240 hiAutomatonCegarLoop]: Abstraction has 10823 states and 14701 transitions. [2024-11-08 00:35:00,503 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-08 00:35:00,503 INFO L425 stractBuchiCegarLoop]: Abstraction has 10823 states and 14701 transitions. [2024-11-08 00:35:00,503 INFO L332 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2024-11-08 00:35:00,503 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10823 states and 14701 transitions. [2024-11-08 00:35:00,540 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 10632 [2024-11-08 00:35:00,540 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:35:00,540 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:35:00,542 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:00,542 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:00,543 INFO L745 eck$LassoCheckResult]: Stem: 116020#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 116021#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 116138#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 116139#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 116122#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 116123#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 115955#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 115956#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 115933#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 115934#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 116216#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 116046#L611 assume !(0 == ~M_E~0); 116047#L611-2 assume !(0 == ~T1_E~0); 116232#L616-1 assume !(0 == ~T2_E~0); 116233#L621-1 assume !(0 == ~T3_E~0); 115802#L626-1 assume !(0 == ~T4_E~0); 115803#L631-1 assume !(0 == ~T5_E~0); 115995#L636-1 assume !(0 == ~E_M~0); 115848#L641-1 assume !(0 == ~E_1~0); 115849#L646-1 assume !(0 == ~E_2~0); 116014#L651-1 assume !(0 == ~E_3~0); 116278#L656-1 assume !(0 == ~E_4~0); 116214#L661-1 assume !(0 == ~E_5~0); 116215#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 116250#L304 assume !(1 == ~m_pc~0); 115877#L304-2 is_master_triggered_~__retres1~0#1 := 0; 115774#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 115775#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 115728#L755 assume !(0 != activate_threads_~tmp~1#1); 115729#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 115681#L323 assume !(1 == ~t1_pc~0); 115682#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 115740#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 115741#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 116313#L763 assume !(0 != activate_threads_~tmp___0~0#1); 116314#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 115746#L342 assume !(1 == ~t2_pc~0); 115748#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 115882#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 115883#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 116326#L771 assume !(0 != activate_threads_~tmp___1~0#1); 116327#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 116084#L361 assume !(1 == ~t3_pc~0); 116085#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 116367#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 116366#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 116274#L779 assume !(0 != activate_threads_~tmp___2~0#1); 116275#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 116082#L380 assume !(1 == ~t4_pc~0); 116083#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 116224#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 116225#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 116358#L787 assume !(0 != activate_threads_~tmp___3~0#1); 116357#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 116356#L399 assume !(1 == ~t5_pc~0); 116354#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 116353#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 116352#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 116351#L795 assume !(0 != activate_threads_~tmp___4~0#1); 116350#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 116328#L679 assume !(1 == ~M_E~0); 116044#L679-2 assume !(1 == ~T1_E~0); 115895#L684-1 assume !(1 == ~T2_E~0); 115896#L689-1 assume !(1 == ~T3_E~0); 116347#L694-1 assume !(1 == ~T4_E~0); 116346#L699-1 assume !(1 == ~T5_E~0); 116345#L704-1 assume !(1 == ~E_M~0); 116069#L709-1 assume !(1 == ~E_1~0); 115999#L714-1 assume !(1 == ~E_2~0); 116000#L719-1 assume !(1 == ~E_3~0); 116201#L724-1 assume !(1 == ~E_4~0); 115785#L729-1 assume !(1 == ~E_5~0); 115786#L734-1 assume { :end_inline_reset_delta_events } true; 116296#L940-2 [2024-11-08 00:35:00,543 INFO L747 eck$LassoCheckResult]: Loop: 116296#L940-2 assume !false; 119313#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 119312#L586-1 assume !false; 119311#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 119309#L464 assume !(0 == ~m_st~0); 119310#L468 assume !(0 == ~t1_st~0); 125608#L472 assume !(0 == ~t2_st~0); 125607#L476 assume !(0 == ~t3_st~0); 125606#L480 assume !(0 == ~t4_st~0); 125605#L484 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 125604#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 125602#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 124658#L511 assume !(0 != eval_~tmp~0#1); 124659#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 125972#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 125971#L611-3 assume !(0 == ~M_E~0); 125970#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 125969#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 124644#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 124642#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 124640#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 124429#L636-3 assume !(0 == ~E_M~0); 124428#L641-3 assume !(0 == ~E_1~0); 124200#L646-3 assume !(0 == ~E_2~0); 123232#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 123231#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 123230#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 123228#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 123224#L304-21 assume 1 == ~m_pc~0; 123226#L305-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 119468#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 119467#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 119464#L755-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 119461#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 119459#L323-21 assume !(1 == ~t1_pc~0); 119457#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 119455#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 119452#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 119449#L763-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 119447#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 119443#L342-21 assume !(1 == ~t2_pc~0); 119438#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 119434#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 119430#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 119427#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 119424#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 119422#L361-21 assume !(1 == ~t3_pc~0); 119417#L361-23 is_transmit3_triggered_~__retres1~3#1 := 0; 119416#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 119413#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 119411#L779-21 assume !(0 != activate_threads_~tmp___2~0#1); 119408#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 119406#L380-21 assume !(1 == ~t4_pc~0); 119401#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 119399#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 119397#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 119395#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 119393#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 119391#L399-21 assume !(1 == ~t5_pc~0); 119389#L399-23 is_transmit5_triggered_~__retres1~5#1 := 0; 119386#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 119383#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 119381#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 119379#L795-23 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 119377#L679-3 assume !(1 == ~M_E~0); 119373#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 119371#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 119370#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 119366#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 119364#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 119362#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 119360#L709-3 assume !(1 == ~E_1~0); 119357#L714-3 assume !(1 == ~E_2~0); 119355#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 119353#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 119351#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 119349#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 119346#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 119344#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 119342#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 119339#L959 assume !(0 == start_simulation_~tmp~3#1); 119335#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 119332#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 119330#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 119328#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 119326#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 119322#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 119320#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 119318#L972 assume !(0 != start_simulation_~tmp___0~1#1); 116296#L940-2 [2024-11-08 00:35:00,544 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:00,544 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 5 times [2024-11-08 00:35:00,544 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:00,544 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1314409470] [2024-11-08 00:35:00,544 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:00,544 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:00,554 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:35:00,554 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 00:35:00,560 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:35:00,568 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 00:35:00,569 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:00,569 INFO L85 PathProgramCache]: Analyzing trace with hash 89536830, now seen corresponding path program 1 times [2024-11-08 00:35:00,569 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:00,569 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1130562843] [2024-11-08 00:35:00,569 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:00,569 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:00,590 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:00,650 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:00,650 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:00,650 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1130562843] [2024-11-08 00:35:00,650 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1130562843] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:00,650 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:00,651 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-08 00:35:00,651 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1660802928] [2024-11-08 00:35:00,651 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:00,651 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:35:00,651 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:35:00,651 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-08 00:35:00,652 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-08 00:35:00,652 INFO L87 Difference]: Start difference. First operand 10823 states and 14701 transitions. cyclomatic complexity: 3882 Second operand has 5 states, 5 states have (on average 17.8) internal successors, (89), 5 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:00,850 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:35:00,850 INFO L93 Difference]: Finished difference Result 10847 states and 14563 transitions. [2024-11-08 00:35:00,850 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10847 states and 14563 transitions. [2024-11-08 00:35:00,895 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 10656 [2024-11-08 00:35:00,938 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10847 states to 10847 states and 14563 transitions. [2024-11-08 00:35:00,938 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10847 [2024-11-08 00:35:00,948 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10847 [2024-11-08 00:35:00,949 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10847 states and 14563 transitions. [2024-11-08 00:35:00,960 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:35:00,961 INFO L218 hiAutomatonCegarLoop]: Abstraction has 10847 states and 14563 transitions. [2024-11-08 00:35:00,970 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10847 states and 14563 transitions. [2024-11-08 00:35:01,074 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10847 to 10847. [2024-11-08 00:35:01,090 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10847 states, 10847 states have (on average 1.342583202728865) internal successors, (14563), 10846 states have internal predecessors, (14563), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:01,122 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10847 states to 10847 states and 14563 transitions. [2024-11-08 00:35:01,122 INFO L240 hiAutomatonCegarLoop]: Abstraction has 10847 states and 14563 transitions. [2024-11-08 00:35:01,123 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-08 00:35:01,123 INFO L425 stractBuchiCegarLoop]: Abstraction has 10847 states and 14563 transitions. [2024-11-08 00:35:01,123 INFO L332 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2024-11-08 00:35:01,123 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10847 states and 14563 transitions. [2024-11-08 00:35:01,157 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 10656 [2024-11-08 00:35:01,158 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:35:01,158 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:35:01,159 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:01,159 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:01,159 INFO L745 eck$LassoCheckResult]: Stem: 137693#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 137694#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 137816#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 137817#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 137799#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 137800#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 137631#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 137632#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 137611#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 137612#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 137890#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 137719#L611 assume !(0 == ~M_E~0); 137720#L611-2 assume !(0 == ~T1_E~0); 137907#L616-1 assume !(0 == ~T2_E~0); 137908#L621-1 assume !(0 == ~T3_E~0); 137481#L626-1 assume !(0 == ~T4_E~0); 137482#L631-1 assume !(0 == ~T5_E~0); 137676#L636-1 assume !(0 == ~E_M~0); 137528#L641-1 assume !(0 == ~E_1~0); 137529#L646-1 assume !(0 == ~E_2~0); 137690#L651-1 assume !(0 == ~E_3~0); 137946#L656-1 assume !(0 == ~E_4~0); 137888#L661-1 assume !(0 == ~E_5~0); 137889#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 137923#L304 assume !(1 == ~m_pc~0); 137557#L304-2 is_master_triggered_~__retres1~0#1 := 0; 137558#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 137641#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 137406#L755 assume !(0 != activate_threads_~tmp~1#1); 137407#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 138021#L323 assume !(1 == ~t1_pc~0); 137744#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 137745#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 137435#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 137436#L763 assume !(0 != activate_threads_~tmp___0~0#1); 137992#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 137993#L342 assume !(1 == ~t2_pc~0); 137886#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 137887#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 137818#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 137819#L771 assume !(0 != activate_threads_~tmp___1~0#1); 137881#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 137882#L361 assume !(1 == ~t3_pc~0); 137788#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 137789#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 138040#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 138041#L779 assume !(0 != activate_threads_~tmp___2~0#1); 137442#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 137443#L380 assume !(1 == ~t4_pc~0); 138011#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 138012#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 137523#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 137524#L787 assume !(0 != activate_threads_~tmp___3~0#1); 138036#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 138035#L399 assume !(1 == ~t5_pc~0); 138033#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 138032#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 138031#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 138030#L795 assume !(0 != activate_threads_~tmp___4~0#1); 138029#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 138006#L679 assume !(1 == ~M_E~0); 137718#L679-2 assume !(1 == ~T1_E~0); 137573#L684-1 assume !(1 == ~T2_E~0); 137574#L689-1 assume !(1 == ~T3_E~0); 138026#L694-1 assume !(1 == ~T4_E~0); 138025#L699-1 assume !(1 == ~T5_E~0); 138024#L704-1 assume !(1 == ~E_M~0); 137743#L709-1 assume !(1 == ~E_1~0); 137680#L714-1 assume !(1 == ~E_2~0); 137681#L719-1 assume !(1 == ~E_3~0); 137876#L724-1 assume !(1 == ~E_4~0); 137464#L729-1 assume !(1 == ~E_5~0); 137465#L734-1 assume { :end_inline_reset_delta_events } true; 137967#L940-2 [2024-11-08 00:35:01,160 INFO L747 eck$LassoCheckResult]: Loop: 137967#L940-2 assume !false; 143852#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 143847#L586-1 assume !false; 143842#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 143835#L464 assume !(0 == ~m_st~0); 143836#L468 assume !(0 == ~t1_st~0); 145175#L472 assume !(0 == ~t2_st~0); 145172#L476 assume !(0 == ~t3_st~0); 145173#L480 assume !(0 == ~t4_st~0); 145174#L484 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 145176#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 148055#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 148053#L511 assume !(0 != eval_~tmp~0#1); 148051#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 146732#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 146731#L611-3 assume !(0 == ~M_E~0); 146725#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 146722#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 146720#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 146718#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 146716#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 146713#L636-3 assume !(0 == ~E_M~0); 146711#L641-3 assume !(0 == ~E_1~0); 146708#L646-3 assume !(0 == ~E_2~0); 146706#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 146704#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 146702#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 146700#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 146698#L304-21 assume 1 == ~m_pc~0; 146697#L305-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 142176#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 142174#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 142171#L755-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 142169#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 142167#L323-21 assume !(1 == ~t1_pc~0); 142165#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 142163#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 142162#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 142159#L763-21 assume !(0 != activate_threads_~tmp___0~0#1); 142157#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 142155#L342-21 assume !(1 == ~t2_pc~0); 142152#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 142150#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 142148#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 142144#L771-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 142142#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 142140#L361-21 assume 1 == ~t3_pc~0; 142138#L362-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 142139#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 142192#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 142128#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 142126#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 142124#L380-21 assume !(1 == ~t4_pc~0); 142122#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 142120#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 142118#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 142116#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 142113#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 142111#L399-21 assume 1 == ~t5_pc~0; 142108#L400-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 142106#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 142104#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 142101#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 142099#L795-23 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 142097#L679-3 assume !(1 == ~M_E~0); 141993#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 142094#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 142092#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 142091#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 142090#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 142089#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 142088#L709-3 assume !(1 == ~E_1~0); 142086#L714-3 assume !(1 == ~E_2~0); 142085#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 142084#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 142082#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 142081#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 142079#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 142078#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 142077#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 142075#L959 assume !(0 == start_simulation_~tmp~3#1); 142076#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 143892#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 143891#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 143890#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 143889#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 143886#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 143884#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 143882#L972 assume !(0 != start_simulation_~tmp___0~1#1); 137967#L940-2 [2024-11-08 00:35:01,160 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:01,160 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 6 times [2024-11-08 00:35:01,160 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:01,160 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2146535038] [2024-11-08 00:35:01,160 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:01,161 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:01,170 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:35:01,170 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 00:35:01,177 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:35:01,192 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 00:35:01,193 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:01,193 INFO L85 PathProgramCache]: Analyzing trace with hash -220741444, now seen corresponding path program 1 times [2024-11-08 00:35:01,193 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:01,193 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1165526409] [2024-11-08 00:35:01,193 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:01,194 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:01,207 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:01,267 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:01,268 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:01,268 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1165526409] [2024-11-08 00:35:01,268 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1165526409] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:01,268 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:01,268 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-08 00:35:01,268 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [355813401] [2024-11-08 00:35:01,268 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:01,268 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:35:01,269 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:35:01,269 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-08 00:35:01,269 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-08 00:35:01,269 INFO L87 Difference]: Start difference. First operand 10847 states and 14563 transitions. cyclomatic complexity: 3720 Second operand has 5 states, 5 states have (on average 17.8) internal successors, (89), 5 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:01,418 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:35:01,418 INFO L93 Difference]: Finished difference Result 10895 states and 14457 transitions. [2024-11-08 00:35:01,419 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10895 states and 14457 transitions. [2024-11-08 00:35:01,468 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 10704 [2024-11-08 00:35:01,514 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10895 states to 10895 states and 14457 transitions. [2024-11-08 00:35:01,515 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10895 [2024-11-08 00:35:01,525 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10895 [2024-11-08 00:35:01,525 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10895 states and 14457 transitions. [2024-11-08 00:35:01,538 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:35:01,538 INFO L218 hiAutomatonCegarLoop]: Abstraction has 10895 states and 14457 transitions. [2024-11-08 00:35:01,550 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10895 states and 14457 transitions. [2024-11-08 00:35:01,707 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10895 to 10895. [2024-11-08 00:35:01,724 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10895 states, 10895 states have (on average 1.3269389628269848) internal successors, (14457), 10894 states have internal predecessors, (14457), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:01,752 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10895 states to 10895 states and 14457 transitions. [2024-11-08 00:35:01,753 INFO L240 hiAutomatonCegarLoop]: Abstraction has 10895 states and 14457 transitions. [2024-11-08 00:35:01,753 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-08 00:35:01,753 INFO L425 stractBuchiCegarLoop]: Abstraction has 10895 states and 14457 transitions. [2024-11-08 00:35:01,753 INFO L332 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2024-11-08 00:35:01,753 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10895 states and 14457 transitions. [2024-11-08 00:35:01,786 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 10704 [2024-11-08 00:35:01,786 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:35:01,786 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:35:01,788 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:01,788 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:01,788 INFO L745 eck$LassoCheckResult]: Stem: 159442#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 159443#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 159563#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 159564#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 159547#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 159548#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 159380#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 159381#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 159359#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 159360#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 159634#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 159468#L611 assume !(0 == ~M_E~0); 159469#L611-2 assume !(0 == ~T1_E~0); 159653#L616-1 assume !(0 == ~T2_E~0); 159654#L621-1 assume !(0 == ~T3_E~0); 159224#L626-1 assume !(0 == ~T4_E~0); 159225#L631-1 assume !(0 == ~T5_E~0); 159421#L636-1 assume !(0 == ~E_M~0); 159274#L641-1 assume !(0 == ~E_1~0); 159275#L646-1 assume !(0 == ~E_2~0); 159438#L651-1 assume !(0 == ~E_3~0); 159700#L656-1 assume !(0 == ~E_4~0); 159632#L661-1 assume !(0 == ~E_5~0); 159633#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 159670#L304 assume !(1 == ~m_pc~0); 159300#L304-2 is_master_triggered_~__retres1~0#1 := 0; 159201#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 159202#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 159152#L755 assume !(0 != activate_threads_~tmp~1#1); 159153#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 159109#L323 assume !(1 == ~t1_pc~0); 159110#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 159168#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 159169#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 159734#L763 assume !(0 != activate_threads_~tmp___0~0#1); 159735#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 159172#L342 assume !(1 == ~t2_pc~0); 159174#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 159308#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 159309#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 159751#L771 assume !(0 != activate_threads_~tmp___1~0#1); 159752#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 159509#L361 assume !(1 == ~t3_pc~0); 159510#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 159717#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 159718#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 159693#L779 assume !(0 != activate_threads_~tmp___2~0#1); 159694#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 159507#L380 assume !(1 == ~t4_pc~0); 159508#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 159644#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 159645#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 159550#L787 assume !(0 != activate_threads_~tmp___3~0#1); 159551#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 159246#L399 assume !(1 == ~t5_pc~0); 159247#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 159780#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 159778#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 159777#L795 assume !(0 != activate_threads_~tmp___4~0#1); 159776#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 159753#L679 assume !(1 == ~M_E~0); 159466#L679-2 assume !(1 == ~T1_E~0); 159321#L684-1 assume !(1 == ~T2_E~0); 159322#L689-1 assume !(1 == ~T3_E~0); 159519#L694-1 assume !(1 == ~T4_E~0); 159772#L699-1 assume !(1 == ~T5_E~0); 159771#L704-1 assume !(1 == ~E_M~0); 159494#L709-1 assume !(1 == ~E_1~0); 159425#L714-1 assume !(1 == ~E_2~0); 159426#L719-1 assume !(1 == ~E_3~0); 159621#L724-1 assume !(1 == ~E_4~0); 159212#L729-1 assume !(1 == ~E_5~0); 159213#L734-1 assume { :end_inline_reset_delta_events } true; 159720#L940-2 [2024-11-08 00:35:01,788 INFO L747 eck$LassoCheckResult]: Loop: 159720#L940-2 assume !false; 160303#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 160251#L586-1 assume !false; 160244#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 160236#L464 assume !(0 == ~m_st~0); 160237#L468 assume !(0 == ~t1_st~0); 163467#L472 assume !(0 == ~t2_st~0); 163452#L476 assume !(0 == ~t3_st~0); 163449#L480 assume !(0 == ~t4_st~0); 163443#L484 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 163440#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 163436#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 163430#L511 assume !(0 != eval_~tmp~0#1); 163428#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 163425#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 163186#L611-3 assume !(0 == ~M_E~0); 163183#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 163181#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 163179#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 163177#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 163175#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 162486#L636-3 assume !(0 == ~E_M~0); 162487#L641-3 assume !(0 == ~E_1~0); 163001#L646-3 assume !(0 == ~E_2~0); 162998#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 162995#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 162472#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 162473#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 162467#L304-21 assume 1 == ~m_pc~0; 162469#L305-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 162465#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 162464#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 162462#L755-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 162461#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 162460#L323-21 assume !(1 == ~t1_pc~0); 162459#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 162458#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 162457#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 162456#L763-21 assume !(0 != activate_threads_~tmp___0~0#1); 162455#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 162454#L342-21 assume !(1 == ~t2_pc~0); 162452#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 162451#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 162449#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 162447#L771-21 assume !(0 != activate_threads_~tmp___1~0#1); 162445#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 162444#L361-21 assume 1 == ~t3_pc~0; 162442#L362-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 162440#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 162438#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 162436#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 162435#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 162432#L380-21 assume !(1 == ~t4_pc~0); 162430#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 162428#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 162426#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 162424#L787-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 162422#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 162420#L399-21 assume !(1 == ~t5_pc~0); 162418#L399-23 is_transmit5_triggered_~__retres1~5#1 := 0; 162415#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 162413#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 162411#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 162409#L795-23 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 162406#L679-3 assume !(1 == ~M_E~0); 161461#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 162403#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 162400#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 162397#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 162394#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 162392#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 162388#L709-3 assume !(1 == ~E_1~0); 162384#L714-3 assume !(1 == ~E_2~0); 160592#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 160428#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 160422#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 160417#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 160409#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 160400#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 160391#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 160382#L959 assume !(0 == start_simulation_~tmp~3#1); 160375#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 160368#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 160360#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 160353#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 160346#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 160336#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 160327#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 160318#L972 assume !(0 != start_simulation_~tmp___0~1#1); 159720#L940-2 [2024-11-08 00:35:01,789 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:01,789 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 7 times [2024-11-08 00:35:01,789 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:01,789 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [768248019] [2024-11-08 00:35:01,789 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:01,789 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:01,799 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:35:01,800 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 00:35:01,807 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:35:01,818 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 00:35:01,819 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:01,820 INFO L85 PathProgramCache]: Analyzing trace with hash -1098726081, now seen corresponding path program 1 times [2024-11-08 00:35:01,820 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:01,820 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1658216628] [2024-11-08 00:35:01,820 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:01,820 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:01,834 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:01,895 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:01,895 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:01,895 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1658216628] [2024-11-08 00:35:01,896 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1658216628] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:01,896 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:01,896 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-08 00:35:01,896 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1750784864] [2024-11-08 00:35:01,896 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:01,896 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:35:01,896 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:35:01,896 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-08 00:35:01,897 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-08 00:35:01,897 INFO L87 Difference]: Start difference. First operand 10895 states and 14457 transitions. cyclomatic complexity: 3566 Second operand has 5 states, 5 states have (on average 17.8) internal successors, (89), 5 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:02,082 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:35:02,083 INFO L93 Difference]: Finished difference Result 11171 states and 14655 transitions. [2024-11-08 00:35:02,083 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11171 states and 14655 transitions. [2024-11-08 00:35:02,136 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 10980 [2024-11-08 00:35:02,179 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11171 states to 11171 states and 14655 transitions. [2024-11-08 00:35:02,180 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11171 [2024-11-08 00:35:02,189 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11171 [2024-11-08 00:35:02,190 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11171 states and 14655 transitions. [2024-11-08 00:35:02,201 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:35:02,202 INFO L218 hiAutomatonCegarLoop]: Abstraction has 11171 states and 14655 transitions. [2024-11-08 00:35:02,213 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11171 states and 14655 transitions. [2024-11-08 00:35:02,420 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11171 to 11171. [2024-11-08 00:35:02,435 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11171 states, 11171 states have (on average 1.3118789723390922) internal successors, (14655), 11170 states have internal predecessors, (14655), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:02,465 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11171 states to 11171 states and 14655 transitions. [2024-11-08 00:35:02,465 INFO L240 hiAutomatonCegarLoop]: Abstraction has 11171 states and 14655 transitions. [2024-11-08 00:35:02,466 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-08 00:35:02,466 INFO L425 stractBuchiCegarLoop]: Abstraction has 11171 states and 14655 transitions. [2024-11-08 00:35:02,466 INFO L332 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2024-11-08 00:35:02,466 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11171 states and 14655 transitions. [2024-11-08 00:35:02,506 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 10980 [2024-11-08 00:35:02,506 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:35:02,506 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:35:02,508 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:02,508 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:02,508 INFO L745 eck$LassoCheckResult]: Stem: 181522#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 181523#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 181650#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 181651#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 181632#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 181633#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 181459#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 181460#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 181438#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 181439#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 181729#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 181548#L611 assume !(0 == ~M_E~0); 181549#L611-2 assume !(0 == ~T1_E~0); 181751#L616-1 assume !(0 == ~T2_E~0); 181752#L621-1 assume !(0 == ~T3_E~0); 181305#L626-1 assume !(0 == ~T4_E~0); 181306#L631-1 assume !(0 == ~T5_E~0); 181500#L636-1 assume !(0 == ~E_M~0); 181351#L641-1 assume !(0 == ~E_1~0); 181352#L646-1 assume !(0 == ~E_2~0); 181518#L651-1 assume !(0 == ~E_3~0); 181805#L656-1 assume !(0 == ~E_4~0); 181727#L661-1 assume !(0 == ~E_5~0); 181728#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 181774#L304 assume !(1 == ~m_pc~0); 181381#L304-2 is_master_triggered_~__retres1~0#1 := 0; 181276#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 181277#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 181230#L755 assume !(0 != activate_threads_~tmp~1#1); 181231#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 181183#L323 assume !(1 == ~t1_pc~0); 181184#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 181243#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 181244#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 181839#L763 assume !(0 != activate_threads_~tmp___0~0#1); 181840#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 181248#L342 assume !(1 == ~t2_pc~0); 181250#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 181386#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 181387#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 181858#L771 assume !(0 != activate_threads_~tmp___1~0#1); 181859#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 181590#L361 assume !(1 == ~t3_pc~0); 181591#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 181902#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 181901#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 181799#L779 assume !(0 != activate_threads_~tmp___2~0#1); 181800#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 181588#L380 assume !(1 == ~t4_pc~0); 181589#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 181740#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 181741#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 181893#L787 assume !(0 != activate_threads_~tmp___3~0#1); 181892#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 181891#L399 assume !(1 == ~t5_pc~0); 181889#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 181888#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 181887#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 181886#L795 assume !(0 != activate_threads_~tmp___4~0#1); 181885#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 181860#L679 assume !(1 == ~M_E~0); 181546#L679-2 assume !(1 == ~T1_E~0); 181399#L684-1 assume !(1 == ~T2_E~0); 181400#L689-1 assume !(1 == ~T3_E~0); 181882#L694-1 assume !(1 == ~T4_E~0); 181881#L699-1 assume !(1 == ~T5_E~0); 181880#L704-1 assume !(1 == ~E_M~0); 181575#L709-1 assume !(1 == ~E_1~0); 181504#L714-1 assume !(1 == ~E_2~0); 181505#L719-1 assume !(1 == ~E_3~0); 181713#L724-1 assume !(1 == ~E_4~0); 181287#L729-1 assume !(1 == ~E_5~0); 181288#L734-1 assume { :end_inline_reset_delta_events } true; 181821#L940-2 [2024-11-08 00:35:02,508 INFO L747 eck$LassoCheckResult]: Loop: 181821#L940-2 assume !false; 184525#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 184522#L586-1 assume !false; 184519#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 184515#L464 assume !(0 == ~m_st~0); 184516#L468 assume !(0 == ~t1_st~0); 186595#L472 assume !(0 == ~t2_st~0); 186592#L476 assume !(0 == ~t3_st~0); 186593#L480 assume !(0 == ~t4_st~0); 186594#L484 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 186596#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 186385#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 186386#L511 assume !(0 != eval_~tmp~0#1); 186982#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 186981#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 186980#L611-3 assume !(0 == ~M_E~0); 186979#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 186978#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 186977#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 186976#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 186975#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 186974#L636-3 assume !(0 == ~E_M~0); 186973#L641-3 assume !(0 == ~E_1~0); 184744#L646-3 assume !(0 == ~E_2~0); 184745#L651-3 assume 0 == ~E_3~0;~E_3~0 := 1; 184736#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 184737#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 184727#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 184728#L304-21 assume 1 == ~m_pc~0; 186972#L305-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 183931#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 183929#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 183923#L755-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 183921#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 183919#L323-21 assume !(1 == ~t1_pc~0); 183917#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 183915#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 183913#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 183911#L763-21 assume !(0 != activate_threads_~tmp___0~0#1); 183909#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 183862#L342-21 assume !(1 == ~t2_pc~0); 183858#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 183856#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 183852#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 183847#L771-21 assume !(0 != activate_threads_~tmp___1~0#1); 183843#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 183839#L361-21 assume 1 == ~t3_pc~0; 183831#L362-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 183825#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 183819#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 183813#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 183806#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 183802#L380-21 assume !(1 == ~t4_pc~0); 183797#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 183793#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 183787#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 183782#L787-21 assume !(0 != activate_threads_~tmp___3~0#1); 183779#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 183776#L399-21 assume 1 == ~t5_pc~0; 183771#L400-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 183765#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 183760#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 183755#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 183748#L795-23 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 183743#L679-3 assume !(1 == ~M_E~0); 183213#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 183735#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 183731#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 183726#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 183720#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 183716#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 183711#L709-3 assume !(1 == ~E_1~0); 183706#L714-3 assume !(1 == ~E_2~0); 183701#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 183695#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 183687#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 183683#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 183677#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 183671#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 183665#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 183659#L959 assume !(0 == start_simulation_~tmp~3#1); 183660#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 185754#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 185748#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 185746#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 185744#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 185742#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 185481#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 185019#L972 assume !(0 != start_simulation_~tmp___0~1#1); 181821#L940-2 [2024-11-08 00:35:02,509 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:02,509 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 8 times [2024-11-08 00:35:02,509 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:02,509 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1016261055] [2024-11-08 00:35:02,509 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:02,510 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:02,521 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:35:02,521 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 00:35:02,528 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:35:02,538 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 00:35:02,539 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:02,539 INFO L85 PathProgramCache]: Analyzing trace with hash 600358336, now seen corresponding path program 1 times [2024-11-08 00:35:02,539 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:02,539 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [959046214] [2024-11-08 00:35:02,539 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:02,539 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:02,553 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:35:02,554 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 00:35:02,563 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:35:02,572 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 00:35:02,572 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:02,573 INFO L85 PathProgramCache]: Analyzing trace with hash -1796293124, now seen corresponding path program 1 times [2024-11-08 00:35:02,573 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:02,573 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [744645012] [2024-11-08 00:35:02,573 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:02,573 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:02,592 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:02,639 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:02,640 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:02,640 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [744645012] [2024-11-08 00:35:02,640 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [744645012] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:02,640 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:02,640 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:02,640 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [238725103] [2024-11-08 00:35:02,640 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:04,053 INFO L204 LassoAnalysis]: Preferences: [2024-11-08 00:35:04,054 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-11-08 00:35:04,054 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-11-08 00:35:04,054 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-11-08 00:35:04,055 INFO L128 ssoRankerPreferences]: Use exernal solver: true [2024-11-08 00:35:04,055 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 00:35:04,055 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-11-08 00:35:04,055 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-11-08 00:35:04,056 INFO L132 ssoRankerPreferences]: Filename of dumped script: token_ring.05.cil-2.c_Iteration21_Loop [2024-11-08 00:35:04,056 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-11-08 00:35:04,056 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-11-08 00:35:04,083 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:04,090 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:04,094 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:04,097 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:04,099 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:04,106 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:04,108 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:04,111 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:04,114 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:04,119 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:04,122 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:04,124 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:04,126 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:04,128 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:04,131 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:04,134 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:04,139 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:04,141 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:04,143 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:04,146 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:04,148 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:04,157 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:04,159 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:04,161 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:04,166 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:04,169 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:04,171 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:04,174 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:04,176 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:04,183 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:04,185 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:04,188 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:04,194 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:04,196 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:04,201 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:04,204 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:04,214 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:04,216 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:04,221 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:04,223 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:04,225 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:04,227 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:04,230 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:04,232 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:04,234 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:04,238 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:04,243 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:04,245 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:04,250 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:04,253 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:04,259 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:04,261 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:04,267 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:04,269 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:04,271 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:04,275 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:04,277 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:04,280 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:04,281 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:04,284 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:04,286 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:04,288 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:04,290 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:04,295 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:04,299 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:04,302 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:04,307 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:04,312 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:04,314 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:04,316 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:04,318 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:04,321 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:04,800 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-11-08 00:35:04,801 INFO L365 LassoAnalysis]: Checking for nontermination... [2024-11-08 00:35:04,803 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 00:35:04,803 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2024-11-08 00:35:04,806 INFO L229 MonitoredProcess]: Starting monitored process 2 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 00:35:04,808 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2024-11-08 00:35:04,809 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-08 00:35:04,809 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-08 00:35:04,831 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-08 00:35:04,831 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_exists_runnable_thread_#res#1=0} Honda state: {ULTIMATE.start_exists_runnable_thread_#res#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-08 00:35:04,844 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Ended with exit code 0 [2024-11-08 00:35:04,845 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 00:35:04,845 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2024-11-08 00:35:04,847 INFO L229 MonitoredProcess]: Starting monitored process 3 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 00:35:04,850 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2024-11-08 00:35:04,850 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-08 00:35:04,850 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-08 00:35:04,872 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-08 00:35:04,873 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t4_st~0=-1} Honda state: {~t4_st~0=-1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-08 00:35:04,885 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Ended with exit code 0 [2024-11-08 00:35:04,885 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 00:35:04,885 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2024-11-08 00:35:04,887 INFO L229 MonitoredProcess]: Starting monitored process 4 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 00:35:04,888 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2024-11-08 00:35:04,888 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-08 00:35:04,888 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-08 00:35:04,900 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-08 00:35:04,901 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp_ndt_2~0#1=0} Honda state: {ULTIMATE.start_eval_~tmp_ndt_2~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-08 00:35:04,916 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Ended with exit code 0 [2024-11-08 00:35:04,916 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 00:35:04,916 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2024-11-08 00:35:04,919 INFO L229 MonitoredProcess]: Starting monitored process 5 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 00:35:04,921 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2024-11-08 00:35:04,922 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-08 00:35:04,923 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-08 00:35:04,938 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-08 00:35:04,938 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~m_pc~0=1} Honda state: {~m_pc~0=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-08 00:35:04,953 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Ended with exit code 0 [2024-11-08 00:35:04,954 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 00:35:04,954 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2024-11-08 00:35:04,956 INFO L229 MonitoredProcess]: Starting monitored process 6 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 00:35:04,958 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2024-11-08 00:35:04,959 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-08 00:35:04,959 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-08 00:35:04,985 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Ended with exit code 0 [2024-11-08 00:35:04,986 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 00:35:04,986 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2024-11-08 00:35:04,988 INFO L229 MonitoredProcess]: Starting monitored process 7 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 00:35:04,988 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2024-11-08 00:35:04,989 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2024-11-08 00:35:04,989 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-08 00:35:05,006 INFO L405 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2024-11-08 00:35:05,021 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Ended with exit code 0 [2024-11-08 00:35:05,021 INFO L204 LassoAnalysis]: Preferences: [2024-11-08 00:35:05,021 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-11-08 00:35:05,021 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-11-08 00:35:05,021 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-11-08 00:35:05,021 INFO L128 ssoRankerPreferences]: Use exernal solver: false [2024-11-08 00:35:05,021 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 00:35:05,021 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-11-08 00:35:05,021 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-11-08 00:35:05,021 INFO L132 ssoRankerPreferences]: Filename of dumped script: token_ring.05.cil-2.c_Iteration21_Loop [2024-11-08 00:35:05,021 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-11-08 00:35:05,021 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-11-08 00:35:05,027 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:05,032 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:05,037 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:05,040 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:05,043 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:05,051 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:05,053 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:05,055 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:05,062 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:05,065 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:05,067 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:05,069 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:05,071 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:05,074 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:05,078 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:05,082 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:05,084 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:05,086 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:05,089 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:05,091 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:05,096 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:05,098 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:05,100 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:05,102 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:05,108 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:05,110 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:05,113 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:05,117 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:05,120 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:05,122 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:05,124 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:05,126 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:05,130 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:05,135 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:05,138 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:05,199 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:05,204 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:05,209 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:05,211 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:05,213 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:05,214 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:05,216 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:05,218 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:05,220 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:05,222 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:05,224 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:05,230 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:05,234 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:05,236 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:05,241 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:05,243 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:05,245 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:05,251 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:05,253 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:05,256 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:05,258 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:05,266 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:05,269 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:05,270 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:05,276 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:05,277 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:05,279 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:05,281 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:05,283 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:05,284 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:05,286 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:05,288 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:05,293 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:05,298 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:05,300 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:05,301 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:05,303 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:05,741 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-11-08 00:35:05,745 INFO L451 LassoAnalysis]: Using template 'affine'. [2024-11-08 00:35:05,746 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 00:35:05,746 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2024-11-08 00:35:05,749 INFO L229 MonitoredProcess]: Starting monitored process 8 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 00:35:05,754 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2024-11-08 00:35:05,755 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-08 00:35:05,770 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-08 00:35:05,770 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-08 00:35:05,771 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-08 00:35:05,771 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-08 00:35:05,771 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-08 00:35:05,776 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-08 00:35:05,776 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-08 00:35:05,781 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-08 00:35:05,796 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Ended with exit code 0 [2024-11-08 00:35:05,797 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 00:35:05,797 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2024-11-08 00:35:05,799 INFO L229 MonitoredProcess]: Starting monitored process 9 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 00:35:05,801 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2024-11-08 00:35:05,802 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-08 00:35:05,815 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-08 00:35:05,815 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-08 00:35:05,815 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-08 00:35:05,816 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2024-11-08 00:35:05,816 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-08 00:35:05,816 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2024-11-08 00:35:05,816 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-08 00:35:05,822 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-08 00:35:05,838 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Ended with exit code 0 [2024-11-08 00:35:05,838 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 00:35:05,839 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2024-11-08 00:35:05,841 INFO L229 MonitoredProcess]: Starting monitored process 10 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 00:35:05,843 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Waiting until timeout for monitored process [2024-11-08 00:35:05,844 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-08 00:35:05,856 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-08 00:35:05,856 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-08 00:35:05,856 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-08 00:35:05,856 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-08 00:35:05,856 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-08 00:35:05,857 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-08 00:35:05,857 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-08 00:35:05,860 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-08 00:35:05,876 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Ended with exit code 0 [2024-11-08 00:35:05,877 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 00:35:05,877 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2024-11-08 00:35:05,879 INFO L229 MonitoredProcess]: Starting monitored process 11 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 00:35:05,881 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-08 00:35:05,882 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Waiting until timeout for monitored process [2024-11-08 00:35:05,894 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-08 00:35:05,894 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-08 00:35:05,894 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-08 00:35:05,895 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-08 00:35:05,895 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-08 00:35:05,896 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-08 00:35:05,896 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-08 00:35:05,897 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-08 00:35:05,912 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Ended with exit code 0 [2024-11-08 00:35:05,912 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 00:35:05,912 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2024-11-08 00:35:05,915 INFO L229 MonitoredProcess]: Starting monitored process 12 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 00:35:05,916 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Waiting until timeout for monitored process [2024-11-08 00:35:05,918 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-08 00:35:05,929 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-08 00:35:05,929 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-08 00:35:05,929 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-08 00:35:05,929 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-08 00:35:05,929 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-08 00:35:05,930 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-08 00:35:05,930 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-08 00:35:05,932 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2024-11-08 00:35:05,939 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2024-11-08 00:35:05,942 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2024-11-08 00:35:05,944 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 00:35:05,944 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2024-11-08 00:35:05,947 INFO L229 MonitoredProcess]: Starting monitored process 13 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 00:35:05,949 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Waiting until timeout for monitored process [2024-11-08 00:35:05,950 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2024-11-08 00:35:05,950 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2024-11-08 00:35:05,950 INFO L474 LassoAnalysis]: Proved termination. [2024-11-08 00:35:05,950 INFO L476 LassoAnalysis]: Termination argument consisting of: Ranking function f(~E_3~0) = -1*~E_3~0 + 1 Supporting invariants [] [2024-11-08 00:35:05,961 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Ended with exit code 0 [2024-11-08 00:35:05,963 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2024-11-08 00:35:05,985 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:06,035 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:06,038 INFO L255 TraceCheckSpWp]: Trace formula consists of 211 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-11-08 00:35:06,040 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-08 00:35:06,164 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:06,167 INFO L255 TraceCheckSpWp]: Trace formula consists of 201 conjuncts, 4 conjuncts are in the unsatisfiable core [2024-11-08 00:35:06,169 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-08 00:35:06,367 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:06,376 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2024-11-08 00:35:06,377 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 11171 states and 14655 transitions. cyclomatic complexity: 3488 Second operand has 5 states, 5 states have (on average 32.4) internal successors, (162), 5 states have internal predecessors, (162), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:06,703 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 11171 states and 14655 transitions. cyclomatic complexity: 3488. Second operand has 5 states, 5 states have (on average 32.4) internal successors, (162), 5 states have internal predecessors, (162), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 30285 states and 40066 transitions. Complement of second has 5 states. [2024-11-08 00:35:06,705 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2024-11-08 00:35:06,706 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 32.4) internal successors, (162), 5 states have internal predecessors, (162), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:06,707 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 725 transitions. [2024-11-08 00:35:06,712 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 725 transitions. Stem has 73 letters. Loop has 89 letters. [2024-11-08 00:35:06,716 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-08 00:35:06,716 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 725 transitions. Stem has 162 letters. Loop has 89 letters. [2024-11-08 00:35:06,717 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-08 00:35:06,717 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 725 transitions. Stem has 73 letters. Loop has 178 letters. [2024-11-08 00:35:06,722 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-08 00:35:06,722 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 30285 states and 40066 transitions. [2024-11-08 00:35:06,901 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 20392 [2024-11-08 00:35:07,051 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 30285 states to 30253 states and 40034 transitions. [2024-11-08 00:35:07,052 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 20680 [2024-11-08 00:35:07,074 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 20729 [2024-11-08 00:35:07,075 INFO L73 IsDeterministic]: Start isDeterministic. Operand 30253 states and 40034 transitions. [2024-11-08 00:35:07,079 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-08 00:35:07,079 INFO L218 hiAutomatonCegarLoop]: Abstraction has 30253 states and 40034 transitions. [2024-11-08 00:35:07,103 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30253 states and 40034 transitions. [2024-11-08 00:35:07,391 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Forceful destruction successful, exit code 0 [2024-11-08 00:35:07,485 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30253 to 30172. [2024-11-08 00:35:07,529 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 30172 states, 30172 states have (on average 1.3225838525785496) internal successors, (39905), 30171 states have internal predecessors, (39905), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:07,614 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 30172 states to 30172 states and 39905 transitions. [2024-11-08 00:35:07,614 INFO L240 hiAutomatonCegarLoop]: Abstraction has 30172 states and 39905 transitions. [2024-11-08 00:35:07,614 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:35:07,614 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:35:07,614 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:35:07,615 INFO L87 Difference]: Start difference. First operand 30172 states and 39905 transitions. Second operand has 3 states, 3 states have (on average 54.0) internal successors, (162), 3 states have internal predecessors, (162), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:07,778 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:35:07,778 INFO L93 Difference]: Finished difference Result 31180 states and 41009 transitions. [2024-11-08 00:35:07,779 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 31180 states and 41009 transitions. [2024-11-08 00:35:07,955 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 21064 [2024-11-08 00:35:08,087 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 31180 states to 31180 states and 41009 transitions. [2024-11-08 00:35:08,088 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21320 [2024-11-08 00:35:08,108 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21320 [2024-11-08 00:35:08,108 INFO L73 IsDeterministic]: Start isDeterministic. Operand 31180 states and 41009 transitions. [2024-11-08 00:35:08,112 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-08 00:35:08,113 INFO L218 hiAutomatonCegarLoop]: Abstraction has 31180 states and 41009 transitions. [2024-11-08 00:35:08,138 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 31180 states and 41009 transitions. [2024-11-08 00:35:08,575 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 31180 to 30172. [2024-11-08 00:35:08,620 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 30172 states, 30172 states have (on average 1.3178112156966724) internal successors, (39761), 30171 states have internal predecessors, (39761), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:08,704 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 30172 states to 30172 states and 39761 transitions. [2024-11-08 00:35:08,705 INFO L240 hiAutomatonCegarLoop]: Abstraction has 30172 states and 39761 transitions. [2024-11-08 00:35:08,705 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:35:08,705 INFO L425 stractBuchiCegarLoop]: Abstraction has 30172 states and 39761 transitions. [2024-11-08 00:35:08,706 INFO L332 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2024-11-08 00:35:08,706 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 30172 states and 39761 transitions. [2024-11-08 00:35:08,831 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 20392 [2024-11-08 00:35:08,831 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:35:08,831 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:35:08,835 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:08,835 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:08,836 INFO L745 eck$LassoCheckResult]: Stem: 285115#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 285116#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 285346#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 285347#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 285312#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 285313#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 285000#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 285001#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 284960#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 284961#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 285503#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 285166#L611 assume !(0 == ~M_E~0); 285167#L611-2 assume !(0 == ~T1_E~0); 285537#L616-1 assume !(0 == ~T2_E~0); 285538#L621-1 assume !(0 == ~T3_E~0); 284709#L626-1 assume !(0 == ~T4_E~0); 284710#L631-1 assume !(0 == ~T5_E~0); 285082#L636-1 assume !(0 == ~E_M~0); 284800#L641-1 assume !(0 == ~E_1~0); 284801#L646-1 assume !(0 == ~E_2~0); 285108#L651-1 assume !(0 == ~E_3~0); 285632#L656-1 assume !(0 == ~E_4~0); 285501#L661-1 assume !(0 == ~E_5~0); 285502#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 285576#L304 assume !(1 == ~m_pc~0); 284862#L304-2 is_master_triggered_~__retres1~0#1 := 0; 284863#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 285016#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 285017#L755 assume !(0 != activate_threads_~tmp~1#1); 285789#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 285790#L323 assume !(1 == ~t1_pc~0); 285217#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 285218#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 284633#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 284634#L763 assume !(0 != activate_threads_~tmp___0~0#1); 285726#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 285727#L342 assume !(1 == ~t2_pc~0); 285499#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 285500#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 285350#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 285351#L771 assume !(0 != activate_threads_~tmp___1~0#1); 285490#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 285491#L361 assume !(1 == ~t3_pc~0); 285294#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 285295#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 285805#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 285806#L779 assume !(0 != activate_threads_~tmp___2~0#1); 284645#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 284646#L380 assume !(1 == ~t4_pc~0); 285769#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 285770#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 284792#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 284793#L787 assume !(0 != activate_threads_~tmp___3~0#1); 285741#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 285742#L399 assume !(1 == ~t5_pc~0); 285023#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 285024#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 285033#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 285034#L795 assume !(0 != activate_threads_~tmp___4~0#1); 285657#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 285658#L679 assume !(1 == ~M_E~0); 285164#L679-2 assume !(1 == ~T1_E~0); 285165#L684-1 assume !(1 == ~T2_E~0); 285253#L689-1 assume !(1 == ~T3_E~0); 285254#L694-1 assume !(1 == ~T4_E~0); 285803#L699-1 assume !(1 == ~T5_E~0); 285802#L704-1 assume !(1 == ~E_M~0); 285216#L709-1 assume !(1 == ~E_1~0); 285089#L714-1 assume !(1 == ~E_2~0); 285090#L719-1 assume !(1 == ~E_3~0); 285478#L724-1 assume !(1 == ~E_4~0); 284676#L729-1 assume !(1 == ~E_5~0); 284677#L734-1 assume { :end_inline_reset_delta_events } true; 285672#L940-2 assume !false; 292233#L941 [2024-11-08 00:35:08,838 INFO L747 eck$LassoCheckResult]: Loop: 292233#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 304691#L586-1 assume !false; 304689#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 304686#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 304684#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 304680#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 304678#L511 assume 0 != eval_~tmp~0#1; 304676#L511-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 304673#L519 assume 0 != eval_~tmp_ndt_1~0#1;~m_st~0 := 1;assume { :begin_inline_master } true;havoc master_#t~nondet4#1, master_#t~nondet5#1, master_~tmp_var~0#1;havoc master_#t~nondet4#1;master_~tmp_var~0#1 := master_#t~nondet4#1;havoc master_#t~nondet4#1; 304674#L68 assume 0 == ~m_pc~0; 306069#L104 assume !false; 306068#L80 havoc master_#t~nondet5#1;~token~0 := master_#t~nondet5#1;havoc master_#t~nondet5#1;~local~0 := ~token~0;~E_1~0 := 1;assume { :begin_inline_immediate_notify } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 306067#L304-3 assume !(1 == ~m_pc~0); 306064#L304-5 is_master_triggered_~__retres1~0#1 := 0; 306063#L315-1 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 306062#is_master_triggered_returnLabel#2 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 306061#L755-3 assume !(0 != activate_threads_~tmp~1#1); 306060#L755-5 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 306059#L323-3 assume !(1 == ~t1_pc~0); 306058#L323-5 is_transmit1_triggered_~__retres1~1#1 := 0; 306057#L334-1 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 306055#is_transmit1_triggered_returnLabel#2 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 306054#L763-3 assume !(0 != activate_threads_~tmp___0~0#1); 306053#L763-5 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 306052#L342-3 assume !(1 == ~t2_pc~0); 306050#L342-5 is_transmit2_triggered_~__retres1~2#1 := 0; 306049#L353-1 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 306048#is_transmit2_triggered_returnLabel#2 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 306047#L771-3 assume !(0 != activate_threads_~tmp___1~0#1); 306046#L771-5 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 306044#L361-3 assume !(1 == ~t3_pc~0); 306041#L361-5 is_transmit3_triggered_~__retres1~3#1 := 0; 306039#L372-1 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 306037#is_transmit3_triggered_returnLabel#2 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 306035#L779-3 assume !(0 != activate_threads_~tmp___2~0#1); 306032#L779-5 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 306030#L380-3 assume !(1 == ~t4_pc~0); 306028#L380-5 is_transmit4_triggered_~__retres1~4#1 := 0; 306026#L391-1 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 306024#is_transmit4_triggered_returnLabel#2 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 306022#L787-3 assume !(0 != activate_threads_~tmp___3~0#1); 306020#L787-5 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 306018#L399-3 assume 1 == ~t5_pc~0; 306016#L400-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 306013#L410-1 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 306011#is_transmit5_triggered_returnLabel#2 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 306008#L795-3 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 306006#L795-5 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true; 306004#immediate_notify_returnLabel#1 assume { :end_inline_immediate_notify } true;~E_1~0 := 2;~m_pc~0 := 1;~m_st~0 := 2; 306002#master_returnLabel#1 havoc master_#t~nondet4#1, master_#t~nondet5#1, master_~tmp_var~0#1;assume { :end_inline_master } true; 305939#L519-2 havoc eval_~tmp_ndt_1~0#1; 305936#L516-1 assume !(0 == ~t1_st~0); 305931#L530-1 assume !(0 == ~t2_st~0); 305932#L544-1 assume !(0 == ~t3_st~0); 307796#L558-1 assume !(0 == ~t4_st~0); 307785#L572-1 assume !(0 == ~t5_st~0); 307779#L586-1 assume !false; 307777#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 307775#L464 assume !(0 == ~m_st~0); 307773#L468 assume !(0 == ~t1_st~0); 307771#L472 assume !(0 == ~t2_st~0); 307769#L476 assume !(0 == ~t3_st~0); 307767#L480 assume !(0 == ~t4_st~0); 307764#L484 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 307761#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 307759#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 307757#L511 assume !(0 != eval_~tmp~0#1); 307754#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 307752#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 307750#L611-3 assume !(0 == ~M_E~0); 307748#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 307746#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 307744#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 307742#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 307740#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 307738#L636-3 assume !(0 == ~E_M~0); 307736#L641-3 assume !(0 == ~E_1~0); 307734#L646-3 assume !(0 == ~E_2~0); 307732#L651-3 assume !(0 == ~E_3~0); 307730#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 307728#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 307726#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 307225#L304-21 assume 1 == ~m_pc~0; 307227#L305-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 300641#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 300640#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 300637#L755-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 300633#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 300631#L323-21 assume !(1 == ~t1_pc~0); 300629#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 300627#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 300625#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 300623#L763-21 assume !(0 != activate_threads_~tmp___0~0#1); 300621#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 300619#L342-21 assume !(1 == ~t2_pc~0); 300617#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 300614#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 300612#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 300610#L771-21 assume !(0 != activate_threads_~tmp___1~0#1); 300608#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 300606#L361-21 assume 1 == ~t3_pc~0; 300604#L362-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 300605#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 300649#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 300593#L779-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 300591#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 300588#L380-21 assume !(1 == ~t4_pc~0); 300586#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 300584#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 300582#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 300580#L787-21 assume !(0 != activate_threads_~tmp___3~0#1); 300578#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 300576#L399-21 assume 1 == ~t5_pc~0; 300573#L400-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 300571#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 300568#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 300566#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 300564#L795-23 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 300562#L679-3 assume !(1 == ~M_E~0); 300450#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 300558#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 300556#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 300554#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 300552#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 300550#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 300548#L709-3 assume !(1 == ~E_1~0); 300547#L714-3 assume !(1 == ~E_2~0); 300546#L719-3 assume !(1 == ~E_3~0); 300545#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 300543#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 300542#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 300541#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 300539#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 300538#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 300536#L959 assume !(0 == start_simulation_~tmp~3#1); 300537#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 304773#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 304771#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 304769#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 304767#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 304765#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 304763#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 304761#L972 assume !(0 != start_simulation_~tmp___0~1#1); 304759#L940-2 assume !false; 292233#L941 [2024-11-08 00:35:08,839 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:08,840 INFO L85 PathProgramCache]: Analyzing trace with hash 959436207, now seen corresponding path program 1 times [2024-11-08 00:35:08,840 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:08,840 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1903144142] [2024-11-08 00:35:08,840 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:08,840 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:08,850 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:35:08,852 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 00:35:08,857 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:35:08,869 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 00:35:08,871 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:08,871 INFO L85 PathProgramCache]: Analyzing trace with hash -1616097876, now seen corresponding path program 1 times [2024-11-08 00:35:08,871 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:08,871 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [251522380] [2024-11-08 00:35:08,872 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:08,872 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:08,887 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:08,924 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:08,924 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:08,924 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [251522380] [2024-11-08 00:35:08,924 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [251522380] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:08,924 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:08,924 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:08,924 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [881608624] [2024-11-08 00:35:08,924 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:08,925 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:35:08,925 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:35:08,925 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:35:08,925 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:35:08,925 INFO L87 Difference]: Start difference. First operand 30172 states and 39761 transitions. cyclomatic complexity: 9601 Second operand has 3 states, 3 states have (on average 48.0) internal successors, (144), 3 states have internal predecessors, (144), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:09,352 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:35:09,352 INFO L93 Difference]: Finished difference Result 53396 states and 70293 transitions. [2024-11-08 00:35:09,352 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 53396 states and 70293 transitions. [2024-11-08 00:35:09,703 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 36248 [2024-11-08 00:35:10,058 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 53396 states to 53396 states and 70293 transitions. [2024-11-08 00:35:10,058 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 36632 [2024-11-08 00:35:10,082 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 36632 [2024-11-08 00:35:10,083 INFO L73 IsDeterministic]: Start isDeterministic. Operand 53396 states and 70293 transitions. [2024-11-08 00:35:10,084 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-08 00:35:10,084 INFO L218 hiAutomatonCegarLoop]: Abstraction has 53396 states and 70293 transitions. [2024-11-08 00:35:10,118 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 53396 states and 70293 transitions. [2024-11-08 00:35:10,578 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 53396 to 53204. [2024-11-08 00:35:10,642 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 53204 states, 53204 states have (on average 1.3175889030899932) internal successors, (70101), 53203 states have internal predecessors, (70101), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:10,742 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 53204 states to 53204 states and 70101 transitions. [2024-11-08 00:35:10,742 INFO L240 hiAutomatonCegarLoop]: Abstraction has 53204 states and 70101 transitions. [2024-11-08 00:35:10,743 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:35:10,743 INFO L425 stractBuchiCegarLoop]: Abstraction has 53204 states and 70101 transitions. [2024-11-08 00:35:10,743 INFO L332 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2024-11-08 00:35:10,743 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 53204 states and 70101 transitions. [2024-11-08 00:35:10,909 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 36120 [2024-11-08 00:35:10,909 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:35:10,909 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:35:10,913 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:10,914 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:10,914 INFO L745 eck$LassoCheckResult]: Stem: 368689#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 368690#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 368923#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 368924#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 368892#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 368893#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 368564#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 368565#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 368524#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 368525#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 369081#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 368741#L611 assume !(0 == ~M_E~0); 368742#L611-2 assume !(0 == ~T1_E~0); 369113#L616-1 assume !(0 == ~T2_E~0); 369114#L621-1 assume !(0 == ~T3_E~0); 368272#L626-1 assume !(0 == ~T4_E~0); 368273#L631-1 assume !(0 == ~T5_E~0); 368645#L636-1 assume !(0 == ~E_M~0); 368364#L641-1 assume !(0 == ~E_1~0); 368365#L646-1 assume !(0 == ~E_2~0); 368680#L651-1 assume !(0 == ~E_3~0); 369207#L656-1 assume !(0 == ~E_4~0); 369079#L661-1 assume !(0 == ~E_5~0); 369080#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 369151#L304 assume !(1 == ~m_pc~0); 368415#L304-2 is_master_triggered_~__retres1~0#1 := 0; 368416#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 368574#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 368575#L755 assume !(0 != activate_threads_~tmp~1#1); 369355#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 369356#L323 assume !(1 == ~t1_pc~0); 368791#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 368792#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 368208#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 368209#L763 assume !(0 != activate_threads_~tmp___0~0#1); 369301#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 369302#L342 assume !(1 == ~t2_pc~0); 369077#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 369078#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 368929#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 368930#L771 assume !(0 != activate_threads_~tmp___1~0#1); 369064#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 369065#L361 assume !(1 == ~t3_pc~0); 368873#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 368874#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 369375#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 369376#L779 assume !(0 != activate_threads_~tmp___2~0#1); 368214#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 368215#L380 assume !(1 == ~t4_pc~0); 369340#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 369341#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 368354#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 368355#L787 assume !(0 != activate_threads_~tmp___3~0#1); 369315#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 369316#L399 assume !(1 == ~t5_pc~0); 368584#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 368585#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 368599#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 368600#L795 assume !(0 != activate_threads_~tmp___4~0#1); 369227#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 369228#L679 assume !(1 == ~M_E~0); 368736#L679-2 assume !(1 == ~T1_E~0); 368737#L684-1 assume !(1 == ~T2_E~0); 368833#L689-1 assume !(1 == ~T3_E~0); 368834#L694-1 assume !(1 == ~T4_E~0); 369373#L699-1 assume !(1 == ~T5_E~0); 369372#L704-1 assume !(1 == ~E_M~0); 368790#L709-1 assume !(1 == ~E_1~0); 368654#L714-1 assume !(1 == ~E_2~0); 368655#L719-1 assume !(1 == ~E_3~0); 369055#L724-1 assume !(1 == ~E_4~0); 368250#L729-1 assume !(1 == ~E_5~0); 368251#L734-1 assume { :end_inline_reset_delta_events } true; 369243#L940-2 assume !false; 374275#L941 [2024-11-08 00:35:10,915 INFO L747 eck$LassoCheckResult]: Loop: 374275#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 409049#L586-1 assume !false; 409040#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 409034#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 409031#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 409026#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 409021#L511 assume 0 != eval_~tmp~0#1; 409015#L511-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 409009#L519 assume 0 != eval_~tmp_ndt_1~0#1;~m_st~0 := 1;assume { :begin_inline_master } true;havoc master_#t~nondet4#1, master_#t~nondet5#1, master_~tmp_var~0#1;havoc master_#t~nondet4#1;master_~tmp_var~0#1 := master_#t~nondet4#1;havoc master_#t~nondet4#1; 409010#L68 assume 0 == ~m_pc~0; 413421#L104 assume !false; 413418#L80 havoc master_#t~nondet5#1;~token~0 := master_#t~nondet5#1;havoc master_#t~nondet5#1;~local~0 := ~token~0;~E_1~0 := 1;assume { :begin_inline_immediate_notify } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 413416#L304-3 assume 1 == ~m_pc~0; 413415#L305-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 398530#L315-1 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 398528#is_master_triggered_returnLabel#2 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 398437#L755-3 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 398434#L755-5 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 398432#L323-3 assume !(1 == ~t1_pc~0); 398430#L323-5 is_transmit1_triggered_~__retres1~1#1 := 0; 398427#L334-1 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 398425#is_transmit1_triggered_returnLabel#2 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 398423#L763-3 assume !(0 != activate_threads_~tmp___0~0#1); 398421#L763-5 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 394109#L342-3 assume !(1 == ~t2_pc~0); 394105#L342-5 is_transmit2_triggered_~__retres1~2#1 := 0; 394103#L353-1 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 394101#is_transmit2_triggered_returnLabel#2 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 394099#L771-3 assume !(0 != activate_threads_~tmp___1~0#1); 394097#L771-5 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 394095#L361-3 assume 1 == ~t3_pc~0; 394092#L362-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 394089#L372-1 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 394087#is_transmit3_triggered_returnLabel#2 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 394081#L779-3 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 394079#L779-5 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 394077#L380-3 assume !(1 == ~t4_pc~0); 394075#L380-5 is_transmit4_triggered_~__retres1~4#1 := 0; 394073#L391-1 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 394071#is_transmit4_triggered_returnLabel#2 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 394069#L787-3 assume !(0 != activate_threads_~tmp___3~0#1); 394067#L787-5 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 394065#L399-3 assume 1 == ~t5_pc~0; 394062#L400-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 394059#L410-1 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 394057#is_transmit5_triggered_returnLabel#2 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 394056#L795-3 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 394053#L795-5 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true; 394047#immediate_notify_returnLabel#1 assume { :end_inline_immediate_notify } true;~E_1~0 := 2;~m_pc~0 := 1;~m_st~0 := 2; 394046#master_returnLabel#1 havoc master_#t~nondet4#1, master_#t~nondet5#1, master_~tmp_var~0#1;assume { :end_inline_master } true; 394041#L519-2 havoc eval_~tmp_ndt_1~0#1; 394039#L516-1 assume !(0 == ~t1_st~0); 394034#L530-1 assume !(0 == ~t2_st~0); 394031#L544-1 assume !(0 == ~t3_st~0); 394025#L558-1 assume !(0 == ~t4_st~0); 394022#L572-1 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0#1;havoc eval_#t~nondet12#1;eval_~tmp_ndt_6~0#1 := eval_#t~nondet12#1;havoc eval_#t~nondet12#1; 393851#L589 assume 0 != eval_~tmp_ndt_6~0#1;~t5_st~0 := 1;assume { :begin_inline_transmit5 } true; 394018#L268 assume 0 == ~t5_pc~0; 394014#L279-1 assume !false; 394012#L280 ~t5_pc~0 := 1;~t5_st~0 := 2; 394009#transmit5_returnLabel#1 assume { :end_inline_transmit5 } true; 393849#L589-2 havoc eval_~tmp_ndt_6~0#1; 393847#L586-1 assume !false; 393845#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 393843#L464 assume !(0 == ~m_st~0); 393839#L468 assume !(0 == ~t1_st~0); 393835#L472 assume !(0 == ~t2_st~0); 393831#L476 assume !(0 == ~t3_st~0); 393826#L480 assume !(0 == ~t4_st~0); 393820#L484 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 393818#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 393816#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 393813#L511 assume !(0 != eval_~tmp~0#1); 393811#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 393809#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 393807#L611-3 assume !(0 == ~M_E~0); 393804#L611-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 393801#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 393799#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 393797#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 393794#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 393792#L636-3 assume !(0 == ~E_M~0); 393790#L641-3 assume !(0 == ~E_1~0); 393788#L646-3 assume !(0 == ~E_2~0); 393786#L651-3 assume !(0 == ~E_3~0); 393782#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 393780#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 393778#L666-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 393775#L304-21 assume 1 == ~m_pc~0; 393746#L305-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 393744#L315-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 393741#is_master_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 393738#L755-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 393736#L755-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 393733#L323-21 assume !(1 == ~t1_pc~0); 393731#L323-23 is_transmit1_triggered_~__retres1~1#1 := 0; 393729#L334-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 393728#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 393727#L763-21 assume !(0 != activate_threads_~tmp___0~0#1); 393726#L763-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 393723#L342-21 assume !(1 == ~t2_pc~0); 393720#L342-23 is_transmit2_triggered_~__retres1~2#1 := 0; 393718#L353-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 393716#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 393714#L771-21 assume !(0 != activate_threads_~tmp___1~0#1); 390244#L771-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 390240#L361-21 assume !(1 == ~t3_pc~0); 390236#L361-23 is_transmit3_triggered_~__retres1~3#1 := 0; 390234#L372-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 390232#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 390229#L779-21 assume !(0 != activate_threads_~tmp___2~0#1); 390226#L779-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 390222#L380-21 assume !(1 == ~t4_pc~0); 390220#L380-23 is_transmit4_triggered_~__retres1~4#1 := 0; 390218#L391-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 390216#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 390213#L787-21 assume !(0 != activate_threads_~tmp___3~0#1); 390211#L787-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 390209#L399-21 assume 1 == ~t5_pc~0; 390205#L400-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 390203#L410-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 390201#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 390197#L795-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 390198#L795-23 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 409281#L679-3 assume !(1 == ~M_E~0); 409277#L679-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 409275#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 409273#L689-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 409271#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 409269#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 409267#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 409265#L709-3 assume !(1 == ~E_1~0); 409263#L714-3 assume !(1 == ~E_2~0); 409261#L719-3 assume !(1 == ~E_3~0); 409257#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 409254#L729-3 assume 1 == ~E_5~0;~E_5~0 := 2; 409252#L734-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 409250#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 409248#L496-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 409246#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 409244#L959 assume !(0 == start_simulation_~tmp~3#1); 409241#L959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 409239#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 409224#L496-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 409218#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 409127#L914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 409126#L921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 409125#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 409123#L972 assume !(0 != start_simulation_~tmp___0~1#1); 409080#L940-2 assume !false; 374275#L941 [2024-11-08 00:35:10,915 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:10,915 INFO L85 PathProgramCache]: Analyzing trace with hash 959436207, now seen corresponding path program 2 times [2024-11-08 00:35:10,915 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:10,916 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1965413156] [2024-11-08 00:35:10,916 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:10,916 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:10,926 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:35:10,926 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 00:35:10,933 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:35:10,950 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 00:35:10,950 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:10,951 INFO L85 PathProgramCache]: Analyzing trace with hash -1043454138, now seen corresponding path program 1 times [2024-11-08 00:35:10,951 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:10,951 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [618829538] [2024-11-08 00:35:10,951 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:10,951 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:10,962 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:10,999 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:11,000 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:11,000 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [618829538] [2024-11-08 00:35:11,000 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [618829538] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:11,000 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:11,000 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:11,001 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [599392042] [2024-11-08 00:35:11,001 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:11,001 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:35:11,001 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:35:11,001 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:35:11,002 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:35:11,002 INFO L87 Difference]: Start difference. First operand 53204 states and 70101 transitions. cyclomatic complexity: 16909 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:11,402 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:35:11,403 INFO L93 Difference]: Finished difference Result 62170 states and 81120 transitions. [2024-11-08 00:35:11,403 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 62170 states and 81120 transitions. [2024-11-08 00:35:11,638 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 42188 [2024-11-08 00:35:12,018 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 62170 states to 62170 states and 81120 transitions. [2024-11-08 00:35:12,019 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 42589 [2024-11-08 00:35:12,046 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 42589 [2024-11-08 00:35:12,047 INFO L73 IsDeterministic]: Start isDeterministic. Operand 62170 states and 81120 transitions. [2024-11-08 00:35:12,048 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-08 00:35:12,048 INFO L218 hiAutomatonCegarLoop]: Abstraction has 62170 states and 81120 transitions. [2024-11-08 00:35:12,090 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 62170 states and 81120 transitions. [2024-11-08 00:35:12,675 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 62170 to 57754. [2024-11-08 00:35:12,737 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 57754 states, 57754 states have (on average 1.3114935762025142) internal successors, (75744), 57753 states have internal predecessors, (75744), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:12,843 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 57754 states to 57754 states and 75744 transitions. [2024-11-08 00:35:12,844 INFO L240 hiAutomatonCegarLoop]: Abstraction has 57754 states and 75744 transitions. [2024-11-08 00:35:12,844 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:35:12,845 INFO L425 stractBuchiCegarLoop]: Abstraction has 57754 states and 75744 transitions. [2024-11-08 00:35:12,845 INFO L332 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2024-11-08 00:35:12,845 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 57754 states and 75744 transitions. [2024-11-08 00:35:13,249 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 39244 [2024-11-08 00:35:13,249 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:35:13,249 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:35:13,250 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:13,250 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:13,250 INFO L745 eck$LassoCheckResult]: Stem: 484060#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 484061#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 484284#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 484285#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 484252#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 484253#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 483942#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 483943#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 483902#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 483903#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 484433#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 484112#L611 assume !(0 == ~M_E~0); 484113#L611-2 assume !(0 == ~T1_E~0); 484462#L616-1 assume !(0 == ~T2_E~0); 484463#L621-1 assume !(0 == ~T3_E~0); 483651#L626-1 assume !(0 == ~T4_E~0); 483652#L631-1 assume !(0 == ~T5_E~0); 484017#L636-1 assume !(0 == ~E_M~0); 483742#L641-1 assume !(0 == ~E_1~0); 483743#L646-1 assume !(0 == ~E_2~0); 484052#L651-1 assume !(0 == ~E_3~0); 484551#L656-1 assume !(0 == ~E_4~0); 484431#L661-1 assume !(0 == ~E_5~0); 484432#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 484500#L304 assume !(1 == ~m_pc~0); 483793#L304-2 is_master_triggered_~__retres1~0#1 := 0; 483614#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 483615#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 483534#L755 assume !(0 != activate_threads_~tmp~1#1); 483535#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 483461#L323 assume !(1 == ~t1_pc~0); 483462#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 483563#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 483564#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 483588#L763 assume !(0 != activate_threads_~tmp___0~0#1); 484631#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 483567#L342 assume !(1 == ~t2_pc~0); 483569#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 483807#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 483808#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 484290#L771 assume !(0 != activate_threads_~tmp___1~0#1); 484418#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 484181#L361 assume !(1 == ~t3_pc~0); 484182#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 484232#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 484583#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 484544#L779 assume !(0 != activate_threads_~tmp___2~0#1); 483593#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 483594#L380 assume !(1 == ~t4_pc~0); 484180#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 484448#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 483731#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 483732#L787 assume !(0 != activate_threads_~tmp___3~0#1); 484259#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 483694#L399 assume !(1 == ~t5_pc~0); 483695#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 483960#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 483974#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 483944#L795 assume !(0 != activate_threads_~tmp___4~0#1); 483945#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 484575#L679 assume !(1 == ~M_E~0); 484109#L679-2 assume !(1 == ~T1_E~0); 483830#L684-1 assume !(1 == ~T2_E~0); 483831#L689-1 assume !(1 == ~T3_E~0); 484196#L694-1 assume !(1 == ~T4_E~0); 484194#L699-1 assume !(1 == ~T5_E~0); 484195#L704-1 assume !(1 == ~E_M~0); 484160#L709-1 assume !(1 == ~E_1~0); 484026#L714-1 assume !(1 == ~E_2~0); 484027#L719-1 assume !(1 == ~E_3~0); 484408#L724-1 assume !(1 == ~E_4~0); 483629#L729-1 assume !(1 == ~E_5~0); 483630#L734-1 assume { :end_inline_reset_delta_events } true; 484584#L940-2 assume !false; 485520#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 502516#L586-1 [2024-11-08 00:35:13,250 INFO L747 eck$LassoCheckResult]: Loop: 502516#L586-1 assume !false; 508662#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 508661#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 508660#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 508659#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 508658#L511 assume 0 != eval_~tmp~0#1; 508657#L511-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 508655#L519 assume !(0 != eval_~tmp_ndt_1~0#1); 508654#L519-2 havoc eval_~tmp_ndt_1~0#1; 508652#L516-1 assume !(0 == ~t1_st~0); 508649#L530-1 assume !(0 == ~t2_st~0); 508646#L544-1 assume !(0 == ~t3_st~0); 508643#L558-1 assume !(0 == ~t4_st~0); 508641#L572-1 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0#1;havoc eval_#t~nondet12#1;eval_~tmp_ndt_6~0#1 := eval_#t~nondet12#1;havoc eval_#t~nondet12#1; 508551#L589 assume !(0 != eval_~tmp_ndt_6~0#1); 508640#L589-2 havoc eval_~tmp_ndt_6~0#1; 502516#L586-1 [2024-11-08 00:35:13,250 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:13,250 INFO L85 PathProgramCache]: Analyzing trace with hash -322248313, now seen corresponding path program 1 times [2024-11-08 00:35:13,250 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:13,250 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2053435553] [2024-11-08 00:35:13,251 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:13,251 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:13,263 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:35:13,263 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 00:35:13,269 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:35:13,278 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 00:35:13,279 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:13,279 INFO L85 PathProgramCache]: Analyzing trace with hash -1215291021, now seen corresponding path program 1 times [2024-11-08 00:35:13,279 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:13,279 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1379668068] [2024-11-08 00:35:13,279 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:13,280 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:13,283 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:35:13,283 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 00:35:13,287 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:35:13,289 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 00:35:13,290 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:13,290 INFO L85 PathProgramCache]: Analyzing trace with hash 1432565497, now seen corresponding path program 1 times [2024-11-08 00:35:13,290 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:13,290 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1672280877] [2024-11-08 00:35:13,290 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:13,290 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:13,302 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:13,330 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:13,330 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:13,330 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1672280877] [2024-11-08 00:35:13,330 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1672280877] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:13,330 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:13,330 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:13,331 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1263609132] [2024-11-08 00:35:13,331 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:13,394 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:35:13,395 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:35:13,395 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:35:13,395 INFO L87 Difference]: Start difference. First operand 57754 states and 75744 transitions. cyclomatic complexity: 18014 Second operand has 3 states, 3 states have (on average 30.333333333333332) internal successors, (91), 3 states have internal predecessors, (91), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:13,839 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:35:13,839 INFO L93 Difference]: Finished difference Result 100454 states and 130307 transitions. [2024-11-08 00:35:13,839 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 100454 states and 130307 transitions. [2024-11-08 00:35:14,363 INFO L131 ngComponentsAnalysis]: Automaton has 28 accepting balls. 66728 [2024-11-08 00:35:14,656 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 100454 states to 100454 states and 130307 transitions. [2024-11-08 00:35:14,657 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 69284 [2024-11-08 00:35:14,708 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 69284 [2024-11-08 00:35:14,708 INFO L73 IsDeterministic]: Start isDeterministic. Operand 100454 states and 130307 transitions. [2024-11-08 00:35:14,709 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-08 00:35:14,710 INFO L218 hiAutomatonCegarLoop]: Abstraction has 100454 states and 130307 transitions. [2024-11-08 00:35:14,791 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 100454 states and 130307 transitions. [2024-11-08 00:35:15,677 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 100454 to 100454. [2024-11-08 00:35:15,762 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 100454 states, 100454 states have (on average 1.29718079917176) internal successors, (130307), 100453 states have internal predecessors, (130307), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:15,970 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 100454 states to 100454 states and 130307 transitions. [2024-11-08 00:35:15,970 INFO L240 hiAutomatonCegarLoop]: Abstraction has 100454 states and 130307 transitions. [2024-11-08 00:35:15,971 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:35:15,971 INFO L425 stractBuchiCegarLoop]: Abstraction has 100454 states and 130307 transitions. [2024-11-08 00:35:15,971 INFO L332 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2024-11-08 00:35:15,971 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 100454 states and 130307 transitions. [2024-11-08 00:35:16,217 INFO L131 ngComponentsAnalysis]: Automaton has 28 accepting balls. 66728 [2024-11-08 00:35:16,218 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:35:16,218 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:35:16,218 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:16,218 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:16,219 INFO L745 eck$LassoCheckResult]: Stem: 642273#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 642274#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 642495#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 642496#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 642462#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 642463#L426-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 642157#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 642158#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 642120#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 642121#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 642645#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 642323#L611 assume !(0 == ~M_E~0); 642324#L611-2 assume !(0 == ~T1_E~0); 642676#L616-1 assume !(0 == ~T2_E~0); 642677#L621-1 assume !(0 == ~T3_E~0); 641869#L626-1 assume !(0 == ~T4_E~0); 641870#L631-1 assume !(0 == ~T5_E~0); 642233#L636-1 assume !(0 == ~E_M~0); 641960#L641-1 assume !(0 == ~E_1~0); 641961#L646-1 assume !(0 == ~E_2~0); 642268#L651-1 assume !(0 == ~E_3~0); 642781#L656-1 assume !(0 == ~E_4~0); 642643#L661-1 assume !(0 == ~E_5~0); 642644#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 642727#L304 assume !(1 == ~m_pc~0); 642012#L304-2 is_master_triggered_~__retres1~0#1 := 0; 641832#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 641833#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 641751#L755 assume !(0 != activate_threads_~tmp~1#1); 641752#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 641677#L323 assume !(1 == ~t1_pc~0); 641678#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 641780#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 641781#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 641804#L763 assume !(0 != activate_threads_~tmp___0~0#1); 642849#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 641784#L342 assume !(1 == ~t2_pc~0); 641786#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 642027#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 642028#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 642501#L771 assume !(0 != activate_threads_~tmp___1~0#1); 642638#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 642393#L361 assume !(1 == ~t3_pc~0); 642394#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 653169#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 653168#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 652719#L779 assume !(0 != activate_threads_~tmp___2~0#1); 641809#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 641810#L380 assume !(1 == ~t4_pc~0); 642392#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 642896#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 652706#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 652704#L787 assume !(0 != activate_threads_~tmp___3~0#1); 652702#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 641913#L399 assume !(1 == ~t5_pc~0); 641914#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 642176#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 642188#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 642159#L795 assume !(0 != activate_threads_~tmp___4~0#1); 642160#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 642805#L679 assume !(1 == ~M_E~0); 642320#L679-2 assume !(1 == ~T1_E~0); 642050#L684-1 assume !(1 == ~T2_E~0); 642051#L689-1 assume !(1 == ~T3_E~0); 642411#L694-1 assume !(1 == ~T4_E~0); 642409#L699-1 assume !(1 == ~T5_E~0); 642410#L704-1 assume !(1 == ~E_M~0); 642370#L709-1 assume !(1 == ~E_1~0); 642242#L714-1 assume !(1 == ~E_2~0); 642243#L719-1 assume !(1 == ~E_3~0); 642628#L724-1 assume !(1 == ~E_4~0); 641847#L729-1 assume !(1 == ~E_5~0); 641848#L734-1 assume { :end_inline_reset_delta_events } true; 642817#L940-2 assume !false; 655966#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 703576#L586-1 [2024-11-08 00:35:16,219 INFO L747 eck$LassoCheckResult]: Loop: 703576#L586-1 assume !false; 707540#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 707538#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 707536#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 707534#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 707532#L511 assume 0 != eval_~tmp~0#1; 707530#L511-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 707527#L519 assume !(0 != eval_~tmp_ndt_1~0#1); 707525#L519-2 havoc eval_~tmp_ndt_1~0#1; 707523#L516-1 assume !(0 == ~t1_st~0); 707520#L530-1 assume !(0 == ~t2_st~0); 707521#L544-1 assume !(0 == ~t3_st~0); 707609#L558-1 assume !(0 == ~t4_st~0); 707547#L572-1 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0#1;havoc eval_#t~nondet12#1;eval_~tmp_ndt_6~0#1 := eval_#t~nondet12#1;havoc eval_#t~nondet12#1; 707544#L589 assume !(0 != eval_~tmp_ndt_6~0#1); 703577#L589-2 havoc eval_~tmp_ndt_6~0#1; 703576#L586-1 [2024-11-08 00:35:16,219 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:16,220 INFO L85 PathProgramCache]: Analyzing trace with hash 1586209477, now seen corresponding path program 1 times [2024-11-08 00:35:16,220 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:16,220 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [626891708] [2024-11-08 00:35:16,220 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:16,220 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:16,227 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:16,244 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:16,244 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:16,244 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [626891708] [2024-11-08 00:35:16,244 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [626891708] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:16,244 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:16,244 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:16,244 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [319208233] [2024-11-08 00:35:16,245 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:16,245 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:35:16,245 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:16,245 INFO L85 PathProgramCache]: Analyzing trace with hash -1215291021, now seen corresponding path program 2 times [2024-11-08 00:35:16,245 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:16,245 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [52449828] [2024-11-08 00:35:16,245 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:16,246 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:16,249 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:35:16,249 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 00:35:16,251 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:35:16,252 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 00:35:16,307 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:35:16,307 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:35:16,307 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:35:16,307 INFO L87 Difference]: Start difference. First operand 100454 states and 130307 transitions. cyclomatic complexity: 29895 Second operand has 3 states, 3 states have (on average 25.0) internal successors, (75), 3 states have internal predecessors, (75), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:16,798 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:35:16,798 INFO L93 Difference]: Finished difference Result 63952 states and 82768 transitions. [2024-11-08 00:35:16,798 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 63952 states and 82768 transitions. [2024-11-08 00:35:17,046 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 43732 [2024-11-08 00:35:17,170 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 63952 states to 63952 states and 82768 transitions. [2024-11-08 00:35:17,170 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 44125 [2024-11-08 00:35:17,199 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 44125 [2024-11-08 00:35:17,199 INFO L73 IsDeterministic]: Start isDeterministic. Operand 63952 states and 82768 transitions. [2024-11-08 00:35:17,200 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-08 00:35:17,200 INFO L218 hiAutomatonCegarLoop]: Abstraction has 63952 states and 82768 transitions. [2024-11-08 00:35:17,244 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 63952 states and 82768 transitions. [2024-11-08 00:35:17,821 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 63952 to 63952. [2024-11-08 00:35:17,873 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 63952 states, 63952 states have (on average 1.2942206654991244) internal successors, (82768), 63951 states have internal predecessors, (82768), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:17,948 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 63952 states to 63952 states and 82768 transitions. [2024-11-08 00:35:17,949 INFO L240 hiAutomatonCegarLoop]: Abstraction has 63952 states and 82768 transitions. [2024-11-08 00:35:17,949 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:35:17,949 INFO L425 stractBuchiCegarLoop]: Abstraction has 63952 states and 82768 transitions. [2024-11-08 00:35:17,949 INFO L332 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2024-11-08 00:35:17,949 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 63952 states and 82768 transitions. [2024-11-08 00:35:18,092 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 43732 [2024-11-08 00:35:18,093 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:35:18,093 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:35:18,093 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:18,093 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:18,094 INFO L745 eck$LassoCheckResult]: Stem: 806680#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 806681#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 806897#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 806898#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 806865#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 806866#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 806566#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 806567#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 806528#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 806529#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 807047#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 806729#L611 assume !(0 == ~M_E~0); 806730#L611-2 assume !(0 == ~T1_E~0); 807085#L616-1 assume !(0 == ~T2_E~0); 807086#L621-1 assume !(0 == ~T3_E~0); 806288#L626-1 assume !(0 == ~T4_E~0); 806289#L631-1 assume !(0 == ~T5_E~0); 806645#L636-1 assume !(0 == ~E_M~0); 806375#L641-1 assume !(0 == ~E_1~0); 806376#L646-1 assume !(0 == ~E_2~0); 806672#L651-1 assume !(0 == ~E_3~0); 807182#L656-1 assume !(0 == ~E_4~0); 807045#L661-1 assume !(0 == ~E_5~0); 807046#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 807128#L304 assume !(1 == ~m_pc~0); 806431#L304-2 is_master_triggered_~__retres1~0#1 := 0; 806241#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 806242#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 806170#L755 assume !(0 != activate_threads_~tmp~1#1); 806171#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 806095#L323 assume !(1 == ~t1_pc~0); 806096#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 806190#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 806191#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 806215#L763 assume !(0 != activate_threads_~tmp___0~0#1); 807255#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 806206#L342 assume !(1 == ~t2_pc~0); 806208#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 806434#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 806435#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 806902#L771 assume !(0 != activate_threads_~tmp___1~0#1); 807039#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 806798#L361 assume !(1 == ~t3_pc~0); 806799#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 806849#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 807216#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 807174#L779 assume !(0 != activate_threads_~tmp___2~0#1); 806226#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 806227#L380 assume !(1 == ~t4_pc~0); 806797#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 807070#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 806369#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 806370#L787 assume !(0 != activate_threads_~tmp___3~0#1); 806869#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 806322#L399 assume !(1 == ~t5_pc~0); 806323#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 806587#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 806596#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 806568#L795 assume !(0 != activate_threads_~tmp___4~0#1); 806569#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 807204#L679 assume !(1 == ~M_E~0); 806728#L679-2 assume !(1 == ~T1_E~0); 806457#L684-1 assume !(1 == ~T2_E~0); 806458#L689-1 assume !(1 == ~T3_E~0); 806813#L694-1 assume !(1 == ~T4_E~0); 806811#L699-1 assume !(1 == ~T5_E~0); 806812#L704-1 assume !(1 == ~E_M~0); 806778#L709-1 assume !(1 == ~E_1~0); 806652#L714-1 assume !(1 == ~E_2~0); 806653#L719-1 assume !(1 == ~E_3~0); 807031#L724-1 assume !(1 == ~E_4~0); 806256#L729-1 assume !(1 == ~E_5~0); 806257#L734-1 assume { :end_inline_reset_delta_events } true; 807219#L940-2 assume !false; 817901#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 832110#L586-1 [2024-11-08 00:35:18,094 INFO L747 eck$LassoCheckResult]: Loop: 832110#L586-1 assume !false; 832108#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 832107#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 830736#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 830734#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 830732#L511 assume 0 != eval_~tmp~0#1; 830730#L511-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 830727#L519 assume !(0 != eval_~tmp_ndt_1~0#1); 830725#L519-2 havoc eval_~tmp_ndt_1~0#1; 830723#L516-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 830718#L533 assume !(0 != eval_~tmp_ndt_2~0#1); 830716#L533-2 havoc eval_~tmp_ndt_2~0#1; 830713#L530-1 assume !(0 == ~t2_st~0); 830709#L544-1 assume !(0 == ~t3_st~0); 830705#L558-1 assume !(0 == ~t4_st~0); 830702#L572-1 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0#1;havoc eval_#t~nondet12#1;eval_~tmp_ndt_6~0#1 := eval_#t~nondet12#1;havoc eval_#t~nondet12#1; 830671#L589 assume !(0 != eval_~tmp_ndt_6~0#1); 830700#L589-2 havoc eval_~tmp_ndt_6~0#1; 832110#L586-1 [2024-11-08 00:35:18,094 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:18,094 INFO L85 PathProgramCache]: Analyzing trace with hash -322248313, now seen corresponding path program 2 times [2024-11-08 00:35:18,094 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:18,094 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [702759265] [2024-11-08 00:35:18,094 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:18,095 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:18,103 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:35:18,103 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 00:35:18,112 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:35:18,122 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 00:35:18,122 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:18,123 INFO L85 PathProgramCache]: Analyzing trace with hash 1778465603, now seen corresponding path program 1 times [2024-11-08 00:35:18,123 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:18,123 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [246065714] [2024-11-08 00:35:18,123 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:18,123 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:18,127 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:35:18,127 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 00:35:18,128 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:35:18,130 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 00:35:18,130 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:18,130 INFO L85 PathProgramCache]: Analyzing trace with hash -547027127, now seen corresponding path program 1 times [2024-11-08 00:35:18,131 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:18,131 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1109963055] [2024-11-08 00:35:18,131 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:18,131 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:18,140 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:18,162 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:18,162 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:18,162 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1109963055] [2024-11-08 00:35:18,162 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1109963055] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:18,162 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:18,163 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:18,163 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1612417486] [2024-11-08 00:35:18,163 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:18,224 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:35:18,224 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:35:18,225 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:35:18,225 INFO L87 Difference]: Start difference. First operand 63952 states and 82768 transitions. cyclomatic complexity: 18840 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:18,898 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:35:18,898 INFO L93 Difference]: Finished difference Result 114830 states and 147469 transitions. [2024-11-08 00:35:18,898 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 114830 states and 147469 transitions. [2024-11-08 00:35:19,347 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 77328 [2024-11-08 00:35:19,604 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 114830 states to 114830 states and 147469 transitions. [2024-11-08 00:35:19,605 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 78033 [2024-11-08 00:35:19,651 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 78033 [2024-11-08 00:35:19,651 INFO L73 IsDeterministic]: Start isDeterministic. Operand 114830 states and 147469 transitions. [2024-11-08 00:35:19,651 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-08 00:35:19,651 INFO L218 hiAutomatonCegarLoop]: Abstraction has 114830 states and 147469 transitions. [2024-11-08 00:35:19,719 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 114830 states and 147469 transitions. [2024-11-08 00:35:20,735 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 114830 to 114830. [2024-11-08 00:35:20,829 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 114830 states, 114830 states have (on average 1.2842375685796394) internal successors, (147469), 114829 states have internal predecessors, (147469), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:20,987 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 114830 states to 114830 states and 147469 transitions. [2024-11-08 00:35:20,987 INFO L240 hiAutomatonCegarLoop]: Abstraction has 114830 states and 147469 transitions. [2024-11-08 00:35:20,988 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:35:20,988 INFO L425 stractBuchiCegarLoop]: Abstraction has 114830 states and 147469 transitions. [2024-11-08 00:35:20,988 INFO L332 stractBuchiCegarLoop]: ======== Iteration 27 ============ [2024-11-08 00:35:20,988 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 114830 states and 147469 transitions. [2024-11-08 00:35:21,661 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 77328 [2024-11-08 00:35:21,661 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:35:21,661 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:35:21,662 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:21,662 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:21,662 INFO L745 eck$LassoCheckResult]: Stem: 985474#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 985475#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 985706#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 985707#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 985675#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 985676#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 985365#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 985366#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 985325#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 985326#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 985856#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 985523#L611 assume !(0 == ~M_E~0); 985524#L611-2 assume !(0 == ~T1_E~0); 985892#L616-1 assume !(0 == ~T2_E~0); 985893#L621-1 assume !(0 == ~T3_E~0); 985070#L626-1 assume !(0 == ~T4_E~0); 985071#L631-1 assume !(0 == ~T5_E~0); 985436#L636-1 assume !(0 == ~E_M~0); 985164#L641-1 assume !(0 == ~E_1~0); 985165#L646-1 assume !(0 == ~E_2~0); 985469#L651-1 assume !(0 == ~E_3~0); 985991#L656-1 assume !(0 == ~E_4~0); 985854#L661-1 assume !(0 == ~E_5~0); 985855#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 985940#L304 assume !(1 == ~m_pc~0); 985216#L304-2 is_master_triggered_~__retres1~0#1 := 0; 985033#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 985034#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 984952#L755 assume !(0 != activate_threads_~tmp~1#1); 984953#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 984879#L323 assume !(1 == ~t1_pc~0); 984880#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 984981#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 984982#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 985006#L763 assume !(0 != activate_threads_~tmp___0~0#1); 986070#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 984985#L342 assume !(1 == ~t2_pc~0); 984987#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 985229#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 985230#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 985712#L771 assume !(0 != activate_threads_~tmp___1~0#1); 985847#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 985605#L361 assume !(1 == ~t3_pc~0); 985606#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 985660#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 986022#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 985984#L779 assume !(0 != activate_threads_~tmp___2~0#1); 985011#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 985012#L380 assume !(1 == ~t4_pc~0); 985604#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 985874#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 985154#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 985155#L787 assume !(0 != activate_threads_~tmp___3~0#1); 985680#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 985114#L399 assume !(1 == ~t5_pc~0); 985115#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 985382#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 985394#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 985367#L795 assume !(0 != activate_threads_~tmp___4~0#1); 985368#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 986015#L679 assume !(1 == ~M_E~0); 985520#L679-2 assume !(1 == ~T1_E~0); 985253#L684-1 assume !(1 == ~T2_E~0); 985254#L689-1 assume !(1 == ~T3_E~0); 985620#L694-1 assume !(1 == ~T4_E~0); 985618#L699-1 assume !(1 == ~T5_E~0); 985619#L704-1 assume !(1 == ~E_M~0); 985582#L709-1 assume !(1 == ~E_1~0); 985444#L714-1 assume !(1 == ~E_2~0); 985445#L719-1 assume !(1 == ~E_3~0); 985837#L724-1 assume !(1 == ~E_4~0); 985048#L729-1 assume !(1 == ~E_5~0); 985049#L734-1 assume { :end_inline_reset_delta_events } true; 986023#L940-2 assume !false; 1002266#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1069461#L586-1 [2024-11-08 00:35:21,662 INFO L747 eck$LassoCheckResult]: Loop: 1069461#L586-1 assume !false; 1069459#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1069457#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1069455#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1069453#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1069436#L511 assume 0 != eval_~tmp~0#1; 1069430#L511-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 1069419#L519 assume !(0 != eval_~tmp_ndt_1~0#1); 1069420#L519-2 havoc eval_~tmp_ndt_1~0#1; 1089903#L516-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 1089901#L533 assume !(0 != eval_~tmp_ndt_2~0#1); 1089900#L533-2 havoc eval_~tmp_ndt_2~0#1; 1039311#L530-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 1039309#L547 assume !(0 != eval_~tmp_ndt_3~0#1); 1039310#L547-2 havoc eval_~tmp_ndt_3~0#1; 1069404#L544-1 assume !(0 == ~t3_st~0); 1069397#L558-1 assume !(0 == ~t4_st~0); 1069398#L572-1 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0#1;havoc eval_#t~nondet12#1;eval_~tmp_ndt_6~0#1 := eval_#t~nondet12#1;havoc eval_#t~nondet12#1; 1069465#L589 assume !(0 != eval_~tmp_ndt_6~0#1); 1069463#L589-2 havoc eval_~tmp_ndt_6~0#1; 1069461#L586-1 [2024-11-08 00:35:21,663 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:21,663 INFO L85 PathProgramCache]: Analyzing trace with hash -322248313, now seen corresponding path program 3 times [2024-11-08 00:35:21,663 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:21,663 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1982648776] [2024-11-08 00:35:21,663 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:21,663 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:21,673 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:35:21,673 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 00:35:21,678 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:35:21,685 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 00:35:21,686 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:21,689 INFO L85 PathProgramCache]: Analyzing trace with hash -911626445, now seen corresponding path program 1 times [2024-11-08 00:35:21,689 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:21,689 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1121265086] [2024-11-08 00:35:21,689 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:21,689 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:21,692 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:35:21,694 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 00:35:21,696 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:35:21,697 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 00:35:21,698 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:21,698 INFO L85 PathProgramCache]: Analyzing trace with hash 1967821241, now seen corresponding path program 1 times [2024-11-08 00:35:21,698 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:21,699 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1854848349] [2024-11-08 00:35:21,699 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:21,699 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:21,706 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:21,730 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:21,731 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:21,731 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1854848349] [2024-11-08 00:35:21,731 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1854848349] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:21,731 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:21,731 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:21,731 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1509964780] [2024-11-08 00:35:21,731 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:21,793 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:35:21,794 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:35:21,794 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:35:21,794 INFO L87 Difference]: Start difference. First operand 114830 states and 147469 transitions. cyclomatic complexity: 32663 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:22,479 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:35:22,480 INFO L93 Difference]: Finished difference Result 208054 states and 266787 transitions. [2024-11-08 00:35:22,480 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 208054 states and 266787 transitions. [2024-11-08 00:35:23,652 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 140312 [2024-11-08 00:35:24,086 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 208054 states to 208054 states and 266787 transitions. [2024-11-08 00:35:24,086 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 141641 [2024-11-08 00:35:24,519 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 141641 [2024-11-08 00:35:24,519 INFO L73 IsDeterministic]: Start isDeterministic. Operand 208054 states and 266787 transitions. [2024-11-08 00:35:24,519 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-08 00:35:24,519 INFO L218 hiAutomatonCegarLoop]: Abstraction has 208054 states and 266787 transitions. [2024-11-08 00:35:24,634 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 208054 states and 266787 transitions. [2024-11-08 00:35:26,220 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 208054 to 197566. [2024-11-08 00:35:26,365 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 197566 states, 197566 states have (on average 1.2847099197230292) internal successors, (253815), 197565 states have internal predecessors, (253815), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:26,626 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 197566 states to 197566 states and 253815 transitions. [2024-11-08 00:35:26,626 INFO L240 hiAutomatonCegarLoop]: Abstraction has 197566 states and 253815 transitions. [2024-11-08 00:35:26,627 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:35:26,627 INFO L425 stractBuchiCegarLoop]: Abstraction has 197566 states and 253815 transitions. [2024-11-08 00:35:26,627 INFO L332 stractBuchiCegarLoop]: ======== Iteration 28 ============ [2024-11-08 00:35:26,627 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 197566 states and 253815 transitions. [2024-11-08 00:35:27,598 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 133320 [2024-11-08 00:35:27,598 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:35:27,598 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:35:27,599 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:27,599 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:27,599 INFO L745 eck$LassoCheckResult]: Stem: 1308377#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 1308378#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 1308620#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1308621#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1308582#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 1308583#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1308256#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1308257#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1308217#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1308218#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1308795#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1308427#L611 assume !(0 == ~M_E~0); 1308428#L611-2 assume !(0 == ~T1_E~0); 1308831#L616-1 assume !(0 == ~T2_E~0); 1308832#L621-1 assume !(0 == ~T3_E~0); 1307959#L626-1 assume !(0 == ~T4_E~0); 1307960#L631-1 assume !(0 == ~T5_E~0); 1308332#L636-1 assume !(0 == ~E_M~0); 1308054#L641-1 assume !(0 == ~E_1~0); 1308055#L646-1 assume !(0 == ~E_2~0); 1308371#L651-1 assume !(0 == ~E_3~0); 1308943#L656-1 assume !(0 == ~E_4~0); 1308793#L661-1 assume !(0 == ~E_5~0); 1308794#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1308879#L304 assume !(1 == ~m_pc~0); 1308105#L304-2 is_master_triggered_~__retres1~0#1 := 0; 1307922#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1307923#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1307844#L755 assume !(0 != activate_threads_~tmp~1#1); 1307845#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1307771#L323 assume !(1 == ~t1_pc~0); 1307772#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1307872#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1307873#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1307897#L763 assume !(0 != activate_threads_~tmp___0~0#1); 1309035#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1307876#L342 assume !(1 == ~t2_pc~0); 1307878#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1308119#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1308120#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1308626#L771 assume !(0 != activate_threads_~tmp___1~0#1); 1308785#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1308505#L361 assume !(1 == ~t3_pc~0); 1308506#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1308561#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1308980#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1308929#L779 assume !(0 != activate_threads_~tmp___2~0#1); 1307902#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1307903#L380 assume !(1 == ~t4_pc~0); 1308504#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1308814#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1308042#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1308043#L787 assume !(0 != activate_threads_~tmp___3~0#1); 1308589#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1308003#L399 assume !(1 == ~t5_pc~0); 1308004#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1308275#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1308287#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1308258#L795 assume !(0 != activate_threads_~tmp___4~0#1); 1308259#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1308966#L679 assume !(1 == ~M_E~0); 1308424#L679-2 assume !(1 == ~T1_E~0); 1308144#L684-1 assume !(1 == ~T2_E~0); 1308145#L689-1 assume !(1 == ~T3_E~0); 1308523#L694-1 assume !(1 == ~T4_E~0); 1308521#L699-1 assume !(1 == ~T5_E~0); 1308522#L704-1 assume !(1 == ~E_M~0); 1308486#L709-1 assume !(1 == ~E_1~0); 1308342#L714-1 assume !(1 == ~E_2~0); 1308343#L719-1 assume !(1 == ~E_3~0); 1308770#L724-1 assume !(1 == ~E_4~0); 1307937#L729-1 assume !(1 == ~E_5~0); 1307938#L734-1 assume { :end_inline_reset_delta_events } true; 1308983#L940-2 assume !false; 1323617#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1438223#L586-1 [2024-11-08 00:35:27,600 INFO L747 eck$LassoCheckResult]: Loop: 1438223#L586-1 assume !false; 1438222#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1438221#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1438220#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1438219#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1438218#L511 assume 0 != eval_~tmp~0#1; 1438217#L511-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 1438214#L519 assume !(0 != eval_~tmp_ndt_1~0#1); 1438212#L519-2 havoc eval_~tmp_ndt_1~0#1; 1438210#L516-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 1438207#L533 assume !(0 != eval_~tmp_ndt_2~0#1); 1438205#L533-2 havoc eval_~tmp_ndt_2~0#1; 1438203#L530-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 1438187#L547 assume !(0 != eval_~tmp_ndt_3~0#1); 1438201#L547-2 havoc eval_~tmp_ndt_3~0#1; 1438474#L544-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet10#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 1438084#L561 assume !(0 != eval_~tmp_ndt_4~0#1); 1438458#L561-2 havoc eval_~tmp_ndt_4~0#1; 1438451#L558-1 assume !(0 == ~t4_st~0); 1438227#L572-1 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0#1;havoc eval_#t~nondet12#1;eval_~tmp_ndt_6~0#1 := eval_#t~nondet12#1;havoc eval_#t~nondet12#1; 1438225#L589 assume !(0 != eval_~tmp_ndt_6~0#1); 1438224#L589-2 havoc eval_~tmp_ndt_6~0#1; 1438223#L586-1 [2024-11-08 00:35:27,600 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:27,600 INFO L85 PathProgramCache]: Analyzing trace with hash -322248313, now seen corresponding path program 4 times [2024-11-08 00:35:27,600 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:27,601 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [687374692] [2024-11-08 00:35:27,601 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:27,601 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:27,609 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:35:27,609 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 00:35:27,613 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:35:27,620 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 00:35:27,620 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:27,620 INFO L85 PathProgramCache]: Analyzing trace with hash -170650365, now seen corresponding path program 1 times [2024-11-08 00:35:27,620 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:27,620 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1252844475] [2024-11-08 00:35:27,620 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:27,621 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:27,623 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:35:27,623 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 00:35:27,625 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:35:27,626 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 00:35:27,626 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:27,626 INFO L85 PathProgramCache]: Analyzing trace with hash 1019637257, now seen corresponding path program 1 times [2024-11-08 00:35:27,627 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:27,627 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2100768425] [2024-11-08 00:35:27,627 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:27,627 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:27,633 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:27,658 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:27,658 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:27,659 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2100768425] [2024-11-08 00:35:27,659 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2100768425] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:27,659 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:27,659 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:27,659 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [452877591] [2024-11-08 00:35:27,659 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:27,724 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:35:27,724 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:35:27,724 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:35:27,725 INFO L87 Difference]: Start difference. First operand 197566 states and 253815 transitions. cyclomatic complexity: 56273 Second operand has 3 states, 3 states have (on average 32.333333333333336) internal successors, (97), 3 states have internal predecessors, (97), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:28,361 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:35:28,361 INFO L93 Difference]: Finished difference Result 249072 states and 319261 transitions. [2024-11-08 00:35:28,361 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 249072 states and 319261 transitions. [2024-11-08 00:35:29,774 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 168716 [2024-11-08 00:35:30,311 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 249072 states to 249072 states and 319261 transitions. [2024-11-08 00:35:30,311 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 170045 [2024-11-08 00:35:30,423 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 170045 [2024-11-08 00:35:30,423 INFO L73 IsDeterministic]: Start isDeterministic. Operand 249072 states and 319261 transitions. [2024-11-08 00:35:30,474 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-08 00:35:30,474 INFO L218 hiAutomatonCegarLoop]: Abstraction has 249072 states and 319261 transitions. [2024-11-08 00:35:30,635 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 249072 states and 319261 transitions. [2024-11-08 00:35:33,008 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 249072 to 243000. [2024-11-08 00:35:33,199 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 243000 states, 243000 states have (on average 1.2820288065843621) internal successors, (311533), 242999 states have internal predecessors, (311533), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:33,592 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 243000 states to 243000 states and 311533 transitions. [2024-11-08 00:35:33,592 INFO L240 hiAutomatonCegarLoop]: Abstraction has 243000 states and 311533 transitions. [2024-11-08 00:35:33,592 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:35:33,593 INFO L425 stractBuchiCegarLoop]: Abstraction has 243000 states and 311533 transitions. [2024-11-08 00:35:33,593 INFO L332 stractBuchiCegarLoop]: ======== Iteration 29 ============ [2024-11-08 00:35:33,593 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 243000 states and 311533 transitions. [2024-11-08 00:35:34,746 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 164668 [2024-11-08 00:35:34,746 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:35:34,746 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:35:34,747 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:34,747 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:34,748 INFO L745 eck$LassoCheckResult]: Stem: 1755021#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 1755022#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 1755258#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1755259#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1755224#L426 assume 1 == ~m_i~0;~m_st~0 := 0; 1755225#L426-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1754902#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1754903#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1754861#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1754862#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1755430#L451-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1755071#L611 assume !(0 == ~M_E~0); 1755072#L611-2 assume !(0 == ~T1_E~0); 1755472#L616-1 assume !(0 == ~T2_E~0); 1755473#L621-1 assume !(0 == ~T3_E~0); 1754617#L626-1 assume !(0 == ~T4_E~0); 1754618#L631-1 assume !(0 == ~T5_E~0); 1754987#L636-1 assume !(0 == ~E_M~0); 1754707#L641-1 assume !(0 == ~E_1~0); 1754708#L646-1 assume !(0 == ~E_2~0); 1755016#L651-1 assume !(0 == ~E_3~0); 1755603#L656-1 assume !(0 == ~E_4~0); 1755428#L661-1 assume !(0 == ~E_5~0); 1755429#L666-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1755528#L304 assume !(1 == ~m_pc~0); 1754763#L304-2 is_master_triggered_~__retres1~0#1 := 0; 1754568#L315 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1754569#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1754498#L755 assume !(0 != activate_threads_~tmp~1#1); 1754499#L755-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1754423#L323 assume !(1 == ~t1_pc~0); 1754424#L323-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1754519#L334 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1754520#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1754544#L763 assume !(0 != activate_threads_~tmp___0~0#1); 1755706#L763-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1754535#L342 assume !(1 == ~t2_pc~0); 1754537#L342-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1754766#L353 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1754767#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1755264#L771 assume !(0 != activate_threads_~tmp___1~0#1); 1755420#L771-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1755149#L361 assume !(1 == ~t3_pc~0); 1755150#L361-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1755204#L372 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1755643#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1755592#L779 assume !(0 != activate_threads_~tmp___2~0#1); 1754553#L779-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1754554#L380 assume !(1 == ~t4_pc~0); 1755148#L380-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1755457#L391 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1754700#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1754701#L787 assume !(0 != activate_threads_~tmp___3~0#1); 1755230#L787-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1754651#L399 assume !(1 == ~t5_pc~0); 1754652#L399-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1754924#L410 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1754936#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1754904#L795 assume !(0 != activate_threads_~tmp___4~0#1); 1754905#L795-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1755630#L679 assume !(1 == ~M_E~0); 1755070#L679-2 assume !(1 == ~T1_E~0); 1754790#L684-1 assume !(1 == ~T2_E~0); 1754791#L689-1 assume !(1 == ~T3_E~0); 1755166#L694-1 assume !(1 == ~T4_E~0); 1755164#L699-1 assume !(1 == ~T5_E~0); 1755165#L704-1 assume !(1 == ~E_M~0); 1755129#L709-1 assume !(1 == ~E_1~0); 1754994#L714-1 assume !(1 == ~E_2~0); 1754995#L719-1 assume !(1 == ~E_3~0); 1755408#L724-1 assume !(1 == ~E_4~0); 1754584#L729-1 assume !(1 == ~E_5~0); 1754585#L734-1 assume { :end_inline_reset_delta_events } true; 1755648#L940-2 assume !false; 1784265#L941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1883514#L586-1 [2024-11-08 00:35:34,748 INFO L747 eck$LassoCheckResult]: Loop: 1883514#L586-1 assume !false; 1919268#L507 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1919267#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1919266#L496 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1919265#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1919264#L511 assume 0 != eval_~tmp~0#1; 1919263#L511-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 1919261#L519 assume !(0 != eval_~tmp_ndt_1~0#1); 1919260#L519-2 havoc eval_~tmp_ndt_1~0#1; 1919259#L516-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 1919257#L533 assume !(0 != eval_~tmp_ndt_2~0#1); 1919258#L533-2 havoc eval_~tmp_ndt_2~0#1; 1922075#L530-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 1883454#L547 assume !(0 != eval_~tmp_ndt_3~0#1); 1919330#L547-2 havoc eval_~tmp_ndt_3~0#1; 1919286#L544-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet10#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 1919282#L561 assume !(0 != eval_~tmp_ndt_4~0#1); 1919280#L561-2 havoc eval_~tmp_ndt_4~0#1; 1919279#L558-1 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;havoc eval_#t~nondet11#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet11#1;havoc eval_#t~nondet11#1; 1919276#L575 assume !(0 != eval_~tmp_ndt_5~0#1); 1919271#L575-2 havoc eval_~tmp_ndt_5~0#1; 1919270#L572-1 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0#1;havoc eval_#t~nondet12#1;eval_~tmp_ndt_6~0#1 := eval_#t~nondet12#1;havoc eval_#t~nondet12#1; 1891861#L589 assume !(0 != eval_~tmp_ndt_6~0#1); 1919269#L589-2 havoc eval_~tmp_ndt_6~0#1; 1883514#L586-1 [2024-11-08 00:35:34,750 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:34,750 INFO L85 PathProgramCache]: Analyzing trace with hash -322248313, now seen corresponding path program 5 times [2024-11-08 00:35:34,750 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:34,750 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [434953453] [2024-11-08 00:35:34,750 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:34,750 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:34,759 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:35:34,759 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 00:35:34,763 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:35:34,770 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 00:35:34,771 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:34,771 INFO L85 PathProgramCache]: Analyzing trace with hash -1600135949, now seen corresponding path program 1 times [2024-11-08 00:35:34,771 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:34,771 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1823323305] [2024-11-08 00:35:34,771 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:34,771 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:34,775 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:35:34,776 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 00:35:34,777 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:35:34,780 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 00:35:34,780 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:34,780 INFO L85 PathProgramCache]: Analyzing trace with hash -195031943, now seen corresponding path program 1 times [2024-11-08 00:35:34,780 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:34,780 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2066216205] [2024-11-08 00:35:34,780 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:34,780 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:34,788 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:35:34,788 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 00:35:34,792 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:35:34,802 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 00:35:36,035 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:35:36,035 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 00:35:36,053 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:35:36,280 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 08.11 12:35:36 BoogieIcfgContainer [2024-11-08 00:35:36,282 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2024-11-08 00:35:36,283 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2024-11-08 00:35:36,283 INFO L270 PluginConnector]: Initializing Witness Printer... [2024-11-08 00:35:36,283 INFO L274 PluginConnector]: Witness Printer initialized [2024-11-08 00:35:36,284 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 08.11 12:34:54" (3/4) ... [2024-11-08 00:35:36,285 INFO L139 WitnessPrinter]: Generating witness for non-termination counterexample [2024-11-08 00:35:36,366 INFO L149 WitnessManager]: Wrote witness to /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/witness.graphml [2024-11-08 00:35:36,366 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2024-11-08 00:35:36,367 INFO L158 Benchmark]: Toolchain (without parser) took 44322.40ms. Allocated memory was 117.4MB in the beginning and 13.4GB in the end (delta: 13.3GB). Free memory was 91.5MB in the beginning and 9.4GB in the end (delta: -9.3GB). Peak memory consumption was 3.9GB. Max. memory is 16.1GB. [2024-11-08 00:35:36,367 INFO L158 Benchmark]: CDTParser took 0.53ms. Allocated memory is still 117.4MB. Free memory is still 81.9MB. There was no memory consumed. Max. memory is 16.1GB. [2024-11-08 00:35:36,367 INFO L158 Benchmark]: CACSL2BoogieTranslator took 299.58ms. Allocated memory is still 117.4MB. Free memory was 91.3MB in the beginning and 75.5MB in the end (delta: 15.9MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. [2024-11-08 00:35:36,367 INFO L158 Benchmark]: Boogie Procedure Inliner took 85.70ms. Allocated memory is still 117.4MB. Free memory was 75.5MB in the beginning and 70.7MB in the end (delta: 4.7MB). There was no memory consumed. Max. memory is 16.1GB. [2024-11-08 00:35:36,368 INFO L158 Benchmark]: Boogie Preprocessor took 101.40ms. Allocated memory is still 117.4MB. Free memory was 70.6MB in the beginning and 64.8MB in the end (delta: 5.8MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2024-11-08 00:35:36,368 INFO L158 Benchmark]: RCFGBuilder took 1494.78ms. Allocated memory was 117.4MB in the beginning and 159.4MB in the end (delta: 41.9MB). Free memory was 64.8MB in the beginning and 122.3MB in the end (delta: -57.5MB). Peak memory consumption was 40.3MB. Max. memory is 16.1GB. [2024-11-08 00:35:36,372 INFO L158 Benchmark]: BuchiAutomizer took 42252.87ms. Allocated memory was 159.4MB in the beginning and 13.4GB in the end (delta: 13.2GB). Free memory was 122.3MB in the beginning and 9.4GB in the end (delta: -9.3GB). Peak memory consumption was 3.9GB. Max. memory is 16.1GB. [2024-11-08 00:35:36,372 INFO L158 Benchmark]: Witness Printer took 83.34ms. Allocated memory is still 13.4GB. Free memory was 9.4GB in the beginning and 9.4GB in the end (delta: 16.8MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. [2024-11-08 00:35:36,378 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.53ms. Allocated memory is still 117.4MB. Free memory is still 81.9MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 299.58ms. Allocated memory is still 117.4MB. Free memory was 91.3MB in the beginning and 75.5MB in the end (delta: 15.9MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 85.70ms. Allocated memory is still 117.4MB. Free memory was 75.5MB in the beginning and 70.7MB in the end (delta: 4.7MB). There was no memory consumed. Max. memory is 16.1GB. * Boogie Preprocessor took 101.40ms. Allocated memory is still 117.4MB. Free memory was 70.6MB in the beginning and 64.8MB in the end (delta: 5.8MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * RCFGBuilder took 1494.78ms. Allocated memory was 117.4MB in the beginning and 159.4MB in the end (delta: 41.9MB). Free memory was 64.8MB in the beginning and 122.3MB in the end (delta: -57.5MB). Peak memory consumption was 40.3MB. Max. memory is 16.1GB. * BuchiAutomizer took 42252.87ms. Allocated memory was 159.4MB in the beginning and 13.4GB in the end (delta: 13.2GB). Free memory was 122.3MB in the beginning and 9.4GB in the end (delta: -9.3GB). Peak memory consumption was 3.9GB. Max. memory is 16.1GB. * Witness Printer took 83.34ms. Allocated memory is still 13.4GB. Free memory was 9.4GB in the beginning and 9.4GB in the end (delta: 16.8MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 29 terminating modules (28 trivial, 1 deterministic, 0 nondeterministic) and one nonterminating remainder module.One deterministic module has affine ranking function (((long long) -1 * E_3) + 1) and consists of 3 locations. 28 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 243000 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 42.0s and 29 iterations. TraceHistogramMax:2. Analysis of lassos took 8.2s. Construction of modules took 1.4s. Büchi inclusion checks took 27.0s. Highest rank in rank-based complementation 3. Minimization of det autom 20. Minimization of nondet autom 9. Automata minimization 13.0s AutomataMinimizationTime, 29 MinimizatonAttempts, 28438 StatesRemovedByMinimization, 14 NontrivialMinimizations. Non-live state removal took 8.4s Buchi closure took 0.8s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [1, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 18221 SdHoareTripleChecker+Valid, 1.7s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 18220 mSDsluCounter, 50736 SdHoareTripleChecker+Invalid, 1.4s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 25185 mSDsCounter, 382 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 1294 IncrementalHoareTripleChecker+Invalid, 1676 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 382 mSolverCounterUnsat, 25551 mSDtfsCounter, 1294 mSolverCounterSat, 0.2s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI9 SFLT0 conc4 concLT1 SILN1 SILU0 SILI13 SILT0 lasso0 LassoPreprocessingBenchmarks: Lassos: inital134 mio100 ax100 hnf100 lsp7 ukn100 mio100 lsp100 div100 bol100 ite100 ukn100 eq179 hnf100 smp100 dnf166 smp73 tf109 neg100 sie116 LassoTerminationAnalysisBenchmarks: ConstraintsSatisfiability: unsat Degree: 0 Time: 25ms VariablesStem: 0 VariablesLoop: 1 DisjunctsStem: 1 DisjunctsLoop: 2 SupportingInvariants: 0 MotzkinApplications: 4 LassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 4 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 1 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.1s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 506]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int t2_pc = 0; [L27] int t3_pc = 0; [L28] int t4_pc = 0; [L29] int t5_pc = 0; [L30] int m_st ; [L31] int t1_st ; [L32] int t2_st ; [L33] int t3_st ; [L34] int t4_st ; [L35] int t5_st ; [L36] int m_i ; [L37] int t1_i ; [L38] int t2_i ; [L39] int t3_i ; [L40] int t4_i ; [L41] int t5_i ; [L42] int M_E = 2; [L43] int T1_E = 2; [L44] int T2_E = 2; [L45] int T3_E = 2; [L46] int T4_E = 2; [L47] int T5_E = 2; [L48] int E_M = 2; [L49] int E_1 = 2; [L50] int E_2 = 2; [L51] int E_3 = 2; [L52] int E_4 = 2; [L53] int E_5 = 2; [L61] int token ; [L63] int local ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0, t4_i=0, t4_pc=0, t4_st=0, t5_i=0, t5_pc=0, t5_st=0, token=0] [L985] int __retres1 ; [L989] CALL init_model() [L896] m_i = 1 [L897] t1_i = 1 [L898] t2_i = 1 [L899] t3_i = 1 [L900] t4_i = 1 [L901] t5_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L989] RET init_model() [L990] CALL start_simulation() [L926] int kernel_st ; [L927] int tmp ; [L928] int tmp___0 ; [L932] kernel_st = 0 [L933] FCALL update_channels() [L934] CALL init_threads() [L426] COND TRUE m_i == 1 [L427] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L431] COND TRUE t1_i == 1 [L432] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L436] COND TRUE t2_i == 1 [L437] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L441] COND TRUE t3_i == 1 [L442] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L446] COND TRUE t4_i == 1 [L447] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L451] COND TRUE t5_i == 1 [L452] t5_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L934] RET init_threads() [L935] CALL fire_delta_events() [L611] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L616] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L621] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L626] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L631] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L636] COND FALSE !(T5_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L641] COND FALSE !(E_M == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L646] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L651] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L656] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L661] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L666] COND FALSE !(E_5 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L935] RET fire_delta_events() [L936] CALL activate_threads() [L744] int tmp ; [L745] int tmp___0 ; [L746] int tmp___1 ; [L747] int tmp___2 ; [L748] int tmp___3 ; [L749] int tmp___4 ; [L753] CALL, EXPR is_master_triggered() [L301] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L304] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L314] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L316] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L753] RET, EXPR is_master_triggered() [L753] tmp = is_master_triggered() [L755] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L761] CALL, EXPR is_transmit1_triggered() [L320] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L323] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L333] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L335] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L761] RET, EXPR is_transmit1_triggered() [L761] tmp___0 = is_transmit1_triggered() [L763] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L769] CALL, EXPR is_transmit2_triggered() [L339] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L342] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L352] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L354] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L769] RET, EXPR is_transmit2_triggered() [L769] tmp___1 = is_transmit2_triggered() [L771] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L777] CALL, EXPR is_transmit3_triggered() [L358] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L361] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L371] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L373] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L777] RET, EXPR is_transmit3_triggered() [L777] tmp___2 = is_transmit3_triggered() [L779] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L785] CALL, EXPR is_transmit4_triggered() [L377] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L380] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L390] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L392] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L785] RET, EXPR is_transmit4_triggered() [L785] tmp___3 = is_transmit4_triggered() [L787] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L793] CALL, EXPR is_transmit5_triggered() [L396] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L399] COND FALSE !(t5_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L409] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L411] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L793] RET, EXPR is_transmit5_triggered() [L793] tmp___4 = is_transmit5_triggered() [L795] COND FALSE !(\read(tmp___4)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L936] RET activate_threads() [L937] CALL reset_delta_events() [L679] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L684] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L689] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L694] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L699] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L704] COND FALSE !(T5_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L709] COND FALSE !(E_M == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L714] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L719] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L724] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L729] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L734] COND FALSE !(E_5 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L937] RET reset_delta_events() [L940] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L943] kernel_st = 1 [L944] CALL eval() [L502] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] Loop: [L506] COND TRUE 1 [L509] CALL, EXPR exists_runnable_thread() [L461] int __retres1 ; [L464] COND TRUE m_st == 0 [L465] __retres1 = 1 [L497] return (__retres1); [L509] RET, EXPR exists_runnable_thread() [L509] tmp = exists_runnable_thread() [L511] COND TRUE \read(tmp) [L516] COND TRUE m_st == 0 [L517] int tmp_ndt_1; [L518] tmp_ndt_1 = __VERIFIER_nondet_int() [L519] COND FALSE !(\read(tmp_ndt_1)) [L530] COND TRUE t1_st == 0 [L531] int tmp_ndt_2; [L532] tmp_ndt_2 = __VERIFIER_nondet_int() [L533] COND FALSE !(\read(tmp_ndt_2)) [L544] COND TRUE t2_st == 0 [L545] int tmp_ndt_3; [L546] tmp_ndt_3 = __VERIFIER_nondet_int() [L547] COND FALSE !(\read(tmp_ndt_3)) [L558] COND TRUE t3_st == 0 [L559] int tmp_ndt_4; [L560] tmp_ndt_4 = __VERIFIER_nondet_int() [L561] COND FALSE !(\read(tmp_ndt_4)) [L572] COND TRUE t4_st == 0 [L573] int tmp_ndt_5; [L574] tmp_ndt_5 = __VERIFIER_nondet_int() [L575] COND FALSE !(\read(tmp_ndt_5)) [L586] COND TRUE t5_st == 0 [L587] int tmp_ndt_6; [L588] tmp_ndt_6 = __VERIFIER_nondet_int() [L589] COND FALSE !(\read(tmp_ndt_6)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 506]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int t2_pc = 0; [L27] int t3_pc = 0; [L28] int t4_pc = 0; [L29] int t5_pc = 0; [L30] int m_st ; [L31] int t1_st ; [L32] int t2_st ; [L33] int t3_st ; [L34] int t4_st ; [L35] int t5_st ; [L36] int m_i ; [L37] int t1_i ; [L38] int t2_i ; [L39] int t3_i ; [L40] int t4_i ; [L41] int t5_i ; [L42] int M_E = 2; [L43] int T1_E = 2; [L44] int T2_E = 2; [L45] int T3_E = 2; [L46] int T4_E = 2; [L47] int T5_E = 2; [L48] int E_M = 2; [L49] int E_1 = 2; [L50] int E_2 = 2; [L51] int E_3 = 2; [L52] int E_4 = 2; [L53] int E_5 = 2; [L61] int token ; [L63] int local ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0, t4_i=0, t4_pc=0, t4_st=0, t5_i=0, t5_pc=0, t5_st=0, token=0] [L985] int __retres1 ; [L989] CALL init_model() [L896] m_i = 1 [L897] t1_i = 1 [L898] t2_i = 1 [L899] t3_i = 1 [L900] t4_i = 1 [L901] t5_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L989] RET init_model() [L990] CALL start_simulation() [L926] int kernel_st ; [L927] int tmp ; [L928] int tmp___0 ; [L932] kernel_st = 0 [L933] FCALL update_channels() [L934] CALL init_threads() [L426] COND TRUE m_i == 1 [L427] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L431] COND TRUE t1_i == 1 [L432] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L436] COND TRUE t2_i == 1 [L437] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L441] COND TRUE t3_i == 1 [L442] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L446] COND TRUE t4_i == 1 [L447] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L451] COND TRUE t5_i == 1 [L452] t5_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L934] RET init_threads() [L935] CALL fire_delta_events() [L611] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L616] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L621] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L626] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L631] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L636] COND FALSE !(T5_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L641] COND FALSE !(E_M == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L646] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L651] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L656] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L661] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L666] COND FALSE !(E_5 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L935] RET fire_delta_events() [L936] CALL activate_threads() [L744] int tmp ; [L745] int tmp___0 ; [L746] int tmp___1 ; [L747] int tmp___2 ; [L748] int tmp___3 ; [L749] int tmp___4 ; [L753] CALL, EXPR is_master_triggered() [L301] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L304] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L314] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L316] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L753] RET, EXPR is_master_triggered() [L753] tmp = is_master_triggered() [L755] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L761] CALL, EXPR is_transmit1_triggered() [L320] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L323] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L333] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L335] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L761] RET, EXPR is_transmit1_triggered() [L761] tmp___0 = is_transmit1_triggered() [L763] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L769] CALL, EXPR is_transmit2_triggered() [L339] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L342] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L352] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L354] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L769] RET, EXPR is_transmit2_triggered() [L769] tmp___1 = is_transmit2_triggered() [L771] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L777] CALL, EXPR is_transmit3_triggered() [L358] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L361] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L371] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L373] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L777] RET, EXPR is_transmit3_triggered() [L777] tmp___2 = is_transmit3_triggered() [L779] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L785] CALL, EXPR is_transmit4_triggered() [L377] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L380] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L390] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L392] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L785] RET, EXPR is_transmit4_triggered() [L785] tmp___3 = is_transmit4_triggered() [L787] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L793] CALL, EXPR is_transmit5_triggered() [L396] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L399] COND FALSE !(t5_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L409] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L411] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L793] RET, EXPR is_transmit5_triggered() [L793] tmp___4 = is_transmit5_triggered() [L795] COND FALSE !(\read(tmp___4)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L936] RET activate_threads() [L937] CALL reset_delta_events() [L679] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L684] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L689] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L694] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L699] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L704] COND FALSE !(T5_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L709] COND FALSE !(E_M == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L714] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L719] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L724] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L729] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L734] COND FALSE !(E_5 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L937] RET reset_delta_events() [L940] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L943] kernel_st = 1 [L944] CALL eval() [L502] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] Loop: [L506] COND TRUE 1 [L509] CALL, EXPR exists_runnable_thread() [L461] int __retres1 ; [L464] COND TRUE m_st == 0 [L465] __retres1 = 1 [L497] return (__retres1); [L509] RET, EXPR exists_runnable_thread() [L509] tmp = exists_runnable_thread() [L511] COND TRUE \read(tmp) [L516] COND TRUE m_st == 0 [L517] int tmp_ndt_1; [L518] tmp_ndt_1 = __VERIFIER_nondet_int() [L519] COND FALSE !(\read(tmp_ndt_1)) [L530] COND TRUE t1_st == 0 [L531] int tmp_ndt_2; [L532] tmp_ndt_2 = __VERIFIER_nondet_int() [L533] COND FALSE !(\read(tmp_ndt_2)) [L544] COND TRUE t2_st == 0 [L545] int tmp_ndt_3; [L546] tmp_ndt_3 = __VERIFIER_nondet_int() [L547] COND FALSE !(\read(tmp_ndt_3)) [L558] COND TRUE t3_st == 0 [L559] int tmp_ndt_4; [L560] tmp_ndt_4 = __VERIFIER_nondet_int() [L561] COND FALSE !(\read(tmp_ndt_4)) [L572] COND TRUE t4_st == 0 [L573] int tmp_ndt_5; [L574] tmp_ndt_5 = __VERIFIER_nondet_int() [L575] COND FALSE !(\read(tmp_ndt_5)) [L586] COND TRUE t5_st == 0 [L587] int tmp_ndt_6; [L588] tmp_ndt_6 = __VERIFIER_nondet_int() [L589] COND FALSE !(\read(tmp_ndt_6)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2024-11-08 00:35:36,427 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)