./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.06.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 4f9af400 extending candidate: java ['java'] extending candidate: /usr/bin/java ['java', '/usr/bin/java'] extending candidate: /opt/oracle-jdk-bin-*/bin/java ['java', '/usr/bin/java'] extending candidate: /opt/openjdk-*/bin/java ['java', '/usr/bin/java'] extending candidate: /usr/lib/jvm/java-*-openjdk-amd64/bin/java ['java', '/usr/bin/java', '/usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java', '/usr/lib/jvm/java-17-openjdk-amd64/bin/java', '/usr/lib/jvm/java-11-openjdk-amd64/bin/java', '/usr/lib/jvm/java-1.17.0-openjdk-amd64/bin/java'] ['/root/.sdkman/candidates/java/21.0.5-tem/bin/java', '-Dosgi.configuration.area=/storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/config', '-Xmx15G', '-Xms4m', '-jar', '/storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar', '-data', '@noDefault', '-ultimatedata', '/storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data', '-tc', '/storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml', '-i', '../sv-benchmarks/c/systemc/token_ring.06.cil-2.c', '-s', '/storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf', '--cacsl2boogietranslator.entry.function', 'main', '--witnessprinter.witness.directory', '/storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux', '--witnessprinter.witness.filename', 'witness', '--witnessprinter.write.witness.besides.input.file', 'false', '--witnessprinter.graph.data.specification', 'CHECK( init(main()), LTL(F end) )\n\n', '--witnessprinter.graph.data.producer', 'Automizer', '--witnessprinter.graph.data.architecture', '32bit', '--witnessprinter.graph.data.programhash', '4d0fbec14d1477738cb6d25ea9b61fc7005f787f2c8a0ac2c555d7e4fa1dbf47'] Calling Ultimate with: /root/.sdkman/candidates/java/21.0.5-tem/bin/java -Dosgi.configuration.area=/storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.06.cil-2.c -s /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 4d0fbec14d1477738cb6d25ea9b61fc7005f787f2c8a0ac2c555d7e4fa1dbf47 --- Real Ultimate output --- This is Ultimate 0.3.0-?-4f9af40 [2024-11-08 00:34:54,524 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-08 00:34:54,578 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-11-08 00:34:54,583 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-08 00:34:54,583 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-08 00:34:54,598 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-08 00:34:54,599 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-08 00:34:54,599 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-08 00:34:54,600 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-08 00:34:54,600 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-08 00:34:54,600 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-08 00:34:54,600 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-08 00:34:54,600 INFO L153 SettingsManager]: * Use SBE=true [2024-11-08 00:34:54,600 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-11-08 00:34:54,600 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-11-08 00:34:54,600 INFO L153 SettingsManager]: * Use old map elimination=false [2024-11-08 00:34:54,600 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-11-08 00:34:54,601 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-11-08 00:34:54,601 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-11-08 00:34:54,601 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-08 00:34:54,601 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-11-08 00:34:54,601 INFO L153 SettingsManager]: * sizeof long=4 [2024-11-08 00:34:54,601 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-08 00:34:54,601 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-11-08 00:34:54,601 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-08 00:34:54,601 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-11-08 00:34:54,601 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-11-08 00:34:54,602 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-11-08 00:34:54,602 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-11-08 00:34:54,602 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-11-08 00:34:54,602 INFO L153 SettingsManager]: * sizeof long double=12 [2024-11-08 00:34:54,602 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-08 00:34:54,602 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-11-08 00:34:54,602 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-08 00:34:54,602 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-11-08 00:34:54,602 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-08 00:34:54,602 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-08 00:34:54,602 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-11-08 00:34:54,602 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-11-08 00:34:54,602 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 4d0fbec14d1477738cb6d25ea9b61fc7005f787f2c8a0ac2c555d7e4fa1dbf47 [2024-11-08 00:34:54,786 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-08 00:34:54,792 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-08 00:34:54,794 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-08 00:34:54,794 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-08 00:34:54,795 INFO L274 PluginConnector]: CDTParser initialized [2024-11-08 00:34:54,795 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.06.cil-2.c [2024-11-08 00:34:55,994 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-11-08 00:34:56,288 INFO L384 CDTParser]: Found 1 translation units. [2024-11-08 00:34:56,288 INFO L180 CDTParser]: Scanning /storage/repos/ultimate-jdk21/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.06.cil-2.c [2024-11-08 00:34:56,302 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/44d2b7299/2a1ffb418d374aad86d0ffc4511ac4ad/FLAGf4dce8a03 [2024-11-08 00:34:56,583 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/44d2b7299/2a1ffb418d374aad86d0ffc4511ac4ad [2024-11-08 00:34:56,585 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-08 00:34:56,586 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-08 00:34:56,587 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-08 00:34:56,587 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-08 00:34:56,590 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-08 00:34:56,591 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 08.11 12:34:56" (1/1) ... [2024-11-08 00:34:56,591 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@55dcadbe and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 12:34:56, skipping insertion in model container [2024-11-08 00:34:56,592 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 08.11 12:34:56" (1/1) ... [2024-11-08 00:34:56,609 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-08 00:34:56,754 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-08 00:34:56,768 INFO L200 MainTranslator]: Completed pre-run [2024-11-08 00:34:56,806 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-08 00:34:56,819 INFO L204 MainTranslator]: Completed translation [2024-11-08 00:34:56,820 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 12:34:56 WrapperNode [2024-11-08 00:34:56,820 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-08 00:34:56,821 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-08 00:34:56,821 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-08 00:34:56,821 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-08 00:34:56,825 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 12:34:56" (1/1) ... [2024-11-08 00:34:56,832 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 12:34:56" (1/1) ... [2024-11-08 00:34:56,871 INFO L138 Inliner]: procedures = 40, calls = 50, calls flagged for inlining = 45, calls inlined = 114, statements flattened = 1665 [2024-11-08 00:34:56,872 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-08 00:34:56,872 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-08 00:34:56,872 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-08 00:34:56,872 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-08 00:34:56,879 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 12:34:56" (1/1) ... [2024-11-08 00:34:56,879 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 12:34:56" (1/1) ... [2024-11-08 00:34:56,883 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 12:34:56" (1/1) ... [2024-11-08 00:34:56,898 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-11-08 00:34:56,899 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 12:34:56" (1/1) ... [2024-11-08 00:34:56,899 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 12:34:56" (1/1) ... [2024-11-08 00:34:56,911 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 12:34:56" (1/1) ... [2024-11-08 00:34:56,923 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 12:34:56" (1/1) ... [2024-11-08 00:34:56,926 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 12:34:56" (1/1) ... [2024-11-08 00:34:56,928 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 12:34:56" (1/1) ... [2024-11-08 00:34:56,932 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-08 00:34:56,933 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-11-08 00:34:56,933 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-11-08 00:34:56,933 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-11-08 00:34:56,934 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 12:34:56" (1/1) ... [2024-11-08 00:34:56,938 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 00:34:56,958 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2024-11-08 00:34:56,969 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 00:34:56,972 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-11-08 00:34:56,996 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-08 00:34:56,996 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-11-08 00:34:56,996 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-08 00:34:56,996 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-08 00:34:57,067 INFO L238 CfgBuilder]: Building ICFG [2024-11-08 00:34:57,068 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-08 00:34:58,137 INFO L? ?]: Removed 318 outVars from TransFormulas that were not future-live. [2024-11-08 00:34:58,137 INFO L287 CfgBuilder]: Performing block encoding [2024-11-08 00:34:58,164 INFO L311 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-08 00:34:58,164 INFO L316 CfgBuilder]: Removed 9 assume(true) statements. [2024-11-08 00:34:58,168 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 08.11 12:34:58 BoogieIcfgContainer [2024-11-08 00:34:58,168 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-11-08 00:34:58,169 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-11-08 00:34:58,169 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-11-08 00:34:58,175 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-11-08 00:34:58,177 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-08 00:34:58,177 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 08.11 12:34:56" (1/3) ... [2024-11-08 00:34:58,178 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@6fa449c7 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 08.11 12:34:58, skipping insertion in model container [2024-11-08 00:34:58,178 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-08 00:34:58,179 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 12:34:56" (2/3) ... [2024-11-08 00:34:58,179 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@6fa449c7 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 08.11 12:34:58, skipping insertion in model container [2024-11-08 00:34:58,179 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-08 00:34:58,179 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 08.11 12:34:58" (3/3) ... [2024-11-08 00:34:58,180 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.06.cil-2.c [2024-11-08 00:34:58,233 INFO L300 stractBuchiCegarLoop]: Interprodecural is true [2024-11-08 00:34:58,234 INFO L301 stractBuchiCegarLoop]: Hoare is None [2024-11-08 00:34:58,234 INFO L302 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-11-08 00:34:58,234 INFO L303 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-11-08 00:34:58,234 INFO L304 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-11-08 00:34:58,234 INFO L305 stractBuchiCegarLoop]: Difference is false [2024-11-08 00:34:58,234 INFO L306 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-11-08 00:34:58,234 INFO L310 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-11-08 00:34:58,239 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 695 states, 694 states have (on average 1.5172910662824208) internal successors, (1053), 694 states have internal predecessors, (1053), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:34:58,284 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 600 [2024-11-08 00:34:58,285 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:34:58,285 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:34:58,292 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:58,293 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:58,293 INFO L332 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-11-08 00:34:58,294 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 695 states, 694 states have (on average 1.5172910662824208) internal successors, (1053), 694 states have internal predecessors, (1053), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:34:58,300 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 600 [2024-11-08 00:34:58,301 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:34:58,301 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:34:58,302 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:58,302 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:58,308 INFO L745 eck$LassoCheckResult]: Stem: 216#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 578#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 324#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 573#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 91#L475true assume !(1 == ~m_i~0);~m_st~0 := 2; 561#L475-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 323#L480-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 628#L485-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 263#L490-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 126#L495-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 467#L500-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 80#L505-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 536#L684true assume !(0 == ~M_E~0); 451#L684-2true assume !(0 == ~T1_E~0); 291#L689-1true assume !(0 == ~T2_E~0); 671#L694-1true assume !(0 == ~T3_E~0); 290#L699-1true assume !(0 == ~T4_E~0); 445#L704-1true assume !(0 == ~T5_E~0); 249#L709-1true assume !(0 == ~T6_E~0); 205#L714-1true assume 0 == ~E_M~0;~E_M~0 := 1; 410#L719-1true assume !(0 == ~E_1~0); 595#L724-1true assume !(0 == ~E_2~0); 65#L729-1true assume !(0 == ~E_3~0); 569#L734-1true assume !(0 == ~E_4~0); 503#L739-1true assume !(0 == ~E_5~0); 179#L744-1true assume !(0 == ~E_6~0); 411#L749-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 43#L334true assume !(1 == ~m_pc~0); 244#L334-2true is_master_triggered_~__retres1~0#1 := 0; 514#L345true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 182#is_master_triggered_returnLabel#1true activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 161#L849true assume !(0 != activate_threads_~tmp~1#1); 375#L849-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 125#L353true assume 1 == ~t1_pc~0; 603#L354true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 327#L364true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 50#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 302#L857true assume !(0 != activate_threads_~tmp___0~0#1); 94#L857-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 567#L372true assume !(1 == ~t2_pc~0); 167#L372-2true is_transmit2_triggered_~__retres1~2#1 := 0; 240#L383true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 328#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 488#L865true assume !(0 != activate_threads_~tmp___1~0#1); 38#L865-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 463#L391true assume 1 == ~t3_pc~0; 586#L392true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 114#L402true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 401#L873true assume !(0 != activate_threads_~tmp___2~0#1); 164#L873-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 485#L410true assume 1 == ~t4_pc~0; 602#L411true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 380#L421true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 103#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 490#L881true assume !(0 != activate_threads_~tmp___3~0#1); 169#L881-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 284#L429true assume !(1 == ~t5_pc~0); 68#L429-2true is_transmit5_triggered_~__retres1~5#1 := 0; 660#L440true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 189#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 349#L889true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 372#L889-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 159#L448true assume 1 == ~t6_pc~0; 88#L449true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 346#L459true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 314#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 541#L897true assume !(0 != activate_threads_~tmp___5~0#1); 648#L897-2true havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 640#L762true assume !(1 == ~M_E~0); 193#L762-2true assume !(1 == ~T1_E~0); 600#L767-1true assume !(1 == ~T2_E~0); 550#L772-1true assume 1 == ~T3_E~0;~T3_E~0 := 2; 373#L777-1true assume !(1 == ~T4_E~0); 276#L782-1true assume !(1 == ~T5_E~0); 83#L787-1true assume !(1 == ~T6_E~0); 82#L792-1true assume !(1 == ~E_M~0); 106#L797-1true assume !(1 == ~E_1~0); 429#L802-1true assume !(1 == ~E_2~0); 247#L807-1true assume !(1 == ~E_3~0); 498#L812-1true assume 1 == ~E_4~0;~E_4~0 := 2; 619#L817-1true assume !(1 == ~E_5~0); 292#L822-1true assume !(1 == ~E_6~0); 512#L827-1true assume { :end_inline_reset_delta_events } true; 162#L1053-2true [2024-11-08 00:34:58,310 INFO L747 eck$LassoCheckResult]: Loop: 162#L1053-2true assume !false; 487#L1054true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 376#L659-1true assume false; 110#eval_returnLabel#1true havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 507#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 266#L684-3true assume 0 == ~M_E~0;~M_E~0 := 1; 438#L684-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 2#L689-3true assume !(0 == ~T2_E~0); 191#L694-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 28#L699-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 359#L704-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 492#L709-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 337#L714-3true assume 0 == ~E_M~0;~E_M~0 := 1; 186#L719-3true assume 0 == ~E_1~0;~E_1~0 := 1; 25#L724-3true assume 0 == ~E_2~0;~E_2~0 := 1; 318#L729-3true assume !(0 == ~E_3~0); 382#L734-3true assume 0 == ~E_4~0;~E_4~0 := 1; 363#L739-3true assume 0 == ~E_5~0;~E_5~0 := 1; 542#L744-3true assume 0 == ~E_6~0;~E_6~0 := 1; 494#L749-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 31#L334-24true assume 1 == ~m_pc~0; 310#L335-8true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 332#L345-8true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 121#is_master_triggered_returnLabel#9true activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 17#L849-24true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 625#L849-26true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 361#L353-24true assume !(1 == ~t1_pc~0); 634#L353-26true is_transmit1_triggered_~__retres1~1#1 := 0; 556#L364-8true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 553#is_transmit1_triggered_returnLabel#9true activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 589#L857-24true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 39#L857-26true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 72#L372-24true assume 1 == ~t2_pc~0; 22#L373-8true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 230#L383-8true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 679#is_transmit2_triggered_returnLabel#9true activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 535#L865-24true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 662#L865-26true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 207#L391-24true assume !(1 == ~t3_pc~0); 633#L391-26true is_transmit3_triggered_~__retres1~3#1 := 0; 412#L402-8true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 362#is_transmit3_triggered_returnLabel#9true activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 277#L873-24true assume !(0 != activate_threads_~tmp___2~0#1); 254#L873-26true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 141#L410-24true assume 1 == ~t4_pc~0; 107#L411-8true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 386#L421-8true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 493#is_transmit4_triggered_returnLabel#9true activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 168#L881-24true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 81#L881-26true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 139#L429-24true assume 1 == ~t5_pc~0; 282#L430-8true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 385#L440-8true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 255#is_transmit5_triggered_returnLabel#9true activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 109#L889-24true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 223#L889-26true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 79#L448-24true assume 1 == ~t6_pc~0; 112#L449-8true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 74#L459-8true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 175#is_transmit6_triggered_returnLabel#9true activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 520#L897-24true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 285#L897-26true havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 511#L762-3true assume 1 == ~M_E~0;~M_E~0 := 2; 251#L762-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 580#L767-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 668#L772-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 546#L777-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 69#L782-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 647#L787-3true assume !(1 == ~T6_E~0); 394#L792-3true assume 1 == ~E_M~0;~E_M~0 := 2; 206#L797-3true assume 1 == ~E_1~0;~E_1~0 := 2; 453#L802-3true assume 1 == ~E_2~0;~E_2~0 := 2; 664#L807-3true assume 1 == ~E_3~0;~E_3~0 := 2; 315#L812-3true assume 1 == ~E_4~0;~E_4~0 := 2; 506#L817-3true assume 1 == ~E_5~0;~E_5~0 := 2; 404#L822-3true assume 1 == ~E_6~0;~E_6~0 := 2; 388#L827-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 221#L518-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 389#L555-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 301#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 620#L1072true assume !(0 == start_simulation_~tmp~3#1); 151#L1072-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 502#L518-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 75#L555-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 49#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 34#L1027true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 605#L1034true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 524#stop_simulation_returnLabel#1true start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 407#L1085true assume !(0 != start_simulation_~tmp___0~1#1); 162#L1053-2true [2024-11-08 00:34:58,314 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:34:58,314 INFO L85 PathProgramCache]: Analyzing trace with hash -376834623, now seen corresponding path program 1 times [2024-11-08 00:34:58,321 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:34:58,323 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [246971463] [2024-11-08 00:34:58,323 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:34:58,323 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:34:58,399 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:34:58,500 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:34:58,501 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:34:58,501 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [246971463] [2024-11-08 00:34:58,504 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [246971463] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:34:58,504 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:34:58,505 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:34:58,508 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2011457161] [2024-11-08 00:34:58,508 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:34:58,511 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:34:58,511 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:34:58,513 INFO L85 PathProgramCache]: Analyzing trace with hash 1316317370, now seen corresponding path program 1 times [2024-11-08 00:34:58,513 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:34:58,514 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2111981097] [2024-11-08 00:34:58,514 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:34:58,514 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:34:58,526 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:34:58,560 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:34:58,560 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:34:58,560 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2111981097] [2024-11-08 00:34:58,560 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2111981097] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:34:58,560 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:34:58,560 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-08 00:34:58,561 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [956467186] [2024-11-08 00:34:58,561 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:34:58,562 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:34:58,562 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:34:58,581 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:34:58,581 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:34:58,584 INFO L87 Difference]: Start difference. First operand has 695 states, 694 states have (on average 1.5172910662824208) internal successors, (1053), 694 states have internal predecessors, (1053), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:34:58,625 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:34:58,625 INFO L93 Difference]: Finished difference Result 693 states and 1031 transitions. [2024-11-08 00:34:58,626 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 693 states and 1031 transitions. [2024-11-08 00:34:58,631 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 597 [2024-11-08 00:34:58,648 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 693 states to 688 states and 1026 transitions. [2024-11-08 00:34:58,649 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 688 [2024-11-08 00:34:58,650 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 688 [2024-11-08 00:34:58,652 INFO L73 IsDeterministic]: Start isDeterministic. Operand 688 states and 1026 transitions. [2024-11-08 00:34:58,654 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:34:58,654 INFO L218 hiAutomatonCegarLoop]: Abstraction has 688 states and 1026 transitions. [2024-11-08 00:34:58,669 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 688 states and 1026 transitions. [2024-11-08 00:34:58,692 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 688 to 688. [2024-11-08 00:34:58,693 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 688 states, 688 states have (on average 1.4912790697674418) internal successors, (1026), 687 states have internal predecessors, (1026), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:34:58,695 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 688 states to 688 states and 1026 transitions. [2024-11-08 00:34:58,696 INFO L240 hiAutomatonCegarLoop]: Abstraction has 688 states and 1026 transitions. [2024-11-08 00:34:58,697 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:34:58,698 INFO L425 stractBuchiCegarLoop]: Abstraction has 688 states and 1026 transitions. [2024-11-08 00:34:58,699 INFO L332 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-11-08 00:34:58,699 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 688 states and 1026 transitions. [2024-11-08 00:34:58,702 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 597 [2024-11-08 00:34:58,703 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:34:58,703 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:34:58,705 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:58,706 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:58,707 INFO L745 eck$LassoCheckResult]: Stem: 1789#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 1790#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1915#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1916#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1583#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 1584#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1911#L480-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1912#L485-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1843#L490-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1637#L495-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1638#L500-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1561#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1562#L684 assume !(0 == ~M_E~0); 2013#L684-2 assume !(0 == ~T1_E~0); 1872#L689-1 assume !(0 == ~T2_E~0); 1873#L694-1 assume !(0 == ~T3_E~0); 1870#L699-1 assume !(0 == ~T4_E~0); 1871#L704-1 assume !(0 == ~T5_E~0); 1828#L709-1 assume !(0 == ~T6_E~0); 1767#L714-1 assume 0 == ~E_M~0;~E_M~0 := 1; 1768#L719-1 assume !(0 == ~E_1~0); 1987#L724-1 assume !(0 == ~E_2~0); 1533#L729-1 assume !(0 == ~E_3~0); 1534#L734-1 assume !(0 == ~E_4~0); 2040#L739-1 assume !(0 == ~E_5~0); 1730#L744-1 assume !(0 == ~E_6~0); 1731#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1490#L334 assume !(1 == ~m_pc~0); 1491#L334-2 is_master_triggered_~__retres1~0#1 := 0; 1820#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1733#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1701#L849 assume !(0 != activate_threads_~tmp~1#1); 1702#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1634#L353 assume 1 == ~t1_pc~0; 1635#L354 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1917#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1505#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1506#L857 assume !(0 != activate_threads_~tmp___0~0#1); 1586#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1587#L372 assume !(1 == ~t2_pc~0); 1690#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1689#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1815#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1918#L865 assume !(0 != activate_threads_~tmp___1~0#1); 1479#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1480#L391 assume 1 == ~t3_pc~0; 2024#L392 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1402#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1428#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1429#L873 assume !(0 != activate_threads_~tmp___2~0#1); 1708#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1709#L410 assume 1 == ~t4_pc~0; 2031#L411 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1932#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1600#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1601#L881 assume !(0 != activate_threads_~tmp___3~0#1); 1717#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1718#L429 assume !(1 == ~t5_pc~0); 1539#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1540#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1743#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1744#L889 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1935#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1700#L448 assume 1 == ~t6_pc~0; 1574#L449 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1575#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1903#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1904#L897 assume !(0 != activate_threads_~tmp___5~0#1); 2059#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2082#L762 assume !(1 == ~M_E~0); 1747#L762-2 assume !(1 == ~T1_E~0); 1748#L767-1 assume !(1 == ~T2_E~0); 2064#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1963#L777-1 assume !(1 == ~T4_E~0); 1858#L782-1 assume !(1 == ~T5_E~0); 1565#L787-1 assume !(1 == ~T6_E~0); 1563#L792-1 assume !(1 == ~E_M~0); 1564#L797-1 assume !(1 == ~E_1~0); 1606#L802-1 assume !(1 == ~E_2~0); 1824#L807-1 assume !(1 == ~E_3~0); 1825#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 2035#L817-1 assume !(1 == ~E_5~0); 1876#L822-1 assume !(1 == ~E_6~0); 1877#L827-1 assume { :end_inline_reset_delta_events } true; 1703#L1053-2 [2024-11-08 00:34:58,708 INFO L747 eck$LassoCheckResult]: Loop: 1703#L1053-2 assume !false; 1704#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1679#L659-1 assume !false; 1668#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1669#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1671#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1937#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1938#L570 assume !(0 != eval_~tmp~0#1); 1611#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1612#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1849#L684-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1850#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1397#L689-3 assume !(0 == ~T2_E~0); 1398#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1457#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1458#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1944#L709-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1929#L714-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1742#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1450#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1451#L729-3 assume !(0 == ~E_3~0); 1908#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1950#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1951#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2033#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1464#L334-24 assume !(1 == ~m_pc~0); 1465#L334-26 is_master_triggered_~__retres1~0#1 := 0; 1604#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1629#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1436#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1437#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1945#L353-24 assume 1 == ~t1_pc~0; 1946#L354-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1975#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2065#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2066#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1481#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1482#L372-24 assume 1 == ~t2_pc~0; 1443#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1444#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1803#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2052#L865-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2053#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1772#L391-24 assume !(1 == ~t3_pc~0); 1773#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 1988#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1948#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1859#L873-24 assume !(0 != activate_threads_~tmp___2~0#1); 1834#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1667#L410-24 assume 1 == ~t4_pc~0; 1605#L411-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1531#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1968#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1713#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1559#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1560#L429-24 assume 1 == ~t5_pc~0; 1664#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1863#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1835#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1609#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1610#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1554#L448-24 assume 1 == ~t6_pc~0; 1555#L449-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1548#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1549#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1724#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1866#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1867#L762-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1832#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1833#L767-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2071#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2061#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1541#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1542#L787-3 assume !(1 == ~T6_E~0); 1976#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1769#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1770#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2015#L807-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1901#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1902#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1982#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1972#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1796#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1441#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1888#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 1889#L1072 assume !(0 == start_simulation_~tmp~3#1); 1684#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1685#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1550#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1504#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 1469#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1470#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2047#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 1985#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 1703#L1053-2 [2024-11-08 00:34:58,709 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:34:58,709 INFO L85 PathProgramCache]: Analyzing trace with hash 765667843, now seen corresponding path program 1 times [2024-11-08 00:34:58,709 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:34:58,709 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1129716353] [2024-11-08 00:34:58,709 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:34:58,709 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:34:58,727 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:34:58,799 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:34:58,799 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:34:58,803 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1129716353] [2024-11-08 00:34:58,803 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1129716353] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:34:58,803 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:34:58,803 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:34:58,803 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1483393112] [2024-11-08 00:34:58,803 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:34:58,804 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:34:58,804 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:34:58,804 INFO L85 PathProgramCache]: Analyzing trace with hash 1886177719, now seen corresponding path program 1 times [2024-11-08 00:34:58,804 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:34:58,804 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1502094525] [2024-11-08 00:34:58,804 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:34:58,804 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:34:58,830 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:34:58,937 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:34:58,937 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:34:58,937 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1502094525] [2024-11-08 00:34:58,937 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1502094525] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:34:58,937 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:34:58,937 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:34:58,937 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [350196814] [2024-11-08 00:34:58,937 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:34:58,938 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:34:58,938 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:34:58,938 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:34:58,938 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:34:58,938 INFO L87 Difference]: Start difference. First operand 688 states and 1026 transitions. cyclomatic complexity: 339 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:34:58,983 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:34:58,987 INFO L93 Difference]: Finished difference Result 688 states and 1025 transitions. [2024-11-08 00:34:58,987 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 688 states and 1025 transitions. [2024-11-08 00:34:58,994 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 597 [2024-11-08 00:34:59,001 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 688 states to 688 states and 1025 transitions. [2024-11-08 00:34:59,005 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 688 [2024-11-08 00:34:59,006 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 688 [2024-11-08 00:34:59,006 INFO L73 IsDeterministic]: Start isDeterministic. Operand 688 states and 1025 transitions. [2024-11-08 00:34:59,011 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:34:59,015 INFO L218 hiAutomatonCegarLoop]: Abstraction has 688 states and 1025 transitions. [2024-11-08 00:34:59,016 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 688 states and 1025 transitions. [2024-11-08 00:34:59,033 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 688 to 688. [2024-11-08 00:34:59,041 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 688 states, 688 states have (on average 1.489825581395349) internal successors, (1025), 687 states have internal predecessors, (1025), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:34:59,049 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 688 states to 688 states and 1025 transitions. [2024-11-08 00:34:59,053 INFO L240 hiAutomatonCegarLoop]: Abstraction has 688 states and 1025 transitions. [2024-11-08 00:34:59,053 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:34:59,054 INFO L425 stractBuchiCegarLoop]: Abstraction has 688 states and 1025 transitions. [2024-11-08 00:34:59,054 INFO L332 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-11-08 00:34:59,054 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 688 states and 1025 transitions. [2024-11-08 00:34:59,062 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 597 [2024-11-08 00:34:59,063 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:34:59,063 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:34:59,064 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:59,066 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:59,069 INFO L745 eck$LassoCheckResult]: Stem: 3170#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 3171#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 3296#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3297#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2964#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 2965#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3294#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3295#L485-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3226#L490-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3020#L495-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3021#L500-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 2942#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2943#L684 assume !(0 == ~M_E~0); 3396#L684-2 assume !(0 == ~T1_E~0); 3255#L689-1 assume !(0 == ~T2_E~0); 3256#L694-1 assume !(0 == ~T3_E~0); 3253#L699-1 assume !(0 == ~T4_E~0); 3254#L704-1 assume !(0 == ~T5_E~0); 3211#L709-1 assume !(0 == ~T6_E~0); 3150#L714-1 assume 0 == ~E_M~0;~E_M~0 := 1; 3151#L719-1 assume !(0 == ~E_1~0); 3370#L724-1 assume !(0 == ~E_2~0); 2916#L729-1 assume !(0 == ~E_3~0); 2917#L734-1 assume !(0 == ~E_4~0); 3423#L739-1 assume !(0 == ~E_5~0); 3113#L744-1 assume !(0 == ~E_6~0); 3114#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2873#L334 assume !(1 == ~m_pc~0); 2874#L334-2 is_master_triggered_~__retres1~0#1 := 0; 3203#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3115#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3084#L849 assume !(0 != activate_threads_~tmp~1#1); 3085#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3017#L353 assume 1 == ~t1_pc~0; 3018#L354 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3300#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2888#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2889#L857 assume !(0 != activate_threads_~tmp___0~0#1); 2969#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2970#L372 assume !(1 == ~t2_pc~0); 3073#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3072#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3198#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3301#L865 assume !(0 != activate_threads_~tmp___1~0#1); 2862#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2863#L391 assume 1 == ~t3_pc~0; 3405#L392 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2785#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2811#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2812#L873 assume !(0 != activate_threads_~tmp___2~0#1); 3091#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3092#L410 assume 1 == ~t4_pc~0; 3413#L411 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3314#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2983#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2984#L881 assume !(0 != activate_threads_~tmp___3~0#1); 3097#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3098#L429 assume !(1 == ~t5_pc~0); 2922#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2923#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3126#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3127#L889 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3318#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3083#L448 assume 1 == ~t6_pc~0; 2957#L449 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2958#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3284#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3285#L897 assume !(0 != activate_threads_~tmp___5~0#1); 3442#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3465#L762 assume !(1 == ~M_E~0); 3130#L762-2 assume !(1 == ~T1_E~0); 3131#L767-1 assume !(1 == ~T2_E~0); 3447#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3346#L777-1 assume !(1 == ~T4_E~0); 3241#L782-1 assume !(1 == ~T5_E~0); 2948#L787-1 assume !(1 == ~T6_E~0); 2946#L792-1 assume !(1 == ~E_M~0); 2947#L797-1 assume !(1 == ~E_1~0); 2988#L802-1 assume !(1 == ~E_2~0); 3207#L807-1 assume !(1 == ~E_3~0); 3208#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 3418#L817-1 assume !(1 == ~E_5~0); 3257#L822-1 assume !(1 == ~E_6~0); 3258#L827-1 assume { :end_inline_reset_delta_events } true; 3086#L1053-2 [2024-11-08 00:34:59,069 INFO L747 eck$LassoCheckResult]: Loop: 3086#L1053-2 assume !false; 3087#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3062#L659-1 assume !false; 3051#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 3052#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 3054#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 3320#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 3321#L570 assume !(0 != eval_~tmp~0#1); 2994#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2995#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3230#L684-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3231#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2780#L689-3 assume !(0 == ~T2_E~0); 2781#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2840#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2841#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3327#L709-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3310#L714-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3120#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2833#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2834#L729-3 assume !(0 == ~E_3~0); 3290#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3333#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3334#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3416#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2847#L334-24 assume !(1 == ~m_pc~0); 2848#L334-26 is_master_triggered_~__retres1~0#1 := 0; 2987#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3012#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2817#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2818#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3329#L353-24 assume 1 == ~t1_pc~0; 3330#L354-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3358#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3448#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3449#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2864#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2865#L372-24 assume 1 == ~t2_pc~0; 2826#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2827#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3186#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3436#L865-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3437#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3155#L391-24 assume !(1 == ~t3_pc~0); 3156#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 3371#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3332#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3242#L873-24 assume !(0 != activate_threads_~tmp___2~0#1); 3220#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3050#L410-24 assume !(1 == ~t4_pc~0); 2913#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 2914#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3351#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3096#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2944#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2945#L429-24 assume !(1 == ~t5_pc~0); 3046#L429-26 is_transmit5_triggered_~__retres1~5#1 := 0; 3246#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3221#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2992#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2993#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2939#L448-24 assume 1 == ~t6_pc~0; 2940#L449-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2931#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2932#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3107#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3249#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3250#L762-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3215#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3216#L767-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3454#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3444#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2924#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2925#L787-3 assume !(1 == ~T6_E~0); 3359#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3152#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3153#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3398#L807-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3286#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3287#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3365#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3355#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 3179#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 2824#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 3271#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 3272#L1072 assume !(0 == start_simulation_~tmp~3#1); 3067#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 3068#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 2933#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 2887#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 2854#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2855#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3430#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 3368#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 3086#L1053-2 [2024-11-08 00:34:59,070 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:34:59,070 INFO L85 PathProgramCache]: Analyzing trace with hash -73365819, now seen corresponding path program 1 times [2024-11-08 00:34:59,070 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:34:59,070 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [310285620] [2024-11-08 00:34:59,070 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:34:59,070 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:34:59,084 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:34:59,117 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:34:59,118 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:34:59,118 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [310285620] [2024-11-08 00:34:59,118 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [310285620] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:34:59,118 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:34:59,118 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:34:59,118 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [777637076] [2024-11-08 00:34:59,118 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:34:59,118 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:34:59,118 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:34:59,118 INFO L85 PathProgramCache]: Analyzing trace with hash 55771641, now seen corresponding path program 1 times [2024-11-08 00:34:59,118 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:34:59,119 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [936152473] [2024-11-08 00:34:59,119 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:34:59,119 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:34:59,130 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:34:59,165 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:34:59,165 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:34:59,165 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [936152473] [2024-11-08 00:34:59,165 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [936152473] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:34:59,165 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:34:59,165 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:34:59,165 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1218091553] [2024-11-08 00:34:59,165 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:34:59,166 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:34:59,166 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:34:59,166 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:34:59,166 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:34:59,166 INFO L87 Difference]: Start difference. First operand 688 states and 1025 transitions. cyclomatic complexity: 338 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:34:59,181 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:34:59,181 INFO L93 Difference]: Finished difference Result 688 states and 1024 transitions. [2024-11-08 00:34:59,182 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 688 states and 1024 transitions. [2024-11-08 00:34:59,185 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 597 [2024-11-08 00:34:59,188 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 688 states to 688 states and 1024 transitions. [2024-11-08 00:34:59,188 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 688 [2024-11-08 00:34:59,189 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 688 [2024-11-08 00:34:59,189 INFO L73 IsDeterministic]: Start isDeterministic. Operand 688 states and 1024 transitions. [2024-11-08 00:34:59,190 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:34:59,190 INFO L218 hiAutomatonCegarLoop]: Abstraction has 688 states and 1024 transitions. [2024-11-08 00:34:59,191 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 688 states and 1024 transitions. [2024-11-08 00:34:59,196 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 688 to 688. [2024-11-08 00:34:59,197 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 688 states, 688 states have (on average 1.4883720930232558) internal successors, (1024), 687 states have internal predecessors, (1024), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:34:59,199 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 688 states to 688 states and 1024 transitions. [2024-11-08 00:34:59,199 INFO L240 hiAutomatonCegarLoop]: Abstraction has 688 states and 1024 transitions. [2024-11-08 00:34:59,200 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:34:59,201 INFO L425 stractBuchiCegarLoop]: Abstraction has 688 states and 1024 transitions. [2024-11-08 00:34:59,201 INFO L332 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-11-08 00:34:59,202 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 688 states and 1024 transitions. [2024-11-08 00:34:59,204 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 597 [2024-11-08 00:34:59,204 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:34:59,205 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:34:59,206 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:59,206 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:59,206 INFO L745 eck$LassoCheckResult]: Stem: 4553#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 4554#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 4679#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4680#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4347#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 4348#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4677#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4678#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4609#L490-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4403#L495-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4404#L500-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4325#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4326#L684 assume !(0 == ~M_E~0); 4779#L684-2 assume !(0 == ~T1_E~0); 4638#L689-1 assume !(0 == ~T2_E~0); 4639#L694-1 assume !(0 == ~T3_E~0); 4636#L699-1 assume !(0 == ~T4_E~0); 4637#L704-1 assume !(0 == ~T5_E~0); 4594#L709-1 assume !(0 == ~T6_E~0); 4533#L714-1 assume 0 == ~E_M~0;~E_M~0 := 1; 4534#L719-1 assume !(0 == ~E_1~0); 4753#L724-1 assume !(0 == ~E_2~0); 4299#L729-1 assume !(0 == ~E_3~0); 4300#L734-1 assume !(0 == ~E_4~0); 4806#L739-1 assume !(0 == ~E_5~0); 4496#L744-1 assume !(0 == ~E_6~0); 4497#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4256#L334 assume !(1 == ~m_pc~0); 4257#L334-2 is_master_triggered_~__retres1~0#1 := 0; 4586#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4498#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4467#L849 assume !(0 != activate_threads_~tmp~1#1); 4468#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4400#L353 assume 1 == ~t1_pc~0; 4401#L354 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4683#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4271#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4272#L857 assume !(0 != activate_threads_~tmp___0~0#1); 4352#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4353#L372 assume !(1 == ~t2_pc~0); 4456#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4455#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4581#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4684#L865 assume !(0 != activate_threads_~tmp___1~0#1); 4245#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4246#L391 assume 1 == ~t3_pc~0; 4788#L392 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4168#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4194#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4195#L873 assume !(0 != activate_threads_~tmp___2~0#1); 4474#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4475#L410 assume 1 == ~t4_pc~0; 4797#L411 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4697#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4366#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4367#L881 assume !(0 != activate_threads_~tmp___3~0#1); 4480#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4481#L429 assume !(1 == ~t5_pc~0); 4305#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4306#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4509#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4510#L889 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4701#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4466#L448 assume 1 == ~t6_pc~0; 4340#L449 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4341#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4667#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4668#L897 assume !(0 != activate_threads_~tmp___5~0#1); 4825#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4848#L762 assume !(1 == ~M_E~0); 4513#L762-2 assume !(1 == ~T1_E~0); 4514#L767-1 assume !(1 == ~T2_E~0); 4830#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4729#L777-1 assume !(1 == ~T4_E~0); 4624#L782-1 assume !(1 == ~T5_E~0); 4331#L787-1 assume !(1 == ~T6_E~0); 4329#L792-1 assume !(1 == ~E_M~0); 4330#L797-1 assume !(1 == ~E_1~0); 4371#L802-1 assume !(1 == ~E_2~0); 4590#L807-1 assume !(1 == ~E_3~0); 4591#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 4801#L817-1 assume !(1 == ~E_5~0); 4642#L822-1 assume !(1 == ~E_6~0); 4643#L827-1 assume { :end_inline_reset_delta_events } true; 4469#L1053-2 [2024-11-08 00:34:59,207 INFO L747 eck$LassoCheckResult]: Loop: 4469#L1053-2 assume !false; 4470#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4445#L659-1 assume !false; 4434#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 4435#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 4437#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 4703#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 4704#L570 assume !(0 != eval_~tmp~0#1); 4377#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4378#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4615#L684-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4616#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4163#L689-3 assume !(0 == ~T2_E~0); 4164#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4223#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4224#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4710#L709-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4693#L714-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4503#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4216#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4217#L729-3 assume !(0 == ~E_3~0); 4673#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4716#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4717#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4799#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4230#L334-24 assume !(1 == ~m_pc~0); 4231#L334-26 is_master_triggered_~__retres1~0#1 := 0; 4370#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4395#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4200#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4201#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4712#L353-24 assume 1 == ~t1_pc~0; 4713#L354-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4741#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4831#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4832#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4247#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4248#L372-24 assume 1 == ~t2_pc~0; 4209#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4210#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4569#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4819#L865-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4820#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4538#L391-24 assume !(1 == ~t3_pc~0); 4539#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 4754#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4715#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4625#L873-24 assume !(0 != activate_threads_~tmp___2~0#1); 4603#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4433#L410-24 assume 1 == ~t4_pc~0; 4372#L411-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4297#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4734#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4479#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4327#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4328#L429-24 assume !(1 == ~t5_pc~0); 4429#L429-26 is_transmit5_triggered_~__retres1~5#1 := 0; 4629#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4604#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4375#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4376#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4322#L448-24 assume 1 == ~t6_pc~0; 4323#L449-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4314#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4315#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4490#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4632#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4633#L762-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4598#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4599#L767-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4837#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4827#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4307#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4308#L787-3 assume !(1 == ~T6_E~0); 4742#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4535#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4536#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4781#L807-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4669#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4670#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4748#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4738#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 4562#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 4207#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 4654#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 4655#L1072 assume !(0 == start_simulation_~tmp~3#1); 4450#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 4451#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 4316#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 4270#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 4237#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4238#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4813#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 4751#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 4469#L1053-2 [2024-11-08 00:34:59,207 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:34:59,207 INFO L85 PathProgramCache]: Analyzing trace with hash -100431421, now seen corresponding path program 1 times [2024-11-08 00:34:59,207 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:34:59,207 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [374141638] [2024-11-08 00:34:59,207 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:34:59,207 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:34:59,219 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:34:59,257 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:34:59,257 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:34:59,257 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [374141638] [2024-11-08 00:34:59,257 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [374141638] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:34:59,257 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:34:59,257 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:34:59,257 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [18479769] [2024-11-08 00:34:59,258 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:34:59,258 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:34:59,258 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:34:59,258 INFO L85 PathProgramCache]: Analyzing trace with hash 929249336, now seen corresponding path program 1 times [2024-11-08 00:34:59,258 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:34:59,258 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1168525920] [2024-11-08 00:34:59,258 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:34:59,258 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:34:59,272 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:34:59,335 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:34:59,336 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:34:59,336 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1168525920] [2024-11-08 00:34:59,336 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1168525920] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:34:59,336 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:34:59,336 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:34:59,336 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [719667607] [2024-11-08 00:34:59,336 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:34:59,337 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:34:59,337 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:34:59,337 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:34:59,338 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:34:59,338 INFO L87 Difference]: Start difference. First operand 688 states and 1024 transitions. cyclomatic complexity: 337 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:34:59,351 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:34:59,351 INFO L93 Difference]: Finished difference Result 688 states and 1023 transitions. [2024-11-08 00:34:59,351 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 688 states and 1023 transitions. [2024-11-08 00:34:59,355 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 597 [2024-11-08 00:34:59,358 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 688 states to 688 states and 1023 transitions. [2024-11-08 00:34:59,358 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 688 [2024-11-08 00:34:59,359 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 688 [2024-11-08 00:34:59,359 INFO L73 IsDeterministic]: Start isDeterministic. Operand 688 states and 1023 transitions. [2024-11-08 00:34:59,360 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:34:59,360 INFO L218 hiAutomatonCegarLoop]: Abstraction has 688 states and 1023 transitions. [2024-11-08 00:34:59,361 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 688 states and 1023 transitions. [2024-11-08 00:34:59,366 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 688 to 688. [2024-11-08 00:34:59,368 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 688 states, 688 states have (on average 1.4869186046511629) internal successors, (1023), 687 states have internal predecessors, (1023), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:34:59,371 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 688 states to 688 states and 1023 transitions. [2024-11-08 00:34:59,372 INFO L240 hiAutomatonCegarLoop]: Abstraction has 688 states and 1023 transitions. [2024-11-08 00:34:59,372 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:34:59,372 INFO L425 stractBuchiCegarLoop]: Abstraction has 688 states and 1023 transitions. [2024-11-08 00:34:59,372 INFO L332 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-11-08 00:34:59,373 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 688 states and 1023 transitions. [2024-11-08 00:34:59,375 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 597 [2024-11-08 00:34:59,375 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:34:59,375 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:34:59,379 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:59,379 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:59,379 INFO L745 eck$LassoCheckResult]: Stem: 5938#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 5939#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 6064#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6065#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5733#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 5734#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6060#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6061#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5992#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5786#L495-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5787#L500-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5710#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5711#L684 assume !(0 == ~M_E~0); 6163#L684-2 assume !(0 == ~T1_E~0); 6021#L689-1 assume !(0 == ~T2_E~0); 6022#L694-1 assume !(0 == ~T3_E~0); 6019#L699-1 assume !(0 == ~T4_E~0); 6020#L704-1 assume !(0 == ~T5_E~0); 5977#L709-1 assume !(0 == ~T6_E~0); 5916#L714-1 assume 0 == ~E_M~0;~E_M~0 := 1; 5917#L719-1 assume !(0 == ~E_1~0); 6136#L724-1 assume !(0 == ~E_2~0); 5682#L729-1 assume !(0 == ~E_3~0); 5683#L734-1 assume !(0 == ~E_4~0); 6189#L739-1 assume !(0 == ~E_5~0); 5879#L744-1 assume !(0 == ~E_6~0); 5880#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5639#L334 assume !(1 == ~m_pc~0); 5640#L334-2 is_master_triggered_~__retres1~0#1 := 0; 5969#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5882#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5850#L849 assume !(0 != activate_threads_~tmp~1#1); 5851#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5783#L353 assume 1 == ~t1_pc~0; 5784#L354 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6066#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5654#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5655#L857 assume !(0 != activate_threads_~tmp___0~0#1); 5735#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5736#L372 assume !(1 == ~t2_pc~0); 5839#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 5838#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5964#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6067#L865 assume !(0 != activate_threads_~tmp___1~0#1); 5628#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5629#L391 assume 1 == ~t3_pc~0; 6173#L392 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5551#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5577#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5578#L873 assume !(0 != activate_threads_~tmp___2~0#1); 5857#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5858#L410 assume 1 == ~t4_pc~0; 6180#L411 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6081#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5749#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5750#L881 assume !(0 != activate_threads_~tmp___3~0#1); 5866#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5867#L429 assume !(1 == ~t5_pc~0); 5688#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 5689#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5892#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5893#L889 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6084#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5849#L448 assume 1 == ~t6_pc~0; 5723#L449 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5724#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6052#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6053#L897 assume !(0 != activate_threads_~tmp___5~0#1); 6208#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6231#L762 assume !(1 == ~M_E~0); 5896#L762-2 assume !(1 == ~T1_E~0); 5897#L767-1 assume !(1 == ~T2_E~0); 6213#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6112#L777-1 assume !(1 == ~T4_E~0); 6007#L782-1 assume !(1 == ~T5_E~0); 5714#L787-1 assume !(1 == ~T6_E~0); 5712#L792-1 assume !(1 == ~E_M~0); 5713#L797-1 assume !(1 == ~E_1~0); 5755#L802-1 assume !(1 == ~E_2~0); 5973#L807-1 assume !(1 == ~E_3~0); 5974#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 6184#L817-1 assume !(1 == ~E_5~0); 6025#L822-1 assume !(1 == ~E_6~0); 6026#L827-1 assume { :end_inline_reset_delta_events } true; 5852#L1053-2 [2024-11-08 00:34:59,379 INFO L747 eck$LassoCheckResult]: Loop: 5852#L1053-2 assume !false; 5853#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5828#L659-1 assume !false; 5817#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 5818#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 5820#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 6086#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 6087#L570 assume !(0 != eval_~tmp~0#1); 5762#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5763#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5998#L684-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5999#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5546#L689-3 assume !(0 == ~T2_E~0); 5547#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5606#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5607#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6093#L709-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6078#L714-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5891#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5599#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5600#L729-3 assume !(0 == ~E_3~0); 6057#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6099#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6100#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 6182#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5613#L334-24 assume !(1 == ~m_pc~0); 5614#L334-26 is_master_triggered_~__retres1~0#1 := 0; 5753#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5778#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5583#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5584#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6094#L353-24 assume !(1 == ~t1_pc~0); 6096#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 6124#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6214#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6215#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5630#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5631#L372-24 assume 1 == ~t2_pc~0; 5592#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5593#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5952#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6201#L865-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6202#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5921#L391-24 assume !(1 == ~t3_pc~0); 5922#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 6137#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6097#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6008#L873-24 assume !(0 != activate_threads_~tmp___2~0#1); 5983#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5816#L410-24 assume 1 == ~t4_pc~0; 5754#L411-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5680#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6117#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5862#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5708#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5709#L429-24 assume !(1 == ~t5_pc~0); 5812#L429-26 is_transmit5_triggered_~__retres1~5#1 := 0; 6012#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5984#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5758#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5759#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5703#L448-24 assume 1 == ~t6_pc~0; 5704#L449-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5697#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5698#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5873#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 6015#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6016#L762-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5981#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5982#L767-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6220#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6210#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5690#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5691#L787-3 assume !(1 == ~T6_E~0); 6125#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5918#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5919#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6164#L807-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6050#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6051#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6131#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 6121#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 5945#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 5590#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 6037#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 6038#L1072 assume !(0 == start_simulation_~tmp~3#1); 5833#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 5834#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 5699#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 5653#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 5620#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5621#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6196#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 6134#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 5852#L1053-2 [2024-11-08 00:34:59,380 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:34:59,380 INFO L85 PathProgramCache]: Analyzing trace with hash 1976905477, now seen corresponding path program 1 times [2024-11-08 00:34:59,381 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:34:59,381 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1440943761] [2024-11-08 00:34:59,381 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:34:59,381 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:34:59,390 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:34:59,417 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:34:59,417 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:34:59,417 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1440943761] [2024-11-08 00:34:59,417 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1440943761] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:34:59,417 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:34:59,417 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:34:59,417 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [867616193] [2024-11-08 00:34:59,417 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:34:59,418 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:34:59,418 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:34:59,418 INFO L85 PathProgramCache]: Analyzing trace with hash 1506177977, now seen corresponding path program 1 times [2024-11-08 00:34:59,418 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:34:59,418 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1079160114] [2024-11-08 00:34:59,418 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:34:59,419 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:34:59,430 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:34:59,472 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:34:59,472 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:34:59,472 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1079160114] [2024-11-08 00:34:59,472 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1079160114] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:34:59,472 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:34:59,472 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:34:59,472 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1876753703] [2024-11-08 00:34:59,472 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:34:59,472 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:34:59,472 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:34:59,473 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:34:59,473 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:34:59,473 INFO L87 Difference]: Start difference. First operand 688 states and 1023 transitions. cyclomatic complexity: 336 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:34:59,493 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:34:59,493 INFO L93 Difference]: Finished difference Result 688 states and 1022 transitions. [2024-11-08 00:34:59,493 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 688 states and 1022 transitions. [2024-11-08 00:34:59,500 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 597 [2024-11-08 00:34:59,506 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 688 states to 688 states and 1022 transitions. [2024-11-08 00:34:59,506 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 688 [2024-11-08 00:34:59,506 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 688 [2024-11-08 00:34:59,507 INFO L73 IsDeterministic]: Start isDeterministic. Operand 688 states and 1022 transitions. [2024-11-08 00:34:59,507 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:34:59,507 INFO L218 hiAutomatonCegarLoop]: Abstraction has 688 states and 1022 transitions. [2024-11-08 00:34:59,508 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 688 states and 1022 transitions. [2024-11-08 00:34:59,520 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 688 to 688. [2024-11-08 00:34:59,521 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 688 states, 688 states have (on average 1.4854651162790697) internal successors, (1022), 687 states have internal predecessors, (1022), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:34:59,523 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 688 states to 688 states and 1022 transitions. [2024-11-08 00:34:59,523 INFO L240 hiAutomatonCegarLoop]: Abstraction has 688 states and 1022 transitions. [2024-11-08 00:34:59,525 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:34:59,526 INFO L425 stractBuchiCegarLoop]: Abstraction has 688 states and 1022 transitions. [2024-11-08 00:34:59,526 INFO L332 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-11-08 00:34:59,526 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 688 states and 1022 transitions. [2024-11-08 00:34:59,528 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 597 [2024-11-08 00:34:59,528 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:34:59,528 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:34:59,529 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:59,529 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:59,529 INFO L745 eck$LassoCheckResult]: Stem: 7319#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 7320#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 7445#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7446#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7113#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 7114#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7443#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7444#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7375#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7169#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 7170#L500-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 7091#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7092#L684 assume !(0 == ~M_E~0); 7545#L684-2 assume !(0 == ~T1_E~0); 7404#L689-1 assume !(0 == ~T2_E~0); 7405#L694-1 assume !(0 == ~T3_E~0); 7402#L699-1 assume !(0 == ~T4_E~0); 7403#L704-1 assume !(0 == ~T5_E~0); 7360#L709-1 assume !(0 == ~T6_E~0); 7299#L714-1 assume 0 == ~E_M~0;~E_M~0 := 1; 7300#L719-1 assume !(0 == ~E_1~0); 7519#L724-1 assume !(0 == ~E_2~0); 7065#L729-1 assume !(0 == ~E_3~0); 7066#L734-1 assume !(0 == ~E_4~0); 7572#L739-1 assume !(0 == ~E_5~0); 7262#L744-1 assume !(0 == ~E_6~0); 7263#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7022#L334 assume !(1 == ~m_pc~0); 7023#L334-2 is_master_triggered_~__retres1~0#1 := 0; 7352#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7264#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7233#L849 assume !(0 != activate_threads_~tmp~1#1); 7234#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7166#L353 assume 1 == ~t1_pc~0; 7167#L354 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7449#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7037#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7038#L857 assume !(0 != activate_threads_~tmp___0~0#1); 7118#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7119#L372 assume !(1 == ~t2_pc~0); 7222#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 7221#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7347#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7450#L865 assume !(0 != activate_threads_~tmp___1~0#1); 7011#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7012#L391 assume 1 == ~t3_pc~0; 7554#L392 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6934#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6960#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6961#L873 assume !(0 != activate_threads_~tmp___2~0#1); 7240#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7241#L410 assume 1 == ~t4_pc~0; 7562#L411 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7463#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7132#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7133#L881 assume !(0 != activate_threads_~tmp___3~0#1); 7246#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7247#L429 assume !(1 == ~t5_pc~0); 7071#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 7072#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7275#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7276#L889 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7467#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7232#L448 assume 1 == ~t6_pc~0; 7106#L449 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 7107#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7433#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7434#L897 assume !(0 != activate_threads_~tmp___5~0#1); 7591#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7614#L762 assume !(1 == ~M_E~0); 7279#L762-2 assume !(1 == ~T1_E~0); 7280#L767-1 assume !(1 == ~T2_E~0); 7596#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7495#L777-1 assume !(1 == ~T4_E~0); 7390#L782-1 assume !(1 == ~T5_E~0); 7097#L787-1 assume !(1 == ~T6_E~0); 7095#L792-1 assume !(1 == ~E_M~0); 7096#L797-1 assume !(1 == ~E_1~0); 7137#L802-1 assume !(1 == ~E_2~0); 7356#L807-1 assume !(1 == ~E_3~0); 7357#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 7567#L817-1 assume !(1 == ~E_5~0); 7406#L822-1 assume !(1 == ~E_6~0); 7407#L827-1 assume { :end_inline_reset_delta_events } true; 7235#L1053-2 [2024-11-08 00:34:59,529 INFO L747 eck$LassoCheckResult]: Loop: 7235#L1053-2 assume !false; 7236#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7211#L659-1 assume !false; 7200#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 7201#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 7203#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 7469#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 7470#L570 assume !(0 != eval_~tmp~0#1); 7143#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7144#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7379#L684-3 assume 0 == ~M_E~0;~M_E~0 := 1; 7380#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6929#L689-3 assume !(0 == ~T2_E~0); 6930#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6989#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6990#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7476#L709-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7459#L714-3 assume 0 == ~E_M~0;~E_M~0 := 1; 7269#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6982#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6983#L729-3 assume !(0 == ~E_3~0); 7439#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7482#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7483#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 7565#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6996#L334-24 assume !(1 == ~m_pc~0); 6997#L334-26 is_master_triggered_~__retres1~0#1 := 0; 7136#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7161#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 6966#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6967#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7478#L353-24 assume 1 == ~t1_pc~0; 7479#L354-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7507#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7597#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7598#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7013#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7014#L372-24 assume !(1 == ~t2_pc~0); 6977#L372-26 is_transmit2_triggered_~__retres1~2#1 := 0; 6976#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7335#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7585#L865-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7586#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7304#L391-24 assume !(1 == ~t3_pc~0); 7305#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 7520#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7481#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7391#L873-24 assume !(0 != activate_threads_~tmp___2~0#1); 7369#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7199#L410-24 assume 1 == ~t4_pc~0; 7138#L411-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7063#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7500#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7245#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7093#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7094#L429-24 assume !(1 == ~t5_pc~0); 7195#L429-26 is_transmit5_triggered_~__retres1~5#1 := 0; 7395#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7370#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7141#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7142#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7088#L448-24 assume 1 == ~t6_pc~0; 7089#L449-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 7080#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7081#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7256#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7398#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7399#L762-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7364#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7365#L767-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7603#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7593#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7073#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7074#L787-3 assume !(1 == ~T6_E~0); 7508#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 7301#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7302#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7547#L807-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7435#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7436#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7514#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 7504#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 7328#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 6973#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 7420#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 7421#L1072 assume !(0 == start_simulation_~tmp~3#1); 7216#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 7217#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 7082#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 7036#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 7003#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7004#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7579#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 7517#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 7235#L1053-2 [2024-11-08 00:34:59,530 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:34:59,530 INFO L85 PathProgramCache]: Analyzing trace with hash 242801027, now seen corresponding path program 1 times [2024-11-08 00:34:59,530 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:34:59,530 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1618484142] [2024-11-08 00:34:59,530 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:34:59,530 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:34:59,539 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:34:59,561 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:34:59,562 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:34:59,562 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1618484142] [2024-11-08 00:34:59,562 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1618484142] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:34:59,562 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:34:59,562 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:34:59,562 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [829638772] [2024-11-08 00:34:59,562 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:34:59,562 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:34:59,562 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:34:59,562 INFO L85 PathProgramCache]: Analyzing trace with hash 1169516665, now seen corresponding path program 1 times [2024-11-08 00:34:59,562 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:34:59,562 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [781505096] [2024-11-08 00:34:59,562 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:34:59,562 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:34:59,572 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:34:59,610 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:34:59,611 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:34:59,611 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [781505096] [2024-11-08 00:34:59,611 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [781505096] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:34:59,612 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:34:59,612 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:34:59,612 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [234054943] [2024-11-08 00:34:59,612 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:34:59,612 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:34:59,612 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:34:59,613 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:34:59,613 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:34:59,613 INFO L87 Difference]: Start difference. First operand 688 states and 1022 transitions. cyclomatic complexity: 335 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:34:59,626 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:34:59,626 INFO L93 Difference]: Finished difference Result 688 states and 1021 transitions. [2024-11-08 00:34:59,626 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 688 states and 1021 transitions. [2024-11-08 00:34:59,631 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 597 [2024-11-08 00:34:59,634 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 688 states to 688 states and 1021 transitions. [2024-11-08 00:34:59,634 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 688 [2024-11-08 00:34:59,635 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 688 [2024-11-08 00:34:59,635 INFO L73 IsDeterministic]: Start isDeterministic. Operand 688 states and 1021 transitions. [2024-11-08 00:34:59,636 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:34:59,636 INFO L218 hiAutomatonCegarLoop]: Abstraction has 688 states and 1021 transitions. [2024-11-08 00:34:59,637 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 688 states and 1021 transitions. [2024-11-08 00:34:59,643 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 688 to 688. [2024-11-08 00:34:59,645 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 688 states, 688 states have (on average 1.4840116279069768) internal successors, (1021), 687 states have internal predecessors, (1021), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:34:59,647 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 688 states to 688 states and 1021 transitions. [2024-11-08 00:34:59,647 INFO L240 hiAutomatonCegarLoop]: Abstraction has 688 states and 1021 transitions. [2024-11-08 00:34:59,649 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:34:59,650 INFO L425 stractBuchiCegarLoop]: Abstraction has 688 states and 1021 transitions. [2024-11-08 00:34:59,650 INFO L332 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-11-08 00:34:59,650 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 688 states and 1021 transitions. [2024-11-08 00:34:59,653 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 597 [2024-11-08 00:34:59,653 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:34:59,653 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:34:59,655 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:59,656 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:59,656 INFO L745 eck$LassoCheckResult]: Stem: 8702#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 8703#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 8828#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8829#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8496#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 8497#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8826#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8827#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8758#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 8552#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 8553#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 8474#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8475#L684 assume !(0 == ~M_E~0); 8928#L684-2 assume !(0 == ~T1_E~0); 8787#L689-1 assume !(0 == ~T2_E~0); 8788#L694-1 assume !(0 == ~T3_E~0); 8785#L699-1 assume !(0 == ~T4_E~0); 8786#L704-1 assume !(0 == ~T5_E~0); 8743#L709-1 assume !(0 == ~T6_E~0); 8682#L714-1 assume 0 == ~E_M~0;~E_M~0 := 1; 8683#L719-1 assume !(0 == ~E_1~0); 8902#L724-1 assume !(0 == ~E_2~0); 8448#L729-1 assume !(0 == ~E_3~0); 8449#L734-1 assume !(0 == ~E_4~0); 8955#L739-1 assume !(0 == ~E_5~0); 8645#L744-1 assume !(0 == ~E_6~0); 8646#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8405#L334 assume !(1 == ~m_pc~0); 8406#L334-2 is_master_triggered_~__retres1~0#1 := 0; 8735#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8647#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 8616#L849 assume !(0 != activate_threads_~tmp~1#1); 8617#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8549#L353 assume 1 == ~t1_pc~0; 8550#L354 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8832#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8420#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 8421#L857 assume !(0 != activate_threads_~tmp___0~0#1); 8501#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8502#L372 assume !(1 == ~t2_pc~0); 8605#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 8604#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8730#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8833#L865 assume !(0 != activate_threads_~tmp___1~0#1); 8394#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8395#L391 assume 1 == ~t3_pc~0; 8937#L392 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8317#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8343#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8344#L873 assume !(0 != activate_threads_~tmp___2~0#1); 8623#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8624#L410 assume 1 == ~t4_pc~0; 8946#L411 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8846#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8515#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8516#L881 assume !(0 != activate_threads_~tmp___3~0#1); 8629#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8630#L429 assume !(1 == ~t5_pc~0); 8454#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 8455#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8658#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8659#L889 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8850#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8615#L448 assume 1 == ~t6_pc~0; 8489#L449 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8490#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8818#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8819#L897 assume !(0 != activate_threads_~tmp___5~0#1); 8974#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8997#L762 assume !(1 == ~M_E~0); 8662#L762-2 assume !(1 == ~T1_E~0); 8663#L767-1 assume !(1 == ~T2_E~0); 8979#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8878#L777-1 assume !(1 == ~T4_E~0); 8773#L782-1 assume !(1 == ~T5_E~0); 8480#L787-1 assume !(1 == ~T6_E~0); 8478#L792-1 assume !(1 == ~E_M~0); 8479#L797-1 assume !(1 == ~E_1~0); 8520#L802-1 assume !(1 == ~E_2~0); 8739#L807-1 assume !(1 == ~E_3~0); 8740#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 8950#L817-1 assume !(1 == ~E_5~0); 8791#L822-1 assume !(1 == ~E_6~0); 8792#L827-1 assume { :end_inline_reset_delta_events } true; 8618#L1053-2 [2024-11-08 00:34:59,659 INFO L747 eck$LassoCheckResult]: Loop: 8618#L1053-2 assume !false; 8619#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8594#L659-1 assume !false; 8583#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 8584#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 8586#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 8852#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 8853#L570 assume !(0 != eval_~tmp~0#1); 8526#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8527#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8764#L684-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8765#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8312#L689-3 assume !(0 == ~T2_E~0); 8313#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8372#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8373#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8859#L709-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8842#L714-3 assume 0 == ~E_M~0;~E_M~0 := 1; 8652#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8365#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8366#L729-3 assume !(0 == ~E_3~0); 8822#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8865#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8866#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 8948#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8379#L334-24 assume !(1 == ~m_pc~0); 8380#L334-26 is_master_triggered_~__retres1~0#1 := 0; 8519#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8544#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 8349#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8350#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8861#L353-24 assume 1 == ~t1_pc~0; 8862#L354-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8890#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8980#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 8981#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8396#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8397#L372-24 assume 1 == ~t2_pc~0; 8358#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8359#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8718#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8968#L865-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8969#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8687#L391-24 assume !(1 == ~t3_pc~0); 8688#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 8903#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8864#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8774#L873-24 assume !(0 != activate_threads_~tmp___2~0#1); 8753#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8582#L410-24 assume 1 == ~t4_pc~0; 8521#L411-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8446#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8883#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8628#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8476#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8477#L429-24 assume !(1 == ~t5_pc~0); 8578#L429-26 is_transmit5_triggered_~__retres1~5#1 := 0; 8778#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8749#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8522#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8523#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8468#L448-24 assume 1 == ~t6_pc~0; 8469#L449-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8463#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8464#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8639#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 8781#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8782#L762-3 assume 1 == ~M_E~0;~M_E~0 := 2; 8747#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8748#L767-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8986#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8976#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8456#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8457#L787-3 assume !(1 == ~T6_E~0); 8891#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8684#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8685#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8930#L807-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8816#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8817#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8897#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8887#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 8710#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 8354#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 8803#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 8804#L1072 assume !(0 == start_simulation_~tmp~3#1); 8599#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 8600#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 8465#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 8419#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 8384#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8385#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8962#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 8900#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 8618#L1053-2 [2024-11-08 00:34:59,660 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:34:59,660 INFO L85 PathProgramCache]: Analyzing trace with hash -644421819, now seen corresponding path program 1 times [2024-11-08 00:34:59,660 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:34:59,660 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [179393892] [2024-11-08 00:34:59,660 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:34:59,661 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:34:59,675 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:34:59,749 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:34:59,750 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:34:59,750 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [179393892] [2024-11-08 00:34:59,750 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [179393892] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:34:59,750 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:34:59,750 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:34:59,750 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [160600179] [2024-11-08 00:34:59,750 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:34:59,750 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:34:59,750 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:34:59,750 INFO L85 PathProgramCache]: Analyzing trace with hash 929249336, now seen corresponding path program 2 times [2024-11-08 00:34:59,750 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:34:59,751 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2025068681] [2024-11-08 00:34:59,751 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:34:59,751 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:34:59,763 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:34:59,790 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:34:59,791 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:34:59,791 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2025068681] [2024-11-08 00:34:59,791 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2025068681] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:34:59,791 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:34:59,791 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:34:59,791 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [150851345] [2024-11-08 00:34:59,791 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:34:59,791 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:34:59,791 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:34:59,792 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-08 00:34:59,792 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-08 00:34:59,792 INFO L87 Difference]: Start difference. First operand 688 states and 1021 transitions. cyclomatic complexity: 334 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:34:59,914 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:34:59,914 INFO L93 Difference]: Finished difference Result 1184 states and 1752 transitions. [2024-11-08 00:34:59,915 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1184 states and 1752 transitions. [2024-11-08 00:34:59,920 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1078 [2024-11-08 00:34:59,924 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1184 states to 1184 states and 1752 transitions. [2024-11-08 00:34:59,925 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1184 [2024-11-08 00:34:59,925 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1184 [2024-11-08 00:34:59,925 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1184 states and 1752 transitions. [2024-11-08 00:34:59,927 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:34:59,927 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1184 states and 1752 transitions. [2024-11-08 00:34:59,929 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1184 states and 1752 transitions. [2024-11-08 00:34:59,940 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1184 to 1183. [2024-11-08 00:34:59,942 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1183 states, 1183 states have (on average 1.4801352493660187) internal successors, (1751), 1182 states have internal predecessors, (1751), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:34:59,945 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1183 states to 1183 states and 1751 transitions. [2024-11-08 00:34:59,945 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1183 states and 1751 transitions. [2024-11-08 00:34:59,945 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-08 00:34:59,946 INFO L425 stractBuchiCegarLoop]: Abstraction has 1183 states and 1751 transitions. [2024-11-08 00:34:59,946 INFO L332 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-11-08 00:34:59,946 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1183 states and 1751 transitions. [2024-11-08 00:34:59,950 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1078 [2024-11-08 00:34:59,950 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:34:59,950 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:34:59,951 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:59,951 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:34:59,951 INFO L745 eck$LassoCheckResult]: Stem: 10586#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 10587#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 10718#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10719#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10380#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 10381#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10716#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10717#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10646#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 10436#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 10437#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 10357#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10358#L684 assume !(0 == ~M_E~0); 10823#L684-2 assume !(0 == ~T1_E~0); 10676#L689-1 assume !(0 == ~T2_E~0); 10677#L694-1 assume !(0 == ~T3_E~0); 10674#L699-1 assume !(0 == ~T4_E~0); 10675#L704-1 assume !(0 == ~T5_E~0); 10631#L709-1 assume !(0 == ~T6_E~0); 10566#L714-1 assume !(0 == ~E_M~0); 10567#L719-1 assume !(0 == ~E_1~0); 10795#L724-1 assume !(0 == ~E_2~0); 10331#L729-1 assume !(0 == ~E_3~0); 10332#L734-1 assume !(0 == ~E_4~0); 10851#L739-1 assume !(0 == ~E_5~0); 10529#L744-1 assume !(0 == ~E_6~0); 10530#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10287#L334 assume !(1 == ~m_pc~0); 10288#L334-2 is_master_triggered_~__retres1~0#1 := 0; 10623#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10531#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 10500#L849 assume !(0 != activate_threads_~tmp~1#1); 10501#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10433#L353 assume 1 == ~t1_pc~0; 10434#L354 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10722#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10303#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 10304#L857 assume !(0 != activate_threads_~tmp___0~0#1); 10385#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10386#L372 assume !(1 == ~t2_pc~0); 10489#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 10488#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10617#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10723#L865 assume !(0 != activate_threads_~tmp___1~0#1); 10276#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10277#L391 assume 1 == ~t3_pc~0; 10832#L392 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10199#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10225#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10226#L873 assume !(0 != activate_threads_~tmp___2~0#1); 10507#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10508#L410 assume 1 == ~t4_pc~0; 10840#L411 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10736#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10399#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10400#L881 assume !(0 != activate_threads_~tmp___3~0#1); 10513#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10514#L429 assume !(1 == ~t5_pc~0); 10337#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 10338#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10542#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10543#L889 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 10741#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10499#L448 assume 1 == ~t6_pc~0; 10373#L449 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10374#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10706#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10707#L897 assume !(0 != activate_threads_~tmp___5~0#1); 10872#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10899#L762 assume 1 == ~M_E~0;~M_E~0 := 2; 10546#L762-2 assume !(1 == ~T1_E~0); 10547#L767-1 assume !(1 == ~T2_E~0); 10977#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10974#L777-1 assume !(1 == ~T4_E~0); 10972#L782-1 assume !(1 == ~T5_E~0); 10970#L787-1 assume !(1 == ~T6_E~0); 10968#L792-1 assume !(1 == ~E_M~0); 10362#L797-1 assume !(1 == ~E_1~0); 10963#L802-1 assume !(1 == ~E_2~0); 10961#L807-1 assume !(1 == ~E_3~0); 10959#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 10958#L817-1 assume !(1 == ~E_5~0); 10942#L822-1 assume !(1 == ~E_6~0); 10934#L827-1 assume { :end_inline_reset_delta_events } true; 10929#L1053-2 [2024-11-08 00:34:59,952 INFO L747 eck$LassoCheckResult]: Loop: 10929#L1053-2 assume !false; 10842#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10478#L659-1 assume !false; 10467#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 10468#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 10470#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 10743#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 10744#L570 assume !(0 != eval_~tmp~0#1); 10788#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10909#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10907#L684-3 assume 0 == ~M_E~0;~M_E~0 := 1; 10908#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11370#L689-3 assume !(0 == ~T2_E~0); 11369#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11368#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11367#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11366#L709-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11365#L714-3 assume !(0 == ~E_M~0); 11364#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11363#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 11362#L729-3 assume !(0 == ~E_3~0); 11361#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 11360#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 11359#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 11358#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11357#L334-24 assume !(1 == ~m_pc~0); 11355#L334-26 is_master_triggered_~__retres1~0#1 := 0; 11354#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11353#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 11352#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 11351#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11350#L353-24 assume 1 == ~t1_pc~0; 11348#L354-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 11347#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11346#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 11345#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11344#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11343#L372-24 assume !(1 == ~t2_pc~0); 11341#L372-26 is_transmit2_triggered_~__retres1~2#1 := 0; 11340#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11339#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11338#L865-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11337#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11336#L391-24 assume 1 == ~t3_pc~0; 11334#L392-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11333#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11332#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 11331#L873-24 assume !(0 != activate_threads_~tmp___2~0#1); 11330#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11329#L410-24 assume !(1 == ~t4_pc~0); 11328#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 11326#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11325#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 11324#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 11323#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11322#L429-24 assume !(1 == ~t5_pc~0); 11320#L429-26 is_transmit5_triggered_~__retres1~5#1 := 0; 11318#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11315#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11313#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 11311#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11309#L448-24 assume 1 == ~t6_pc~0; 11306#L449-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11304#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11301#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11299#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 11297#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11296#L762-3 assume 1 == ~M_E~0;~M_E~0 := 2; 10854#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11295#L767-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11294#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11293#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11292#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 11291#L787-3 assume !(1 == ~T6_E~0); 11290#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 10783#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 11289#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 11288#L807-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10708#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10709#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 10790#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 10778#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 10597#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 10238#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 10692#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 10693#L1072 assume !(0 == start_simulation_~tmp~3#1); 10483#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 10484#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 10348#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 10301#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 10302#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10978#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10943#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 10935#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 10929#L1053-2 [2024-11-08 00:34:59,952 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:34:59,952 INFO L85 PathProgramCache]: Analyzing trace with hash -1050737979, now seen corresponding path program 1 times [2024-11-08 00:34:59,952 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:34:59,952 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1786427853] [2024-11-08 00:34:59,952 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:34:59,952 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:34:59,960 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:00,000 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:00,001 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:00,001 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1786427853] [2024-11-08 00:35:00,001 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1786427853] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:00,001 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:00,001 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-08 00:35:00,001 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1706566090] [2024-11-08 00:35:00,001 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:00,001 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:35:00,002 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:00,002 INFO L85 PathProgramCache]: Analyzing trace with hash -1871021509, now seen corresponding path program 1 times [2024-11-08 00:35:00,002 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:00,004 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1581989089] [2024-11-08 00:35:00,004 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:00,004 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:00,013 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:00,049 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:00,050 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:00,050 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1581989089] [2024-11-08 00:35:00,050 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1581989089] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:00,050 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:00,051 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:00,051 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2138719703] [2024-11-08 00:35:00,051 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:00,051 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:35:00,051 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:35:00,051 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:35:00,051 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:35:00,052 INFO L87 Difference]: Start difference. First operand 1183 states and 1751 transitions. cyclomatic complexity: 570 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 2 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:00,115 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:35:00,115 INFO L93 Difference]: Finished difference Result 2142 states and 3143 transitions. [2024-11-08 00:35:00,115 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2142 states and 3143 transitions. [2024-11-08 00:35:00,125 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2034 [2024-11-08 00:35:00,133 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2142 states to 2142 states and 3143 transitions. [2024-11-08 00:35:00,133 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2142 [2024-11-08 00:35:00,135 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2142 [2024-11-08 00:35:00,135 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2142 states and 3143 transitions. [2024-11-08 00:35:00,137 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:35:00,137 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2142 states and 3143 transitions. [2024-11-08 00:35:00,139 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2142 states and 3143 transitions. [2024-11-08 00:35:00,163 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2142 to 2138. [2024-11-08 00:35:00,166 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2138 states, 2138 states have (on average 1.4681945743685687) internal successors, (3139), 2137 states have internal predecessors, (3139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:00,172 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2138 states to 2138 states and 3139 transitions. [2024-11-08 00:35:00,173 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2138 states and 3139 transitions. [2024-11-08 00:35:00,173 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:35:00,175 INFO L425 stractBuchiCegarLoop]: Abstraction has 2138 states and 3139 transitions. [2024-11-08 00:35:00,176 INFO L332 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-11-08 00:35:00,176 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2138 states and 3139 transitions. [2024-11-08 00:35:00,183 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2030 [2024-11-08 00:35:00,183 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:35:00,183 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:35:00,184 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:00,184 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:00,184 INFO L745 eck$LassoCheckResult]: Stem: 13932#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 13933#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 14067#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14068#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 13715#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 13716#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14063#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14064#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 13988#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 13770#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 13771#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 13692#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13693#L684 assume !(0 == ~M_E~0); 14181#L684-2 assume !(0 == ~T1_E~0); 14023#L689-1 assume !(0 == ~T2_E~0); 14024#L694-1 assume !(0 == ~T3_E~0); 14021#L699-1 assume !(0 == ~T4_E~0); 14022#L704-1 assume !(0 == ~T5_E~0); 13972#L709-1 assume !(0 == ~T6_E~0); 13910#L714-1 assume !(0 == ~E_M~0); 13911#L719-1 assume !(0 == ~E_1~0); 14151#L724-1 assume !(0 == ~E_2~0); 13662#L729-1 assume !(0 == ~E_3~0); 13663#L734-1 assume !(0 == ~E_4~0); 14219#L739-1 assume !(0 == ~E_5~0); 13873#L744-1 assume !(0 == ~E_6~0); 13874#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13619#L334 assume !(1 == ~m_pc~0); 13620#L334-2 is_master_triggered_~__retres1~0#1 := 0; 13964#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13876#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 13841#L849 assume !(0 != activate_threads_~tmp~1#1); 13842#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13768#L353 assume !(1 == ~t1_pc~0); 13769#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 14069#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13634#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 13635#L857 assume !(0 != activate_threads_~tmp___0~0#1); 13719#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13720#L372 assume !(1 == ~t2_pc~0); 13828#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 13827#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13959#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 14070#L865 assume !(0 != activate_threads_~tmp___1~0#1); 13607#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13608#L391 assume 1 == ~t3_pc~0; 14194#L392 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 13531#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13556#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 13557#L873 assume !(0 != activate_threads_~tmp___2~0#1); 13848#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13849#L410 assume 1 == ~t4_pc~0; 14205#L411 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 14087#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13734#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 13735#L881 assume !(0 != activate_threads_~tmp___3~0#1); 13858#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13859#L429 assume !(1 == ~t5_pc~0); 13668#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 13669#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13886#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 13887#L889 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 14091#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13838#L448 assume 1 == ~t6_pc~0; 13706#L449 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13707#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14054#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14055#L897 assume !(0 != activate_threads_~tmp___5~0#1); 14243#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14282#L762 assume 1 == ~M_E~0;~M_E~0 := 2; 14283#L762-2 assume !(1 == ~T1_E~0); 15334#L767-1 assume !(1 == ~T2_E~0); 15332#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15330#L777-1 assume !(1 == ~T4_E~0); 15329#L782-1 assume !(1 == ~T5_E~0); 15327#L787-1 assume !(1 == ~T6_E~0); 15325#L792-1 assume !(1 == ~E_M~0); 13695#L797-1 assume !(1 == ~E_1~0); 15322#L802-1 assume !(1 == ~E_2~0); 15320#L807-1 assume !(1 == ~E_3~0); 15319#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 15318#L817-1 assume !(1 == ~E_5~0); 15317#L822-1 assume !(1 == ~E_6~0); 15263#L827-1 assume { :end_inline_reset_delta_events } true; 13843#L1053-2 [2024-11-08 00:35:00,185 INFO L747 eck$LassoCheckResult]: Loop: 13843#L1053-2 assume !false; 13844#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 15216#L659-1 assume !false; 15215#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 15213#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 15207#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 15206#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 14142#L570 assume !(0 != eval_~tmp~0#1); 13745#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 13746#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14222#L684-3 assume 0 == ~M_E~0;~M_E~0 := 1; 15202#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 15663#L689-3 assume !(0 == ~T2_E~0); 15662#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 15661#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 15660#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 15659#L709-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 15658#L714-3 assume !(0 == ~E_M~0); 15657#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 15656#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 15655#L729-3 assume !(0 == ~E_3~0); 15654#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 15653#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 15652#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 15651#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15650#L334-24 assume !(1 == ~m_pc~0); 15648#L334-26 is_master_triggered_~__retres1~0#1 := 0; 15647#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15646#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 15645#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 15644#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15643#L353-24 assume !(1 == ~t1_pc~0); 15642#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 15641#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15640#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 15639#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 15638#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15637#L372-24 assume !(1 == ~t2_pc~0); 15635#L372-26 is_transmit2_triggered_~__retres1~2#1 := 0; 15634#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15581#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 15580#L865-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 15579#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15578#L391-24 assume 1 == ~t3_pc~0; 15576#L392-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15575#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15574#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 15573#L873-24 assume !(0 != activate_threads_~tmp___2~0#1); 15572#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15571#L410-24 assume 1 == ~t4_pc~0; 15569#L411-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 15568#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15567#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15566#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 15564#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15562#L429-24 assume !(1 == ~t5_pc~0); 15559#L429-26 is_transmit5_triggered_~__retres1~5#1 := 0; 14124#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13979#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 13743#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 13744#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13941#L448-24 assume 1 == ~t6_pc~0; 15547#L449-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 15545#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13866#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13867#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 14015#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14016#L762-3 assume 1 == ~M_E~0;~M_E~0 := 2; 14223#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15534#L767-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14291#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14292#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15529#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14284#L787-3 assume !(1 == ~T6_E~0); 14285#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 14137#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 15527#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 15526#L807-3 assume 1 == ~E_3~0;~E_3~0 := 2; 15525#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 15524#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 15523#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 15522#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 15517#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 15514#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 15513#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 14278#L1072 assume !(0 == start_simulation_~tmp~3#1); 14279#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 14217#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 13679#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 13633#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 13597#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 13598#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 15265#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 15264#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 13843#L1053-2 [2024-11-08 00:35:00,185 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:00,185 INFO L85 PathProgramCache]: Analyzing trace with hash 1143388102, now seen corresponding path program 1 times [2024-11-08 00:35:00,185 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:00,185 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [41108311] [2024-11-08 00:35:00,185 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:00,185 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:00,194 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:00,228 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:00,228 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:00,228 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [41108311] [2024-11-08 00:35:00,228 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [41108311] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:00,228 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:00,229 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-08 00:35:00,229 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1407346445] [2024-11-08 00:35:00,229 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:00,229 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:35:00,229 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:00,230 INFO L85 PathProgramCache]: Analyzing trace with hash -420615173, now seen corresponding path program 1 times [2024-11-08 00:35:00,230 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:00,230 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2013685582] [2024-11-08 00:35:00,230 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:00,230 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:00,241 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:00,261 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:00,261 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:00,262 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2013685582] [2024-11-08 00:35:00,262 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2013685582] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:00,262 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:00,262 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:00,262 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [708030778] [2024-11-08 00:35:00,262 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:00,262 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:35:00,262 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:35:00,263 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:35:00,263 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:35:00,263 INFO L87 Difference]: Start difference. First operand 2138 states and 3139 transitions. cyclomatic complexity: 1005 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 2 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:00,338 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:35:00,339 INFO L93 Difference]: Finished difference Result 3935 states and 5736 transitions. [2024-11-08 00:35:00,339 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3935 states and 5736 transitions. [2024-11-08 00:35:00,376 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3820 [2024-11-08 00:35:00,390 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3935 states to 3935 states and 5736 transitions. [2024-11-08 00:35:00,390 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3935 [2024-11-08 00:35:00,393 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3935 [2024-11-08 00:35:00,393 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3935 states and 5736 transitions. [2024-11-08 00:35:00,396 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:35:00,397 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3935 states and 5736 transitions. [2024-11-08 00:35:00,399 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3935 states and 5736 transitions. [2024-11-08 00:35:00,436 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3935 to 3927. [2024-11-08 00:35:00,441 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3927 states, 3927 states have (on average 1.458619811560988) internal successors, (5728), 3926 states have internal predecessors, (5728), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:00,452 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3927 states to 3927 states and 5728 transitions. [2024-11-08 00:35:00,453 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3927 states and 5728 transitions. [2024-11-08 00:35:00,453 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:35:00,454 INFO L425 stractBuchiCegarLoop]: Abstraction has 3927 states and 5728 transitions. [2024-11-08 00:35:00,454 INFO L332 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-11-08 00:35:00,454 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3927 states and 5728 transitions. [2024-11-08 00:35:00,463 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3812 [2024-11-08 00:35:00,464 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:35:00,464 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:35:00,464 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:00,465 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:00,465 INFO L745 eck$LassoCheckResult]: Stem: 20011#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 20012#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 20153#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20154#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19794#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 19795#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 20149#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 20150#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20069#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 19848#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 19849#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 19770#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 19771#L684 assume !(0 == ~M_E~0); 20278#L684-2 assume !(0 == ~T1_E~0); 20105#L689-1 assume !(0 == ~T2_E~0); 20106#L694-1 assume !(0 == ~T3_E~0); 20103#L699-1 assume !(0 == ~T4_E~0); 20104#L704-1 assume !(0 == ~T5_E~0); 20054#L709-1 assume !(0 == ~T6_E~0); 19985#L714-1 assume !(0 == ~E_M~0); 19986#L719-1 assume !(0 == ~E_1~0); 20239#L724-1 assume !(0 == ~E_2~0); 19742#L729-1 assume !(0 == ~E_3~0); 19743#L734-1 assume !(0 == ~E_4~0); 20324#L739-1 assume !(0 == ~E_5~0); 19944#L744-1 assume !(0 == ~E_6~0); 19945#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19698#L334 assume !(1 == ~m_pc~0); 19699#L334-2 is_master_triggered_~__retres1~0#1 := 0; 20043#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19948#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 19914#L849 assume !(0 != activate_threads_~tmp~1#1); 19915#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19844#L353 assume !(1 == ~t1_pc~0); 19845#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 20155#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19713#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 19714#L857 assume !(0 != activate_threads_~tmp___0~0#1); 19796#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19797#L372 assume !(1 == ~t2_pc~0); 19903#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 19902#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20037#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 20156#L865 assume !(0 != activate_threads_~tmp___1~0#1); 19687#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19688#L391 assume !(1 == ~t3_pc~0); 19610#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 19611#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19636#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 19637#L873 assume !(0 != activate_threads_~tmp___2~0#1); 19921#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19922#L410 assume 1 == ~t4_pc~0; 20307#L411 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 20171#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19810#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 19811#L881 assume !(0 != activate_threads_~tmp___3~0#1); 19931#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19932#L429 assume !(1 == ~t5_pc~0); 19748#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 19749#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19959#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19960#L889 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 20175#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19913#L448 assume 1 == ~t6_pc~0; 19784#L449 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 19785#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 20140#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20141#L897 assume !(0 != activate_threads_~tmp___5~0#1); 20352#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20406#L762 assume 1 == ~M_E~0;~M_E~0 := 2; 19966#L762-2 assume !(1 == ~T1_E~0); 19967#L767-1 assume !(1 == ~T2_E~0); 20383#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 22291#L777-1 assume !(1 == ~T4_E~0); 22288#L782-1 assume !(1 == ~T5_E~0); 22286#L787-1 assume !(1 == ~T6_E~0); 22284#L792-1 assume !(1 == ~E_M~0); 19773#L797-1 assume !(1 == ~E_1~0); 22281#L802-1 assume !(1 == ~E_2~0); 22279#L807-1 assume !(1 == ~E_3~0); 22276#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 22274#L817-1 assume !(1 == ~E_5~0); 22272#L822-1 assume !(1 == ~E_6~0); 22263#L827-1 assume { :end_inline_reset_delta_events } true; 22155#L1053-2 [2024-11-08 00:35:00,465 INFO L747 eck$LassoCheckResult]: Loop: 22155#L1053-2 assume !false; 22142#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 22136#L659-1 assume !false; 22134#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 22122#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 22113#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 22109#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 22103#L570 assume !(0 != eval_~tmp~0#1); 22104#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 22732#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 22730#L684-3 assume 0 == ~M_E~0;~M_E~0 := 1; 22728#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22725#L689-3 assume !(0 == ~T2_E~0); 22723#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 22721#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 22719#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 22717#L709-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 22715#L714-3 assume !(0 == ~E_M~0); 22712#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 22710#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 22708#L729-3 assume !(0 == ~E_3~0); 22706#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 22704#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 22702#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 22699#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22697#L334-24 assume !(1 == ~m_pc~0); 22693#L334-26 is_master_triggered_~__retres1~0#1 := 0; 22691#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22682#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 22681#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 22679#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22677#L353-24 assume !(1 == ~t1_pc~0); 22676#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 22675#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22673#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 22642#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 22641#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22640#L372-24 assume !(1 == ~t2_pc~0); 22638#L372-26 is_transmit2_triggered_~__retres1~2#1 := 0; 22637#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22636#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 22635#L865-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 22634#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22633#L391-24 assume !(1 == ~t3_pc~0); 22632#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 22631#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22630#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 22629#L873-24 assume !(0 != activate_threads_~tmp___2~0#1); 22628#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22627#L410-24 assume 1 == ~t4_pc~0; 22625#L411-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 22624#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22623#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 22622#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 22621#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22620#L429-24 assume !(1 == ~t5_pc~0); 22618#L429-26 is_transmit5_triggered_~__retres1~5#1 := 0; 22617#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22616#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 22615#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 22614#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22613#L448-24 assume 1 == ~t6_pc~0; 22611#L449-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 22610#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22609#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 22608#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 22607#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22606#L762-3 assume 1 == ~M_E~0;~M_E~0 := 2; 20330#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 22605#L767-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 22604#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 22603#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 22602#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 20409#L787-3 assume !(1 == ~T6_E~0); 20223#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 19987#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 19988#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 22594#L807-3 assume 1 == ~E_3~0;~E_3~0 := 2; 22591#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 20327#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 20328#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 22585#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 22447#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 22442#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 22438#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 22437#L1072 assume !(0 == start_simulation_~tmp~3#1); 22436#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 22352#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 22344#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 22341#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 22338#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 22335#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 22331#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 22264#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 22155#L1053-2 [2024-11-08 00:35:00,465 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:00,466 INFO L85 PathProgramCache]: Analyzing trace with hash 186459719, now seen corresponding path program 1 times [2024-11-08 00:35:00,466 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:00,466 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [162034900] [2024-11-08 00:35:00,466 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:00,466 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:00,474 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:00,509 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:00,509 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:00,509 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [162034900] [2024-11-08 00:35:00,509 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [162034900] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:00,509 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:00,509 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-08 00:35:00,509 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1086247407] [2024-11-08 00:35:00,509 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:00,509 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:35:00,509 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:00,509 INFO L85 PathProgramCache]: Analyzing trace with hash 1773510908, now seen corresponding path program 1 times [2024-11-08 00:35:00,509 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:00,509 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1478016440] [2024-11-08 00:35:00,509 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:00,509 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:00,518 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:00,540 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:00,540 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:00,540 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1478016440] [2024-11-08 00:35:00,540 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1478016440] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:00,540 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:00,540 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:00,540 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [271652950] [2024-11-08 00:35:00,541 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:00,541 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:35:00,541 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:35:00,541 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:35:00,541 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:35:00,541 INFO L87 Difference]: Start difference. First operand 3927 states and 5728 transitions. cyclomatic complexity: 1809 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 2 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:00,615 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:35:00,615 INFO L93 Difference]: Finished difference Result 7294 states and 10581 transitions. [2024-11-08 00:35:00,615 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7294 states and 10581 transitions. [2024-11-08 00:35:00,681 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 7152 [2024-11-08 00:35:00,705 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7294 states to 7294 states and 10581 transitions. [2024-11-08 00:35:00,705 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7294 [2024-11-08 00:35:00,709 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7294 [2024-11-08 00:35:00,710 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7294 states and 10581 transitions. [2024-11-08 00:35:00,718 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:35:00,718 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7294 states and 10581 transitions. [2024-11-08 00:35:00,722 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7294 states and 10581 transitions. [2024-11-08 00:35:00,789 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7294 to 7278. [2024-11-08 00:35:00,798 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7278 states, 7278 states have (on average 1.4516350645781808) internal successors, (10565), 7277 states have internal predecessors, (10565), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:00,814 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7278 states to 7278 states and 10565 transitions. [2024-11-08 00:35:00,814 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7278 states and 10565 transitions. [2024-11-08 00:35:00,814 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:35:00,815 INFO L425 stractBuchiCegarLoop]: Abstraction has 7278 states and 10565 transitions. [2024-11-08 00:35:00,815 INFO L332 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-11-08 00:35:00,815 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7278 states and 10565 transitions. [2024-11-08 00:35:00,833 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 7136 [2024-11-08 00:35:00,834 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:35:00,834 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:35:00,834 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:00,835 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:00,835 INFO L745 eck$LassoCheckResult]: Stem: 31230#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 31231#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 31365#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 31366#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 31018#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 31019#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 31363#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 31364#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 31288#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 31074#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 31075#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 30995#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 30996#L684 assume !(0 == ~M_E~0); 31482#L684-2 assume !(0 == ~T1_E~0); 31322#L689-1 assume !(0 == ~T2_E~0); 31323#L694-1 assume !(0 == ~T3_E~0); 31320#L699-1 assume !(0 == ~T4_E~0); 31321#L704-1 assume !(0 == ~T5_E~0); 31271#L709-1 assume !(0 == ~T6_E~0); 31211#L714-1 assume !(0 == ~E_M~0); 31212#L719-1 assume !(0 == ~E_1~0); 31450#L724-1 assume !(0 == ~E_2~0); 30969#L729-1 assume !(0 == ~E_3~0); 30970#L734-1 assume !(0 == ~E_4~0); 31513#L739-1 assume !(0 == ~E_5~0); 31171#L744-1 assume !(0 == ~E_6~0); 31172#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30926#L334 assume !(1 == ~m_pc~0); 30927#L334-2 is_master_triggered_~__retres1~0#1 := 0; 31263#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31173#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 31141#L849 assume !(0 != activate_threads_~tmp~1#1); 31142#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 31072#L353 assume !(1 == ~t1_pc~0); 31073#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 31369#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30941#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 30942#L857 assume !(0 != activate_threads_~tmp___0~0#1); 31023#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 31024#L372 assume !(1 == ~t2_pc~0); 31128#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 31127#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 31258#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 31370#L865 assume !(0 != activate_threads_~tmp___1~0#1); 30915#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30916#L391 assume !(1 == ~t3_pc~0); 30838#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 30839#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30864#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 30865#L873 assume !(0 != activate_threads_~tmp___2~0#1); 31148#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 31149#L410 assume !(1 == ~t4_pc~0); 31380#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 31381#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 31038#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 31039#L881 assume !(0 != activate_threads_~tmp___3~0#1); 31154#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 31155#L429 assume !(1 == ~t5_pc~0); 30975#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 30976#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 31184#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 31185#L889 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 31388#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 31138#L448 assume 1 == ~t6_pc~0; 31011#L449 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 31012#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 31353#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 31354#L897 assume !(0 != activate_threads_~tmp___5~0#1); 31539#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 31584#L762 assume 1 == ~M_E~0;~M_E~0 := 2; 31585#L762-2 assume !(1 == ~T1_E~0); 33412#L767-1 assume !(1 == ~T2_E~0); 33410#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 33408#L777-1 assume !(1 == ~T4_E~0); 33406#L782-1 assume !(1 == ~T5_E~0); 33404#L787-1 assume !(1 == ~T6_E~0); 33402#L792-1 assume !(1 == ~E_M~0); 31000#L797-1 assume !(1 == ~E_1~0); 33399#L802-1 assume !(1 == ~E_2~0); 33397#L807-1 assume !(1 == ~E_3~0); 33395#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 33393#L817-1 assume !(1 == ~E_5~0); 33391#L822-1 assume !(1 == ~E_6~0); 31517#L827-1 assume { :end_inline_reset_delta_events } true; 31518#L1053-2 [2024-11-08 00:35:00,835 INFO L747 eck$LassoCheckResult]: Loop: 31518#L1053-2 assume !false; 34268#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 34263#L659-1 assume !false; 34261#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 34128#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 34121#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 34119#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 34116#L570 assume !(0 != eval_~tmp~0#1); 34117#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 35683#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 35680#L684-3 assume 0 == ~M_E~0;~M_E~0 := 1; 35677#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 35674#L689-3 assume !(0 == ~T2_E~0); 35671#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 35667#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 35665#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 35662#L709-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 35613#L714-3 assume !(0 == ~E_M~0); 35610#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 35608#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 35351#L729-3 assume !(0 == ~E_3~0); 35350#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 35349#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 35348#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 35347#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 35346#L334-24 assume 1 == ~m_pc~0; 35344#L335-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 35341#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 35339#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 35337#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 35335#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 35333#L353-24 assume !(1 == ~t1_pc~0); 35331#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 35329#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 35327#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 35324#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 35322#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 35320#L372-24 assume !(1 == ~t2_pc~0); 35317#L372-26 is_transmit2_triggered_~__retres1~2#1 := 0; 35315#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35313#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 35312#L865-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 35309#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 35307#L391-24 assume !(1 == ~t3_pc~0); 35305#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 35303#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 35301#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 35299#L873-24 assume !(0 != activate_threads_~tmp___2~0#1); 35297#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 35295#L410-24 assume !(1 == ~t4_pc~0); 35293#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 35291#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 35289#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 35287#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 35284#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 35282#L429-24 assume 1 == ~t5_pc~0; 35280#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 35277#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 35275#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 35273#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 35272#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 35271#L448-24 assume 1 == ~t6_pc~0; 35269#L449-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 35087#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 35084#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 35082#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 35080#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 35078#L762-3 assume 1 == ~M_E~0;~M_E~0 := 2; 33651#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 35075#L767-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 35072#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 34976#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 34966#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 34961#L787-3 assume !(1 == ~T6_E~0); 34955#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 33615#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 34938#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 34933#L807-3 assume 1 == ~E_3~0;~E_3~0 := 2; 34926#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 34919#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 34914#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 34910#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 34812#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 34805#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 34800#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 34795#L1072 assume !(0 == start_simulation_~tmp~3#1); 34787#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 34288#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 34281#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 34279#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 34277#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 34275#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 34273#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 34271#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 31518#L1053-2 [2024-11-08 00:35:00,835 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:00,835 INFO L85 PathProgramCache]: Analyzing trace with hash -1390098040, now seen corresponding path program 1 times [2024-11-08 00:35:00,836 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:00,836 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1755271782] [2024-11-08 00:35:00,836 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:00,836 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:00,843 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:00,925 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:00,925 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:00,925 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1755271782] [2024-11-08 00:35:00,925 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1755271782] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:00,925 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:00,926 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-08 00:35:00,926 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1566130975] [2024-11-08 00:35:00,926 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:00,926 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:35:00,927 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:00,928 INFO L85 PathProgramCache]: Analyzing trace with hash 719332731, now seen corresponding path program 1 times [2024-11-08 00:35:00,928 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:00,928 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1947444154] [2024-11-08 00:35:00,928 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:00,928 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:00,937 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:00,963 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:00,963 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:00,963 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1947444154] [2024-11-08 00:35:00,963 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1947444154] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:00,963 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:00,964 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:00,964 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [786308785] [2024-11-08 00:35:00,964 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:00,964 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:35:00,964 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:35:00,965 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-08 00:35:00,965 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-08 00:35:00,965 INFO L87 Difference]: Start difference. First operand 7278 states and 10565 transitions. cyclomatic complexity: 3303 Second operand has 5 states, 5 states have (on average 16.8) internal successors, (84), 5 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:01,164 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:35:01,164 INFO L93 Difference]: Finished difference Result 7593 states and 10880 transitions. [2024-11-08 00:35:01,164 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7593 states and 10880 transitions. [2024-11-08 00:35:01,198 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 7448 [2024-11-08 00:35:01,232 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7593 states to 7593 states and 10880 transitions. [2024-11-08 00:35:01,232 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7593 [2024-11-08 00:35:01,239 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7593 [2024-11-08 00:35:01,240 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7593 states and 10880 transitions. [2024-11-08 00:35:01,251 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:35:01,251 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7593 states and 10880 transitions. [2024-11-08 00:35:01,257 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7593 states and 10880 transitions. [2024-11-08 00:35:01,350 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7593 to 7593. [2024-11-08 00:35:01,365 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7593 states, 7593 states have (on average 1.4328987225075727) internal successors, (10880), 7592 states have internal predecessors, (10880), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:01,387 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7593 states to 7593 states and 10880 transitions. [2024-11-08 00:35:01,387 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7593 states and 10880 transitions. [2024-11-08 00:35:01,387 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-08 00:35:01,389 INFO L425 stractBuchiCegarLoop]: Abstraction has 7593 states and 10880 transitions. [2024-11-08 00:35:01,389 INFO L332 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-11-08 00:35:01,389 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7593 states and 10880 transitions. [2024-11-08 00:35:01,415 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 7448 [2024-11-08 00:35:01,416 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:35:01,416 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:35:01,417 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:01,417 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:01,417 INFO L745 eck$LassoCheckResult]: Stem: 46115#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 46116#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 46250#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 46251#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 45899#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 45900#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 46248#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 46249#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 46176#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 45957#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 45958#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 45877#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 45878#L684 assume !(0 == ~M_E~0); 46372#L684-2 assume !(0 == ~T1_E~0); 46207#L689-1 assume !(0 == ~T2_E~0); 46208#L694-1 assume !(0 == ~T3_E~0); 46205#L699-1 assume !(0 == ~T4_E~0); 46206#L704-1 assume !(0 == ~T5_E~0); 46159#L709-1 assume !(0 == ~T6_E~0); 46096#L714-1 assume !(0 == ~E_M~0); 46097#L719-1 assume !(0 == ~E_1~0); 46342#L724-1 assume !(0 == ~E_2~0); 45851#L729-1 assume !(0 == ~E_3~0); 45852#L734-1 assume !(0 == ~E_4~0); 46409#L739-1 assume !(0 == ~E_5~0); 46055#L744-1 assume !(0 == ~E_6~0); 46056#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 45807#L334 assume !(1 == ~m_pc~0); 45808#L334-2 is_master_triggered_~__retres1~0#1 := 0; 46151#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 46057#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 46026#L849 assume !(0 != activate_threads_~tmp~1#1); 46027#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 45955#L353 assume !(1 == ~t1_pc~0); 45956#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 46254#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 45822#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 45823#L857 assume !(0 != activate_threads_~tmp___0~0#1); 45904#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 45905#L372 assume !(1 == ~t2_pc~0); 46013#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 46012#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 46146#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 46255#L865 assume !(0 != activate_threads_~tmp___1~0#1); 45796#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 45797#L391 assume !(1 == ~t3_pc~0); 45718#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 45719#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 45745#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 45746#L873 assume !(0 != activate_threads_~tmp___2~0#1); 46033#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 46034#L410 assume !(1 == ~t4_pc~0); 46269#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 46270#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 45918#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 45919#L881 assume !(0 != activate_threads_~tmp___3~0#1); 46040#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 46041#L429 assume !(1 == ~t5_pc~0); 45857#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 45858#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 46068#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 46069#L889 assume !(0 != activate_threads_~tmp___4~0#1); 46275#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 46023#L448 assume 1 == ~t6_pc~0; 45892#L449 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 45893#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 46238#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 46239#L897 assume !(0 != activate_threads_~tmp___5~0#1); 46437#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 46483#L762 assume 1 == ~M_E~0;~M_E~0 := 2; 46075#L762-2 assume !(1 == ~T1_E~0); 46076#L767-1 assume !(1 == ~T2_E~0); 46442#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 46443#L777-1 assume !(1 == ~T4_E~0); 49051#L782-1 assume !(1 == ~T5_E~0); 45883#L787-1 assume !(1 == ~T6_E~0); 45881#L792-1 assume !(1 == ~E_M~0); 45882#L797-1 assume !(1 == ~E_1~0); 46356#L802-1 assume !(1 == ~E_2~0); 46357#L807-1 assume !(1 == ~E_3~0); 46402#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 46403#L817-1 assume !(1 == ~E_5~0); 46209#L822-1 assume !(1 == ~E_6~0); 46210#L827-1 assume { :end_inline_reset_delta_events } true; 48969#L1053-2 [2024-11-08 00:35:01,418 INFO L747 eck$LassoCheckResult]: Loop: 48969#L1053-2 assume !false; 48962#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 48955#L659-1 assume !false; 48952#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 48894#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 48887#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 48885#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 48882#L570 assume !(0 != eval_~tmp~0#1); 48883#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 51207#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 51205#L684-3 assume 0 == ~M_E~0;~M_E~0 := 1; 51197#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 51195#L689-3 assume !(0 == ~T2_E~0); 51193#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 51190#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 51186#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 51182#L709-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 51178#L714-3 assume !(0 == ~E_M~0); 51177#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 51176#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 51175#L729-3 assume !(0 == ~E_3~0); 51174#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 51173#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 51171#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 51170#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 51169#L334-24 assume 1 == ~m_pc~0; 51168#L335-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 51166#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 51164#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 51162#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 51160#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 51147#L353-24 assume !(1 == ~t1_pc~0); 49318#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 49315#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 49311#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 49307#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 49301#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 49296#L372-24 assume !(1 == ~t2_pc~0); 49291#L372-26 is_transmit2_triggered_~__retres1~2#1 := 0; 49287#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 49281#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 49277#L865-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 49272#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49268#L391-24 assume !(1 == ~t3_pc~0); 49264#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 49258#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 47361#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 47362#L873-24 assume !(0 != activate_threads_~tmp___2~0#1); 47357#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 47358#L410-24 assume !(1 == ~t4_pc~0); 47353#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 47354#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 47349#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 47350#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 47345#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 47346#L429-24 assume 1 == ~t5_pc~0; 49200#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 49201#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 49202#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 49195#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 49194#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 49193#L448-24 assume 1 == ~t6_pc~0; 49191#L449-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 49190#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 49189#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 47320#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 47317#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 47314#L762-3 assume 1 == ~M_E~0;~M_E~0 := 2; 47315#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 49178#L767-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 49176#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 49174#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 47302#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 47299#L787-3 assume !(1 == ~T6_E~0); 47300#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 47297#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 49163#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 49161#L807-3 assume 1 == ~E_3~0;~E_3~0 := 2; 49159#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 49157#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 49155#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 49153#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 47264#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 47262#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 47255#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 47256#L1072 assume !(0 == start_simulation_~tmp~3#1); 49072#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 49025#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 49013#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 49006#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 49000#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 48994#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 48989#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 48975#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 48969#L1053-2 [2024-11-08 00:35:01,418 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:01,418 INFO L85 PathProgramCache]: Analyzing trace with hash 1099430922, now seen corresponding path program 1 times [2024-11-08 00:35:01,418 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:01,418 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [881315221] [2024-11-08 00:35:01,418 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:01,418 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:01,428 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:01,456 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:01,456 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:01,456 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [881315221] [2024-11-08 00:35:01,456 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [881315221] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:01,456 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:01,456 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-08 00:35:01,457 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1775650099] [2024-11-08 00:35:01,457 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:01,457 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:35:01,458 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:01,458 INFO L85 PathProgramCache]: Analyzing trace with hash 719332731, now seen corresponding path program 2 times [2024-11-08 00:35:01,458 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:01,458 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1156942794] [2024-11-08 00:35:01,458 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:01,458 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:01,468 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:01,496 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:01,496 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:01,496 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1156942794] [2024-11-08 00:35:01,496 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1156942794] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:01,496 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:01,496 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:01,496 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [326306670] [2024-11-08 00:35:01,496 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:01,497 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:35:01,497 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:35:01,497 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:35:01,497 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:35:01,498 INFO L87 Difference]: Start difference. First operand 7593 states and 10880 transitions. cyclomatic complexity: 3303 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 2 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:01,642 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:35:01,642 INFO L93 Difference]: Finished difference Result 14548 states and 20713 transitions. [2024-11-08 00:35:01,643 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 14548 states and 20713 transitions. [2024-11-08 00:35:01,712 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 14332 [2024-11-08 00:35:01,763 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 14548 states to 14548 states and 20713 transitions. [2024-11-08 00:35:01,763 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14548 [2024-11-08 00:35:01,776 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14548 [2024-11-08 00:35:01,776 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14548 states and 20713 transitions. [2024-11-08 00:35:01,793 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:35:01,793 INFO L218 hiAutomatonCegarLoop]: Abstraction has 14548 states and 20713 transitions. [2024-11-08 00:35:01,805 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14548 states and 20713 transitions. [2024-11-08 00:35:01,929 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14548 to 14516. [2024-11-08 00:35:01,953 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14516 states, 14516 states have (on average 1.424703775144668) internal successors, (20681), 14515 states have internal predecessors, (20681), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:01,988 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14516 states to 14516 states and 20681 transitions. [2024-11-08 00:35:01,988 INFO L240 hiAutomatonCegarLoop]: Abstraction has 14516 states and 20681 transitions. [2024-11-08 00:35:01,989 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:35:01,990 INFO L425 stractBuchiCegarLoop]: Abstraction has 14516 states and 20681 transitions. [2024-11-08 00:35:01,990 INFO L332 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-11-08 00:35:01,990 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14516 states and 20681 transitions. [2024-11-08 00:35:02,091 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 14300 [2024-11-08 00:35:02,092 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:35:02,092 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:35:02,093 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:02,093 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:02,094 INFO L745 eck$LassoCheckResult]: Stem: 68264#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 68265#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 68410#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 68411#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 68043#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 68044#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 68408#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 68409#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 68329#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 68106#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 68107#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 68023#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 68024#L684 assume !(0 == ~M_E~0); 68539#L684-2 assume !(0 == ~T1_E~0); 68364#L689-1 assume !(0 == ~T2_E~0); 68365#L694-1 assume !(0 == ~T3_E~0); 68362#L699-1 assume !(0 == ~T4_E~0); 68363#L704-1 assume !(0 == ~T5_E~0); 68311#L709-1 assume !(0 == ~T6_E~0); 68244#L714-1 assume !(0 == ~E_M~0); 68245#L719-1 assume !(0 == ~E_1~0); 68504#L724-1 assume !(0 == ~E_2~0); 67996#L729-1 assume !(0 == ~E_3~0); 67997#L734-1 assume !(0 == ~E_4~0); 68573#L739-1 assume !(0 == ~E_5~0); 68202#L744-1 assume !(0 == ~E_6~0); 68203#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 67952#L334 assume !(1 == ~m_pc~0); 67953#L334-2 is_master_triggered_~__retres1~0#1 := 0; 68303#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 68205#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 68173#L849 assume !(0 != activate_threads_~tmp~1#1); 68174#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 68104#L353 assume !(1 == ~t1_pc~0); 68105#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 68416#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 67968#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 67969#L857 assume !(0 != activate_threads_~tmp___0~0#1); 68049#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 68050#L372 assume !(1 == ~t2_pc~0); 68160#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 68159#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 68297#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 68417#L865 assume !(0 != activate_threads_~tmp___1~0#1); 67941#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 67942#L391 assume !(1 == ~t3_pc~0); 67866#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 67867#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 67891#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 67892#L873 assume !(0 != activate_threads_~tmp___2~0#1); 68180#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 68181#L410 assume !(1 == ~t4_pc~0); 68431#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 68432#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 68063#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 68064#L881 assume !(0 != activate_threads_~tmp___3~0#1); 68186#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 68187#L429 assume !(1 == ~t5_pc~0); 68002#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 68003#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 68216#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 68217#L889 assume !(0 != activate_threads_~tmp___4~0#1); 68438#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 68170#L448 assume !(1 == ~t6_pc~0); 68087#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 68088#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 68399#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 68400#L897 assume !(0 != activate_threads_~tmp___5~0#1); 68601#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 68648#L762 assume 1 == ~M_E~0;~M_E~0 := 2; 68649#L762-2 assume !(1 == ~T1_E~0); 75092#L767-1 assume !(1 == ~T2_E~0); 75091#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 75090#L777-1 assume !(1 == ~T4_E~0); 75089#L782-1 assume !(1 == ~T5_E~0); 75088#L787-1 assume !(1 == ~T6_E~0); 75087#L792-1 assume !(1 == ~E_M~0); 68028#L797-1 assume !(1 == ~E_1~0); 75086#L802-1 assume !(1 == ~E_2~0); 75083#L807-1 assume !(1 == ~E_3~0); 68567#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 68568#L817-1 assume !(1 == ~E_5~0); 68368#L822-1 assume !(1 == ~E_6~0); 68369#L827-1 assume { :end_inline_reset_delta_events } true; 68580#L1053-2 [2024-11-08 00:35:02,094 INFO L747 eck$LassoCheckResult]: Loop: 68580#L1053-2 assume !false; 80144#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 80133#L659-1 assume !false; 80131#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 80126#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 80119#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 80117#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 80114#L570 assume !(0 != eval_~tmp~0#1); 80115#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 81063#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 81059#L684-3 assume 0 == ~M_E~0;~M_E~0 := 1; 81057#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 81055#L689-3 assume !(0 == ~T2_E~0); 81053#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 81050#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 81048#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 81047#L709-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 81046#L714-3 assume !(0 == ~E_M~0); 81045#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 81043#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 81041#L729-3 assume !(0 == ~E_3~0); 81039#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 81037#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 81035#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 81033#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 81031#L334-24 assume 1 == ~m_pc~0; 81029#L335-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 81026#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 81024#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 81022#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 81020#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 81018#L353-24 assume !(1 == ~t1_pc~0); 81016#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 81014#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 81012#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 81010#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 81009#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 81008#L372-24 assume 1 == ~t2_pc~0; 81007#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 81004#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 81002#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 81000#L865-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 80998#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 80996#L391-24 assume !(1 == ~t3_pc~0); 80994#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 80992#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 80990#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 80988#L873-24 assume !(0 != activate_threads_~tmp___2~0#1); 80952#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 80943#L410-24 assume !(1 == ~t4_pc~0); 80937#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 80932#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 80909#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 80902#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 80895#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 80886#L429-24 assume 1 == ~t5_pc~0; 80877#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 80870#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 80862#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 80856#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 80852#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 80848#L448-24 assume !(1 == ~t6_pc~0); 80841#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 80809#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 80803#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 80798#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 80792#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 80785#L762-3 assume 1 == ~M_E~0;~M_E~0 := 2; 80776#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 80769#L767-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 80763#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 80757#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 80751#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 80745#L787-3 assume !(1 == ~T6_E~0); 80738#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 79527#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 80724#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 80718#L807-3 assume 1 == ~E_3~0;~E_3~0 := 2; 80712#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 80703#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 80655#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 80652#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 80588#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 80579#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 80572#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 80565#L1072 assume !(0 == start_simulation_~tmp~3#1); 80560#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 80551#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 80520#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 80502#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 80497#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 80488#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 80483#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 80478#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 68580#L1053-2 [2024-11-08 00:35:02,094 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:02,095 INFO L85 PathProgramCache]: Analyzing trace with hash 125941963, now seen corresponding path program 1 times [2024-11-08 00:35:02,095 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:02,095 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1088085467] [2024-11-08 00:35:02,095 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:02,095 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:02,105 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:02,137 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:02,137 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:02,137 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1088085467] [2024-11-08 00:35:02,137 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1088085467] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:02,137 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:02,138 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-08 00:35:02,138 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [731804525] [2024-11-08 00:35:02,138 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:02,138 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:35:02,139 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:02,139 INFO L85 PathProgramCache]: Analyzing trace with hash -1097492357, now seen corresponding path program 1 times [2024-11-08 00:35:02,139 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:02,139 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1523730824] [2024-11-08 00:35:02,139 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:02,139 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:02,147 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:02,169 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:02,169 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:02,169 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1523730824] [2024-11-08 00:35:02,169 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1523730824] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:02,169 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:02,169 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:02,170 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1785563010] [2024-11-08 00:35:02,170 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:02,171 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:35:02,171 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:35:02,172 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:35:02,172 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:35:02,172 INFO L87 Difference]: Start difference. First operand 14516 states and 20681 transitions. cyclomatic complexity: 6197 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 2 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:02,258 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:35:02,258 INFO L93 Difference]: Finished difference Result 21621 states and 30826 transitions. [2024-11-08 00:35:02,259 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 21621 states and 30826 transitions. [2024-11-08 00:35:02,336 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 21356 [2024-11-08 00:35:02,403 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 21621 states to 21621 states and 30826 transitions. [2024-11-08 00:35:02,403 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21621 [2024-11-08 00:35:02,427 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21621 [2024-11-08 00:35:02,427 INFO L73 IsDeterministic]: Start isDeterministic. Operand 21621 states and 30826 transitions. [2024-11-08 00:35:02,455 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:35:02,455 INFO L218 hiAutomatonCegarLoop]: Abstraction has 21621 states and 30826 transitions. [2024-11-08 00:35:02,477 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21621 states and 30826 transitions. [2024-11-08 00:35:02,744 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21621 to 15146. [2024-11-08 00:35:02,770 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 15146 states, 15146 states have (on average 1.4282979004357585) internal successors, (21633), 15145 states have internal predecessors, (21633), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:02,802 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15146 states to 15146 states and 21633 transitions. [2024-11-08 00:35:02,802 INFO L240 hiAutomatonCegarLoop]: Abstraction has 15146 states and 21633 transitions. [2024-11-08 00:35:02,803 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:35:02,803 INFO L425 stractBuchiCegarLoop]: Abstraction has 15146 states and 21633 transitions. [2024-11-08 00:35:02,804 INFO L332 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2024-11-08 00:35:02,804 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 15146 states and 21633 transitions. [2024-11-08 00:35:02,839 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 14944 [2024-11-08 00:35:02,839 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:35:02,839 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:35:02,840 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:02,840 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:02,840 INFO L745 eck$LassoCheckResult]: Stem: 104411#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 104412#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 104551#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 104552#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 104190#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 104191#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 104547#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 104548#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 104474#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 104249#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 104250#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 104170#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 104171#L684 assume !(0 == ~M_E~0); 104673#L684-2 assume !(0 == ~T1_E~0); 104505#L689-1 assume !(0 == ~T2_E~0); 104506#L694-1 assume !(0 == ~T3_E~0); 104503#L699-1 assume !(0 == ~T4_E~0); 104504#L704-1 assume !(0 == ~T5_E~0); 104458#L709-1 assume !(0 == ~T6_E~0); 104386#L714-1 assume !(0 == ~E_M~0); 104387#L719-1 assume !(0 == ~E_1~0); 104641#L724-1 assume !(0 == ~E_2~0); 104142#L729-1 assume !(0 == ~E_3~0); 104143#L734-1 assume !(0 == ~E_4~0); 104705#L739-1 assume !(0 == ~E_5~0); 104343#L744-1 assume !(0 == ~E_6~0); 104344#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 104098#L334 assume !(1 == ~m_pc~0); 104099#L334-2 is_master_triggered_~__retres1~0#1 := 0; 104447#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 104348#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 104314#L849 assume !(0 != activate_threads_~tmp~1#1); 104315#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 104245#L353 assume !(1 == ~t1_pc~0); 104246#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 104553#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 104113#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 104114#L857 assume !(0 != activate_threads_~tmp___0~0#1); 104192#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 104193#L372 assume !(1 == ~t2_pc~0); 104303#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 104302#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 104442#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 104554#L865 assume !(0 != activate_threads_~tmp___1~0#1); 104087#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 104088#L391 assume !(1 == ~t3_pc~0); 104010#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 104011#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 104036#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 104037#L873 assume !(0 != activate_threads_~tmp___2~0#1); 104321#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 104322#L410 assume !(1 == ~t4_pc~0); 104567#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 104568#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 104207#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 104208#L881 assume !(0 != activate_threads_~tmp___3~0#1); 104330#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 104331#L429 assume !(1 == ~t5_pc~0); 104148#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 104149#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 104359#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 104360#L889 assume !(0 != activate_threads_~tmp___4~0#1); 104574#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 104313#L448 assume !(1 == ~t6_pc~0); 104228#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 104229#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 104538#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 104539#L897 assume !(0 != activate_threads_~tmp___5~0#1); 104733#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 104784#L762 assume !(1 == ~M_E~0); 104366#L762-2 assume !(1 == ~T1_E~0); 104367#L767-1 assume !(1 == ~T2_E~0); 104738#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 104607#L777-1 assume !(1 == ~T4_E~0); 104489#L782-1 assume !(1 == ~T5_E~0); 104174#L787-1 assume !(1 == ~T6_E~0); 104172#L792-1 assume !(1 == ~E_M~0); 104173#L797-1 assume !(1 == ~E_1~0); 104215#L802-1 assume !(1 == ~E_2~0); 104451#L807-1 assume !(1 == ~E_3~0); 104452#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 104702#L817-1 assume !(1 == ~E_5~0); 104507#L822-1 assume !(1 == ~E_6~0); 104508#L827-1 assume { :end_inline_reset_delta_events } true; 104712#L1053-2 [2024-11-08 00:35:02,841 INFO L747 eck$LassoCheckResult]: Loop: 104712#L1053-2 assume !false; 110334#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 110316#L659-1 assume !false; 110309#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 110229#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 110220#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 110218#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 110215#L570 assume !(0 != eval_~tmp~0#1); 110213#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 110210#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 110208#L684-3 assume !(0 == ~M_E~0); 110206#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 110204#L689-3 assume !(0 == ~T2_E~0); 110202#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 110200#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 110198#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 110196#L709-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 110195#L714-3 assume !(0 == ~E_M~0); 110187#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 110185#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 110183#L729-3 assume !(0 == ~E_3~0); 110180#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 110178#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 110176#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 110174#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 110172#L334-24 assume !(1 == ~m_pc~0); 110169#L334-26 is_master_triggered_~__retres1~0#1 := 0; 110167#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 110152#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 110143#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 110134#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 110126#L353-24 assume !(1 == ~t1_pc~0); 110119#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 110113#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 110110#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 110107#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 110098#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 110095#L372-24 assume !(1 == ~t2_pc~0); 110091#L372-26 is_transmit2_triggered_~__retres1~2#1 := 0; 110087#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 110083#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 110080#L865-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 110077#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 110074#L391-24 assume !(1 == ~t3_pc~0); 110071#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 110068#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 110065#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 110062#L873-24 assume !(0 != activate_threads_~tmp___2~0#1); 110059#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 110056#L410-24 assume !(1 == ~t4_pc~0); 110053#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 110050#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 110046#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 110043#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 110040#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 110037#L429-24 assume 1 == ~t5_pc~0; 110033#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 110029#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 110024#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 110020#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 110017#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 110014#L448-24 assume !(1 == ~t6_pc~0); 110011#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 110008#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 110005#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 110002#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 109999#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 109995#L762-3 assume !(1 == ~M_E~0); 109481#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 109987#L767-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 109981#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 109975#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 109970#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 109965#L787-3 assume !(1 == ~T6_E~0); 109961#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 109957#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 109952#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 109947#L807-3 assume 1 == ~E_3~0;~E_3~0 := 2; 109943#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 109938#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 109933#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 109930#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 109863#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 109856#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 109852#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 109824#L1072 assume !(0 == start_simulation_~tmp~3#1); 109825#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 110421#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 110414#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 110412#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 110410#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 110408#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 110406#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 110403#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 104712#L1053-2 [2024-11-08 00:35:02,841 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:02,841 INFO L85 PathProgramCache]: Analyzing trace with hash -1153921715, now seen corresponding path program 1 times [2024-11-08 00:35:02,841 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:02,841 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1963770153] [2024-11-08 00:35:02,841 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:02,841 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:02,848 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:02,882 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:02,882 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:02,883 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1963770153] [2024-11-08 00:35:02,883 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1963770153] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:02,883 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:02,883 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:02,883 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [769075437] [2024-11-08 00:35:02,883 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:02,883 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:35:02,883 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:02,883 INFO L85 PathProgramCache]: Analyzing trace with hash 324500925, now seen corresponding path program 1 times [2024-11-08 00:35:02,884 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:02,884 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1380301158] [2024-11-08 00:35:02,884 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:02,884 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:02,892 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:03,013 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:03,013 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:03,013 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1380301158] [2024-11-08 00:35:03,013 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1380301158] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:03,013 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:03,013 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:03,014 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1948832427] [2024-11-08 00:35:03,014 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:03,015 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:35:03,015 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:35:03,015 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-08 00:35:03,015 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-08 00:35:03,016 INFO L87 Difference]: Start difference. First operand 15146 states and 21633 transitions. cyclomatic complexity: 6503 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:03,135 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:35:03,135 INFO L93 Difference]: Finished difference Result 24188 states and 34429 transitions. [2024-11-08 00:35:03,135 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 24188 states and 34429 transitions. [2024-11-08 00:35:03,231 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 23856 [2024-11-08 00:35:03,311 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 24188 states to 24188 states and 34429 transitions. [2024-11-08 00:35:03,311 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 24188 [2024-11-08 00:35:03,333 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 24188 [2024-11-08 00:35:03,334 INFO L73 IsDeterministic]: Start isDeterministic. Operand 24188 states and 34429 transitions. [2024-11-08 00:35:03,365 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:35:03,365 INFO L218 hiAutomatonCegarLoop]: Abstraction has 24188 states and 34429 transitions. [2024-11-08 00:35:03,385 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24188 states and 34429 transitions. [2024-11-08 00:35:03,561 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24188 to 17289. [2024-11-08 00:35:03,584 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17289 states, 17289 states have (on average 1.427497252588351) internal successors, (24680), 17288 states have internal predecessors, (24680), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:03,625 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17289 states to 17289 states and 24680 transitions. [2024-11-08 00:35:03,625 INFO L240 hiAutomatonCegarLoop]: Abstraction has 17289 states and 24680 transitions. [2024-11-08 00:35:03,625 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-08 00:35:03,627 INFO L425 stractBuchiCegarLoop]: Abstraction has 17289 states and 24680 transitions. [2024-11-08 00:35:03,627 INFO L332 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2024-11-08 00:35:03,627 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 17289 states and 24680 transitions. [2024-11-08 00:35:03,679 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 17024 [2024-11-08 00:35:03,679 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:35:03,679 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:35:03,681 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:03,681 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:03,682 INFO L745 eck$LassoCheckResult]: Stem: 143760#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 143761#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 143898#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 143899#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 143537#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 143538#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 143894#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 143895#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 143820#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 143596#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 143597#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 143517#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 143518#L684 assume !(0 == ~M_E~0); 144031#L684-2 assume !(0 == ~T1_E~0); 143851#L689-1 assume !(0 == ~T2_E~0); 143852#L694-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 143849#L699-1 assume !(0 == ~T4_E~0); 143850#L704-1 assume !(0 == ~T5_E~0); 143806#L709-1 assume !(0 == ~T6_E~0); 143807#L714-1 assume !(0 == ~E_M~0); 144197#L719-1 assume !(0 == ~E_1~0); 144126#L724-1 assume !(0 == ~E_2~0); 144127#L729-1 assume !(0 == ~E_3~0); 144118#L734-1 assume !(0 == ~E_4~0); 144064#L739-1 assume !(0 == ~E_5~0); 144065#L744-1 assume !(0 == ~E_6~0); 144195#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 143441#L334 assume !(1 == ~m_pc~0); 143442#L334-2 is_master_triggered_~__retres1~0#1 := 0; 143795#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 144076#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 143662#L849 assume !(0 != activate_threads_~tmp~1#1); 143663#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 144191#L353 assume !(1 == ~t1_pc~0); 144190#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 143901#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 143456#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 143457#L857 assume !(0 != activate_threads_~tmp___0~0#1); 143539#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 143540#L372 assume !(1 == ~t2_pc~0); 143649#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 143648#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 143789#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 144187#L865 assume !(0 != activate_threads_~tmp___1~0#1); 143430#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 143431#L391 assume !(1 == ~t3_pc~0); 144041#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 144185#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 144184#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 144183#L873 assume !(0 != activate_threads_~tmp___2~0#1); 143669#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 143670#L410 assume !(1 == ~t4_pc~0); 144051#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 143964#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 143553#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 143554#L881 assume !(0 != activate_threads_~tmp___3~0#1); 144055#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 143844#L429 assume !(1 == ~t5_pc~0); 143492#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 143493#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 143708#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 143709#L889 assume !(0 != activate_threads_~tmp___4~0#1); 143923#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 143661#L448 assume !(1 == ~t6_pc~0); 143575#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 143576#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 143886#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 143887#L897 assume !(0 != activate_threads_~tmp___5~0#1); 144155#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 144156#L762 assume !(1 == ~M_E~0); 144171#L762-2 assume !(1 == ~T1_E~0); 144129#L767-1 assume !(1 == ~T2_E~0); 144130#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 143956#L777-1 assume !(1 == ~T4_E~0); 143836#L782-1 assume !(1 == ~T5_E~0); 143521#L787-1 assume !(1 == ~T6_E~0); 143519#L792-1 assume !(1 == ~E_M~0); 143520#L797-1 assume !(1 == ~E_1~0); 143559#L802-1 assume !(1 == ~E_2~0); 143799#L807-1 assume !(1 == ~E_3~0); 143800#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 144061#L817-1 assume !(1 == ~E_5~0); 143855#L822-1 assume !(1 == ~E_6~0); 143856#L827-1 assume { :end_inline_reset_delta_events } true; 144075#L1053-2 [2024-11-08 00:35:03,682 INFO L747 eck$LassoCheckResult]: Loop: 144075#L1053-2 assume !false; 156064#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 156059#L659-1 assume !false; 156057#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 156052#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 156044#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 156042#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 156039#L570 assume !(0 != eval_~tmp~0#1); 156040#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 144069#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 143826#L684-3 assume !(0 == ~M_E~0); 143827#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 143350#L689-3 assume !(0 == ~T2_E~0); 143351#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 160308#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 160307#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 160306#L709-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 160305#L714-3 assume !(0 == ~E_M~0); 160304#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 160303#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 160302#L729-3 assume !(0 == ~E_3~0); 160301#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 160300#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 160299#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 160298#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 160297#L334-24 assume !(1 == ~m_pc~0); 160295#L334-26 is_master_triggered_~__retres1~0#1 := 0; 160294#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 160293#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 160292#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 160291#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 160290#L353-24 assume !(1 == ~t1_pc~0); 160289#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 160288#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 160287#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 160286#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 160285#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 160284#L372-24 assume !(1 == ~t2_pc~0); 160282#L372-26 is_transmit2_triggered_~__retres1~2#1 := 0; 160281#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 160280#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 160279#L865-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 160278#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 160277#L391-24 assume !(1 == ~t3_pc~0); 160276#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 160275#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 160274#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 160273#L873-24 assume !(0 != activate_threads_~tmp___2~0#1); 160272#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 160271#L410-24 assume !(1 == ~t4_pc~0); 160270#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 160269#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 160268#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 160267#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 160266#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 160265#L429-24 assume 1 == ~t5_pc~0; 160263#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 160261#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 160259#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 160257#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 160256#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 160255#L448-24 assume !(1 == ~t6_pc~0); 160254#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 160253#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 160252#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 160251#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 160250#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 160249#L762-3 assume !(1 == ~M_E~0); 148570#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 160248#L767-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 160246#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 144097#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 143494#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 143495#L787-3 assume !(1 == ~T6_E~0); 160090#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 143739#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 143740#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 144032#L807-3 assume 1 == ~E_3~0;~E_3~0 := 2; 143884#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 143885#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 143992#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 143971#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 143764#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 143391#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 144361#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 144349#L1072 assume !(0 == start_simulation_~tmp~3#1); 144350#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 156084#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 156078#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 156075#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 156071#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 156070#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 156069#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 156068#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 144075#L1053-2 [2024-11-08 00:35:03,683 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:03,683 INFO L85 PathProgramCache]: Analyzing trace with hash -661295541, now seen corresponding path program 1 times [2024-11-08 00:35:03,683 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:03,683 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [232099673] [2024-11-08 00:35:03,683 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:03,683 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:03,692 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:03,738 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:03,738 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:03,738 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [232099673] [2024-11-08 00:35:03,738 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [232099673] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:03,738 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:03,738 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:03,738 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [812241455] [2024-11-08 00:35:03,738 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:03,739 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:35:03,739 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:03,739 INFO L85 PathProgramCache]: Analyzing trace with hash 324500925, now seen corresponding path program 2 times [2024-11-08 00:35:03,739 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:03,739 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1235562255] [2024-11-08 00:35:03,739 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:03,739 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:03,750 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:03,774 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:03,774 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:03,774 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1235562255] [2024-11-08 00:35:03,774 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1235562255] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:03,774 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:03,774 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:03,774 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1508021675] [2024-11-08 00:35:03,774 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:03,775 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:35:03,775 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:35:03,775 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-08 00:35:03,775 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-08 00:35:03,775 INFO L87 Difference]: Start difference. First operand 17289 states and 24680 transitions. cyclomatic complexity: 7407 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:03,874 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:35:03,874 INFO L93 Difference]: Finished difference Result 22034 states and 31247 transitions. [2024-11-08 00:35:03,874 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 22034 states and 31247 transitions. [2024-11-08 00:35:03,968 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 21776 [2024-11-08 00:35:04,041 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 22034 states to 22034 states and 31247 transitions. [2024-11-08 00:35:04,041 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22034 [2024-11-08 00:35:04,061 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22034 [2024-11-08 00:35:04,061 INFO L73 IsDeterministic]: Start isDeterministic. Operand 22034 states and 31247 transitions. [2024-11-08 00:35:04,219 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:35:04,220 INFO L218 hiAutomatonCegarLoop]: Abstraction has 22034 states and 31247 transitions. [2024-11-08 00:35:04,234 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22034 states and 31247 transitions. [2024-11-08 00:35:04,393 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22034 to 15146. [2024-11-08 00:35:04,408 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 15146 states, 15146 states have (on average 1.4218275452264624) internal successors, (21535), 15145 states have internal predecessors, (21535), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:04,435 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15146 states to 15146 states and 21535 transitions. [2024-11-08 00:35:04,435 INFO L240 hiAutomatonCegarLoop]: Abstraction has 15146 states and 21535 transitions. [2024-11-08 00:35:04,436 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-08 00:35:04,437 INFO L425 stractBuchiCegarLoop]: Abstraction has 15146 states and 21535 transitions. [2024-11-08 00:35:04,437 INFO L332 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2024-11-08 00:35:04,437 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 15146 states and 21535 transitions. [2024-11-08 00:35:04,469 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 14944 [2024-11-08 00:35:04,470 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:35:04,470 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:35:04,471 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:04,471 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:04,471 INFO L745 eck$LassoCheckResult]: Stem: 183087#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 183088#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 183216#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 183217#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 182869#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 182870#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 183212#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 183213#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 183142#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 182927#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 182928#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 182849#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 182850#L684 assume !(0 == ~M_E~0); 183330#L684-2 assume !(0 == ~T1_E~0); 183172#L689-1 assume !(0 == ~T2_E~0); 183173#L694-1 assume !(0 == ~T3_E~0); 183170#L699-1 assume !(0 == ~T4_E~0); 183171#L704-1 assume !(0 == ~T5_E~0); 183130#L709-1 assume !(0 == ~T6_E~0); 183063#L714-1 assume !(0 == ~E_M~0); 183064#L719-1 assume !(0 == ~E_1~0); 183299#L724-1 assume !(0 == ~E_2~0); 182820#L729-1 assume !(0 == ~E_3~0); 182821#L734-1 assume !(0 == ~E_4~0); 183360#L739-1 assume !(0 == ~E_5~0); 183022#L744-1 assume !(0 == ~E_6~0); 183023#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 182775#L334 assume !(1 == ~m_pc~0); 182776#L334-2 is_master_triggered_~__retres1~0#1 := 0; 183119#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 183026#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 182992#L849 assume !(0 != activate_threads_~tmp~1#1); 182993#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 182923#L353 assume !(1 == ~t1_pc~0); 182924#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 183218#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 182790#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 182791#L857 assume !(0 != activate_threads_~tmp___0~0#1); 182871#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 182872#L372 assume !(1 == ~t2_pc~0); 182981#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 182980#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 183114#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 183219#L865 assume !(0 != activate_threads_~tmp___1~0#1); 182764#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 182765#L391 assume !(1 == ~t3_pc~0); 182687#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 182688#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 182713#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 182714#L873 assume !(0 != activate_threads_~tmp___2~0#1); 182999#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 183000#L410 assume !(1 == ~t4_pc~0); 183234#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 183235#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 182885#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 182886#L881 assume !(0 != activate_threads_~tmp___3~0#1); 183009#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 183010#L429 assume !(1 == ~t5_pc~0); 182826#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 182827#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 183037#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 183038#L889 assume !(0 != activate_threads_~tmp___4~0#1); 183238#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 182991#L448 assume !(1 == ~t6_pc~0); 182906#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 182907#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 183204#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 183205#L897 assume !(0 != activate_threads_~tmp___5~0#1); 183385#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 183429#L762 assume !(1 == ~M_E~0); 183044#L762-2 assume !(1 == ~T1_E~0); 183045#L767-1 assume !(1 == ~T2_E~0); 183390#L772-1 assume !(1 == ~T3_E~0); 183267#L777-1 assume !(1 == ~T4_E~0); 183157#L782-1 assume !(1 == ~T5_E~0); 182853#L787-1 assume !(1 == ~T6_E~0); 182851#L792-1 assume !(1 == ~E_M~0); 182852#L797-1 assume !(1 == ~E_1~0); 182893#L802-1 assume !(1 == ~E_2~0); 183123#L807-1 assume !(1 == ~E_3~0); 183124#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 183357#L817-1 assume !(1 == ~E_5~0); 183176#L822-1 assume !(1 == ~E_6~0); 183177#L827-1 assume { :end_inline_reset_delta_events } true; 183366#L1053-2 [2024-11-08 00:35:04,472 INFO L747 eck$LassoCheckResult]: Loop: 183366#L1053-2 assume !false; 189580#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 188371#L659-1 assume !false; 188365#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 187759#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 187752#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 187750#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 187747#L570 assume !(0 != eval_~tmp~0#1); 187746#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 187738#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 187736#L684-3 assume !(0 == ~M_E~0); 187734#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 187731#L689-3 assume !(0 == ~T2_E~0); 187729#L694-3 assume !(0 == ~T3_E~0); 187727#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 187725#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 187723#L709-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 187721#L714-3 assume !(0 == ~E_M~0); 187719#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 187717#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 187715#L729-3 assume !(0 == ~E_3~0); 187713#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 187711#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 187709#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 187707#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 187705#L334-24 assume 1 == ~m_pc~0; 187702#L335-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 187699#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 187697#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 187695#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 187692#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 187690#L353-24 assume !(1 == ~t1_pc~0); 187688#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 187686#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 187684#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 187682#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 187671#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 187662#L372-24 assume !(1 == ~t2_pc~0); 187652#L372-26 is_transmit2_triggered_~__retres1~2#1 := 0; 187647#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 187526#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 187523#L865-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 187521#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 187519#L391-24 assume !(1 == ~t3_pc~0); 187517#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 187515#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 187513#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 187511#L873-24 assume !(0 != activate_threads_~tmp___2~0#1); 187509#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 187507#L410-24 assume !(1 == ~t4_pc~0); 187505#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 187503#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 187501#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 187498#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 187496#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 187494#L429-24 assume !(1 == ~t5_pc~0); 187490#L429-26 is_transmit5_triggered_~__retres1~5#1 := 0; 187488#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 187486#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 187484#L889-24 assume !(0 != activate_threads_~tmp___4~0#1); 187481#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 187479#L448-24 assume !(1 == ~t6_pc~0); 187477#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 187475#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 187473#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 187470#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 187468#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 187466#L762-3 assume !(1 == ~M_E~0); 186304#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 187463#L767-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 187459#L772-3 assume !(1 == ~T3_E~0); 187457#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 187455#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 187453#L787-3 assume !(1 == ~T6_E~0); 187450#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 187448#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 187446#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 187444#L807-3 assume 1 == ~E_3~0;~E_3~0 := 2; 187442#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 187440#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 187438#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 187436#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 187426#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 187422#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 187420#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 186466#L1072 assume !(0 == start_simulation_~tmp~3#1); 186467#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 189672#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 189665#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 189663#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 189661#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 189659#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 189657#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 189653#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 183366#L1053-2 [2024-11-08 00:35:04,472 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:04,472 INFO L85 PathProgramCache]: Analyzing trace with hash -895756277, now seen corresponding path program 1 times [2024-11-08 00:35:04,472 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:04,472 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1898830735] [2024-11-08 00:35:04,472 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:04,472 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:04,482 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:04,518 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:04,518 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:04,518 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1898830735] [2024-11-08 00:35:04,519 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1898830735] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:04,519 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:04,519 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:04,519 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [446148864] [2024-11-08 00:35:04,519 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:04,519 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:35:04,519 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:04,519 INFO L85 PathProgramCache]: Analyzing trace with hash 489053887, now seen corresponding path program 1 times [2024-11-08 00:35:04,519 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:04,520 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2106065438] [2024-11-08 00:35:04,520 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:04,520 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:04,527 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:04,545 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:04,546 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:04,546 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2106065438] [2024-11-08 00:35:04,546 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2106065438] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:04,546 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:04,546 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:04,546 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1504777661] [2024-11-08 00:35:04,546 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:04,546 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:35:04,547 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:35:04,547 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-08 00:35:04,547 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-08 00:35:04,547 INFO L87 Difference]: Start difference. First operand 15146 states and 21535 transitions. cyclomatic complexity: 6405 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:04,666 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:35:04,666 INFO L93 Difference]: Finished difference Result 23948 states and 33803 transitions. [2024-11-08 00:35:04,666 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 23948 states and 33803 transitions. [2024-11-08 00:35:04,740 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 23616 [2024-11-08 00:35:04,800 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 23948 states to 23948 states and 33803 transitions. [2024-11-08 00:35:04,800 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 23948 [2024-11-08 00:35:04,818 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 23948 [2024-11-08 00:35:04,818 INFO L73 IsDeterministic]: Start isDeterministic. Operand 23948 states and 33803 transitions. [2024-11-08 00:35:04,835 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:35:04,836 INFO L218 hiAutomatonCegarLoop]: Abstraction has 23948 states and 33803 transitions. [2024-11-08 00:35:04,852 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23948 states and 33803 transitions. [2024-11-08 00:35:05,051 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23948 to 17289. [2024-11-08 00:35:05,069 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17289 states, 17289 states have (on average 1.4158135230493378) internal successors, (24478), 17288 states have internal predecessors, (24478), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:05,094 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17289 states to 17289 states and 24478 transitions. [2024-11-08 00:35:05,095 INFO L240 hiAutomatonCegarLoop]: Abstraction has 17289 states and 24478 transitions. [2024-11-08 00:35:05,095 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-08 00:35:05,095 INFO L425 stractBuchiCegarLoop]: Abstraction has 17289 states and 24478 transitions. [2024-11-08 00:35:05,095 INFO L332 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2024-11-08 00:35:05,095 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 17289 states and 24478 transitions. [2024-11-08 00:35:05,135 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 17024 [2024-11-08 00:35:05,135 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:35:05,135 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:35:05,136 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:05,136 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:05,136 INFO L745 eck$LassoCheckResult]: Stem: 222190#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 222191#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 222331#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 222332#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 221969#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 221970#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 222329#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 222330#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 222251#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 222032#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 222033#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 221949#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 221950#L684 assume !(0 == ~M_E~0); 222458#L684-2 assume !(0 == ~T1_E~0); 222285#L689-1 assume !(0 == ~T2_E~0); 222286#L694-1 assume !(0 == ~T3_E~0); 222283#L699-1 assume !(0 == ~T4_E~0); 222284#L704-1 assume !(0 == ~T5_E~0); 222236#L709-1 assume !(0 == ~T6_E~0); 222173#L714-1 assume !(0 == ~E_M~0); 222174#L719-1 assume !(0 == ~E_1~0); 222426#L724-1 assume !(0 == ~E_2~0); 221921#L729-1 assume !(0 == ~E_3~0); 221922#L734-1 assume 0 == ~E_4~0;~E_4~0 := 1; 222499#L739-1 assume !(0 == ~E_5~0); 222131#L744-1 assume !(0 == ~E_6~0); 222132#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 221877#L334 assume !(1 == ~m_pc~0); 221878#L334-2 is_master_triggered_~__retres1~0#1 := 0; 222228#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 222133#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 222134#L849 assume !(0 != activate_threads_~tmp~1#1); 222626#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 222625#L353 assume !(1 == ~t1_pc~0); 222624#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 222335#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 221892#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 221893#L857 assume !(0 != activate_threads_~tmp___0~0#1); 222622#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 222547#L372 assume !(1 == ~t2_pc~0); 222548#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 222621#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 222336#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 222337#L865 assume !(0 != activate_threads_~tmp___1~0#1); 222483#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 222619#L391 assume !(1 == ~t3_pc~0); 221791#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 221792#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 221816#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 221817#L873 assume !(0 != activate_threads_~tmp___2~0#1); 222419#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 222615#L410 assume !(1 == ~t4_pc~0); 222349#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 222350#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 221988#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 221989#L881 assume !(0 != activate_threads_~tmp___3~0#1); 222485#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 222275#L429 assume !(1 == ~t5_pc~0); 222276#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 222610#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 222608#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 222606#L889 assume !(0 != activate_threads_~tmp___4~0#1); 222605#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 222098#L448 assume !(1 == ~t6_pc~0); 222011#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 222012#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 222353#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 222523#L897 assume !(0 != activate_threads_~tmp___5~0#1); 222524#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 222582#L762 assume !(1 == ~M_E~0); 222152#L762-2 assume !(1 == ~T1_E~0); 222153#L767-1 assume !(1 == ~T2_E~0); 222530#L772-1 assume !(1 == ~T3_E~0); 222388#L777-1 assume !(1 == ~T4_E~0); 222389#L782-1 assume !(1 == ~T5_E~0); 221955#L787-1 assume !(1 == ~T6_E~0); 221956#L792-1 assume !(1 == ~E_M~0); 222600#L797-1 assume !(1 == ~E_1~0); 222599#L802-1 assume !(1 == ~E_2~0); 222598#L807-1 assume !(1 == ~E_3~0); 222597#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 222494#L817-1 assume !(1 == ~E_5~0); 222287#L822-1 assume !(1 == ~E_6~0); 222288#L827-1 assume { :end_inline_reset_delta_events } true; 222504#L1053-2 [2024-11-08 00:35:05,137 INFO L747 eck$LassoCheckResult]: Loop: 222504#L1053-2 assume !false; 225692#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 225683#L659-1 assume !false; 225169#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 225158#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 225151#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 225150#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 225141#L570 assume !(0 != eval_~tmp~0#1); 225139#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 225137#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 225134#L684-3 assume !(0 == ~M_E~0); 225132#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 225130#L689-3 assume !(0 == ~T2_E~0); 225128#L694-3 assume !(0 == ~T3_E~0); 225126#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 225124#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 225122#L709-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 225120#L714-3 assume !(0 == ~E_M~0); 225109#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 225107#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 225106#L729-3 assume !(0 == ~E_3~0); 225103#L734-3 assume !(0 == ~E_4~0); 225104#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 226630#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 226628#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 226626#L334-24 assume 1 == ~m_pc~0; 226624#L335-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 226621#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 226619#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 226617#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 226615#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 226613#L353-24 assume !(1 == ~t1_pc~0); 226611#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 226609#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 226607#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 226604#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 226602#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 226600#L372-24 assume 1 == ~t2_pc~0; 226597#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 226594#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 226592#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 226588#L865-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 226584#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 226581#L391-24 assume !(1 == ~t3_pc~0); 226578#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 226575#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 226572#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 226569#L873-24 assume !(0 != activate_threads_~tmp___2~0#1); 226566#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 226563#L410-24 assume !(1 == ~t4_pc~0); 226560#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 226557#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 226554#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 226550#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 226545#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 226541#L429-24 assume !(1 == ~t5_pc~0); 226537#L429-26 is_transmit5_triggered_~__retres1~5#1 := 0; 226533#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 226529#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 226524#L889-24 assume !(0 != activate_threads_~tmp___4~0#1); 226519#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 226516#L448-24 assume !(1 == ~t6_pc~0); 226513#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 226510#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 226505#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 226502#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 226499#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 226497#L762-3 assume !(1 == ~M_E~0); 224570#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 226494#L767-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 226492#L772-3 assume !(1 == ~T3_E~0); 226491#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 226489#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 226485#L787-3 assume !(1 == ~T6_E~0); 226482#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 225161#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 225111#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 225105#L807-3 assume 1 == ~E_3~0;~E_3~0 := 2; 225041#L812-3 assume !(1 == ~E_4~0); 225037#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 225034#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 225031#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 225024#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 224971#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 224969#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 224922#L1072 assume !(0 == start_simulation_~tmp~3#1); 224923#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 225729#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 225722#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 225720#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 225718#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 225716#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 225714#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 225712#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 222504#L1053-2 [2024-11-08 00:35:05,137 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:05,137 INFO L85 PathProgramCache]: Analyzing trace with hash 1437636361, now seen corresponding path program 1 times [2024-11-08 00:35:05,137 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:05,137 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1297893697] [2024-11-08 00:35:05,137 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:05,138 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:05,144 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:05,171 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:05,171 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:05,171 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1297893697] [2024-11-08 00:35:05,171 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1297893697] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:05,171 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:05,171 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:05,172 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [919784699] [2024-11-08 00:35:05,172 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:05,172 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:35:05,172 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:05,172 INFO L85 PathProgramCache]: Analyzing trace with hash 1611642942, now seen corresponding path program 1 times [2024-11-08 00:35:05,172 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:05,172 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2042192444] [2024-11-08 00:35:05,172 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:05,173 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:05,179 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:05,197 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:05,198 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:05,198 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2042192444] [2024-11-08 00:35:05,198 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2042192444] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:05,198 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:05,198 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:05,198 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [737326720] [2024-11-08 00:35:05,198 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:05,198 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:35:05,198 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:35:05,198 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-08 00:35:05,199 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-08 00:35:05,199 INFO L87 Difference]: Start difference. First operand 17289 states and 24478 transitions. cyclomatic complexity: 7205 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:05,294 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:35:05,295 INFO L93 Difference]: Finished difference Result 21622 states and 30409 transitions. [2024-11-08 00:35:05,295 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 21622 states and 30409 transitions. [2024-11-08 00:35:05,457 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 21356 [2024-11-08 00:35:05,509 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 21622 states to 21622 states and 30409 transitions. [2024-11-08 00:35:05,509 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21622 [2024-11-08 00:35:05,524 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21622 [2024-11-08 00:35:05,524 INFO L73 IsDeterministic]: Start isDeterministic. Operand 21622 states and 30409 transitions. [2024-11-08 00:35:05,538 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:35:05,538 INFO L218 hiAutomatonCegarLoop]: Abstraction has 21622 states and 30409 transitions. [2024-11-08 00:35:05,550 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21622 states and 30409 transitions. [2024-11-08 00:35:05,685 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21622 to 15146. [2024-11-08 00:35:05,701 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 15146 states, 15146 states have (on average 1.4084906906113825) internal successors, (21333), 15145 states have internal predecessors, (21333), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:05,725 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15146 states to 15146 states and 21333 transitions. [2024-11-08 00:35:05,726 INFO L240 hiAutomatonCegarLoop]: Abstraction has 15146 states and 21333 transitions. [2024-11-08 00:35:05,726 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-08 00:35:05,726 INFO L425 stractBuchiCegarLoop]: Abstraction has 15146 states and 21333 transitions. [2024-11-08 00:35:05,726 INFO L332 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2024-11-08 00:35:05,727 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 15146 states and 21333 transitions. [2024-11-08 00:35:05,768 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 14944 [2024-11-08 00:35:05,769 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:35:05,769 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:35:05,770 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:05,770 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:05,770 INFO L745 eck$LassoCheckResult]: Stem: 261102#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 261103#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 261239#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 261240#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 260889#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 260890#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 261237#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 261238#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 261163#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 260950#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 260951#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 260870#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 260871#L684 assume !(0 == ~M_E~0); 261357#L684-2 assume !(0 == ~T1_E~0); 261195#L689-1 assume !(0 == ~T2_E~0); 261196#L694-1 assume !(0 == ~T3_E~0); 261193#L699-1 assume !(0 == ~T4_E~0); 261194#L704-1 assume !(0 == ~T5_E~0); 261148#L709-1 assume !(0 == ~T6_E~0); 261083#L714-1 assume !(0 == ~E_M~0); 261084#L719-1 assume !(0 == ~E_1~0); 261326#L724-1 assume !(0 == ~E_2~0); 260843#L729-1 assume !(0 == ~E_3~0); 260844#L734-1 assume !(0 == ~E_4~0); 261388#L739-1 assume !(0 == ~E_5~0); 261046#L744-1 assume !(0 == ~E_6~0); 261047#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 260799#L334 assume !(1 == ~m_pc~0); 260800#L334-2 is_master_triggered_~__retres1~0#1 := 0; 261140#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 261048#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 261017#L849 assume !(0 != activate_threads_~tmp~1#1); 261018#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 260948#L353 assume !(1 == ~t1_pc~0); 260949#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 261244#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 260814#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 260815#L857 assume !(0 != activate_threads_~tmp___0~0#1); 260894#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 260895#L372 assume !(1 == ~t2_pc~0); 261006#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 261005#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 261134#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 261245#L865 assume !(0 != activate_threads_~tmp___1~0#1); 260788#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 260789#L391 assume !(1 == ~t3_pc~0); 260712#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 260713#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 260738#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 260739#L873 assume !(0 != activate_threads_~tmp___2~0#1); 261024#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 261025#L410 assume !(1 == ~t4_pc~0); 261258#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 261259#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 260908#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 260909#L881 assume !(0 != activate_threads_~tmp___3~0#1); 261030#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 261031#L429 assume !(1 == ~t5_pc~0); 260849#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 260850#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 261059#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 261060#L889 assume !(0 != activate_threads_~tmp___4~0#1); 261264#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 261016#L448 assume !(1 == ~t6_pc~0); 260931#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 260932#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 261226#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 261227#L897 assume !(0 != activate_threads_~tmp___5~0#1); 261414#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 261456#L762 assume !(1 == ~M_E~0); 261063#L762-2 assume !(1 == ~T1_E~0); 261064#L767-1 assume !(1 == ~T2_E~0); 261419#L772-1 assume !(1 == ~T3_E~0); 261292#L777-1 assume !(1 == ~T4_E~0); 261180#L782-1 assume !(1 == ~T5_E~0); 260876#L787-1 assume !(1 == ~T6_E~0); 260874#L792-1 assume !(1 == ~E_M~0); 260875#L797-1 assume !(1 == ~E_1~0); 260913#L802-1 assume !(1 == ~E_2~0); 261144#L807-1 assume !(1 == ~E_3~0); 261145#L812-1 assume !(1 == ~E_4~0); 261382#L817-1 assume !(1 == ~E_5~0); 261197#L822-1 assume !(1 == ~E_6~0); 261198#L827-1 assume { :end_inline_reset_delta_events } true; 261394#L1053-2 [2024-11-08 00:35:05,771 INFO L747 eck$LassoCheckResult]: Loop: 261394#L1053-2 assume !false; 265864#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 265860#L659-1 assume !false; 265859#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 265856#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 265849#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 265847#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 265844#L570 assume !(0 != eval_~tmp~0#1); 265839#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 265837#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 265835#L684-3 assume !(0 == ~M_E~0); 265834#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 265833#L689-3 assume !(0 == ~T2_E~0); 265832#L694-3 assume !(0 == ~T3_E~0); 265831#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 265829#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 265828#L709-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 265827#L714-3 assume !(0 == ~E_M~0); 265823#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 265821#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 265819#L729-3 assume !(0 == ~E_3~0); 265817#L734-3 assume !(0 == ~E_4~0); 265814#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 265812#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 265810#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 265807#L334-24 assume 1 == ~m_pc~0; 265804#L335-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 265801#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 265798#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 265796#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 265794#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 265792#L353-24 assume !(1 == ~t1_pc~0); 265712#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 265703#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 265694#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 265685#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 265676#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 265669#L372-24 assume 1 == ~t2_pc~0; 265664#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 265658#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 265652#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 265634#L865-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 265631#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 265550#L391-24 assume !(1 == ~t3_pc~0); 265479#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 265467#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 265458#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 265449#L873-24 assume !(0 != activate_threads_~tmp___2~0#1); 265441#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 265435#L410-24 assume !(1 == ~t4_pc~0); 265432#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 265429#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 265426#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 265424#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 265421#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 265418#L429-24 assume 1 == ~t5_pc~0; 265415#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 265412#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 265408#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 265404#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 265400#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 265394#L448-24 assume !(1 == ~t6_pc~0); 265390#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 265386#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 265381#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 265377#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 265373#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 265370#L762-3 assume !(1 == ~M_E~0); 263333#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 265364#L767-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 265360#L772-3 assume !(1 == ~T3_E~0); 265357#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 265355#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 265352#L787-3 assume !(1 == ~T6_E~0); 265350#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 265348#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 265346#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 265345#L807-3 assume 1 == ~E_3~0;~E_3~0 := 2; 265344#L812-3 assume !(1 == ~E_4~0); 265343#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 265341#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 265338#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 265330#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 265326#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 264480#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 263326#L1072 assume !(0 == start_simulation_~tmp~3#1); 263327#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 266169#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 266162#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 266160#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 266159#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 265876#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 265872#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 265868#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 261394#L1053-2 [2024-11-08 00:35:05,771 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:05,771 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 1 times [2024-11-08 00:35:05,771 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:05,771 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1509058691] [2024-11-08 00:35:05,771 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:05,771 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:05,780 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:35:05,780 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 00:35:05,786 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:35:05,830 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 00:35:05,830 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:05,831 INFO L85 PathProgramCache]: Analyzing trace with hash -882390469, now seen corresponding path program 1 times [2024-11-08 00:35:05,831 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:05,831 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1839355422] [2024-11-08 00:35:05,831 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:05,831 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:05,845 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:05,872 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:05,872 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:05,872 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1839355422] [2024-11-08 00:35:05,872 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1839355422] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:05,872 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:05,873 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:05,873 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [320527499] [2024-11-08 00:35:05,873 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:05,873 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:35:05,873 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:35:05,874 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:35:05,874 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:35:05,874 INFO L87 Difference]: Start difference. First operand 15146 states and 21333 transitions. cyclomatic complexity: 6203 Second operand has 3 states, 3 states have (on average 31.333333333333332) internal successors, (94), 3 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:05,932 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:35:05,932 INFO L93 Difference]: Finished difference Result 17289 states and 24330 transitions. [2024-11-08 00:35:05,932 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17289 states and 24330 transitions. [2024-11-08 00:35:06,076 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 17024 [2024-11-08 00:35:06,111 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17289 states to 17289 states and 24330 transitions. [2024-11-08 00:35:06,111 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17289 [2024-11-08 00:35:06,121 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17289 [2024-11-08 00:35:06,122 INFO L73 IsDeterministic]: Start isDeterministic. Operand 17289 states and 24330 transitions. [2024-11-08 00:35:06,131 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:35:06,132 INFO L218 hiAutomatonCegarLoop]: Abstraction has 17289 states and 24330 transitions. [2024-11-08 00:35:06,141 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17289 states and 24330 transitions. [2024-11-08 00:35:06,225 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17289 to 17289. [2024-11-08 00:35:06,241 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17289 states, 17289 states have (on average 1.407253166753427) internal successors, (24330), 17288 states have internal predecessors, (24330), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:06,261 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17289 states to 17289 states and 24330 transitions. [2024-11-08 00:35:06,262 INFO L240 hiAutomatonCegarLoop]: Abstraction has 17289 states and 24330 transitions. [2024-11-08 00:35:06,262 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:35:06,262 INFO L425 stractBuchiCegarLoop]: Abstraction has 17289 states and 24330 transitions. [2024-11-08 00:35:06,262 INFO L332 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2024-11-08 00:35:06,262 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 17289 states and 24330 transitions. [2024-11-08 00:35:06,299 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 17024 [2024-11-08 00:35:06,299 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:35:06,299 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:35:06,300 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:06,300 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:06,301 INFO L745 eck$LassoCheckResult]: Stem: 293549#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 293550#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 293690#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 293691#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 293330#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 293331#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 293688#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 293689#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 293612#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 293391#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 293392#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 293311#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 293312#L684 assume !(0 == ~M_E~0); 293826#L684-2 assume !(0 == ~T1_E~0); 293644#L689-1 assume !(0 == ~T2_E~0); 293645#L694-1 assume !(0 == ~T3_E~0); 293642#L699-1 assume !(0 == ~T4_E~0); 293643#L704-1 assume !(0 == ~T5_E~0); 293593#L709-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 293531#L714-1 assume !(0 == ~E_M~0); 293532#L719-1 assume !(0 == ~E_1~0); 293789#L724-1 assume !(0 == ~E_2~0); 293286#L729-1 assume !(0 == ~E_3~0); 293287#L734-1 assume !(0 == ~E_4~0); 294005#L739-1 assume !(0 == ~E_5~0); 294004#L744-1 assume !(0 == ~E_6~0); 294003#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 293241#L334 assume !(1 == ~m_pc~0); 293242#L334-2 is_master_triggered_~__retres1~0#1 := 0; 293585#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 293491#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 293492#L849 assume !(0 != activate_threads_~tmp~1#1); 293998#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 293997#L353 assume !(1 == ~t1_pc~0); 293996#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 293696#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 293257#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 293258#L857 assume !(0 != activate_threads_~tmp___0~0#1); 293994#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 293912#L372 assume !(1 == ~t2_pc~0); 293913#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 293993#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 293697#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 293698#L865 assume !(0 != activate_threads_~tmp___1~0#1); 293848#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 293991#L391 assume !(1 == ~t3_pc~0); 293990#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 293989#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 293988#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 293987#L873 assume !(0 != activate_threads_~tmp___2~0#1); 293466#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 293467#L410 assume !(1 == ~t4_pc~0); 293710#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 293711#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 293349#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 293350#L881 assume !(0 != activate_threads_~tmp___3~0#1); 293472#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 293473#L429 assume !(1 == ~t5_pc~0); 293292#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 293293#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 294006#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 293717#L889 assume !(0 != activate_threads_~tmp___4~0#1); 293718#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 293749#L448 assume !(1 == ~t6_pc~0); 293973#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 293972#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 293678#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 293679#L897 assume !(0 != activate_threads_~tmp___5~0#1); 293952#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 293953#L762 assume !(1 == ~M_E~0); 293971#L762-2 assume !(1 == ~T1_E~0); 293931#L767-1 assume !(1 == ~T2_E~0); 293932#L772-1 assume !(1 == ~T3_E~0); 293970#L777-1 assume !(1 == ~T4_E~0); 293627#L782-1 assume !(1 == ~T5_E~0); 293317#L787-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 293315#L792-1 assume !(1 == ~E_M~0); 293316#L797-1 assume !(1 == ~E_1~0); 293355#L802-1 assume !(1 == ~E_2~0); 293589#L807-1 assume !(1 == ~E_3~0); 293590#L812-1 assume !(1 == ~E_4~0); 293856#L817-1 assume !(1 == ~E_5~0); 293646#L822-1 assume !(1 == ~E_6~0); 293647#L827-1 assume { :end_inline_reset_delta_events } true; 293868#L1053-2 [2024-11-08 00:35:06,301 INFO L747 eck$LassoCheckResult]: Loop: 293868#L1053-2 assume !false; 300197#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 300192#L659-1 assume !false; 300190#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 300185#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 300178#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 300177#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 300174#L570 assume !(0 != eval_~tmp~0#1); 300175#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 300501#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 300499#L684-3 assume !(0 == ~M_E~0); 300497#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 300495#L689-3 assume !(0 == ~T2_E~0); 300493#L694-3 assume !(0 == ~T3_E~0); 300491#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 300489#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 300486#L709-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 300484#L714-3 assume !(0 == ~E_M~0); 300480#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 300478#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 300476#L729-3 assume !(0 == ~E_3~0); 300474#L734-3 assume !(0 == ~E_4~0); 300471#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 300469#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 300467#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 300465#L334-24 assume !(1 == ~m_pc~0); 300462#L334-26 is_master_triggered_~__retres1~0#1 := 0; 300460#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 300458#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 300456#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 300455#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 300454#L353-24 assume !(1 == ~t1_pc~0); 300452#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 300451#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 300450#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 300448#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 300447#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 300446#L372-24 assume !(1 == ~t2_pc~0); 300337#L372-26 is_transmit2_triggered_~__retres1~2#1 := 0; 300335#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 300333#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 300331#L865-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 300329#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 300327#L391-24 assume !(1 == ~t3_pc~0); 300325#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 300323#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 300321#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 300319#L873-24 assume !(0 != activate_threads_~tmp___2~0#1); 300317#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 300315#L410-24 assume !(1 == ~t4_pc~0); 300313#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 300311#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 300309#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 300307#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 300305#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 300301#L429-24 assume !(1 == ~t5_pc~0); 300297#L429-26 is_transmit5_triggered_~__retres1~5#1 := 0; 300295#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 300293#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 300290#L889-24 assume !(0 != activate_threads_~tmp___4~0#1); 300287#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 300285#L448-24 assume !(1 == ~t6_pc~0); 300283#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 300281#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 300279#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 300277#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 300275#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 300272#L762-3 assume !(1 == ~M_E~0); 300269#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 300267#L767-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 300265#L772-3 assume !(1 == ~T3_E~0); 300263#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 300261#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 300259#L787-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 300256#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 300254#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 300252#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 300250#L807-3 assume 1 == ~E_3~0;~E_3~0 := 2; 300248#L812-3 assume !(1 == ~E_4~0); 300246#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 300244#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 300243#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 300237#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 300233#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 300231#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 300228#L1072 assume !(0 == start_simulation_~tmp~3#1); 300225#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 300220#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 300213#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 300209#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 300207#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 300205#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 300203#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 300200#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 293868#L1053-2 [2024-11-08 00:35:06,301 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:06,301 INFO L85 PathProgramCache]: Analyzing trace with hash -843787639, now seen corresponding path program 1 times [2024-11-08 00:35:06,301 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:06,301 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [865304685] [2024-11-08 00:35:06,302 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:06,302 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:06,308 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:06,336 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:06,336 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:06,336 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [865304685] [2024-11-08 00:35:06,336 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [865304685] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:06,336 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:06,336 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:06,336 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2096645612] [2024-11-08 00:35:06,336 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:06,337 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:35:06,338 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:06,338 INFO L85 PathProgramCache]: Analyzing trace with hash -1728129986, now seen corresponding path program 1 times [2024-11-08 00:35:06,338 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:06,338 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1421521266] [2024-11-08 00:35:06,338 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:06,338 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:06,346 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:06,404 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:06,404 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:06,404 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1421521266] [2024-11-08 00:35:06,404 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1421521266] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:06,404 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:06,404 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-08 00:35:06,404 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [935920744] [2024-11-08 00:35:06,405 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:06,405 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:35:06,405 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:35:06,405 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-08 00:35:06,405 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-08 00:35:06,405 INFO L87 Difference]: Start difference. First operand 17289 states and 24330 transitions. cyclomatic complexity: 7057 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:06,487 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:35:06,487 INFO L93 Difference]: Finished difference Result 22042 states and 30930 transitions. [2024-11-08 00:35:06,487 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 22042 states and 30930 transitions. [2024-11-08 00:35:06,573 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 21776 [2024-11-08 00:35:06,635 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 22042 states to 22042 states and 30930 transitions. [2024-11-08 00:35:06,636 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22042 [2024-11-08 00:35:06,888 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22042 [2024-11-08 00:35:06,888 INFO L73 IsDeterministic]: Start isDeterministic. Operand 22042 states and 30930 transitions. [2024-11-08 00:35:06,893 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:35:06,893 INFO L218 hiAutomatonCegarLoop]: Abstraction has 22042 states and 30930 transitions. [2024-11-08 00:35:06,899 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22042 states and 30930 transitions. [2024-11-08 00:35:06,984 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22042 to 15146. [2024-11-08 00:35:07,000 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 15146 states, 15146 states have (on average 1.4063118975307012) internal successors, (21300), 15145 states have internal predecessors, (21300), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:07,018 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15146 states to 15146 states and 21300 transitions. [2024-11-08 00:35:07,018 INFO L240 hiAutomatonCegarLoop]: Abstraction has 15146 states and 21300 transitions. [2024-11-08 00:35:07,019 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-08 00:35:07,019 INFO L425 stractBuchiCegarLoop]: Abstraction has 15146 states and 21300 transitions. [2024-11-08 00:35:07,019 INFO L332 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2024-11-08 00:35:07,019 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 15146 states and 21300 transitions. [2024-11-08 00:35:07,054 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 14944 [2024-11-08 00:35:07,054 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:35:07,054 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:35:07,056 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:07,056 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:07,056 INFO L745 eck$LassoCheckResult]: Stem: 332887#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 332888#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 333021#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 333022#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 332675#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 332676#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 333017#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 333018#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 332945#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 332735#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 332736#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 332655#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 332656#L684 assume !(0 == ~M_E~0); 333137#L684-2 assume !(0 == ~T1_E~0); 332975#L689-1 assume !(0 == ~T2_E~0); 332976#L694-1 assume !(0 == ~T3_E~0); 332973#L699-1 assume !(0 == ~T4_E~0); 332974#L704-1 assume !(0 == ~T5_E~0); 332932#L709-1 assume !(0 == ~T6_E~0); 332866#L714-1 assume !(0 == ~E_M~0); 332867#L719-1 assume !(0 == ~E_1~0); 333107#L724-1 assume !(0 == ~E_2~0); 332626#L729-1 assume !(0 == ~E_3~0); 332627#L734-1 assume !(0 == ~E_4~0); 333167#L739-1 assume !(0 == ~E_5~0); 332827#L744-1 assume !(0 == ~E_6~0); 332828#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 332583#L334 assume !(1 == ~m_pc~0); 332584#L334-2 is_master_triggered_~__retres1~0#1 := 0; 332921#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 332830#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 332798#L849 assume !(0 != activate_threads_~tmp~1#1); 332799#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 332731#L353 assume !(1 == ~t1_pc~0); 332732#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 333025#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 332598#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 332599#L857 assume !(0 != activate_threads_~tmp___0~0#1); 332677#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 332678#L372 assume !(1 == ~t2_pc~0); 332787#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 332786#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 332915#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 333026#L865 assume !(0 != activate_threads_~tmp___1~0#1); 332572#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 332573#L391 assume !(1 == ~t3_pc~0); 332496#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 332497#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 332522#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 332523#L873 assume !(0 != activate_threads_~tmp___2~0#1); 332805#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 332806#L410 assume !(1 == ~t4_pc~0); 333039#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 333040#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 332691#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 332692#L881 assume !(0 != activate_threads_~tmp___3~0#1); 332814#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 332815#L429 assume !(1 == ~t5_pc~0); 332632#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 332633#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 332840#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 332841#L889 assume !(0 != activate_threads_~tmp___4~0#1); 333043#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 332797#L448 assume !(1 == ~t6_pc~0); 332714#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 332715#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 333009#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 333010#L897 assume !(0 != activate_threads_~tmp___5~0#1); 333189#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 333230#L762 assume !(1 == ~M_E~0); 332847#L762-2 assume !(1 == ~T1_E~0); 332848#L767-1 assume !(1 == ~T2_E~0); 333195#L772-1 assume !(1 == ~T3_E~0); 333074#L777-1 assume !(1 == ~T4_E~0); 332961#L782-1 assume !(1 == ~T5_E~0); 332659#L787-1 assume !(1 == ~T6_E~0); 332657#L792-1 assume !(1 == ~E_M~0); 332658#L797-1 assume !(1 == ~E_1~0); 332698#L802-1 assume !(1 == ~E_2~0); 332925#L807-1 assume !(1 == ~E_3~0); 332926#L812-1 assume !(1 == ~E_4~0); 333163#L817-1 assume !(1 == ~E_5~0); 332977#L822-1 assume !(1 == ~E_6~0); 332978#L827-1 assume { :end_inline_reset_delta_events } true; 333172#L1053-2 [2024-11-08 00:35:07,056 INFO L747 eck$LassoCheckResult]: Loop: 333172#L1053-2 assume !false; 335811#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 335806#L659-1 assume !false; 335803#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 335644#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 335637#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 335634#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 335631#L570 assume !(0 != eval_~tmp~0#1); 335632#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 347602#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 347601#L684-3 assume !(0 == ~M_E~0); 347600#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 347599#L689-3 assume !(0 == ~T2_E~0); 347598#L694-3 assume !(0 == ~T3_E~0); 347596#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 347593#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 347591#L709-3 assume !(0 == ~T6_E~0); 347589#L714-3 assume !(0 == ~E_M~0); 347587#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 347585#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 347583#L729-3 assume !(0 == ~E_3~0); 347580#L734-3 assume !(0 == ~E_4~0); 347579#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 347551#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 333159#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 332557#L334-24 assume 1 == ~m_pc~0; 332559#L335-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 332695#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 332726#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 332526#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 332527#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 333056#L353-24 assume !(1 == ~t1_pc~0); 333057#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 333199#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 333197#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 333198#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 332574#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 332575#L372-24 assume 1 == ~t2_pc~0; 332537#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 332538#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 332901#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 333183#L865-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 333184#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 332871#L391-24 assume !(1 == ~t3_pc~0); 332872#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 333108#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 333053#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 332962#L873-24 assume !(0 != activate_threads_~tmp___2~0#1); 332938#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 332763#L410-24 assume !(1 == ~t4_pc~0); 332623#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 332624#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 333083#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 332810#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 332653#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 332654#L429-24 assume !(1 == ~t5_pc~0); 332759#L429-26 is_transmit5_triggered_~__retres1~5#1 := 0; 333081#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 333082#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 332699#L889-24 assume !(0 != activate_threads_~tmp___4~0#1); 332700#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 332646#L448-24 assume !(1 == ~t6_pc~0); 332647#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 332641#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 332642#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 332821#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 332969#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 332970#L762-3 assume !(1 == ~M_E~0); 332933#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 332934#L767-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 333206#L772-3 assume !(1 == ~T3_E~0); 333192#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 332634#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 332635#L787-3 assume !(1 == ~T6_E~0); 333093#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 332868#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 332869#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 333138#L807-3 assume 1 == ~E_3~0;~E_3~0 := 2; 333007#L812-3 assume !(1 == ~E_4~0); 333008#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 333101#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 333087#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 332891#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 332535#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 332993#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 332994#L1072 assume !(0 == start_simulation_~tmp~3#1); 333224#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 335829#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 335823#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 335821#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 335820#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 335819#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 335816#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 335812#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 333172#L1053-2 [2024-11-08 00:35:07,059 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:07,059 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 2 times [2024-11-08 00:35:07,059 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:07,059 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [661004173] [2024-11-08 00:35:07,059 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:07,059 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:07,068 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:35:07,068 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 00:35:07,072 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:35:07,083 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 00:35:07,084 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:07,084 INFO L85 PathProgramCache]: Analyzing trace with hash -1844290692, now seen corresponding path program 1 times [2024-11-08 00:35:07,084 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:07,084 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [565421932] [2024-11-08 00:35:07,084 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:07,084 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:07,093 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:07,252 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:07,252 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:07,252 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [565421932] [2024-11-08 00:35:07,252 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [565421932] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:07,252 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:07,252 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-08 00:35:07,252 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [833105801] [2024-11-08 00:35:07,252 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:07,252 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:35:07,252 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:35:07,253 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-08 00:35:07,253 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-08 00:35:07,253 INFO L87 Difference]: Start difference. First operand 15146 states and 21300 transitions. cyclomatic complexity: 6170 Second operand has 5 states, 5 states have (on average 18.8) internal successors, (94), 5 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:07,332 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:35:07,333 INFO L93 Difference]: Finished difference Result 15370 states and 21524 transitions. [2024-11-08 00:35:07,333 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 15370 states and 21524 transitions. [2024-11-08 00:35:07,382 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 15168 [2024-11-08 00:35:07,415 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 15370 states to 15370 states and 21524 transitions. [2024-11-08 00:35:07,416 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 15370 [2024-11-08 00:35:07,426 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 15370 [2024-11-08 00:35:07,427 INFO L73 IsDeterministic]: Start isDeterministic. Operand 15370 states and 21524 transitions. [2024-11-08 00:35:07,439 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:35:07,440 INFO L218 hiAutomatonCegarLoop]: Abstraction has 15370 states and 21524 transitions. [2024-11-08 00:35:07,449 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15370 states and 21524 transitions. [2024-11-08 00:35:07,547 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15370 to 15242. [2024-11-08 00:35:07,563 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 15242 states, 15242 states have (on average 1.403752788347986) internal successors, (21396), 15241 states have internal predecessors, (21396), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:07,581 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15242 states to 15242 states and 21396 transitions. [2024-11-08 00:35:07,581 INFO L240 hiAutomatonCegarLoop]: Abstraction has 15242 states and 21396 transitions. [2024-11-08 00:35:07,581 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-08 00:35:07,582 INFO L425 stractBuchiCegarLoop]: Abstraction has 15242 states and 21396 transitions. [2024-11-08 00:35:07,582 INFO L332 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2024-11-08 00:35:07,582 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 15242 states and 21396 transitions. [2024-11-08 00:35:07,614 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 15040 [2024-11-08 00:35:07,615 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:35:07,615 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:35:07,615 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:07,616 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:07,616 INFO L745 eck$LassoCheckResult]: Stem: 363423#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 363424#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 363579#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 363580#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 363201#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 363202#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 363575#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 363576#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 363490#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 363256#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 363257#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 363182#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 363183#L684 assume !(0 == ~M_E~0); 363722#L684-2 assume !(0 == ~T1_E~0); 363527#L689-1 assume !(0 == ~T2_E~0); 363528#L694-1 assume !(0 == ~T3_E~0); 363525#L699-1 assume !(0 == ~T4_E~0); 363526#L704-1 assume !(0 == ~T5_E~0); 363471#L709-1 assume !(0 == ~T6_E~0); 363401#L714-1 assume !(0 == ~E_M~0); 363402#L719-1 assume !(0 == ~E_1~0); 363683#L724-1 assume !(0 == ~E_2~0); 363151#L729-1 assume !(0 == ~E_3~0); 363152#L734-1 assume !(0 == ~E_4~0); 363772#L739-1 assume !(0 == ~E_5~0); 363356#L744-1 assume !(0 == ~E_6~0); 363357#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 363106#L334 assume !(1 == ~m_pc~0); 363107#L334-2 is_master_triggered_~__retres1~0#1 := 0; 363463#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 363360#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 363323#L849 assume !(0 != activate_threads_~tmp~1#1); 363324#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 363254#L353 assume !(1 == ~t1_pc~0); 363255#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 363581#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 363122#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 363123#L857 assume !(0 != activate_threads_~tmp___0~0#1); 363204#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 363205#L372 assume !(1 == ~t2_pc~0); 363312#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 363311#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 363455#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 363582#L865 assume !(0 != activate_threads_~tmp___1~0#1); 363095#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 363096#L391 assume !(1 == ~t3_pc~0); 363020#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 363021#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 363045#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 363046#L873 assume !(0 != activate_threads_~tmp___2~0#1); 363330#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 363331#L410 assume !(1 == ~t4_pc~0); 363597#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 363598#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 363218#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 363219#L881 assume !(0 != activate_threads_~tmp___3~0#1); 363340#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 363341#L429 assume !(1 == ~t5_pc~0); 363157#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 363158#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 363371#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 363372#L889 assume !(0 != activate_threads_~tmp___4~0#1); 363604#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 363322#L448 assume !(1 == ~t6_pc~0); 363237#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 363238#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 363566#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 363567#L897 assume !(0 != activate_threads_~tmp___5~0#1); 363801#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 363862#L762 assume !(1 == ~M_E~0); 363379#L762-2 assume !(1 == ~T1_E~0); 363380#L767-1 assume !(1 == ~T2_E~0); 363806#L772-1 assume !(1 == ~T3_E~0); 363635#L777-1 assume !(1 == ~T4_E~0); 363508#L782-1 assume !(1 == ~T5_E~0); 363186#L787-1 assume !(1 == ~T6_E~0); 363184#L792-1 assume !(1 == ~E_M~0); 363185#L797-1 assume !(1 == ~E_1~0); 363224#L802-1 assume !(1 == ~E_2~0); 363467#L807-1 assume !(1 == ~E_3~0); 363468#L812-1 assume !(1 == ~E_4~0); 363766#L817-1 assume !(1 == ~E_5~0); 363529#L822-1 assume !(1 == ~E_6~0); 363530#L827-1 assume { :end_inline_reset_delta_events } true; 363778#L1053-2 [2024-11-08 00:35:07,616 INFO L747 eck$LassoCheckResult]: Loop: 363778#L1053-2 assume !false; 368290#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 368283#L659-1 assume !false; 368242#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 368239#L518 assume !(0 == ~m_st~0); 368240#L522 assume !(0 == ~t1_st~0); 368235#L526 assume !(0 == ~t2_st~0); 368236#L530 assume !(0 == ~t3_st~0); 368238#L534 assume !(0 == ~t4_st~0); 368233#L538 assume !(0 == ~t5_st~0); 368234#L542 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 368237#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 368228#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 368229#L570 assume !(0 != eval_~tmp~0#1); 370631#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 370628#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 370625#L684-3 assume !(0 == ~M_E~0); 370623#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 370621#L689-3 assume !(0 == ~T2_E~0); 370618#L694-3 assume !(0 == ~T3_E~0); 370614#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 370611#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 370608#L709-3 assume !(0 == ~T6_E~0); 370604#L714-3 assume !(0 == ~E_M~0); 370601#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 370598#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 370595#L729-3 assume !(0 == ~E_3~0); 370592#L734-3 assume !(0 == ~E_4~0); 370589#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 370587#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 370585#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 370582#L334-24 assume !(1 == ~m_pc~0); 370577#L334-26 is_master_triggered_~__retres1~0#1 := 0; 370574#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 370571#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 370567#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 370564#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 370561#L353-24 assume !(1 == ~t1_pc~0); 370558#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 370555#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 370552#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 370549#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 370546#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 370543#L372-24 assume 1 == ~t2_pc~0; 370539#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 370535#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 370532#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 370529#L865-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 370526#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 370524#L391-24 assume !(1 == ~t3_pc~0); 370522#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 370519#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 370515#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 370511#L873-24 assume !(0 != activate_threads_~tmp___2~0#1); 370507#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 370503#L410-24 assume !(1 == ~t4_pc~0); 370499#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 370496#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 370493#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 370490#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 370488#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 370474#L429-24 assume 1 == ~t5_pc~0; 370469#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 370465#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 370461#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 370457#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 370454#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 370451#L448-24 assume !(1 == ~t6_pc~0); 370447#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 370444#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 370442#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 370439#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 370436#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 370429#L762-3 assume !(1 == ~M_E~0); 370423#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 370418#L767-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 370414#L772-3 assume !(1 == ~T3_E~0); 370411#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 370408#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 370405#L787-3 assume !(1 == ~T6_E~0); 370402#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 370397#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 370393#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 370386#L807-3 assume 1 == ~E_3~0;~E_3~0 := 2; 370380#L812-3 assume !(1 == ~E_4~0); 370368#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 370361#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 370356#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 370176#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 370165#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 369881#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 369878#L1072 assume !(0 == start_simulation_~tmp~3#1); 369876#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 369874#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 368633#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 368347#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 368346#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 368345#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 368320#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 368311#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 363778#L1053-2 [2024-11-08 00:35:07,616 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:07,616 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 3 times [2024-11-08 00:35:07,617 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:07,617 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [358833456] [2024-11-08 00:35:07,617 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:07,617 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:07,625 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:35:07,625 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 00:35:07,632 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:35:07,642 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 00:35:07,642 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:07,643 INFO L85 PathProgramCache]: Analyzing trace with hash -1173818935, now seen corresponding path program 1 times [2024-11-08 00:35:07,643 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:07,643 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1595230612] [2024-11-08 00:35:07,643 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:07,643 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:07,651 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:07,716 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:07,717 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:07,717 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1595230612] [2024-11-08 00:35:07,717 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1595230612] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:07,717 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:07,717 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-08 00:35:07,717 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1417989580] [2024-11-08 00:35:07,717 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:07,717 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:35:07,717 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:35:07,717 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-08 00:35:07,717 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-08 00:35:07,718 INFO L87 Difference]: Start difference. First operand 15242 states and 21396 transitions. cyclomatic complexity: 6170 Second operand has 5 states, 5 states have (on average 20.0) internal successors, (100), 5 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:07,865 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:35:07,865 INFO L93 Difference]: Finished difference Result 15869 states and 22023 transitions. [2024-11-08 00:35:07,865 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 15869 states and 22023 transitions. [2024-11-08 00:35:07,972 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 15664 [2024-11-08 00:35:07,997 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 15869 states to 15869 states and 22023 transitions. [2024-11-08 00:35:07,997 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 15869 [2024-11-08 00:35:08,004 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 15869 [2024-11-08 00:35:08,004 INFO L73 IsDeterministic]: Start isDeterministic. Operand 15869 states and 22023 transitions. [2024-11-08 00:35:08,014 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:35:08,014 INFO L218 hiAutomatonCegarLoop]: Abstraction has 15869 states and 22023 transitions. [2024-11-08 00:35:08,020 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15869 states and 22023 transitions. [2024-11-08 00:35:08,139 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15869 to 15869. [2024-11-08 00:35:08,155 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 15869 states, 15869 states have (on average 1.3878001134286975) internal successors, (22023), 15868 states have internal predecessors, (22023), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:08,181 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15869 states to 15869 states and 22023 transitions. [2024-11-08 00:35:08,181 INFO L240 hiAutomatonCegarLoop]: Abstraction has 15869 states and 22023 transitions. [2024-11-08 00:35:08,181 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-08 00:35:08,181 INFO L425 stractBuchiCegarLoop]: Abstraction has 15869 states and 22023 transitions. [2024-11-08 00:35:08,181 INFO L332 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2024-11-08 00:35:08,181 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 15869 states and 22023 transitions. [2024-11-08 00:35:08,224 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 15664 [2024-11-08 00:35:08,226 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:35:08,226 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:35:08,227 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:08,227 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:08,227 INFO L745 eck$LassoCheckResult]: Stem: 394539#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 394540#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 394691#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 394692#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 394315#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 394316#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 394687#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 394688#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 394605#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 394377#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 394378#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 394298#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 394299#L684 assume !(0 == ~M_E~0); 394830#L684-2 assume !(0 == ~T1_E~0); 394640#L689-1 assume !(0 == ~T2_E~0); 394641#L694-1 assume !(0 == ~T3_E~0); 394638#L699-1 assume !(0 == ~T4_E~0); 394639#L704-1 assume !(0 == ~T5_E~0); 394587#L709-1 assume !(0 == ~T6_E~0); 394520#L714-1 assume !(0 == ~E_M~0); 394521#L719-1 assume !(0 == ~E_1~0); 394790#L724-1 assume !(0 == ~E_2~0); 394269#L729-1 assume !(0 == ~E_3~0); 394270#L734-1 assume !(0 == ~E_4~0); 394872#L739-1 assume !(0 == ~E_5~0); 394476#L744-1 assume !(0 == ~E_6~0); 394477#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 394226#L334 assume !(1 == ~m_pc~0); 394227#L334-2 is_master_triggered_~__retres1~0#1 := 0; 394579#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 394993#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 394444#L849 assume !(0 != activate_threads_~tmp~1#1); 394445#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 394375#L353 assume !(1 == ~t1_pc~0); 394376#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 394694#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 394241#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 394242#L857 assume !(0 != activate_threads_~tmp___0~0#1); 394321#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 394322#L372 assume !(1 == ~t2_pc~0); 394433#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 394432#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 394571#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 394695#L865 assume !(0 != activate_threads_~tmp___1~0#1); 394215#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 394216#L391 assume !(1 == ~t3_pc~0); 394139#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 394140#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 394165#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 394166#L873 assume !(0 != activate_threads_~tmp___2~0#1); 394451#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 394452#L410 assume !(1 == ~t4_pc~0); 394711#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 394712#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 394335#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 394336#L881 assume !(0 != activate_threads_~tmp___3~0#1); 394458#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 394459#L429 assume !(1 == ~t5_pc~0); 394275#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 394276#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 394492#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 394493#L889 assume !(0 != activate_threads_~tmp___4~0#1); 394716#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 394443#L448 assume !(1 == ~t6_pc~0); 394357#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 394358#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 394679#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 394680#L897 assume !(0 != activate_threads_~tmp___5~0#1); 394902#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 394966#L762 assume !(1 == ~M_E~0); 394498#L762-2 assume !(1 == ~T1_E~0); 394499#L767-1 assume !(1 == ~T2_E~0); 394908#L772-1 assume !(1 == ~T3_E~0); 394749#L777-1 assume !(1 == ~T4_E~0); 394623#L782-1 assume !(1 == ~T5_E~0); 394302#L787-1 assume !(1 == ~T6_E~0); 394300#L792-1 assume !(1 == ~E_M~0); 394301#L797-1 assume !(1 == ~E_1~0); 394341#L802-1 assume !(1 == ~E_2~0); 394583#L807-1 assume !(1 == ~E_3~0); 394584#L812-1 assume !(1 == ~E_4~0); 394864#L817-1 assume !(1 == ~E_5~0); 394642#L822-1 assume !(1 == ~E_6~0); 394643#L827-1 assume { :end_inline_reset_delta_events } true; 394877#L1053-2 [2024-11-08 00:35:08,227 INFO L747 eck$LassoCheckResult]: Loop: 394877#L1053-2 assume !false; 401753#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 399170#L659-1 assume !false; 401752#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 401750#L518 assume !(0 == ~m_st~0); 401751#L522 assume !(0 == ~t1_st~0); 401746#L526 assume !(0 == ~t2_st~0); 401747#L530 assume !(0 == ~t3_st~0); 401749#L534 assume !(0 == ~t4_st~0); 401744#L538 assume !(0 == ~t5_st~0); 401745#L542 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 401748#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 401738#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 401739#L570 assume !(0 != eval_~tmp~0#1); 402022#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 402020#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 402018#L684-3 assume !(0 == ~M_E~0); 402016#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 402013#L689-3 assume !(0 == ~T2_E~0); 402010#L694-3 assume !(0 == ~T3_E~0); 402007#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 402004#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 402001#L709-3 assume !(0 == ~T6_E~0); 401998#L714-3 assume !(0 == ~E_M~0); 401995#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 401992#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 401989#L729-3 assume !(0 == ~E_3~0); 401986#L734-3 assume !(0 == ~E_4~0); 401983#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 401980#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 401977#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 401968#L334-24 assume 1 == ~m_pc~0; 401964#L335-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 401959#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 401953#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 401949#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 401945#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 401941#L353-24 assume !(1 == ~t1_pc~0); 401937#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 401933#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 401929#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 401926#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 401923#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 401920#L372-24 assume !(1 == ~t2_pc~0); 401916#L372-26 is_transmit2_triggered_~__retres1~2#1 := 0; 401912#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 401909#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 401906#L865-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 401903#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 401899#L391-24 assume !(1 == ~t3_pc~0); 401896#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 401893#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 401890#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 401887#L873-24 assume !(0 != activate_threads_~tmp___2~0#1); 401884#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 401881#L410-24 assume !(1 == ~t4_pc~0); 401878#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 401875#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 401872#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 401869#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 401866#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 401863#L429-24 assume !(1 == ~t5_pc~0); 401860#L429-26 is_transmit5_triggered_~__retres1~5#1 := 0; 401855#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 401850#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 401845#L889-24 assume !(0 != activate_threads_~tmp___4~0#1); 401840#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 401836#L448-24 assume !(1 == ~t6_pc~0); 401832#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 401828#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 401824#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 401821#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 401818#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 401815#L762-3 assume !(1 == ~M_E~0); 401811#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 401809#L767-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 401807#L772-3 assume !(1 == ~T3_E~0); 401805#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 401802#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 401800#L787-3 assume !(1 == ~T6_E~0); 401798#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 401796#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 401794#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 401792#L807-3 assume 1 == ~E_3~0;~E_3~0 := 2; 401790#L812-3 assume !(1 == ~E_4~0); 401788#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 401786#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 401784#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 401778#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 401774#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 401772#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 401769#L1072 assume !(0 == start_simulation_~tmp~3#1); 401767#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 401765#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 401759#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 401758#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 401757#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 401756#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 401755#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 401754#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 394877#L1053-2 [2024-11-08 00:35:08,228 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:08,228 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 4 times [2024-11-08 00:35:08,228 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:08,228 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [726777021] [2024-11-08 00:35:08,228 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:08,229 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:08,239 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:35:08,243 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 00:35:08,251 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:35:08,264 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 00:35:08,265 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:08,265 INFO L85 PathProgramCache]: Analyzing trace with hash 422852940, now seen corresponding path program 1 times [2024-11-08 00:35:08,265 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:08,265 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2030899016] [2024-11-08 00:35:08,265 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:08,265 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:08,276 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:08,326 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:08,326 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:08,326 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2030899016] [2024-11-08 00:35:08,326 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2030899016] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:08,326 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:08,327 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-08 00:35:08,327 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2108595351] [2024-11-08 00:35:08,327 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:08,327 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:35:08,327 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:35:08,327 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-08 00:35:08,327 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-08 00:35:08,327 INFO L87 Difference]: Start difference. First operand 15869 states and 22023 transitions. cyclomatic complexity: 6170 Second operand has 5 states, 5 states have (on average 20.0) internal successors, (100), 5 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:08,501 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:35:08,501 INFO L93 Difference]: Finished difference Result 16205 states and 22262 transitions. [2024-11-08 00:35:08,501 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 16205 states and 22262 transitions. [2024-11-08 00:35:08,562 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 16000 [2024-11-08 00:35:08,598 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 16205 states to 16205 states and 22262 transitions. [2024-11-08 00:35:08,599 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16205 [2024-11-08 00:35:08,609 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 16205 [2024-11-08 00:35:08,610 INFO L73 IsDeterministic]: Start isDeterministic. Operand 16205 states and 22262 transitions. [2024-11-08 00:35:08,623 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:35:08,623 INFO L218 hiAutomatonCegarLoop]: Abstraction has 16205 states and 22262 transitions. [2024-11-08 00:35:08,634 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16205 states and 22262 transitions. [2024-11-08 00:35:08,828 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16205 to 16205. [2024-11-08 00:35:08,842 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16205 states, 16205 states have (on average 1.3737735266892934) internal successors, (22262), 16204 states have internal predecessors, (22262), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:08,861 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16205 states to 16205 states and 22262 transitions. [2024-11-08 00:35:08,861 INFO L240 hiAutomatonCegarLoop]: Abstraction has 16205 states and 22262 transitions. [2024-11-08 00:35:08,861 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-08 00:35:08,861 INFO L425 stractBuchiCegarLoop]: Abstraction has 16205 states and 22262 transitions. [2024-11-08 00:35:08,861 INFO L332 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2024-11-08 00:35:08,862 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 16205 states and 22262 transitions. [2024-11-08 00:35:08,899 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 16000 [2024-11-08 00:35:08,899 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:35:08,899 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:35:08,900 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:08,900 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:08,900 INFO L745 eck$LassoCheckResult]: Stem: 426618#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 426619#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 426750#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 426751#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 426400#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 426401#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 426748#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 426749#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 426678#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 426457#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 426458#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 426381#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 426382#L684 assume !(0 == ~M_E~0); 426875#L684-2 assume !(0 == ~T1_E~0); 426708#L689-1 assume !(0 == ~T2_E~0); 426709#L694-1 assume !(0 == ~T3_E~0); 426706#L699-1 assume !(0 == ~T4_E~0); 426707#L704-1 assume !(0 == ~T5_E~0); 426663#L709-1 assume !(0 == ~T6_E~0); 426600#L714-1 assume !(0 == ~E_M~0); 426601#L719-1 assume !(0 == ~E_1~0); 426842#L724-1 assume !(0 == ~E_2~0); 426354#L729-1 assume !(0 == ~E_3~0); 426355#L734-1 assume !(0 == ~E_4~0); 426918#L739-1 assume !(0 == ~E_5~0); 426556#L744-1 assume !(0 == ~E_6~0); 426557#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 426309#L334 assume !(1 == ~m_pc~0); 426310#L334-2 is_master_triggered_~__retres1~0#1 := 0; 426654#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 427018#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 426525#L849 assume !(0 != activate_threads_~tmp~1#1); 426526#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 426455#L353 assume !(1 == ~t1_pc~0); 426456#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 426754#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 426325#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 426326#L857 assume !(0 != activate_threads_~tmp___0~0#1); 426405#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 426406#L372 assume !(1 == ~t2_pc~0); 426512#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 426511#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 426649#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 426755#L865 assume !(0 != activate_threads_~tmp___1~0#1); 426298#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 426299#L391 assume !(1 == ~t3_pc~0); 426221#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 426222#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 426247#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 426248#L873 assume !(0 != activate_threads_~tmp___2~0#1); 426532#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 426533#L410 assume !(1 == ~t4_pc~0); 426768#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 426769#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 426419#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 426420#L881 assume !(0 != activate_threads_~tmp___3~0#1); 426538#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 426539#L429 assume !(1 == ~t5_pc~0); 426360#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 426361#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 426572#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 426573#L889 assume !(0 != activate_threads_~tmp___4~0#1); 426774#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 426522#L448 assume !(1 == ~t6_pc~0); 426438#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 426439#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 426740#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 426741#L897 assume !(0 != activate_threads_~tmp___5~0#1); 426949#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 426997#L762 assume !(1 == ~M_E~0); 426580#L762-2 assume !(1 == ~T1_E~0); 426581#L767-1 assume !(1 == ~T2_E~0); 426955#L772-1 assume !(1 == ~T3_E~0); 426803#L777-1 assume !(1 == ~T4_E~0); 426693#L782-1 assume !(1 == ~T5_E~0); 426387#L787-1 assume !(1 == ~T6_E~0); 426385#L792-1 assume !(1 == ~E_M~0); 426386#L797-1 assume !(1 == ~E_1~0); 426424#L802-1 assume !(1 == ~E_2~0); 426658#L807-1 assume !(1 == ~E_3~0); 426659#L812-1 assume !(1 == ~E_4~0); 426911#L817-1 assume !(1 == ~E_5~0); 426710#L822-1 assume !(1 == ~E_6~0); 426711#L827-1 assume { :end_inline_reset_delta_events } true; 426922#L1053-2 [2024-11-08 00:35:08,900 INFO L747 eck$LassoCheckResult]: Loop: 426922#L1053-2 assume !false; 433892#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 433888#L659-1 assume !false; 433887#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 433886#L518 assume !(0 == ~m_st~0); 433885#L522 assume !(0 == ~t1_st~0); 433884#L526 assume !(0 == ~t2_st~0); 433883#L530 assume !(0 == ~t3_st~0); 433882#L534 assume !(0 == ~t4_st~0); 433881#L538 assume !(0 == ~t5_st~0); 433879#L542 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 433877#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 433874#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 433871#L570 assume !(0 != eval_~tmp~0#1); 433868#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 433865#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 433863#L684-3 assume !(0 == ~M_E~0); 433861#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 433859#L689-3 assume !(0 == ~T2_E~0); 433857#L694-3 assume !(0 == ~T3_E~0); 433855#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 433853#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 433851#L709-3 assume !(0 == ~T6_E~0); 433849#L714-3 assume !(0 == ~E_M~0); 433846#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 433844#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 433842#L729-3 assume !(0 == ~E_3~0); 433840#L734-3 assume !(0 == ~E_4~0); 433838#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 433836#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 433834#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 433832#L334-24 assume !(1 == ~m_pc~0); 433830#L334-26 is_master_triggered_~__retres1~0#1 := 0; 433827#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 433824#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 433821#L849-24 assume !(0 != activate_threads_~tmp~1#1); 433818#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 433816#L353-24 assume !(1 == ~t1_pc~0); 433813#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 433809#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 433805#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 433799#L857-24 assume !(0 != activate_threads_~tmp___0~0#1); 433794#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 433790#L372-24 assume 1 == ~t2_pc~0; 433786#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 433780#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 433776#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 433772#L865-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 433767#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 433764#L391-24 assume !(1 == ~t3_pc~0); 433761#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 433757#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 433754#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 433749#L873-24 assume !(0 != activate_threads_~tmp___2~0#1); 433746#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 433743#L410-24 assume !(1 == ~t4_pc~0); 433739#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 433735#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 433731#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 433727#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 433725#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 433723#L429-24 assume 1 == ~t5_pc~0; 433720#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 433716#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 433712#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 433708#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 433705#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 433702#L448-24 assume !(1 == ~t6_pc~0); 433699#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 433695#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 433691#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 433686#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 433681#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 433677#L762-3 assume !(1 == ~M_E~0); 433446#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 433670#L767-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 433667#L772-3 assume !(1 == ~T3_E~0); 433666#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 433656#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 433652#L787-3 assume !(1 == ~T6_E~0); 433648#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 433642#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 433638#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 433633#L807-3 assume 1 == ~E_3~0;~E_3~0 := 2; 433626#L812-3 assume !(1 == ~E_4~0); 433620#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 433614#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 433611#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 433604#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 433599#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 433595#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 433590#L1072 assume !(0 == start_simulation_~tmp~3#1); 433591#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 433921#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 433914#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 433912#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 433910#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 433906#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 433904#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 433901#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 426922#L1053-2 [2024-11-08 00:35:08,900 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:08,900 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 5 times [2024-11-08 00:35:08,901 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:08,901 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1659217619] [2024-11-08 00:35:08,901 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:08,901 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:08,908 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:35:08,908 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 00:35:08,915 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:35:08,925 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 00:35:08,925 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:08,925 INFO L85 PathProgramCache]: Analyzing trace with hash 1995668301, now seen corresponding path program 1 times [2024-11-08 00:35:08,926 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:08,927 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [678606034] [2024-11-08 00:35:08,927 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:08,927 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:08,934 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:08,954 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:08,955 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:08,955 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [678606034] [2024-11-08 00:35:08,955 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [678606034] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:08,955 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:08,955 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:08,955 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [756480518] [2024-11-08 00:35:08,955 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:08,955 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:35:08,955 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:35:08,955 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:35:08,955 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:35:08,955 INFO L87 Difference]: Start difference. First operand 16205 states and 22262 transitions. cyclomatic complexity: 6073 Second operand has 3 states, 3 states have (on average 33.333333333333336) internal successors, (100), 3 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:09,039 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:35:09,039 INFO L93 Difference]: Finished difference Result 30301 states and 41054 transitions. [2024-11-08 00:35:09,040 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 30301 states and 41054 transitions. [2024-11-08 00:35:09,151 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 29984 [2024-11-08 00:35:09,221 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 30301 states to 30301 states and 41054 transitions. [2024-11-08 00:35:09,222 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 30301 [2024-11-08 00:35:09,242 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 30301 [2024-11-08 00:35:09,242 INFO L73 IsDeterministic]: Start isDeterministic. Operand 30301 states and 41054 transitions. [2024-11-08 00:35:09,262 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:35:09,262 INFO L218 hiAutomatonCegarLoop]: Abstraction has 30301 states and 41054 transitions. [2024-11-08 00:35:09,280 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30301 states and 41054 transitions. [2024-11-08 00:35:09,634 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30301 to 28813. [2024-11-08 00:35:09,657 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 28813 states, 28813 states have (on average 1.358761670079478) internal successors, (39150), 28812 states have internal predecessors, (39150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:09,700 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28813 states to 28813 states and 39150 transitions. [2024-11-08 00:35:09,700 INFO L240 hiAutomatonCegarLoop]: Abstraction has 28813 states and 39150 transitions. [2024-11-08 00:35:09,701 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:35:09,701 INFO L425 stractBuchiCegarLoop]: Abstraction has 28813 states and 39150 transitions. [2024-11-08 00:35:09,701 INFO L332 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2024-11-08 00:35:09,701 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 28813 states and 39150 transitions. [2024-11-08 00:35:09,771 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 28496 [2024-11-08 00:35:09,771 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:35:09,771 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:35:09,773 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:09,773 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:09,773 INFO L745 eck$LassoCheckResult]: Stem: 473134#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 473135#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 473277#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 473278#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 472915#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 472916#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 473273#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 473274#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 473195#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 472976#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 472977#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 472895#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 472896#L684 assume !(0 == ~M_E~0); 473411#L684-2 assume !(0 == ~T1_E~0); 473229#L689-1 assume !(0 == ~T2_E~0); 473230#L694-1 assume !(0 == ~T3_E~0); 473227#L699-1 assume !(0 == ~T4_E~0); 473228#L704-1 assume !(0 == ~T5_E~0); 473181#L709-1 assume !(0 == ~T6_E~0); 473110#L714-1 assume !(0 == ~E_M~0); 473111#L719-1 assume !(0 == ~E_1~0); 473374#L724-1 assume !(0 == ~E_2~0); 472864#L729-1 assume !(0 == ~E_3~0); 472865#L734-1 assume !(0 == ~E_4~0); 473451#L739-1 assume !(0 == ~E_5~0); 473069#L744-1 assume !(0 == ~E_6~0); 473070#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 472819#L334 assume !(1 == ~m_pc~0); 472820#L334-2 is_master_triggered_~__retres1~0#1 := 0; 473169#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 473579#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 473040#L849 assume !(0 != activate_threads_~tmp~1#1); 473041#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 472972#L353 assume !(1 == ~t1_pc~0); 472973#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 473280#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 472835#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 472836#L857 assume !(0 != activate_threads_~tmp___0~0#1); 472917#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 472918#L372 assume !(1 == ~t2_pc~0); 473028#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 473027#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 473162#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 473281#L865 assume !(0 != activate_threads_~tmp___1~0#1); 472808#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 472809#L391 assume !(1 == ~t3_pc~0); 472733#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 472734#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 472758#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 472759#L873 assume !(0 != activate_threads_~tmp___2~0#1); 473047#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 473048#L410 assume !(1 == ~t4_pc~0); 473293#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 473294#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 472931#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 472932#L881 assume !(0 != activate_threads_~tmp___3~0#1); 473055#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 473056#L429 assume !(1 == ~t5_pc~0); 472870#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 472871#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 473084#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 473085#L889 assume !(0 != activate_threads_~tmp___4~0#1); 473300#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 473039#L448 assume !(1 == ~t6_pc~0); 472954#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 472955#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 473265#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 473266#L897 assume !(0 != activate_threads_~tmp___5~0#1); 473486#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 473550#L762 assume !(1 == ~M_E~0); 473091#L762-2 assume !(1 == ~T1_E~0); 473092#L767-1 assume !(1 == ~T2_E~0); 473491#L772-1 assume !(1 == ~T3_E~0); 473332#L777-1 assume !(1 == ~T4_E~0); 473212#L782-1 assume !(1 == ~T5_E~0); 472899#L787-1 assume !(1 == ~T6_E~0); 472897#L792-1 assume !(1 == ~E_M~0); 472898#L797-1 assume !(1 == ~E_1~0); 472938#L802-1 assume !(1 == ~E_2~0); 473173#L807-1 assume !(1 == ~E_3~0); 473174#L812-1 assume !(1 == ~E_4~0); 473448#L817-1 assume !(1 == ~E_5~0); 473231#L822-1 assume !(1 == ~E_6~0); 473232#L827-1 assume { :end_inline_reset_delta_events } true; 473459#L1053-2 [2024-11-08 00:35:09,773 INFO L747 eck$LassoCheckResult]: Loop: 473459#L1053-2 assume !false; 478510#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 478505#L659-1 assume !false; 478503#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 478499#L518 assume !(0 == ~m_st~0); 478500#L522 assume !(0 == ~t1_st~0); 479045#L526 assume !(0 == ~t2_st~0); 479043#L530 assume !(0 == ~t3_st~0); 479041#L534 assume !(0 == ~t4_st~0); 479039#L538 assume !(0 == ~t5_st~0); 479036#L542 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 479032#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 479030#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 479028#L570 assume !(0 != eval_~tmp~0#1); 479026#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 479023#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 479021#L684-3 assume !(0 == ~M_E~0); 479019#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 479017#L689-3 assume !(0 == ~T2_E~0); 479015#L694-3 assume !(0 == ~T3_E~0); 479013#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 479011#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 479009#L709-3 assume !(0 == ~T6_E~0); 479005#L714-3 assume !(0 == ~E_M~0); 479003#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 479002#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 479001#L729-3 assume !(0 == ~E_3~0); 479000#L734-3 assume !(0 == ~E_4~0); 478999#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 478996#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 478994#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 478992#L334-24 assume 1 == ~m_pc~0; 478988#L335-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 478986#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 478984#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 478982#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 478981#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 478979#L353-24 assume !(1 == ~t1_pc~0); 478976#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 478973#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 478970#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 478967#L857-24 assume !(0 != activate_threads_~tmp___0~0#1); 478963#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 478961#L372-24 assume 1 == ~t2_pc~0; 478957#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 478950#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 478945#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 478941#L865-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 478934#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 478930#L391-24 assume !(1 == ~t3_pc~0); 478926#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 478922#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 478918#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 478913#L873-24 assume !(0 != activate_threads_~tmp___2~0#1); 478908#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 478742#L410-24 assume !(1 == ~t4_pc~0); 478739#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 478737#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 478735#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 478733#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 478731#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 478729#L429-24 assume 1 == ~t5_pc~0; 478727#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 478728#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 478814#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 478714#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 478712#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 478710#L448-24 assume !(1 == ~t6_pc~0); 478707#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 478706#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 478704#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 478701#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 478699#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 478697#L762-3 assume !(1 == ~M_E~0); 477417#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 478694#L767-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 478692#L772-3 assume !(1 == ~T3_E~0); 478690#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 478688#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 478686#L787-3 assume !(1 == ~T6_E~0); 478684#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 478682#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 478680#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 478679#L807-3 assume 1 == ~E_3~0;~E_3~0 := 2; 478678#L812-3 assume !(1 == ~E_4~0); 478676#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 478673#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 478671#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 478668#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 478666#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 478664#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 478662#L1072 assume !(0 == start_simulation_~tmp~3#1); 478659#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 478656#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 478654#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 478652#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 478650#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 478648#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 478646#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 478644#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 473459#L1053-2 [2024-11-08 00:35:09,773 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:09,774 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 6 times [2024-11-08 00:35:09,774 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:09,774 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [713683350] [2024-11-08 00:35:09,774 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:09,774 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:09,783 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:35:09,783 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 00:35:09,788 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:35:09,794 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 00:35:09,795 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:09,795 INFO L85 PathProgramCache]: Analyzing trace with hash -1750748022, now seen corresponding path program 1 times [2024-11-08 00:35:09,795 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:09,795 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1487561426] [2024-11-08 00:35:09,795 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:09,795 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:09,805 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:09,858 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:09,858 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:09,858 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1487561426] [2024-11-08 00:35:09,858 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1487561426] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:09,858 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:09,858 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-08 00:35:09,859 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [623817956] [2024-11-08 00:35:09,859 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:09,859 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:35:09,862 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:35:09,862 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-08 00:35:09,862 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-08 00:35:09,863 INFO L87 Difference]: Start difference. First operand 28813 states and 39150 transitions. cyclomatic complexity: 10353 Second operand has 5 states, 5 states have (on average 20.0) internal successors, (100), 5 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:10,094 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:35:10,095 INFO L93 Difference]: Finished difference Result 28861 states and 38829 transitions. [2024-11-08 00:35:10,095 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 28861 states and 38829 transitions. [2024-11-08 00:35:10,333 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 28544 [2024-11-08 00:35:10,389 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 28861 states to 28861 states and 38829 transitions. [2024-11-08 00:35:10,389 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 28861 [2024-11-08 00:35:10,406 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 28861 [2024-11-08 00:35:10,407 INFO L73 IsDeterministic]: Start isDeterministic. Operand 28861 states and 38829 transitions. [2024-11-08 00:35:10,426 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:35:10,427 INFO L218 hiAutomatonCegarLoop]: Abstraction has 28861 states and 38829 transitions. [2024-11-08 00:35:10,443 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28861 states and 38829 transitions. [2024-11-08 00:35:10,593 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28861 to 28861. [2024-11-08 00:35:10,615 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 28861 states, 28861 states have (on average 1.345379577977201) internal successors, (38829), 28860 states have internal predecessors, (38829), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:10,651 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28861 states to 28861 states and 38829 transitions. [2024-11-08 00:35:10,651 INFO L240 hiAutomatonCegarLoop]: Abstraction has 28861 states and 38829 transitions. [2024-11-08 00:35:10,652 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-08 00:35:10,652 INFO L425 stractBuchiCegarLoop]: Abstraction has 28861 states and 38829 transitions. [2024-11-08 00:35:10,652 INFO L332 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2024-11-08 00:35:10,652 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 28861 states and 38829 transitions. [2024-11-08 00:35:10,830 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 28544 [2024-11-08 00:35:10,830 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:35:10,830 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:35:10,831 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:10,831 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:10,831 INFO L745 eck$LassoCheckResult]: Stem: 530816#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 530817#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 530963#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 530964#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 530593#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 530594#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 530959#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 530960#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 530885#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 530652#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 530653#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 530573#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 530574#L684 assume !(0 == ~M_E~0); 531091#L684-2 assume !(0 == ~T1_E~0); 530915#L689-1 assume !(0 == ~T2_E~0); 530916#L694-1 assume !(0 == ~T3_E~0); 530913#L699-1 assume !(0 == ~T4_E~0); 530914#L704-1 assume !(0 == ~T5_E~0); 530866#L709-1 assume !(0 == ~T6_E~0); 530795#L714-1 assume !(0 == ~E_M~0); 530796#L719-1 assume !(0 == ~E_1~0); 531055#L724-1 assume !(0 == ~E_2~0); 530546#L729-1 assume !(0 == ~E_3~0); 530547#L734-1 assume !(0 == ~E_4~0); 531133#L739-1 assume !(0 == ~E_5~0); 530753#L744-1 assume !(0 == ~E_6~0); 530754#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 530502#L334 assume !(1 == ~m_pc~0); 530503#L334-2 is_master_triggered_~__retres1~0#1 := 0; 530857#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 531252#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 530723#L849 assume !(0 != activate_threads_~tmp~1#1); 530724#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 530650#L353 assume !(1 == ~t1_pc~0); 530651#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 530966#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 530517#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 530518#L857 assume !(0 != activate_threads_~tmp___0~0#1); 530595#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 530596#L372 assume !(1 == ~t2_pc~0); 530710#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 530709#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 530852#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 530967#L865 assume !(0 != activate_threads_~tmp___1~0#1); 530491#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 530492#L391 assume !(1 == ~t3_pc~0); 530415#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 530416#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 530440#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 530441#L873 assume !(0 != activate_threads_~tmp___2~0#1); 530730#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 530731#L410 assume !(1 == ~t4_pc~0); 530983#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 530984#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 530610#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 530611#L881 assume !(0 != activate_threads_~tmp___3~0#1); 530737#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 530738#L429 assume !(1 == ~t5_pc~0); 530552#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 530553#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 530768#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 530769#L889 assume !(0 != activate_threads_~tmp___4~0#1); 530988#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 530720#L448 assume !(1 == ~t6_pc~0); 530632#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 530633#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 530951#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 530952#L897 assume !(0 != activate_threads_~tmp___5~0#1); 531165#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 531227#L762 assume !(1 == ~M_E~0); 530776#L762-2 assume !(1 == ~T1_E~0); 530777#L767-1 assume !(1 == ~T2_E~0); 531174#L772-1 assume !(1 == ~T3_E~0); 531022#L777-1 assume !(1 == ~T4_E~0); 530900#L782-1 assume !(1 == ~T5_E~0); 530577#L787-1 assume !(1 == ~T6_E~0); 530575#L792-1 assume !(1 == ~E_M~0); 530576#L797-1 assume !(1 == ~E_1~0); 530616#L802-1 assume !(1 == ~E_2~0); 530861#L807-1 assume !(1 == ~E_3~0); 530862#L812-1 assume !(1 == ~E_4~0); 531126#L817-1 assume !(1 == ~E_5~0); 530917#L822-1 assume !(1 == ~E_6~0); 530918#L827-1 assume { :end_inline_reset_delta_events } true; 531140#L1053-2 [2024-11-08 00:35:10,832 INFO L747 eck$LassoCheckResult]: Loop: 531140#L1053-2 assume !false; 538926#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 538921#L659-1 assume !false; 538919#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 538916#L518 assume !(0 == ~m_st~0); 538917#L522 assume !(0 == ~t1_st~0); 539154#L526 assume !(0 == ~t2_st~0); 539152#L530 assume !(0 == ~t3_st~0); 539150#L534 assume !(0 == ~t4_st~0); 539148#L538 assume !(0 == ~t5_st~0); 539145#L542 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 539143#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 539141#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 539139#L570 assume !(0 != eval_~tmp~0#1); 539137#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 539134#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 539132#L684-3 assume !(0 == ~M_E~0); 539130#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 539127#L689-3 assume !(0 == ~T2_E~0); 539125#L694-3 assume !(0 == ~T3_E~0); 539123#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 539121#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 539119#L709-3 assume !(0 == ~T6_E~0); 539117#L714-3 assume !(0 == ~E_M~0); 539115#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 539113#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 539111#L729-3 assume !(0 == ~E_3~0); 539108#L734-3 assume !(0 == ~E_4~0); 539106#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 539104#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 539102#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 539100#L334-24 assume 1 == ~m_pc~0; 539097#L335-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 539095#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 539093#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 539090#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 539088#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 539086#L353-24 assume !(1 == ~t1_pc~0); 539084#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 539082#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 539080#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 539078#L857-24 assume !(0 != activate_threads_~tmp___0~0#1); 539076#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 539074#L372-24 assume !(1 == ~t2_pc~0); 539069#L372-26 is_transmit2_triggered_~__retres1~2#1 := 0; 539067#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 539065#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 539063#L865-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 539060#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 539058#L391-24 assume !(1 == ~t3_pc~0); 539056#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 539053#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 539051#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 539049#L873-24 assume !(0 != activate_threads_~tmp___2~0#1); 539047#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 539045#L410-24 assume !(1 == ~t4_pc~0); 539041#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 539039#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 539037#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 539035#L881-24 assume !(0 != activate_threads_~tmp___3~0#1); 539033#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 539031#L429-24 assume !(1 == ~t5_pc~0); 539027#L429-26 is_transmit5_triggered_~__retres1~5#1 := 0; 539025#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 539023#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 539021#L889-24 assume !(0 != activate_threads_~tmp___4~0#1); 539018#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 539016#L448-24 assume !(1 == ~t6_pc~0); 539014#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 539012#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 539010#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 539007#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 539005#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 539003#L762-3 assume !(1 == ~M_E~0); 538997#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 538995#L767-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 538992#L772-3 assume !(1 == ~T3_E~0); 538990#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 538988#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 538986#L787-3 assume !(1 == ~T6_E~0); 538984#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 538982#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 538980#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 538978#L807-3 assume 1 == ~E_3~0;~E_3~0 := 2; 538973#L812-3 assume !(1 == ~E_4~0); 538971#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 538969#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 538966#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 538963#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 538961#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 538959#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 538955#L1072 assume !(0 == start_simulation_~tmp~3#1); 538951#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 538948#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 538944#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 538940#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 538939#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 538937#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 538933#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 538930#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 531140#L1053-2 [2024-11-08 00:35:10,832 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:10,832 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 7 times [2024-11-08 00:35:10,832 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:10,832 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1383079333] [2024-11-08 00:35:10,832 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:10,832 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:10,839 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:35:10,840 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 00:35:10,844 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:35:10,853 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 00:35:10,853 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:10,853 INFO L85 PathProgramCache]: Analyzing trace with hash 1407199440, now seen corresponding path program 1 times [2024-11-08 00:35:10,853 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:10,854 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [264567123] [2024-11-08 00:35:10,854 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:10,854 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:10,864 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:10,911 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:10,911 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:10,911 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [264567123] [2024-11-08 00:35:10,912 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [264567123] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:10,912 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:10,912 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-08 00:35:10,912 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1728035852] [2024-11-08 00:35:10,912 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:10,912 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:35:10,912 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:35:10,912 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-08 00:35:10,912 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-08 00:35:10,913 INFO L87 Difference]: Start difference. First operand 28861 states and 38829 transitions. cyclomatic complexity: 9984 Second operand has 5 states, 5 states have (on average 20.0) internal successors, (100), 5 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:11,123 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:35:11,124 INFO L93 Difference]: Finished difference Result 30016 states and 39984 transitions. [2024-11-08 00:35:11,124 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 30016 states and 39984 transitions. [2024-11-08 00:35:11,238 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 29696 [2024-11-08 00:35:11,308 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 30016 states to 30016 states and 39984 transitions. [2024-11-08 00:35:11,308 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 30016 [2024-11-08 00:35:11,328 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 30016 [2024-11-08 00:35:11,328 INFO L73 IsDeterministic]: Start isDeterministic. Operand 30016 states and 39984 transitions. [2024-11-08 00:35:11,347 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:35:11,347 INFO L218 hiAutomatonCegarLoop]: Abstraction has 30016 states and 39984 transitions. [2024-11-08 00:35:11,363 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30016 states and 39984 transitions. [2024-11-08 00:35:11,576 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30016 to 30016. [2024-11-08 00:35:11,601 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 30016 states, 30016 states have (on average 1.3320895522388059) internal successors, (39984), 30015 states have internal predecessors, (39984), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:11,647 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 30016 states to 30016 states and 39984 transitions. [2024-11-08 00:35:11,648 INFO L240 hiAutomatonCegarLoop]: Abstraction has 30016 states and 39984 transitions. [2024-11-08 00:35:11,648 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-08 00:35:11,648 INFO L425 stractBuchiCegarLoop]: Abstraction has 30016 states and 39984 transitions. [2024-11-08 00:35:11,648 INFO L332 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2024-11-08 00:35:11,648 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 30016 states and 39984 transitions. [2024-11-08 00:35:11,809 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 29696 [2024-11-08 00:35:11,809 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:35:11,809 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:35:11,810 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:11,810 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:11,811 INFO L745 eck$LassoCheckResult]: Stem: 589701#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 589702#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 589843#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 589844#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 589477#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 589478#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 589841#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 589842#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 589768#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 589539#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 589540#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 589458#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 589459#L684 assume !(0 == ~M_E~0); 589977#L684-2 assume !(0 == ~T1_E~0); 589798#L689-1 assume !(0 == ~T2_E~0); 589799#L694-1 assume !(0 == ~T3_E~0); 589796#L699-1 assume !(0 == ~T4_E~0); 589797#L704-1 assume !(0 == ~T5_E~0); 589751#L709-1 assume !(0 == ~T6_E~0); 589682#L714-1 assume !(0 == ~E_M~0); 589683#L719-1 assume !(0 == ~E_1~0); 589945#L724-1 assume !(0 == ~E_2~0); 589431#L729-1 assume !(0 == ~E_3~0); 589432#L734-1 assume !(0 == ~E_4~0); 590017#L739-1 assume !(0 == ~E_5~0); 589640#L744-1 assume !(0 == ~E_6~0); 589641#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 589387#L334 assume !(1 == ~m_pc~0); 589388#L334-2 is_master_triggered_~__retres1~0#1 := 0; 589743#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 590112#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 589609#L849 assume !(0 != activate_threads_~tmp~1#1); 589610#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 589537#L353 assume !(1 == ~t1_pc~0); 589538#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 589848#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 589402#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 589403#L857 assume !(0 != activate_threads_~tmp___0~0#1); 589482#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 589483#L372 assume !(1 == ~t2_pc~0); 589596#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 589620#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 589849#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 589850#L865 assume !(0 != activate_threads_~tmp___1~0#1); 589376#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 589377#L391 assume !(1 == ~t3_pc~0); 589300#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 589301#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 589326#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 589327#L873 assume !(0 != activate_threads_~tmp___2~0#1); 589616#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 589617#L410 assume !(1 == ~t4_pc~0); 589863#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 589864#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 589497#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 589498#L881 assume !(0 != activate_threads_~tmp___3~0#1); 589622#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 589623#L429 assume !(1 == ~t5_pc~0); 589437#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 589438#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 589656#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 589657#L889 assume !(0 != activate_threads_~tmp___4~0#1); 589869#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 589606#L448 assume !(1 == ~t6_pc~0); 589520#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 589521#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 589831#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 589832#L897 assume !(0 != activate_threads_~tmp___5~0#1); 590047#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 590094#L762 assume !(1 == ~M_E~0); 589662#L762-2 assume !(1 == ~T1_E~0); 589663#L767-1 assume !(1 == ~T2_E~0); 590054#L772-1 assume !(1 == ~T3_E~0); 589907#L777-1 assume !(1 == ~T4_E~0); 589783#L782-1 assume !(1 == ~T5_E~0); 589464#L787-1 assume !(1 == ~T6_E~0); 589462#L792-1 assume !(1 == ~E_M~0); 589463#L797-1 assume !(1 == ~E_1~0); 589502#L802-1 assume !(1 == ~E_2~0); 589747#L807-1 assume !(1 == ~E_3~0); 589748#L812-1 assume !(1 == ~E_4~0); 590010#L817-1 assume !(1 == ~E_5~0); 589800#L822-1 assume !(1 == ~E_6~0); 589801#L827-1 assume { :end_inline_reset_delta_events } true; 590025#L1053-2 [2024-11-08 00:35:11,811 INFO L747 eck$LassoCheckResult]: Loop: 590025#L1053-2 assume !false; 601678#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 601636#L659-1 assume !false; 601675#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 601673#L518 assume !(0 == ~m_st~0); 596298#L522 assume !(0 == ~t1_st~0); 596297#L526 assume !(0 == ~t2_st~0); 596296#L530 assume !(0 == ~t3_st~0); 596295#L534 assume !(0 == ~t4_st~0); 596294#L538 assume !(0 == ~t5_st~0); 596292#L542 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 596291#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 596289#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 596287#L570 assume !(0 != eval_~tmp~0#1); 596286#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 596285#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 596283#L684-3 assume !(0 == ~M_E~0); 596279#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 596277#L689-3 assume !(0 == ~T2_E~0); 596275#L694-3 assume !(0 == ~T3_E~0); 596273#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 596270#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 596268#L709-3 assume !(0 == ~T6_E~0); 596266#L714-3 assume !(0 == ~E_M~0); 596264#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 596262#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 596260#L729-3 assume !(0 == ~E_3~0); 596258#L734-3 assume !(0 == ~E_4~0); 596256#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 596253#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 596251#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 596249#L334-24 assume 1 == ~m_pc~0; 596246#L335-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 596244#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 596242#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 596239#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 596237#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 596235#L353-24 assume !(1 == ~t1_pc~0); 596233#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 596231#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 596229#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 596227#L857-24 assume !(0 != activate_threads_~tmp___0~0#1); 596225#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 596223#L372-24 assume !(1 == ~t2_pc~0); 596219#L372-26 is_transmit2_triggered_~__retres1~2#1 := 0; 596218#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 596217#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 596211#L865-24 assume !(0 != activate_threads_~tmp___1~0#1); 596208#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 596206#L391-24 assume !(1 == ~t3_pc~0); 596202#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 596200#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 596198#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 596192#L873-24 assume !(0 != activate_threads_~tmp___2~0#1); 596190#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 596188#L410-24 assume !(1 == ~t4_pc~0); 596186#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 596184#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 596182#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 596180#L881-24 assume !(0 != activate_threads_~tmp___3~0#1); 596178#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 596173#L429-24 assume !(1 == ~t5_pc~0); 596169#L429-26 is_transmit5_triggered_~__retres1~5#1 := 0; 596167#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 596165#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 596164#L889-24 assume !(0 != activate_threads_~tmp___4~0#1); 596161#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 596159#L448-24 assume !(1 == ~t6_pc~0); 596157#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 596155#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 596152#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 596150#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 596148#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 596146#L762-3 assume !(1 == ~M_E~0); 596008#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 596143#L767-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 596141#L772-3 assume !(1 == ~T3_E~0); 596139#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 596137#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 596135#L787-3 assume !(1 == ~T6_E~0); 596133#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 596131#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 596129#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 596127#L807-3 assume 1 == ~E_3~0;~E_3~0 := 2; 596125#L812-3 assume !(1 == ~E_4~0); 596123#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 596121#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 596119#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 596116#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 596114#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 596112#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 596109#L1072 assume !(0 == start_simulation_~tmp~3#1); 596110#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 608155#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 608153#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 608151#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 608150#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 608149#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 608148#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 608147#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 590025#L1053-2 [2024-11-08 00:35:11,811 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:11,811 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 8 times [2024-11-08 00:35:11,811 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:11,811 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [184320300] [2024-11-08 00:35:11,812 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:11,812 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:11,818 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:35:11,819 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 00:35:11,822 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:35:11,827 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 00:35:11,828 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:11,828 INFO L85 PathProgramCache]: Analyzing trace with hash 1851100114, now seen corresponding path program 1 times [2024-11-08 00:35:11,828 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:11,828 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [435310687] [2024-11-08 00:35:11,828 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:11,828 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:11,836 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:11,869 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:11,870 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:11,870 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [435310687] [2024-11-08 00:35:11,870 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [435310687] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:11,870 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:11,870 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-08 00:35:11,870 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1695459544] [2024-11-08 00:35:11,870 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:11,871 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:35:11,871 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:35:11,871 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-08 00:35:11,871 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-08 00:35:11,871 INFO L87 Difference]: Start difference. First operand 30016 states and 39984 transitions. cyclomatic complexity: 9984 Second operand has 5 states, 5 states have (on average 20.0) internal successors, (100), 5 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:12,054 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:35:12,054 INFO L93 Difference]: Finished difference Result 30640 states and 40431 transitions. [2024-11-08 00:35:12,054 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 30640 states and 40431 transitions. [2024-11-08 00:35:12,155 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 30320 [2024-11-08 00:35:12,217 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 30640 states to 30640 states and 40431 transitions. [2024-11-08 00:35:12,218 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 30640 [2024-11-08 00:35:12,238 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 30640 [2024-11-08 00:35:12,239 INFO L73 IsDeterministic]: Start isDeterministic. Operand 30640 states and 40431 transitions. [2024-11-08 00:35:12,257 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:35:12,257 INFO L218 hiAutomatonCegarLoop]: Abstraction has 30640 states and 40431 transitions. [2024-11-08 00:35:12,271 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30640 states and 40431 transitions. [2024-11-08 00:35:12,416 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30640 to 30640. [2024-11-08 00:35:12,441 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 30640 states, 30640 states have (on average 1.3195496083550913) internal successors, (40431), 30639 states have internal predecessors, (40431), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:12,854 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 30640 states to 30640 states and 40431 transitions. [2024-11-08 00:35:12,854 INFO L240 hiAutomatonCegarLoop]: Abstraction has 30640 states and 40431 transitions. [2024-11-08 00:35:12,855 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-08 00:35:12,855 INFO L425 stractBuchiCegarLoop]: Abstraction has 30640 states and 40431 transitions. [2024-11-08 00:35:12,855 INFO L332 stractBuchiCegarLoop]: ======== Iteration 27 ============ [2024-11-08 00:35:12,855 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 30640 states and 40431 transitions. [2024-11-08 00:35:12,920 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 30320 [2024-11-08 00:35:12,921 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:35:12,921 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:35:12,922 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:12,922 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:12,922 INFO L745 eck$LassoCheckResult]: Stem: 650365#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 650366#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 650519#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 650520#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 650140#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 650141#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 650517#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 650518#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 650437#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 650204#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 650205#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 650121#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 650122#L684 assume !(0 == ~M_E~0); 650663#L684-2 assume !(0 == ~T1_E~0); 650472#L689-1 assume !(0 == ~T2_E~0); 650473#L694-1 assume !(0 == ~T3_E~0); 650470#L699-1 assume !(0 == ~T4_E~0); 650471#L704-1 assume !(0 == ~T5_E~0); 650419#L709-1 assume !(0 == ~T6_E~0); 650346#L714-1 assume !(0 == ~E_M~0); 650347#L719-1 assume !(0 == ~E_1~0); 650626#L724-1 assume !(0 == ~E_2~0); 650095#L729-1 assume !(0 == ~E_3~0); 650096#L734-1 assume !(0 == ~E_4~0); 650702#L739-1 assume !(0 == ~E_5~0); 650306#L744-1 assume !(0 == ~E_6~0); 650307#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 650051#L334 assume !(1 == ~m_pc~0); 650052#L334-2 is_master_triggered_~__retres1~0#1 := 0; 650410#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 650815#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 650276#L849 assume !(0 != activate_threads_~tmp~1#1); 650277#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 650202#L353 assume !(1 == ~t1_pc~0); 650203#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 650523#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 650066#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 650067#L857 assume !(0 != activate_threads_~tmp___0~0#1); 650145#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 650146#L372 assume !(1 == ~t2_pc~0); 650263#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 650287#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 650524#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 650525#L865 assume !(0 != activate_threads_~tmp___1~0#1); 650040#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 650041#L391 assume !(1 == ~t3_pc~0); 649964#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 649965#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 649989#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 649990#L873 assume !(0 != activate_threads_~tmp___2~0#1); 650283#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 650284#L410 assume !(1 == ~t4_pc~0); 650539#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 650540#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 650162#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 650163#L881 assume !(0 != activate_threads_~tmp___3~0#1); 650289#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 650290#L429 assume !(1 == ~t5_pc~0); 650101#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 650102#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 650322#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 650323#L889 assume !(0 != activate_threads_~tmp___4~0#1); 650547#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 650273#L448 assume !(1 == ~t6_pc~0); 650183#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 650184#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 650506#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 650507#L897 assume !(0 != activate_threads_~tmp___5~0#1); 650735#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 650797#L762 assume !(1 == ~M_E~0); 650326#L762-2 assume !(1 == ~T1_E~0); 650327#L767-1 assume !(1 == ~T2_E~0); 650741#L772-1 assume !(1 == ~T3_E~0); 650583#L777-1 assume !(1 == ~T4_E~0); 650454#L782-1 assume !(1 == ~T5_E~0); 650127#L787-1 assume !(1 == ~T6_E~0); 650125#L792-1 assume !(1 == ~E_M~0); 650126#L797-1 assume !(1 == ~E_1~0); 650167#L802-1 assume !(1 == ~E_2~0); 650414#L807-1 assume !(1 == ~E_3~0); 650415#L812-1 assume !(1 == ~E_4~0); 650697#L817-1 assume !(1 == ~E_5~0); 650474#L822-1 assume !(1 == ~E_6~0); 650475#L827-1 assume { :end_inline_reset_delta_events } true; 650709#L1053-2 [2024-11-08 00:35:12,922 INFO L747 eck$LassoCheckResult]: Loop: 650709#L1053-2 assume !false; 673154#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 673149#L659-1 assume !false; 673147#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 673145#L518 assume !(0 == ~m_st~0); 663638#L522 assume !(0 == ~t1_st~0); 663636#L526 assume !(0 == ~t2_st~0); 663635#L530 assume !(0 == ~t3_st~0); 663634#L534 assume !(0 == ~t4_st~0); 663633#L538 assume !(0 == ~t5_st~0); 663630#L542 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 663629#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 663628#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 663626#L570 assume !(0 != eval_~tmp~0#1); 663624#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 663623#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 663622#L684-3 assume !(0 == ~M_E~0); 663621#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 663619#L689-3 assume !(0 == ~T2_E~0); 663618#L694-3 assume !(0 == ~T3_E~0); 663617#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 663616#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 663614#L709-3 assume !(0 == ~T6_E~0); 663612#L714-3 assume !(0 == ~E_M~0); 663610#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 663609#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 663607#L729-3 assume !(0 == ~E_3~0); 663605#L734-3 assume !(0 == ~E_4~0); 663603#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 663601#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 663599#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 663597#L334-24 assume 1 == ~m_pc~0; 663592#L335-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 663590#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 663588#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 663585#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 663582#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 663580#L353-24 assume !(1 == ~t1_pc~0); 663578#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 663576#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 663574#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 663572#L857-24 assume !(0 != activate_threads_~tmp___0~0#1); 663570#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 663568#L372-24 assume 1 == ~t2_pc~0; 663566#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 663567#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 663625#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 663557#L865-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 663555#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 663553#L391-24 assume !(1 == ~t3_pc~0); 663549#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 663547#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 663545#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 663543#L873-24 assume !(0 != activate_threads_~tmp___2~0#1); 663540#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 663538#L410-24 assume !(1 == ~t4_pc~0); 663536#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 663534#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 663532#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 663530#L881-24 assume !(0 != activate_threads_~tmp___3~0#1); 663528#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 663526#L429-24 assume !(1 == ~t5_pc~0); 663520#L429-26 is_transmit5_triggered_~__retres1~5#1 := 0; 663518#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 663516#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 663514#L889-24 assume !(0 != activate_threads_~tmp___4~0#1); 663511#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 663509#L448-24 assume !(1 == ~t6_pc~0); 663507#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 663505#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 663503#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 663501#L897-24 assume !(0 != activate_threads_~tmp___5~0#1); 663499#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 663497#L762-3 assume !(1 == ~M_E~0); 662907#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 663494#L767-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 663492#L772-3 assume !(1 == ~T3_E~0); 663490#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 663489#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 663488#L787-3 assume !(1 == ~T6_E~0); 663482#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 663480#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 663478#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 663475#L807-3 assume 1 == ~E_3~0;~E_3~0 := 2; 663474#L812-3 assume !(1 == ~E_4~0); 663472#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 663469#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 663467#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 663464#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 663463#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 663462#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 663459#L1072 assume !(0 == start_simulation_~tmp~3#1); 663460#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 673170#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 673168#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 673166#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 673164#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 673161#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 673159#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 673157#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 650709#L1053-2 [2024-11-08 00:35:12,923 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:12,923 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 9 times [2024-11-08 00:35:12,923 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:12,923 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1425860945] [2024-11-08 00:35:12,923 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:12,923 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:12,932 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:35:12,932 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 00:35:12,936 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:35:12,949 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 00:35:12,949 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:12,950 INFO L85 PathProgramCache]: Analyzing trace with hash -1741831791, now seen corresponding path program 1 times [2024-11-08 00:35:12,951 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:12,951 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1719756497] [2024-11-08 00:35:12,951 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:12,951 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:12,961 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:35:12,961 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 00:35:12,965 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:35:12,975 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 00:35:12,975 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:12,975 INFO L85 PathProgramCache]: Analyzing trace with hash 1849523801, now seen corresponding path program 1 times [2024-11-08 00:35:12,976 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:12,976 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1172079434] [2024-11-08 00:35:12,976 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:12,976 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:12,986 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:13,014 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:13,014 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:13,014 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1172079434] [2024-11-08 00:35:13,014 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1172079434] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:13,014 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:13,014 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:13,014 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1028999239] [2024-11-08 00:35:13,014 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:14,094 INFO L204 LassoAnalysis]: Preferences: [2024-11-08 00:35:14,096 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-11-08 00:35:14,096 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-11-08 00:35:14,096 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-11-08 00:35:14,096 INFO L128 ssoRankerPreferences]: Use exernal solver: true [2024-11-08 00:35:14,096 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 00:35:14,096 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-11-08 00:35:14,096 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-11-08 00:35:14,097 INFO L132 ssoRankerPreferences]: Filename of dumped script: token_ring.06.cil-2.c_Iteration27_Loop [2024-11-08 00:35:14,097 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-11-08 00:35:14,097 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-11-08 00:35:14,114 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:14,121 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:14,123 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:14,125 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:14,127 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:14,128 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:14,131 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:14,133 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:14,135 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:14,136 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:14,139 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:14,141 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:14,143 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:14,145 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:14,147 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:14,149 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:14,150 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:14,152 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:14,154 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:14,157 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:14,158 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:14,160 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:14,162 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:14,164 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:14,166 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:14,168 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:14,169 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:14,171 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:14,172 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:14,174 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:14,177 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:14,180 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:14,183 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:14,187 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:14,189 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:14,191 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:14,192 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:14,194 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:14,195 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:14,197 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:14,198 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:14,200 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:14,204 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:14,207 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:14,210 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:14,212 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:14,216 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:14,220 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:14,223 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:14,226 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:14,228 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:14,229 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:14,231 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:14,235 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:14,237 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:14,238 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:14,240 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:14,241 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:14,243 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:14,246 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:14,248 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:14,249 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:14,251 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:14,252 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:14,255 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:14,257 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:14,261 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:14,262 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:14,264 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:14,266 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:14,267 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:14,269 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:14,274 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:14,276 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:14,278 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:14,281 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:14,284 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:14,286 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:14,289 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:14,290 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:14,293 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:14,295 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:14,663 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-11-08 00:35:14,663 INFO L365 LassoAnalysis]: Checking for nontermination... [2024-11-08 00:35:14,664 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 00:35:14,664 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2024-11-08 00:35:14,666 INFO L229 MonitoredProcess]: Starting monitored process 2 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 00:35:14,668 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2024-11-08 00:35:14,671 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-08 00:35:14,671 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-08 00:35:14,687 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-08 00:35:14,688 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_master_triggered_~__retres1~0#1=0} Honda state: {ULTIMATE.start_is_master_triggered_~__retres1~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-08 00:35:14,699 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Ended with exit code 0 [2024-11-08 00:35:14,703 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 00:35:14,703 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2024-11-08 00:35:14,705 INFO L229 MonitoredProcess]: Starting monitored process 3 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 00:35:14,710 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2024-11-08 00:35:14,711 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-08 00:35:14,711 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-08 00:35:14,727 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-08 00:35:14,727 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_exists_runnable_thread_#res#1=0} Honda state: {ULTIMATE.start_exists_runnable_thread_#res#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-08 00:35:14,738 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Ended with exit code 0 [2024-11-08 00:35:14,739 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 00:35:14,739 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2024-11-08 00:35:14,741 INFO L229 MonitoredProcess]: Starting monitored process 4 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 00:35:14,742 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2024-11-08 00:35:14,743 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-08 00:35:14,743 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-08 00:35:14,757 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-08 00:35:14,757 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_#t~ret15#1=0} Honda state: {ULTIMATE.start_activate_threads_#t~ret15#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-08 00:35:14,779 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Ended with exit code 0 [2024-11-08 00:35:14,779 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 00:35:14,779 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2024-11-08 00:35:14,783 INFO L229 MonitoredProcess]: Starting monitored process 5 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 00:35:14,788 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2024-11-08 00:35:14,790 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-08 00:35:14,790 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-08 00:35:14,808 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-08 00:35:14,808 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit4_triggered_#res#1=0} Honda state: {ULTIMATE.start_is_transmit4_triggered_#res#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-08 00:35:14,822 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Ended with exit code 0 [2024-11-08 00:35:14,822 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 00:35:14,822 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2024-11-08 00:35:14,824 INFO L229 MonitoredProcess]: Starting monitored process 6 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 00:35:14,825 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2024-11-08 00:35:14,827 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-08 00:35:14,827 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-08 00:35:14,840 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-08 00:35:14,840 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp_ndt_2~0#1=0} Honda state: {ULTIMATE.start_eval_~tmp_ndt_2~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-08 00:35:14,851 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Ended with exit code 0 [2024-11-08 00:35:14,851 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 00:35:14,852 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2024-11-08 00:35:14,853 INFO L229 MonitoredProcess]: Starting monitored process 7 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 00:35:14,855 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2024-11-08 00:35:14,855 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-08 00:35:14,855 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-08 00:35:14,877 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-08 00:35:14,877 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t4_st~0=-1} Honda state: {~t4_st~0=-1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-08 00:35:14,887 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Ended with exit code 0 [2024-11-08 00:35:14,888 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 00:35:14,888 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2024-11-08 00:35:14,890 INFO L229 MonitoredProcess]: Starting monitored process 8 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 00:35:14,891 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2024-11-08 00:35:14,892 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-08 00:35:14,892 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-08 00:35:14,904 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-08 00:35:14,904 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit2_triggered_~__retres1~2#1=0} Honda state: {ULTIMATE.start_is_transmit2_triggered_~__retres1~2#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-08 00:35:14,915 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Ended with exit code 0 [2024-11-08 00:35:14,915 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 00:35:14,915 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2024-11-08 00:35:14,917 INFO L229 MonitoredProcess]: Starting monitored process 9 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 00:35:14,918 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2024-11-08 00:35:14,921 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-08 00:35:14,921 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-08 00:35:14,933 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-08 00:35:14,933 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_#t~nondet7#1=0} Honda state: {ULTIMATE.start_eval_#t~nondet7#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-08 00:35:14,944 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Ended with exit code 0 [2024-11-08 00:35:14,944 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 00:35:14,945 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2024-11-08 00:35:14,946 INFO L229 MonitoredProcess]: Starting monitored process 10 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 00:35:14,947 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Waiting until timeout for monitored process [2024-11-08 00:35:14,949 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-08 00:35:14,949 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-08 00:35:14,972 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-08 00:35:14,972 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_start_simulation_#t~ret21#1=0} Honda state: {ULTIMATE.start_start_simulation_#t~ret21#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-08 00:35:14,983 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Forceful destruction successful, exit code 0 [2024-11-08 00:35:14,983 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 00:35:14,984 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2024-11-08 00:35:14,986 INFO L229 MonitoredProcess]: Starting monitored process 11 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 00:35:14,987 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Waiting until timeout for monitored process [2024-11-08 00:35:14,988 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-08 00:35:14,988 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-08 00:35:15,007 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-08 00:35:15,007 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~E_4~0=-8} Honda state: {~E_4~0=-8} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-08 00:35:15,018 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Forceful destruction successful, exit code 0 [2024-11-08 00:35:15,019 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 00:35:15,019 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2024-11-08 00:35:15,020 INFO L229 MonitoredProcess]: Starting monitored process 12 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 00:35:15,022 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Waiting until timeout for monitored process [2024-11-08 00:35:15,023 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-08 00:35:15,023 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-08 00:35:15,034 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-08 00:35:15,034 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~m_pc~0=1} Honda state: {~m_pc~0=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-08 00:35:15,046 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Forceful destruction successful, exit code 0 [2024-11-08 00:35:15,046 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 00:35:15,046 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2024-11-08 00:35:15,048 INFO L229 MonitoredProcess]: Starting monitored process 13 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 00:35:15,049 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Waiting until timeout for monitored process [2024-11-08 00:35:15,052 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-08 00:35:15,052 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-08 00:35:15,063 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-08 00:35:15,063 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_#t~ret16#1=0} Honda state: {ULTIMATE.start_activate_threads_#t~ret16#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-08 00:35:15,074 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Ended with exit code 0 [2024-11-08 00:35:15,075 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 00:35:15,075 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2024-11-08 00:35:15,077 INFO L229 MonitoredProcess]: Starting monitored process 14 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 00:35:15,078 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Waiting until timeout for monitored process [2024-11-08 00:35:15,079 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-08 00:35:15,079 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-08 00:35:15,098 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-08 00:35:15,098 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t3_pc~0=4} Honda state: {~t3_pc~0=4} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-08 00:35:15,109 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Ended with exit code 0 [2024-11-08 00:35:15,110 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 00:35:15,110 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2024-11-08 00:35:15,112 INFO L229 MonitoredProcess]: Starting monitored process 15 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 00:35:15,115 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Waiting until timeout for monitored process [2024-11-08 00:35:15,116 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-08 00:35:15,116 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-08 00:35:15,134 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-08 00:35:15,134 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t1_st~0=-1} Honda state: {~t1_st~0=-1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-08 00:35:15,146 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Forceful destruction successful, exit code 0 [2024-11-08 00:35:15,146 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 00:35:15,146 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2024-11-08 00:35:15,148 INFO L229 MonitoredProcess]: Starting monitored process 16 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 00:35:15,149 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Waiting until timeout for monitored process [2024-11-08 00:35:15,150 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-08 00:35:15,150 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-08 00:35:15,162 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-08 00:35:15,162 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_start_simulation_#t~ret22#1=0} Honda state: {ULTIMATE.start_start_simulation_#t~ret22#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-08 00:35:15,172 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Forceful destruction successful, exit code 0 [2024-11-08 00:35:15,173 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 00:35:15,173 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2024-11-08 00:35:15,175 INFO L229 MonitoredProcess]: Starting monitored process 17 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 00:35:15,176 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Waiting until timeout for monitored process [2024-11-08 00:35:15,177 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-08 00:35:15,177 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-08 00:35:15,192 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-08 00:35:15,192 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit5_triggered_#res#1=0} Honda state: {ULTIMATE.start_is_transmit5_triggered_#res#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-08 00:35:15,203 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Forceful destruction successful, exit code 0 [2024-11-08 00:35:15,203 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 00:35:15,203 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2024-11-08 00:35:15,205 INFO L229 MonitoredProcess]: Starting monitored process 18 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 00:35:15,206 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Waiting until timeout for monitored process [2024-11-08 00:35:15,207 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-08 00:35:15,207 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-08 00:35:15,219 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-08 00:35:15,219 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_#t~nondet6#1=0} Honda state: {ULTIMATE.start_eval_#t~nondet6#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-08 00:35:15,229 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Ended with exit code 0 [2024-11-08 00:35:15,230 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 00:35:15,230 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2024-11-08 00:35:15,232 INFO L229 MonitoredProcess]: Starting monitored process 19 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 00:35:15,237 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Waiting until timeout for monitored process [2024-11-08 00:35:15,238 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-08 00:35:15,238 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-08 00:35:15,256 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-08 00:35:15,256 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t5_st~0=4} Honda state: {~t5_st~0=4} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-08 00:35:15,267 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Forceful destruction successful, exit code 0 [2024-11-08 00:35:15,267 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 00:35:15,267 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2024-11-08 00:35:15,269 INFO L229 MonitoredProcess]: Starting monitored process 20 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 00:35:15,271 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (20)] Waiting until timeout for monitored process [2024-11-08 00:35:15,272 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-08 00:35:15,272 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-08 00:35:15,284 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-08 00:35:15,284 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit1_triggered_~__retres1~1#1=0} Honda state: {ULTIMATE.start_is_transmit1_triggered_~__retres1~1#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-08 00:35:15,294 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (20)] Ended with exit code 0 [2024-11-08 00:35:15,295 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 00:35:15,295 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2024-11-08 00:35:15,297 INFO L229 MonitoredProcess]: Starting monitored process 21 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 00:35:15,298 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (21)] Waiting until timeout for monitored process [2024-11-08 00:35:15,299 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-08 00:35:15,299 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-08 00:35:15,311 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-08 00:35:15,311 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_~tmp___4~0#1=0} Honda state: {ULTIMATE.start_activate_threads_~tmp___4~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-08 00:35:15,321 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (21)] Ended with exit code 0 [2024-11-08 00:35:15,322 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 00:35:15,322 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2024-11-08 00:35:15,324 INFO L229 MonitoredProcess]: Starting monitored process 22 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 00:35:15,325 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (22)] Waiting until timeout for monitored process [2024-11-08 00:35:15,325 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-08 00:35:15,325 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-08 00:35:15,336 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-08 00:35:15,337 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_start_simulation_~tmp___0~1#1=0} Honda state: {ULTIMATE.start_start_simulation_~tmp___0~1#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-08 00:35:15,347 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (22)] Forceful destruction successful, exit code 0 [2024-11-08 00:35:15,348 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 00:35:15,348 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2024-11-08 00:35:15,350 INFO L229 MonitoredProcess]: Starting monitored process 23 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 00:35:15,351 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (23)] Waiting until timeout for monitored process [2024-11-08 00:35:15,352 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-08 00:35:15,352 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-08 00:35:15,363 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-08 00:35:15,364 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_~tmp___2~0#1=0} Honda state: {ULTIMATE.start_activate_threads_~tmp___2~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-08 00:35:15,374 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (23)] Ended with exit code 0 [2024-11-08 00:35:15,376 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 00:35:15,377 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2024-11-08 00:35:15,380 INFO L229 MonitoredProcess]: Starting monitored process 24 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 00:35:15,381 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (24)] Waiting until timeout for monitored process [2024-11-08 00:35:15,382 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-08 00:35:15,382 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-08 00:35:15,395 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-08 00:35:15,395 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_~tmp___0~0#1=0} Honda state: {ULTIMATE.start_activate_threads_~tmp___0~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-08 00:35:15,405 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (24)] Forceful destruction successful, exit code 0 [2024-11-08 00:35:15,406 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 00:35:15,406 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2024-11-08 00:35:15,408 INFO L229 MonitoredProcess]: Starting monitored process 25 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 00:35:15,409 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (25)] Waiting until timeout for monitored process [2024-11-08 00:35:15,410 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-08 00:35:15,410 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-08 00:35:15,421 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-08 00:35:15,421 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_~tmp___1~0#1=0} Honda state: {ULTIMATE.start_activate_threads_~tmp___1~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-08 00:35:15,432 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (25)] Forceful destruction successful, exit code 0 [2024-11-08 00:35:15,433 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 00:35:15,433 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2024-11-08 00:35:15,434 INFO L229 MonitoredProcess]: Starting monitored process 26 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 00:35:15,435 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (26)] Waiting until timeout for monitored process [2024-11-08 00:35:15,436 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-08 00:35:15,436 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-08 00:35:15,449 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-08 00:35:15,449 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_~tmp~1#1=0} Honda state: {ULTIMATE.start_activate_threads_~tmp~1#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-08 00:35:15,459 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (26)] Ended with exit code 0 [2024-11-08 00:35:15,460 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 00:35:15,460 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2024-11-08 00:35:15,462 INFO L229 MonitoredProcess]: Starting monitored process 27 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 00:35:15,462 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (27)] Waiting until timeout for monitored process [2024-11-08 00:35:15,464 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-08 00:35:15,464 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-08 00:35:15,476 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-08 00:35:15,476 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit3_triggered_#res#1=0} Honda state: {ULTIMATE.start_is_transmit3_triggered_#res#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-08 00:35:15,487 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (27)] Forceful destruction successful, exit code 0 [2024-11-08 00:35:15,487 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 00:35:15,488 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2024-11-08 00:35:15,489 INFO L229 MonitoredProcess]: Starting monitored process 28 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 00:35:15,490 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (28)] Waiting until timeout for monitored process [2024-11-08 00:35:15,491 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-08 00:35:15,492 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-08 00:35:15,503 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-08 00:35:15,503 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit4_triggered_~__retres1~4#1=0} Honda state: {ULTIMATE.start_is_transmit4_triggered_~__retres1~4#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-08 00:35:15,514 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (28)] Ended with exit code 0 [2024-11-08 00:35:15,514 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 00:35:15,514 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2024-11-08 00:35:15,516 INFO L229 MonitoredProcess]: Starting monitored process 29 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 00:35:15,517 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (29)] Waiting until timeout for monitored process [2024-11-08 00:35:15,518 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-08 00:35:15,518 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-08 00:35:15,529 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-08 00:35:15,529 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp_ndt_1~0#1=0} Honda state: {ULTIMATE.start_eval_~tmp_ndt_1~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-08 00:35:15,540 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (29)] Ended with exit code 0 [2024-11-08 00:35:15,541 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 00:35:15,541 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2024-11-08 00:35:15,543 INFO L229 MonitoredProcess]: Starting monitored process 30 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 00:35:15,544 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (30)] Waiting until timeout for monitored process [2024-11-08 00:35:15,545 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-08 00:35:15,545 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-08 00:35:15,556 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-08 00:35:15,557 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_#t~nondet10#1=0} Honda state: {ULTIMATE.start_eval_#t~nondet10#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-08 00:35:15,567 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (30)] Forceful destruction successful, exit code 0 [2024-11-08 00:35:15,568 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 00:35:15,568 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2024-11-08 00:35:15,570 INFO L229 MonitoredProcess]: Starting monitored process 31 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 00:35:15,571 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (31)] Waiting until timeout for monitored process [2024-11-08 00:35:15,572 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-08 00:35:15,572 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-08 00:35:15,594 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (31)] Forceful destruction successful, exit code 0 [2024-11-08 00:35:15,595 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 00:35:15,595 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2024-11-08 00:35:15,596 INFO L229 MonitoredProcess]: Starting monitored process 32 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 00:35:15,598 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (32)] Waiting until timeout for monitored process [2024-11-08 00:35:15,599 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2024-11-08 00:35:15,599 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-08 00:35:15,611 INFO L405 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2024-11-08 00:35:15,622 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (32)] Ended with exit code 0 [2024-11-08 00:35:15,623 INFO L204 LassoAnalysis]: Preferences: [2024-11-08 00:35:15,623 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-11-08 00:35:15,623 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-11-08 00:35:15,623 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-11-08 00:35:15,623 INFO L128 ssoRankerPreferences]: Use exernal solver: false [2024-11-08 00:35:15,623 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 00:35:15,623 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-11-08 00:35:15,623 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-11-08 00:35:15,624 INFO L132 ssoRankerPreferences]: Filename of dumped script: token_ring.06.cil-2.c_Iteration27_Loop [2024-11-08 00:35:15,624 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-11-08 00:35:15,624 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-11-08 00:35:15,626 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:15,628 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:15,629 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:15,631 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:15,634 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:15,636 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:15,637 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:15,639 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:15,640 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:15,642 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:15,645 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:15,647 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:15,649 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:15,650 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:15,652 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:15,656 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:15,657 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:15,659 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:15,660 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:15,662 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:15,664 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:15,665 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:15,666 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:15,668 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:15,669 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:15,671 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:15,672 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:15,673 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:15,675 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:15,676 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:15,677 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:15,681 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:15,685 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:15,687 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:15,690 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:15,692 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:15,694 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:15,695 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:15,697 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:15,698 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:15,699 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:15,701 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:15,704 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:15,706 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:15,708 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:15,709 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:15,716 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:15,721 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:15,725 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:15,728 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:15,730 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:15,731 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:15,733 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:15,736 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:15,738 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:15,739 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:15,741 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:15,743 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:15,747 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:15,749 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:15,750 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:15,752 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:15,753 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:15,754 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:15,756 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:15,759 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:15,761 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:15,762 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:15,763 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:15,765 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:15,766 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:15,768 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:15,769 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:15,772 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:15,774 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:15,776 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:15,779 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:15,783 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:15,784 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:15,787 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:15,789 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:15,791 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-08 00:35:16,144 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-11-08 00:35:16,147 INFO L451 LassoAnalysis]: Using template 'affine'. [2024-11-08 00:35:16,148 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 00:35:16,148 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2024-11-08 00:35:16,151 INFO L229 MonitoredProcess]: Starting monitored process 33 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 00:35:16,154 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (33)] Waiting until timeout for monitored process [2024-11-08 00:35:16,154 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-08 00:35:16,165 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-08 00:35:16,165 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-08 00:35:16,166 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-08 00:35:16,166 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-08 00:35:16,166 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-08 00:35:16,169 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-08 00:35:16,169 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-08 00:35:16,171 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-08 00:35:16,181 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (33)] Ended with exit code 0 [2024-11-08 00:35:16,182 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 00:35:16,182 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2024-11-08 00:35:16,183 INFO L229 MonitoredProcess]: Starting monitored process 34 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 00:35:16,185 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (34)] Waiting until timeout for monitored process [2024-11-08 00:35:16,186 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-08 00:35:16,197 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-08 00:35:16,198 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-08 00:35:16,198 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-08 00:35:16,198 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-08 00:35:16,198 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-08 00:35:16,199 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-08 00:35:16,199 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-08 00:35:16,200 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-08 00:35:16,211 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (34)] Forceful destruction successful, exit code 0 [2024-11-08 00:35:16,211 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 00:35:16,213 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2024-11-08 00:35:16,215 INFO L229 MonitoredProcess]: Starting monitored process 35 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 00:35:16,216 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (35)] Waiting until timeout for monitored process [2024-11-08 00:35:16,217 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-08 00:35:16,227 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-08 00:35:16,227 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-08 00:35:16,227 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-08 00:35:16,227 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-08 00:35:16,227 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-08 00:35:16,228 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-08 00:35:16,228 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-08 00:35:16,229 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-08 00:35:16,240 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (35)] Forceful destruction successful, exit code 0 [2024-11-08 00:35:16,240 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 00:35:16,240 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2024-11-08 00:35:16,242 INFO L229 MonitoredProcess]: Starting monitored process 36 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 00:35:16,268 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-08 00:35:16,276 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (36)] Waiting until timeout for monitored process [2024-11-08 00:35:16,278 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-08 00:35:16,279 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-08 00:35:16,279 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-08 00:35:16,279 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-08 00:35:16,279 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-08 00:35:16,279 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-08 00:35:16,279 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-08 00:35:16,280 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-08 00:35:16,291 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (36)] Forceful destruction successful, exit code 0 [2024-11-08 00:35:16,291 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 00:35:16,291 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2024-11-08 00:35:16,293 INFO L229 MonitoredProcess]: Starting monitored process 37 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 00:35:16,294 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (37)] Waiting until timeout for monitored process [2024-11-08 00:35:16,295 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-08 00:35:16,305 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-08 00:35:16,305 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-08 00:35:16,305 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-08 00:35:16,305 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2024-11-08 00:35:16,305 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-08 00:35:16,306 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2024-11-08 00:35:16,306 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-08 00:35:16,308 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-08 00:35:16,318 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (37)] Forceful destruction successful, exit code 0 [2024-11-08 00:35:16,319 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 00:35:16,319 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2024-11-08 00:35:16,320 INFO L229 MonitoredProcess]: Starting monitored process 38 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 00:35:16,321 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (38)] Waiting until timeout for monitored process [2024-11-08 00:35:16,323 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-08 00:35:16,333 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-08 00:35:16,333 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-08 00:35:16,333 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-08 00:35:16,333 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-08 00:35:16,333 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-08 00:35:16,334 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-08 00:35:16,334 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-08 00:35:16,335 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-08 00:35:16,345 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (38)] Forceful destruction successful, exit code 0 [2024-11-08 00:35:16,345 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 00:35:16,346 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2024-11-08 00:35:16,347 INFO L229 MonitoredProcess]: Starting monitored process 39 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 00:35:16,348 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (39)] Waiting until timeout for monitored process [2024-11-08 00:35:16,350 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-08 00:35:16,360 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-08 00:35:16,360 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-08 00:35:16,360 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-08 00:35:16,360 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-08 00:35:16,360 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-08 00:35:16,361 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-08 00:35:16,361 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-08 00:35:16,362 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-08 00:35:16,372 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (39)] Ended with exit code 0 [2024-11-08 00:35:16,373 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 00:35:16,373 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2024-11-08 00:35:16,375 INFO L229 MonitoredProcess]: Starting monitored process 40 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 00:35:16,375 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (40)] Waiting until timeout for monitored process [2024-11-08 00:35:16,377 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-08 00:35:16,387 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-08 00:35:16,387 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-08 00:35:16,387 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-08 00:35:16,387 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-08 00:35:16,387 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-08 00:35:16,388 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-08 00:35:16,388 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-08 00:35:16,389 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-08 00:35:16,400 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (40)] Forceful destruction successful, exit code 0 [2024-11-08 00:35:16,401 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 00:35:16,401 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2024-11-08 00:35:16,403 INFO L229 MonitoredProcess]: Starting monitored process 41 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 00:35:16,404 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (41)] Waiting until timeout for monitored process [2024-11-08 00:35:16,405 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-08 00:35:16,416 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-08 00:35:16,416 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-08 00:35:16,416 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-08 00:35:16,416 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-08 00:35:16,416 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-08 00:35:16,417 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-08 00:35:16,417 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-08 00:35:16,418 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-08 00:35:16,428 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (41)] Forceful destruction successful, exit code 0 [2024-11-08 00:35:16,429 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 00:35:16,429 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2024-11-08 00:35:16,431 INFO L229 MonitoredProcess]: Starting monitored process 42 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 00:35:16,432 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (42)] Waiting until timeout for monitored process [2024-11-08 00:35:16,436 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-08 00:35:16,446 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-08 00:35:16,447 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-08 00:35:16,447 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-08 00:35:16,447 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2024-11-08 00:35:16,447 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-08 00:35:16,447 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2024-11-08 00:35:16,447 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-08 00:35:16,452 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-08 00:35:16,475 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (42)] Ended with exit code 0 [2024-11-08 00:35:16,475 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 00:35:16,475 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2024-11-08 00:35:16,481 INFO L229 MonitoredProcess]: Starting monitored process 43 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 00:35:16,483 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-08 00:35:16,486 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (43)] Waiting until timeout for monitored process [2024-11-08 00:35:16,505 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-08 00:35:16,506 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-08 00:35:16,506 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-08 00:35:16,506 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-08 00:35:16,506 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-08 00:35:16,506 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-08 00:35:16,506 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-08 00:35:16,508 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-08 00:35:16,523 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (43)] Forceful destruction successful, exit code 0 [2024-11-08 00:35:16,524 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 00:35:16,524 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2024-11-08 00:35:16,526 INFO L229 MonitoredProcess]: Starting monitored process 44 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 00:35:16,527 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (44)] Waiting until timeout for monitored process [2024-11-08 00:35:16,528 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-08 00:35:16,537 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-08 00:35:16,538 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-08 00:35:16,538 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-08 00:35:16,538 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-08 00:35:16,538 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-08 00:35:16,538 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-08 00:35:16,538 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-08 00:35:16,539 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-08 00:35:16,552 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (44)] Ended with exit code 0 [2024-11-08 00:35:16,552 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 00:35:16,553 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2024-11-08 00:35:16,555 INFO L229 MonitoredProcess]: Starting monitored process 45 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 00:35:16,559 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-08 00:35:16,560 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (45)] Waiting until timeout for monitored process [2024-11-08 00:35:16,576 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-08 00:35:16,576 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-08 00:35:16,577 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-08 00:35:16,577 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-08 00:35:16,577 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-08 00:35:16,577 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-08 00:35:16,577 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-08 00:35:16,578 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-08 00:35:16,588 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (45)] Forceful destruction successful, exit code 0 [2024-11-08 00:35:16,589 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 00:35:16,589 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2024-11-08 00:35:16,591 INFO L229 MonitoredProcess]: Starting monitored process 46 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 00:35:16,592 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (46)] Waiting until timeout for monitored process [2024-11-08 00:35:16,592 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-08 00:35:16,602 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-08 00:35:16,602 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-08 00:35:16,603 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-08 00:35:16,603 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-08 00:35:16,603 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-08 00:35:16,603 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-08 00:35:16,603 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-08 00:35:16,604 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-08 00:35:16,614 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (46)] Ended with exit code 0 [2024-11-08 00:35:16,615 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 00:35:16,615 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2024-11-08 00:35:16,617 INFO L229 MonitoredProcess]: Starting monitored process 47 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 00:35:16,617 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (47)] Waiting until timeout for monitored process [2024-11-08 00:35:16,619 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-08 00:35:16,628 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-08 00:35:16,629 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-08 00:35:16,629 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-08 00:35:16,629 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2024-11-08 00:35:16,629 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-08 00:35:16,630 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2024-11-08 00:35:16,630 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-08 00:35:16,631 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-08 00:35:16,646 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (47)] Ended with exit code 0 [2024-11-08 00:35:16,647 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 00:35:16,647 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2024-11-08 00:35:16,651 INFO L229 MonitoredProcess]: Starting monitored process 48 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 00:35:16,653 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (48)] Waiting until timeout for monitored process [2024-11-08 00:35:16,653 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-08 00:35:16,663 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-08 00:35:16,663 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-08 00:35:16,663 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-08 00:35:16,663 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-08 00:35:16,663 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-08 00:35:16,664 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-08 00:35:16,664 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-08 00:35:16,666 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-08 00:35:16,675 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (48)] Ended with exit code 0 [2024-11-08 00:35:16,676 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 00:35:16,676 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2024-11-08 00:35:16,678 INFO L229 MonitoredProcess]: Starting monitored process 49 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 00:35:16,679 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (49)] Waiting until timeout for monitored process [2024-11-08 00:35:16,680 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-08 00:35:16,690 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-08 00:35:16,690 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-08 00:35:16,690 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-08 00:35:16,690 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2024-11-08 00:35:16,690 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-08 00:35:16,691 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2024-11-08 00:35:16,691 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-08 00:35:16,692 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-08 00:35:16,703 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (49)] Forceful destruction successful, exit code 0 [2024-11-08 00:35:16,703 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 00:35:16,703 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2024-11-08 00:35:16,705 INFO L229 MonitoredProcess]: Starting monitored process 50 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 00:35:16,706 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (50)] Waiting until timeout for monitored process [2024-11-08 00:35:16,706 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-08 00:35:16,716 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-08 00:35:16,716 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-08 00:35:16,716 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-08 00:35:16,717 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-08 00:35:16,717 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-08 00:35:16,717 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-08 00:35:16,717 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-08 00:35:16,718 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-08 00:35:16,729 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (50)] Ended with exit code 0 [2024-11-08 00:35:16,729 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 00:35:16,729 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2024-11-08 00:35:16,731 INFO L229 MonitoredProcess]: Starting monitored process 51 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 00:35:16,732 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (51)] Waiting until timeout for monitored process [2024-11-08 00:35:16,733 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-08 00:35:16,745 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-08 00:35:16,745 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-08 00:35:16,745 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-08 00:35:16,745 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2024-11-08 00:35:16,745 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-08 00:35:16,750 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2024-11-08 00:35:16,750 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-08 00:35:16,751 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-08 00:35:16,774 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (51)] Forceful destruction successful, exit code 0 [2024-11-08 00:35:16,775 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 00:35:16,776 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2024-11-08 00:35:16,779 INFO L229 MonitoredProcess]: Starting monitored process 52 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 00:35:16,780 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (52)] Waiting until timeout for monitored process [2024-11-08 00:35:16,781 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-08 00:35:16,791 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-08 00:35:16,791 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-08 00:35:16,791 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-08 00:35:16,791 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-08 00:35:16,791 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-08 00:35:16,792 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-08 00:35:16,792 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-08 00:35:16,793 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-08 00:35:16,805 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (52)] Forceful destruction successful, exit code 0 [2024-11-08 00:35:16,805 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 00:35:16,805 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2024-11-08 00:35:16,807 INFO L229 MonitoredProcess]: Starting monitored process 53 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 00:35:16,808 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (53)] Waiting until timeout for monitored process [2024-11-08 00:35:16,809 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-08 00:35:16,821 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-08 00:35:16,821 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-08 00:35:16,821 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-08 00:35:16,821 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-08 00:35:16,821 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-08 00:35:16,822 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-08 00:35:16,822 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-08 00:35:16,824 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-08 00:35:16,838 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (53)] Ended with exit code 0 [2024-11-08 00:35:16,839 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 00:35:16,839 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2024-11-08 00:35:16,841 INFO L229 MonitoredProcess]: Starting monitored process 54 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 00:35:16,842 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (54)] Waiting until timeout for monitored process [2024-11-08 00:35:16,843 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-08 00:35:16,855 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-08 00:35:16,856 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-08 00:35:16,856 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-08 00:35:16,856 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-08 00:35:16,856 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-08 00:35:16,856 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-08 00:35:16,856 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-08 00:35:16,858 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-08 00:35:16,872 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (54)] Ended with exit code 0 [2024-11-08 00:35:16,873 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 00:35:16,873 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2024-11-08 00:35:16,875 INFO L229 MonitoredProcess]: Starting monitored process 55 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 00:35:16,875 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (55)] Waiting until timeout for monitored process [2024-11-08 00:35:16,876 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-08 00:35:16,886 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-08 00:35:16,886 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-08 00:35:16,886 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-08 00:35:16,886 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-08 00:35:16,886 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-08 00:35:16,887 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-08 00:35:16,887 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-08 00:35:16,888 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-08 00:35:16,898 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (55)] Ended with exit code 0 [2024-11-08 00:35:16,898 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 00:35:16,898 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2024-11-08 00:35:16,900 INFO L229 MonitoredProcess]: Starting monitored process 56 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 00:35:16,901 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (56)] Waiting until timeout for monitored process [2024-11-08 00:35:16,902 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-08 00:35:16,911 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-08 00:35:16,912 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-08 00:35:16,912 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-08 00:35:16,912 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-08 00:35:16,912 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-08 00:35:16,912 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-08 00:35:16,912 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-08 00:35:16,913 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-08 00:35:16,923 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (56)] Forceful destruction successful, exit code 0 [2024-11-08 00:35:16,924 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 00:35:16,924 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2024-11-08 00:35:16,926 INFO L229 MonitoredProcess]: Starting monitored process 57 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 00:35:16,927 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (57)] Waiting until timeout for monitored process [2024-11-08 00:35:16,928 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-08 00:35:16,938 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-08 00:35:16,938 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-08 00:35:16,938 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-08 00:35:16,938 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-08 00:35:16,938 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-08 00:35:16,938 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-08 00:35:16,938 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-08 00:35:16,940 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-08 00:35:16,950 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (57)] Ended with exit code 0 [2024-11-08 00:35:16,951 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 00:35:16,951 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2024-11-08 00:35:16,953 INFO L229 MonitoredProcess]: Starting monitored process 58 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 00:35:16,954 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (58)] Waiting until timeout for monitored process [2024-11-08 00:35:16,955 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-08 00:35:16,964 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-08 00:35:16,964 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-08 00:35:16,965 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-08 00:35:16,965 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-08 00:35:16,965 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-08 00:35:16,965 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-08 00:35:16,966 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-08 00:35:16,967 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-08 00:35:16,978 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (58)] Ended with exit code 0 [2024-11-08 00:35:16,978 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 00:35:16,979 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2024-11-08 00:35:16,981 INFO L229 MonitoredProcess]: Starting monitored process 59 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 00:35:16,984 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (59)] Waiting until timeout for monitored process [2024-11-08 00:35:16,985 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-08 00:35:16,998 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-08 00:35:16,998 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-08 00:35:16,998 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-08 00:35:16,998 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-08 00:35:16,998 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-08 00:35:16,999 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-08 00:35:16,999 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-08 00:35:17,000 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-08 00:35:17,012 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (59)] Ended with exit code 0 [2024-11-08 00:35:17,013 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 00:35:17,013 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2024-11-08 00:35:17,015 INFO L229 MonitoredProcess]: Starting monitored process 60 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 00:35:17,016 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (60)] Waiting until timeout for monitored process [2024-11-08 00:35:17,017 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-08 00:35:17,027 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-08 00:35:17,027 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-08 00:35:17,027 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-08 00:35:17,027 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-08 00:35:17,027 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-08 00:35:17,028 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-08 00:35:17,028 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-08 00:35:17,029 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-08 00:35:17,039 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (60)] Forceful destruction successful, exit code 0 [2024-11-08 00:35:17,040 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 00:35:17,040 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2024-11-08 00:35:17,042 INFO L229 MonitoredProcess]: Starting monitored process 61 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 00:35:17,043 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (61)] Waiting until timeout for monitored process [2024-11-08 00:35:17,044 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-08 00:35:17,054 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-08 00:35:17,054 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-08 00:35:17,054 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-08 00:35:17,054 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-08 00:35:17,054 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-08 00:35:17,054 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-08 00:35:17,054 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-08 00:35:17,055 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-08 00:35:17,066 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (61)] Forceful destruction successful, exit code 0 [2024-11-08 00:35:17,066 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 00:35:17,067 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2024-11-08 00:35:17,068 INFO L229 MonitoredProcess]: Starting monitored process 62 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 00:35:17,069 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (62)] Waiting until timeout for monitored process [2024-11-08 00:35:17,070 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-08 00:35:17,080 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-08 00:35:17,081 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-08 00:35:17,081 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-08 00:35:17,081 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-08 00:35:17,081 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-08 00:35:17,081 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-08 00:35:17,081 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-08 00:35:17,082 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-08 00:35:17,093 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (62)] Ended with exit code 0 [2024-11-08 00:35:17,093 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 00:35:17,093 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2024-11-08 00:35:17,095 INFO L229 MonitoredProcess]: Starting monitored process 63 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 00:35:17,096 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (63)] Waiting until timeout for monitored process [2024-11-08 00:35:17,096 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-08 00:35:17,106 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-08 00:35:17,107 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-08 00:35:17,107 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-08 00:35:17,107 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-08 00:35:17,107 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-08 00:35:17,108 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-08 00:35:17,108 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-08 00:35:17,109 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2024-11-08 00:35:17,112 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2024-11-08 00:35:17,114 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2024-11-08 00:35:17,116 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 00:35:17,116 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2024-11-08 00:35:17,120 INFO L229 MonitoredProcess]: Starting monitored process 64 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 00:35:17,121 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (64)] Waiting until timeout for monitored process [2024-11-08 00:35:17,121 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2024-11-08 00:35:17,121 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2024-11-08 00:35:17,122 INFO L474 LassoAnalysis]: Proved termination. [2024-11-08 00:35:17,122 INFO L476 LassoAnalysis]: Termination argument consisting of: Ranking function f(~T5_E~0) = -1*~T5_E~0 + 1 Supporting invariants [] [2024-11-08 00:35:17,133 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (63)] Forceful destruction successful, exit code 0 [2024-11-08 00:35:17,138 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2024-11-08 00:35:17,168 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:17,235 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:17,238 INFO L255 TraceCheckSpWp]: Trace formula consists of 241 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-11-08 00:35:17,239 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-08 00:35:17,354 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:17,356 INFO L255 TraceCheckSpWp]: Trace formula consists of 212 conjuncts, 4 conjuncts are in the unsatisfiable core [2024-11-08 00:35:17,357 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-08 00:35:17,502 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:17,510 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2024-11-08 00:35:17,510 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 30640 states and 40431 transitions. cyclomatic complexity: 9807 Second operand has 5 states, 5 states have (on average 36.8) internal successors, (184), 5 states have internal predecessors, (184), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:17,813 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 30640 states and 40431 transitions. cyclomatic complexity: 9807. Second operand has 5 states, 5 states have (on average 36.8) internal successors, (184), 5 states have internal predecessors, (184), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 61506 states and 81442 transitions. Complement of second has 4 states. [2024-11-08 00:35:17,814 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2024-11-08 00:35:17,814 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 36.8) internal successors, (184), 5 states have internal predecessors, (184), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:17,815 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 980 transitions. [2024-11-08 00:35:17,818 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 980 transitions. Stem has 84 letters. Loop has 100 letters. [2024-11-08 00:35:17,819 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-08 00:35:17,819 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 980 transitions. Stem has 184 letters. Loop has 100 letters. [2024-11-08 00:35:17,820 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-08 00:35:17,820 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 980 transitions. Stem has 84 letters. Loop has 200 letters. [2024-11-08 00:35:17,822 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-08 00:35:17,822 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 61506 states and 81442 transitions. [2024-11-08 00:35:18,142 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (64)] Ended with exit code 0 [2024-11-08 00:35:18,200 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 30320 [2024-11-08 00:35:18,370 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 61506 states to 61506 states and 81442 transitions. [2024-11-08 00:35:18,371 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 30641 [2024-11-08 00:35:18,395 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 30802 [2024-11-08 00:35:18,396 INFO L73 IsDeterministic]: Start isDeterministic. Operand 61506 states and 81442 transitions. [2024-11-08 00:35:18,396 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-08 00:35:18,396 INFO L218 hiAutomatonCegarLoop]: Abstraction has 61506 states and 81442 transitions. [2024-11-08 00:35:18,433 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 61506 states and 81442 transitions. [2024-11-08 00:35:19,052 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 61506 to 61345. [2024-11-08 00:35:19,100 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 61345 states, 61345 states have (on average 1.3228951014752628) internal successors, (81153), 61344 states have internal predecessors, (81153), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:19,199 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 61345 states to 61345 states and 81153 transitions. [2024-11-08 00:35:19,199 INFO L240 hiAutomatonCegarLoop]: Abstraction has 61345 states and 81153 transitions. [2024-11-08 00:35:19,199 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:35:19,200 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:35:19,200 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:35:19,200 INFO L87 Difference]: Start difference. First operand 61345 states and 81153 transitions. Second operand has 3 states, 3 states have (on average 61.333333333333336) internal successors, (184), 3 states have internal predecessors, (184), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:19,448 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:35:19,448 INFO L93 Difference]: Finished difference Result 64609 states and 84897 transitions. [2024-11-08 00:35:19,448 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 64609 states and 84897 transitions. [2024-11-08 00:35:19,699 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 31952 [2024-11-08 00:35:19,887 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 64609 states to 64609 states and 84897 transitions. [2024-11-08 00:35:19,887 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 32273 [2024-11-08 00:35:19,912 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 32273 [2024-11-08 00:35:19,912 INFO L73 IsDeterministic]: Start isDeterministic. Operand 64609 states and 84897 transitions. [2024-11-08 00:35:19,913 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-08 00:35:19,913 INFO L218 hiAutomatonCegarLoop]: Abstraction has 64609 states and 84897 transitions. [2024-11-08 00:35:19,955 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 64609 states and 84897 transitions. [2024-11-08 00:35:20,680 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 64609 to 61345. [2024-11-08 00:35:20,729 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 61345 states, 61345 states have (on average 1.3187219822316407) internal successors, (80897), 61344 states have internal predecessors, (80897), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:20,806 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 61345 states to 61345 states and 80897 transitions. [2024-11-08 00:35:20,806 INFO L240 hiAutomatonCegarLoop]: Abstraction has 61345 states and 80897 transitions. [2024-11-08 00:35:20,807 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:35:20,807 INFO L425 stractBuchiCegarLoop]: Abstraction has 61345 states and 80897 transitions. [2024-11-08 00:35:20,811 INFO L332 stractBuchiCegarLoop]: ======== Iteration 28 ============ [2024-11-08 00:35:20,811 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 61345 states and 80897 transitions. [2024-11-08 00:35:20,928 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 30320 [2024-11-08 00:35:20,929 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:35:20,929 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:35:20,930 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:20,930 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:20,930 INFO L745 eck$LassoCheckResult]: Stem: 869396#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 869397#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 869674#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 869675#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 868976#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 868977#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 869672#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 869673#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 869523#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 869092#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 869093#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 868942#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 868943#L684 assume !(0 == ~M_E~0); 869925#L684-2 assume !(0 == ~T1_E~0); 869589#L689-1 assume !(0 == ~T2_E~0); 869590#L694-1 assume !(0 == ~T3_E~0); 869587#L699-1 assume !(0 == ~T4_E~0); 869588#L704-1 assume !(0 == ~T5_E~0); 869490#L709-1 assume !(0 == ~T6_E~0); 869363#L714-1 assume !(0 == ~E_M~0); 869364#L719-1 assume !(0 == ~E_1~0); 869855#L724-1 assume !(0 == ~E_2~0); 868893#L729-1 assume !(0 == ~E_3~0); 868894#L734-1 assume !(0 == ~E_4~0); 870011#L739-1 assume !(0 == ~E_5~0); 869287#L744-1 assume !(0 == ~E_6~0); 869288#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 868808#L334 assume !(1 == ~m_pc~0); 868809#L334-2 is_master_triggered_~__retres1~0#1 := 0; 869475#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 870227#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 869229#L849 assume !(0 != activate_threads_~tmp~1#1); 869230#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 869090#L353 assume !(1 == ~t1_pc~0); 869091#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 869681#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 868835#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 868836#L857 assume !(0 != activate_threads_~tmp___0~0#1); 868985#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 868986#L372 assume !(1 == ~t2_pc~0); 869203#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 869249#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 869682#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 869683#L865 assume !(0 != activate_threads_~tmp___1~0#1); 868788#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 868789#L391 assume !(1 == ~t3_pc~0); 868641#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 868642#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 868689#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 868690#L873 assume !(0 != activate_threads_~tmp___2~0#1); 869241#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 869242#L410 assume !(1 == ~t4_pc~0); 869710#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 869711#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 869014#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 869015#L881 assume !(0 != activate_threads_~tmp___3~0#1); 869252#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 869253#L429 assume !(1 == ~t5_pc~0); 868903#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 868904#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 870228#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 869721#L889 assume !(0 != activate_threads_~tmp___4~0#1); 869722#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 869224#L448 assume !(1 == ~t6_pc~0); 869057#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 869058#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 869654#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 869655#L897 assume !(0 != activate_threads_~tmp___5~0#1); 870072#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 870180#L762 assume !(1 == ~M_E~0); 869321#L762-2 assume !(1 == ~T1_E~0); 869322#L767-1 assume !(1 == ~T2_E~0); 870083#L772-1 assume !(1 == ~T3_E~0); 869788#L777-1 assume !(1 == ~T4_E~0); 869557#L782-1 assume !(1 == ~T5_E~0); 868950#L787-1 assume !(1 == ~T6_E~0); 868948#L792-1 assume !(1 == ~E_M~0); 868949#L797-1 assume !(1 == ~E_1~0); 869024#L802-1 assume !(1 == ~E_2~0); 869482#L807-1 assume !(1 == ~E_3~0); 869483#L812-1 assume !(1 == ~E_4~0); 869999#L817-1 assume !(1 == ~E_5~0); 869591#L822-1 assume !(1 == ~E_6~0); 869592#L827-1 assume { :end_inline_reset_delta_events } true; 870021#L1053-2 assume !false; 880824#L1054 [2024-11-08 00:35:20,931 INFO L747 eck$LassoCheckResult]: Loop: 880824#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 891484#L659-1 assume !false; 891527#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 891525#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 891523#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 891521#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 891519#L570 assume 0 != eval_~tmp~0#1; 891515#L570-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 891512#L578 assume 0 != eval_~tmp_ndt_1~0#1;~m_st~0 := 1;assume { :begin_inline_master } true;havoc master_#t~nondet4#1; 891513#L74 assume 0 == ~m_pc~0; 898288#L99-1 assume !false; 898287#L86 havoc master_#t~nondet4#1;~token~0 := master_#t~nondet4#1;havoc master_#t~nondet4#1;~local~0 := ~token~0;~E_1~0 := 1;assume { :begin_inline_immediate_notify } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 898286#L334-3 assume !(1 == ~m_pc~0); 898285#L334-5 is_master_triggered_~__retres1~0#1 := 0; 898283#L345-1 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 898281#is_master_triggered_returnLabel#2 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 898279#L849-3 assume !(0 != activate_threads_~tmp~1#1); 898275#L849-5 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 898272#L353-3 assume !(1 == ~t1_pc~0); 898269#L353-5 is_transmit1_triggered_~__retres1~1#1 := 0; 898266#L364-1 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 898263#is_transmit1_triggered_returnLabel#2 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 898260#L857-3 assume !(0 != activate_threads_~tmp___0~0#1); 898257#L857-5 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 898253#L372-3 assume 1 == ~t2_pc~0; 898249#L373-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 898244#L383-1 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 898239#is_transmit2_triggered_returnLabel#2 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 898235#L865-3 assume !(0 != activate_threads_~tmp___1~0#1); 898231#L865-5 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 898227#L391-3 assume !(1 == ~t3_pc~0); 898223#L391-5 is_transmit3_triggered_~__retres1~3#1 := 0; 898219#L402-1 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 898215#is_transmit3_triggered_returnLabel#2 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 898212#L873-3 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 898209#L873-5 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 898205#L410-3 assume !(1 == ~t4_pc~0); 898201#L410-5 is_transmit4_triggered_~__retres1~4#1 := 0; 898197#L421-1 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 898193#is_transmit4_triggered_returnLabel#2 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 898182#L881-3 assume !(0 != activate_threads_~tmp___3~0#1); 898167#L881-5 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 898163#L429-3 assume !(1 == ~t5_pc~0); 898159#L429-5 is_transmit5_triggered_~__retres1~5#1 := 0; 898154#L440-1 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 898149#is_transmit5_triggered_returnLabel#2 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 898145#L889-3 assume !(0 != activate_threads_~tmp___4~0#1); 898141#L889-5 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 898137#L448-3 assume !(1 == ~t6_pc~0); 898133#L448-5 is_transmit6_triggered_~__retres1~6#1 := 0; 898128#L459-1 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 898123#is_transmit6_triggered_returnLabel#2 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 898117#L897-3 assume !(0 != activate_threads_~tmp___5~0#1); 898101#L897-5 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true; 891690#immediate_notify_returnLabel#1 assume { :end_inline_immediate_notify } true;~E_1~0 := 2;~m_pc~0 := 1;~m_st~0 := 2; 891689#master_returnLabel#1 havoc master_#t~nondet4#1;assume { :end_inline_master } true; 891686#L578-2 havoc eval_~tmp_ndt_1~0#1; 891684#L575-1 assume !(0 == ~t1_st~0); 891680#L589-1 assume !(0 == ~t2_st~0); 891681#L603-1 assume !(0 == ~t3_st~0); 892277#L617-1 assume !(0 == ~t4_st~0); 892274#L631-1 assume !(0 == ~t5_st~0); 892275#L645-1 assume !(0 == ~t6_st~0); 894131#L659-1 assume !false; 894440#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 894438#L518 assume !(0 == ~m_st~0); 894436#L522 assume !(0 == ~t1_st~0); 894434#L526 assume !(0 == ~t2_st~0); 894432#L530 assume !(0 == ~t3_st~0); 894430#L534 assume !(0 == ~t4_st~0); 894428#L538 assume !(0 == ~t5_st~0); 894425#L542 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 894423#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 894421#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 894419#L570 assume !(0 != eval_~tmp~0#1); 894418#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 894417#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 894410#L684-3 assume !(0 == ~M_E~0); 894408#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 894406#L689-3 assume !(0 == ~T2_E~0); 894403#L694-3 assume !(0 == ~T3_E~0); 894402#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 894400#L704-3 assume !(0 == ~T5_E~0); 894395#L709-3 assume !(0 == ~T6_E~0); 894394#L714-3 assume !(0 == ~E_M~0); 894393#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 894391#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 894390#L729-3 assume !(0 == ~E_3~0); 894389#L734-3 assume !(0 == ~E_4~0); 894387#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 894386#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 894385#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 894384#L334-24 assume 1 == ~m_pc~0; 894382#L335-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 894380#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 894379#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 894378#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 894377#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 894375#L353-24 assume !(1 == ~t1_pc~0); 894374#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 894373#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 894372#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 894370#L857-24 assume !(0 != activate_threads_~tmp___0~0#1); 894368#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 894366#L372-24 assume 1 == ~t2_pc~0; 894364#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 894365#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 894376#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 894357#L865-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 894355#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 894353#L391-24 assume !(1 == ~t3_pc~0); 894351#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 891644#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 891639#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 891637#L873-24 assume !(0 != activate_threads_~tmp___2~0#1); 891635#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 891633#L410-24 assume !(1 == ~t4_pc~0); 891631#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 891629#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 891627#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 891625#L881-24 assume !(0 != activate_threads_~tmp___3~0#1); 891621#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 891619#L429-24 assume !(1 == ~t5_pc~0); 891615#L429-26 is_transmit5_triggered_~__retres1~5#1 := 0; 891613#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 891610#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 891608#L889-24 assume !(0 != activate_threads_~tmp___4~0#1); 891605#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 891603#L448-24 assume !(1 == ~t6_pc~0); 891601#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 891599#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 891597#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 891595#L897-24 assume !(0 != activate_threads_~tmp___5~0#1); 891593#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 891591#L762-3 assume !(1 == ~M_E~0); 891587#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 891585#L767-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 891583#L772-3 assume !(1 == ~T3_E~0); 891581#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 891577#L782-3 assume !(1 == ~T5_E~0); 891573#L787-3 assume !(1 == ~T6_E~0); 891570#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 891568#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 891566#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 891564#L807-3 assume 1 == ~E_3~0;~E_3~0 := 2; 891562#L812-3 assume !(1 == ~E_4~0); 891560#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 891558#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 891556#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 891552#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 891550#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 891548#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 891544#L1072 assume !(0 == start_simulation_~tmp~3#1); 891542#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 891541#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 891539#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 891538#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 891536#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 891535#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 891534#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 891533#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 891531#L1053-2 assume !false; 880824#L1054 [2024-11-08 00:35:20,931 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:20,931 INFO L85 PathProgramCache]: Analyzing trace with hash -1996793376, now seen corresponding path program 1 times [2024-11-08 00:35:20,931 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:20,932 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1844351966] [2024-11-08 00:35:20,932 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:20,932 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:20,939 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:35:20,939 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 00:35:20,942 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:35:20,948 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 00:35:20,949 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:20,949 INFO L85 PathProgramCache]: Analyzing trace with hash 242640886, now seen corresponding path program 1 times [2024-11-08 00:35:20,949 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:20,949 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1817256813] [2024-11-08 00:35:20,949 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:20,949 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:20,956 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:20,971 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:20,972 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:20,972 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1817256813] [2024-11-08 00:35:20,972 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1817256813] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:20,972 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:20,972 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:20,972 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1452939339] [2024-11-08 00:35:20,972 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:20,972 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:35:20,972 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:35:20,973 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:35:20,973 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:35:20,973 INFO L87 Difference]: Start difference. First operand 61345 states and 80897 transitions. cyclomatic complexity: 19584 Second operand has 3 states, 3 states have (on average 54.0) internal successors, (162), 3 states have internal predecessors, (162), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:21,420 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:35:21,421 INFO L93 Difference]: Finished difference Result 70139 states and 91843 transitions. [2024-11-08 00:35:21,421 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 70139 states and 91843 transitions. [2024-11-08 00:35:21,634 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 34692 [2024-11-08 00:35:21,799 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 70139 states to 70139 states and 91843 transitions. [2024-11-08 00:35:21,799 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 35046 [2024-11-08 00:35:21,822 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 35046 [2024-11-08 00:35:21,822 INFO L73 IsDeterministic]: Start isDeterministic. Operand 70139 states and 91843 transitions. [2024-11-08 00:35:21,823 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-08 00:35:21,823 INFO L218 hiAutomatonCegarLoop]: Abstraction has 70139 states and 91843 transitions. [2024-11-08 00:35:21,864 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 70139 states and 91843 transitions. [2024-11-08 00:35:22,465 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 70139 to 68219. [2024-11-08 00:35:22,519 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 68219 states, 68219 states have (on average 1.3125229041762558) internal successors, (89539), 68218 states have internal predecessors, (89539), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:22,604 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 68219 states to 68219 states and 89539 transitions. [2024-11-08 00:35:22,604 INFO L240 hiAutomatonCegarLoop]: Abstraction has 68219 states and 89539 transitions. [2024-11-08 00:35:22,605 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:35:22,605 INFO L425 stractBuchiCegarLoop]: Abstraction has 68219 states and 89539 transitions. [2024-11-08 00:35:22,605 INFO L332 stractBuchiCegarLoop]: ======== Iteration 29 ============ [2024-11-08 00:35:22,606 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 68219 states and 89539 transitions. [2024-11-08 00:35:22,734 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 33732 [2024-11-08 00:35:22,734 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:35:22,734 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:35:22,735 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:22,735 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:22,735 INFO L745 eck$LassoCheckResult]: Stem: 1000881#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 1000882#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1001166#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1001167#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1000467#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 1000468#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1001164#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1001165#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1001013#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1000577#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1000578#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1000433#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1000434#L684 assume !(0 == ~M_E~0); 1001431#L684-2 assume !(0 == ~T1_E~0); 1001080#L689-1 assume !(0 == ~T2_E~0); 1001081#L694-1 assume !(0 == ~T3_E~0); 1001078#L699-1 assume !(0 == ~T4_E~0); 1001079#L704-1 assume !(0 == ~T5_E~0); 1000979#L709-1 assume !(0 == ~T6_E~0); 1000844#L714-1 assume !(0 == ~E_M~0); 1000845#L719-1 assume !(0 == ~E_1~0); 1001357#L724-1 assume !(0 == ~E_2~0); 1000383#L729-1 assume !(0 == ~E_3~0); 1000384#L734-1 assume !(0 == ~E_4~0); 1001512#L739-1 assume !(0 == ~E_5~0); 1000768#L744-1 assume !(0 == ~E_6~0); 1000769#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1000301#L334 assume !(1 == ~m_pc~0); 1000302#L334-2 is_master_triggered_~__retres1~0#1 := 0; 1000963#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1001737#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1000713#L849 assume !(0 != activate_threads_~tmp~1#1); 1000714#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1000575#L353 assume !(1 == ~t1_pc~0); 1000576#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1001172#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1000328#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1000329#L857 assume !(0 != activate_threads_~tmp___0~0#1); 1000475#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1000476#L372 assume !(1 == ~t2_pc~0); 1000689#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1000733#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1001173#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1001174#L865 assume !(0 != activate_threads_~tmp___1~0#1); 1000281#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1000282#L391 assume !(1 == ~t3_pc~0); 1000131#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1000132#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1000182#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1000183#L873 assume !(0 != activate_threads_~tmp___2~0#1); 1000725#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1000726#L410 assume !(1 == ~t4_pc~0); 1001200#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1001201#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1000503#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1000504#L881 assume !(0 != activate_threads_~tmp___3~0#1); 1000736#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1000737#L429 assume !(1 == ~t5_pc~0); 1000393#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1000394#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1001738#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1001213#L889 assume !(0 != activate_threads_~tmp___4~0#1); 1001214#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1000710#L448 assume !(1 == ~t6_pc~0); 1000543#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1000544#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1001145#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1001146#L897 assume !(0 != activate_threads_~tmp___5~0#1); 1001577#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1001690#L762 assume !(1 == ~M_E~0); 1000803#L762-2 assume !(1 == ~T1_E~0); 1000804#L767-1 assume !(1 == ~T2_E~0); 1001587#L772-1 assume !(1 == ~T3_E~0); 1001282#L777-1 assume !(1 == ~T4_E~0); 1001044#L782-1 assume !(1 == ~T5_E~0); 1000441#L787-1 assume !(1 == ~T6_E~0); 1000439#L792-1 assume !(1 == ~E_M~0); 1000440#L797-1 assume !(1 == ~E_1~0); 1000511#L802-1 assume !(1 == ~E_2~0); 1000971#L807-1 assume !(1 == ~E_3~0); 1000972#L812-1 assume !(1 == ~E_4~0); 1001500#L817-1 assume !(1 == ~E_5~0); 1001082#L822-1 assume !(1 == ~E_6~0); 1001083#L827-1 assume { :end_inline_reset_delta_events } true; 1001525#L1053-2 assume !false; 1014287#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1047162#L659-1 [2024-11-08 00:35:22,735 INFO L747 eck$LassoCheckResult]: Loop: 1047162#L659-1 assume !false; 1047161#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1047160#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1047159#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1047157#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1047155#L570 assume 0 != eval_~tmp~0#1; 1047154#L570-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 1047152#L578 assume !(0 != eval_~tmp_ndt_1~0#1); 1047153#L578-2 havoc eval_~tmp_ndt_1~0#1; 1047188#L575-1 assume !(0 == ~t1_st~0); 1047182#L589-1 assume !(0 == ~t2_st~0); 1047179#L603-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 1047176#L620 assume !(0 != eval_~tmp_ndt_4~0#1); 1047175#L620-2 havoc eval_~tmp_ndt_4~0#1; 1047171#L617-1 assume !(0 == ~t4_st~0); 1047168#L631-1 assume !(0 == ~t5_st~0); 1047164#L645-1 assume !(0 == ~t6_st~0); 1047162#L659-1 [2024-11-08 00:35:22,735 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:22,736 INFO L85 PathProgramCache]: Analyzing trace with hash -1771052117, now seen corresponding path program 1 times [2024-11-08 00:35:22,736 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:22,736 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2144319750] [2024-11-08 00:35:22,736 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:22,736 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:22,742 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:35:22,742 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 00:35:22,745 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:35:22,751 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 00:35:22,752 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:22,752 INFO L85 PathProgramCache]: Analyzing trace with hash -530594514, now seen corresponding path program 1 times [2024-11-08 00:35:22,752 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:22,752 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1656685577] [2024-11-08 00:35:22,752 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:22,752 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:22,755 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:35:22,755 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 00:35:22,756 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:35:22,757 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 00:35:22,757 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:22,757 INFO L85 PathProgramCache]: Analyzing trace with hash -97359164, now seen corresponding path program 1 times [2024-11-08 00:35:22,757 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:22,757 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1726255686] [2024-11-08 00:35:22,757 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:22,757 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:22,763 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:22,778 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:22,778 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:22,778 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1726255686] [2024-11-08 00:35:22,778 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1726255686] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:22,778 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:22,778 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:22,778 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1186296463] [2024-11-08 00:35:22,778 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:22,823 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:35:22,823 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:35:22,823 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:35:22,823 INFO L87 Difference]: Start difference. First operand 68219 states and 89539 transitions. cyclomatic complexity: 21352 Second operand has 3 states, 3 states have (on average 34.333333333333336) internal successors, (103), 3 states have internal predecessors, (103), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:23,072 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:35:23,072 INFO L93 Difference]: Finished difference Result 128512 states and 167391 transitions. [2024-11-08 00:35:23,072 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 128512 states and 167391 transitions. [2024-11-08 00:35:23,767 INFO L131 ngComponentsAnalysis]: Automaton has 28 accepting balls. 61904 [2024-11-08 00:35:24,075 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 128512 states to 128512 states and 167391 transitions. [2024-11-08 00:35:24,075 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 64230 [2024-11-08 00:35:24,116 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 64230 [2024-11-08 00:35:24,117 INFO L73 IsDeterministic]: Start isDeterministic. Operand 128512 states and 167391 transitions. [2024-11-08 00:35:24,118 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-08 00:35:24,118 INFO L218 hiAutomatonCegarLoop]: Abstraction has 128512 states and 167391 transitions. [2024-11-08 00:35:24,200 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 128512 states and 167391 transitions. [2024-11-08 00:35:25,142 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 128512 to 124888. [2024-11-08 00:35:25,245 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 124888 states, 124888 states have (on average 1.3045208506822112) internal successors, (162919), 124887 states have internal predecessors, (162919), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:25,414 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 124888 states to 124888 states and 162919 transitions. [2024-11-08 00:35:25,415 INFO L240 hiAutomatonCegarLoop]: Abstraction has 124888 states and 162919 transitions. [2024-11-08 00:35:25,415 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:35:25,415 INFO L425 stractBuchiCegarLoop]: Abstraction has 124888 states and 162919 transitions. [2024-11-08 00:35:25,415 INFO L332 stractBuchiCegarLoop]: ======== Iteration 30 ============ [2024-11-08 00:35:25,415 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 124888 states and 162919 transitions. [2024-11-08 00:35:25,955 INFO L131 ngComponentsAnalysis]: Automaton has 28 accepting balls. 60092 [2024-11-08 00:35:25,956 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:35:25,956 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:35:25,956 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:25,956 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:25,957 INFO L745 eck$LassoCheckResult]: Stem: 1197631#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 1197632#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1197920#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1197921#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1197207#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 1197208#L475-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 1197918#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1197919#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1197760#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1197319#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1197320#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1197173#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1197174#L684 assume !(0 == ~M_E~0); 1198202#L684-2 assume !(0 == ~T1_E~0); 1197825#L689-1 assume !(0 == ~T2_E~0); 1197826#L694-1 assume !(0 == ~T3_E~0); 1197823#L699-1 assume !(0 == ~T4_E~0); 1197824#L704-1 assume !(0 == ~T5_E~0); 1197728#L709-1 assume !(0 == ~T6_E~0); 1197593#L714-1 assume !(0 == ~E_M~0); 1197594#L719-1 assume !(0 == ~E_1~0); 1198124#L724-1 assume !(0 == ~E_2~0); 1197123#L729-1 assume !(0 == ~E_3~0); 1197124#L734-1 assume !(0 == ~E_4~0); 1198293#L739-1 assume !(0 == ~E_5~0); 1197514#L744-1 assume !(0 == ~E_6~0); 1197515#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1197038#L334 assume !(1 == ~m_pc~0); 1197039#L334-2 is_master_triggered_~__retres1~0#1 := 0; 1197712#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1198309#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1197458#L849 assume !(0 != activate_threads_~tmp~1#1); 1197459#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1197317#L353 assume !(1 == ~t1_pc~0); 1197318#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1197928#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1197067#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1197068#L857 assume !(0 != activate_threads_~tmp___0~0#1); 1197215#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1197216#L372 assume !(1 == ~t2_pc~0); 1203026#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1198551#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1197929#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1197930#L865 assume !(0 != activate_threads_~tmp___1~0#1); 1197018#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1197019#L391 assume !(1 == ~t3_pc~0); 1196870#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1196871#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1196920#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1196921#L873 assume !(0 != activate_threads_~tmp___2~0#1); 1197470#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1197471#L410 assume !(1 == ~t4_pc~0); 1197961#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1197962#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1197243#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1197244#L881 assume !(0 != activate_threads_~tmp___3~0#1); 1197481#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1197482#L429 assume !(1 == ~t5_pc~0); 1197133#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1197134#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1198552#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1197975#L889 assume !(0 != activate_threads_~tmp___4~0#1); 1197976#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1197453#L448 assume !(1 == ~t6_pc~0); 1197283#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1197284#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1197896#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1197897#L897 assume !(0 != activate_threads_~tmp___5~0#1); 1198362#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1198479#L762 assume !(1 == ~M_E~0); 1197553#L762-2 assume !(1 == ~T1_E~0); 1197554#L767-1 assume !(1 == ~T2_E~0); 1198374#L772-1 assume !(1 == ~T3_E~0); 1198049#L777-1 assume !(1 == ~T4_E~0); 1197791#L782-1 assume !(1 == ~T5_E~0); 1197181#L787-1 assume !(1 == ~T6_E~0); 1197179#L792-1 assume !(1 == ~E_M~0); 1197180#L797-1 assume !(1 == ~E_1~0); 1197253#L802-1 assume !(1 == ~E_2~0); 1197721#L807-1 assume !(1 == ~E_3~0); 1197722#L812-1 assume !(1 == ~E_4~0); 1198280#L817-1 assume !(1 == ~E_5~0); 1197827#L822-1 assume !(1 == ~E_6~0); 1197828#L827-1 assume { :end_inline_reset_delta_events } true; 1202946#L1053-2 assume !false; 1202947#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1226037#L659-1 [2024-11-08 00:35:25,957 INFO L747 eck$LassoCheckResult]: Loop: 1226037#L659-1 assume !false; 1226033#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1225930#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1225927#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1225925#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1225923#L570 assume 0 != eval_~tmp~0#1; 1225921#L570-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 1225919#L578 assume !(0 != eval_~tmp_ndt_1~0#1); 1225917#L578-2 havoc eval_~tmp_ndt_1~0#1; 1225914#L575-1 assume !(0 == ~t1_st~0); 1225911#L589-1 assume !(0 == ~t2_st~0); 1225908#L603-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 1225892#L620 assume !(0 != eval_~tmp_ndt_4~0#1); 1225888#L620-2 havoc eval_~tmp_ndt_4~0#1; 1225879#L617-1 assume !(0 == ~t4_st~0); 1225880#L631-1 assume !(0 == ~t5_st~0); 1226045#L645-1 assume !(0 == ~t6_st~0); 1226037#L659-1 [2024-11-08 00:35:25,957 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:25,957 INFO L85 PathProgramCache]: Analyzing trace with hash 1466077101, now seen corresponding path program 1 times [2024-11-08 00:35:25,957 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:25,957 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [915040585] [2024-11-08 00:35:25,957 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:25,958 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:25,963 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:25,975 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:25,975 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:25,975 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [915040585] [2024-11-08 00:35:25,975 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [915040585] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:25,975 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:25,975 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:25,976 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1654503639] [2024-11-08 00:35:25,976 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:25,976 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:35:25,976 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:25,976 INFO L85 PathProgramCache]: Analyzing trace with hash -530594514, now seen corresponding path program 2 times [2024-11-08 00:35:25,976 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:25,976 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [539595396] [2024-11-08 00:35:25,976 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:25,976 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:25,978 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:35:25,979 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 00:35:25,979 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:35:25,981 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 00:35:26,024 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:35:26,024 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:35:26,025 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:35:26,025 INFO L87 Difference]: Start difference. First operand 124888 states and 162919 transitions. cyclomatic complexity: 38087 Second operand has 3 states, 3 states have (on average 28.666666666666668) internal successors, (86), 3 states have internal predecessors, (86), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:26,171 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:35:26,171 INFO L93 Difference]: Finished difference Result 81723 states and 106714 transitions. [2024-11-08 00:35:26,172 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 81723 states and 106714 transitions. [2024-11-08 00:35:26,400 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 40464 [2024-11-08 00:35:26,555 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 81723 states to 81723 states and 106714 transitions. [2024-11-08 00:35:26,555 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 40842 [2024-11-08 00:35:26,581 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 40842 [2024-11-08 00:35:26,582 INFO L73 IsDeterministic]: Start isDeterministic. Operand 81723 states and 106714 transitions. [2024-11-08 00:35:26,582 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-08 00:35:26,582 INFO L218 hiAutomatonCegarLoop]: Abstraction has 81723 states and 106714 transitions. [2024-11-08 00:35:26,630 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 81723 states and 106714 transitions. [2024-11-08 00:35:27,338 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 81723 to 81723. [2024-11-08 00:35:27,404 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 81723 states, 81723 states have (on average 1.3058013044063483) internal successors, (106714), 81722 states have internal predecessors, (106714), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:27,510 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 81723 states to 81723 states and 106714 transitions. [2024-11-08 00:35:27,510 INFO L240 hiAutomatonCegarLoop]: Abstraction has 81723 states and 106714 transitions. [2024-11-08 00:35:27,511 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:35:27,511 INFO L425 stractBuchiCegarLoop]: Abstraction has 81723 states and 106714 transitions. [2024-11-08 00:35:27,511 INFO L332 stractBuchiCegarLoop]: ======== Iteration 31 ============ [2024-11-08 00:35:27,511 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 81723 states and 106714 transitions. [2024-11-08 00:35:27,673 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 40464 [2024-11-08 00:35:27,674 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:35:27,674 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:35:27,674 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:27,674 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:27,674 INFO L745 eck$LassoCheckResult]: Stem: 1404241#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 1404242#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1404537#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1404538#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1403822#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 1403823#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1404535#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1404536#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1404375#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1403934#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1403935#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1403788#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1403789#L684 assume !(0 == ~M_E~0); 1404795#L684-2 assume !(0 == ~T1_E~0); 1404447#L689-1 assume !(0 == ~T2_E~0); 1404448#L694-1 assume !(0 == ~T3_E~0); 1404445#L699-1 assume !(0 == ~T4_E~0); 1404446#L704-1 assume !(0 == ~T5_E~0); 1404341#L709-1 assume !(0 == ~T6_E~0); 1404203#L714-1 assume !(0 == ~E_M~0); 1404204#L719-1 assume !(0 == ~E_1~0); 1404722#L724-1 assume !(0 == ~E_2~0); 1403739#L729-1 assume !(0 == ~E_3~0); 1403740#L734-1 assume !(0 == ~E_4~0); 1404877#L739-1 assume !(0 == ~E_5~0); 1404128#L744-1 assume !(0 == ~E_6~0); 1404129#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1403655#L334 assume !(1 == ~m_pc~0); 1403656#L334-2 is_master_triggered_~__retres1~0#1 := 0; 1404324#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1405090#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1404071#L849 assume !(0 != activate_threads_~tmp~1#1); 1404072#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1403932#L353 assume !(1 == ~t1_pc~0); 1403933#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1404544#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1403682#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1403683#L857 assume !(0 != activate_threads_~tmp___0~0#1); 1403831#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1403832#L372 assume !(1 == ~t2_pc~0); 1404045#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1404091#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1404545#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1404546#L865 assume !(0 != activate_threads_~tmp___1~0#1); 1403635#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1403636#L391 assume !(1 == ~t3_pc~0); 1403487#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1403488#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1403537#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1403538#L873 assume !(0 != activate_threads_~tmp___2~0#1); 1404083#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1404084#L410 assume !(1 == ~t4_pc~0); 1404571#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1404572#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1403860#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1403861#L881 assume !(0 != activate_threads_~tmp___3~0#1); 1404094#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1404095#L429 assume !(1 == ~t5_pc~0); 1403749#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1403750#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1405091#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1404583#L889 assume !(0 != activate_threads_~tmp___4~0#1); 1404584#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1404066#L448 assume !(1 == ~t6_pc~0); 1403897#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1403898#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1404513#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1404514#L897 assume !(0 != activate_threads_~tmp___5~0#1); 1404935#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1405040#L762 assume !(1 == ~M_E~0); 1404162#L762-2 assume !(1 == ~T1_E~0); 1404163#L767-1 assume !(1 == ~T2_E~0); 1404949#L772-1 assume !(1 == ~T3_E~0); 1404652#L777-1 assume !(1 == ~T4_E~0); 1404410#L782-1 assume !(1 == ~T5_E~0); 1403796#L787-1 assume !(1 == ~T6_E~0); 1403794#L792-1 assume !(1 == ~E_M~0); 1403795#L797-1 assume !(1 == ~E_1~0); 1403869#L802-1 assume !(1 == ~E_2~0); 1404333#L807-1 assume !(1 == ~E_3~0); 1404334#L812-1 assume !(1 == ~E_4~0); 1404865#L817-1 assume !(1 == ~E_5~0); 1404449#L822-1 assume !(1 == ~E_6~0); 1404450#L827-1 assume { :end_inline_reset_delta_events } true; 1404889#L1053-2 assume !false; 1418470#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1418426#L659-1 [2024-11-08 00:35:27,675 INFO L747 eck$LassoCheckResult]: Loop: 1418426#L659-1 assume !false; 1418467#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1418464#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1418462#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1418460#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1418458#L570 assume 0 != eval_~tmp~0#1; 1418456#L570-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 1418453#L578 assume !(0 != eval_~tmp_ndt_1~0#1); 1418451#L578-2 havoc eval_~tmp_ndt_1~0#1; 1418449#L575-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 1418447#L592 assume !(0 != eval_~tmp_ndt_2~0#1); 1418446#L592-2 havoc eval_~tmp_ndt_2~0#1; 1418441#L589-1 assume !(0 == ~t2_st~0); 1418438#L603-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 1418436#L620 assume !(0 != eval_~tmp_ndt_4~0#1); 1418435#L620-2 havoc eval_~tmp_ndt_4~0#1; 1418431#L617-1 assume !(0 == ~t4_st~0); 1418428#L631-1 assume !(0 == ~t5_st~0); 1418425#L645-1 assume !(0 == ~t6_st~0); 1418426#L659-1 [2024-11-08 00:35:27,675 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:27,675 INFO L85 PathProgramCache]: Analyzing trace with hash -1771052117, now seen corresponding path program 2 times [2024-11-08 00:35:27,675 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:27,675 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1789088885] [2024-11-08 00:35:27,675 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:27,675 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:27,681 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:35:27,681 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 00:35:27,684 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:35:27,691 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 00:35:27,691 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:27,691 INFO L85 PathProgramCache]: Analyzing trace with hash -423087371, now seen corresponding path program 1 times [2024-11-08 00:35:27,691 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:27,691 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [161874302] [2024-11-08 00:35:27,691 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:27,691 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:27,694 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:35:27,694 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 00:35:27,695 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:35:27,696 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 00:35:27,696 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:27,696 INFO L85 PathProgramCache]: Analyzing trace with hash -695743733, now seen corresponding path program 1 times [2024-11-08 00:35:27,696 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:27,696 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [589754238] [2024-11-08 00:35:27,696 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:27,697 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:27,702 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:27,716 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:27,716 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:27,716 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [589754238] [2024-11-08 00:35:27,716 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [589754238] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:27,716 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:27,716 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:27,716 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [332218720] [2024-11-08 00:35:27,716 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:27,768 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:35:27,769 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:35:27,769 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:35:27,769 INFO L87 Difference]: Start difference. First operand 81723 states and 106714 transitions. cyclomatic complexity: 25023 Second operand has 3 states, 3 states have (on average 35.0) internal successors, (105), 3 states have internal predecessors, (105), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:28,428 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:35:28,429 INFO L93 Difference]: Finished difference Result 154787 states and 201378 transitions. [2024-11-08 00:35:28,429 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 154787 states and 201378 transitions. [2024-11-08 00:35:28,981 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 76652 [2024-11-08 00:35:29,352 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 154787 states to 154787 states and 201378 transitions. [2024-11-08 00:35:29,353 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 77310 [2024-11-08 00:35:29,405 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 77310 [2024-11-08 00:35:29,405 INFO L73 IsDeterministic]: Start isDeterministic. Operand 154787 states and 201378 transitions. [2024-11-08 00:35:29,407 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-08 00:35:29,407 INFO L218 hiAutomatonCegarLoop]: Abstraction has 154787 states and 201378 transitions. [2024-11-08 00:35:29,504 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 154787 states and 201378 transitions. [2024-11-08 00:35:30,684 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 154787 to 147451. [2024-11-08 00:35:30,801 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 147451 states, 147451 states have (on average 1.3053421136513146) internal successors, (192474), 147450 states have internal predecessors, (192474), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:31,381 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 147451 states to 147451 states and 192474 transitions. [2024-11-08 00:35:31,381 INFO L240 hiAutomatonCegarLoop]: Abstraction has 147451 states and 192474 transitions. [2024-11-08 00:35:31,381 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:35:31,382 INFO L425 stractBuchiCegarLoop]: Abstraction has 147451 states and 192474 transitions. [2024-11-08 00:35:31,382 INFO L332 stractBuchiCegarLoop]: ======== Iteration 32 ============ [2024-11-08 00:35:31,382 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 147451 states and 192474 transitions. [2024-11-08 00:35:31,695 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 72984 [2024-11-08 00:35:31,695 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:35:31,695 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:35:31,699 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:31,700 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:31,700 INFO L745 eck$LassoCheckResult]: Stem: 1640778#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 1640779#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1641076#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1641077#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1640348#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 1640349#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1641070#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1641071#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1640907#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1640457#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1640458#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1640312#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1640313#L684 assume !(0 == ~M_E~0); 1641366#L684-2 assume !(0 == ~T1_E~0); 1640978#L689-1 assume !(0 == ~T2_E~0); 1640979#L694-1 assume !(0 == ~T3_E~0); 1640976#L699-1 assume !(0 == ~T4_E~0); 1640977#L704-1 assume !(0 == ~T5_E~0); 1640875#L709-1 assume !(0 == ~T6_E~0); 1640730#L714-1 assume !(0 == ~E_M~0); 1640731#L719-1 assume !(0 == ~E_1~0); 1641275#L724-1 assume !(0 == ~E_2~0); 1640255#L729-1 assume !(0 == ~E_3~0); 1640256#L734-1 assume !(0 == ~E_4~0); 1641464#L739-1 assume !(0 == ~E_5~0); 1640649#L744-1 assume !(0 == ~E_6~0); 1640650#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1640172#L334 assume !(1 == ~m_pc~0); 1640173#L334-2 is_master_triggered_~__retres1~0#1 := 0; 1640852#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1641737#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1640591#L849 assume !(0 != activate_threads_~tmp~1#1); 1640592#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1640451#L353 assume !(1 == ~t1_pc~0); 1640452#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1641079#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1640199#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1640200#L857 assume !(0 != activate_threads_~tmp___0~0#1); 1640350#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1640351#L372 assume !(1 == ~t2_pc~0); 1640565#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1640612#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1641080#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1641081#L865 assume !(0 != activate_threads_~tmp___1~0#1); 1640152#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1640153#L391 assume !(1 == ~t3_pc~0); 1640005#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1640006#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1640055#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1640056#L873 assume !(0 != activate_threads_~tmp___2~0#1); 1640603#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1640604#L410 assume !(1 == ~t4_pc~0); 1641114#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1641115#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1640377#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1640378#L881 assume !(0 != activate_threads_~tmp___3~0#1); 1640623#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1640624#L429 assume !(1 == ~t5_pc~0); 1640265#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1640266#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1641738#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1641124#L889 assume !(0 != activate_threads_~tmp___4~0#1); 1641125#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1640590#L448 assume !(1 == ~t6_pc~0); 1640419#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1640420#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1641054#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1641055#L897 assume !(0 != activate_threads_~tmp___5~0#1); 1641532#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1641661#L762 assume !(1 == ~M_E~0); 1640693#L762-2 assume !(1 == ~T1_E~0); 1640694#L767-1 assume !(1 == ~T2_E~0); 1641545#L772-1 assume !(1 == ~T3_E~0); 1641199#L777-1 assume !(1 == ~T4_E~0); 1640937#L782-1 assume !(1 == ~T5_E~0); 1640316#L787-1 assume !(1 == ~T6_E~0); 1640314#L792-1 assume !(1 == ~E_M~0); 1640315#L797-1 assume !(1 == ~E_1~0); 1640390#L802-1 assume !(1 == ~E_2~0); 1640861#L807-1 assume !(1 == ~E_3~0); 1640862#L812-1 assume !(1 == ~E_4~0); 1641458#L817-1 assume !(1 == ~E_5~0); 1640984#L822-1 assume !(1 == ~E_6~0); 1640985#L827-1 assume { :end_inline_reset_delta_events } true; 1641478#L1053-2 assume !false; 1646391#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1646386#L659-1 [2024-11-08 00:35:31,700 INFO L747 eck$LassoCheckResult]: Loop: 1646386#L659-1 assume !false; 1646384#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1646282#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1646160#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1645897#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1645895#L570 assume 0 != eval_~tmp~0#1; 1645884#L570-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 1645872#L578 assume !(0 != eval_~tmp_ndt_1~0#1); 1645865#L578-2 havoc eval_~tmp_ndt_1~0#1; 1645833#L575-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 1645791#L592 assume !(0 != eval_~tmp_ndt_2~0#1); 1645792#L592-2 havoc eval_~tmp_ndt_2~0#1; 1646993#L589-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 1646863#L606 assume !(0 != eval_~tmp_ndt_3~0#1); 1646988#L606-2 havoc eval_~tmp_ndt_3~0#1; 1646986#L603-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 1646983#L620 assume !(0 != eval_~tmp_ndt_4~0#1); 1646981#L620-2 havoc eval_~tmp_ndt_4~0#1; 1646598#L617-1 assume !(0 == ~t4_st~0); 1646594#L631-1 assume !(0 == ~t5_st~0); 1646389#L645-1 assume !(0 == ~t6_st~0); 1646386#L659-1 [2024-11-08 00:35:31,701 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:31,704 INFO L85 PathProgramCache]: Analyzing trace with hash -1771052117, now seen corresponding path program 3 times [2024-11-08 00:35:31,704 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:31,704 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [724231777] [2024-11-08 00:35:31,704 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:31,704 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:31,712 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:35:31,713 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 00:35:31,716 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:35:31,724 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 00:35:31,725 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:31,725 INFO L85 PathProgramCache]: Analyzing trace with hash 1515958958, now seen corresponding path program 1 times [2024-11-08 00:35:31,725 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:31,725 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1971991733] [2024-11-08 00:35:31,725 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:31,725 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:31,727 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:35:31,728 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 00:35:31,729 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:35:31,730 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 00:35:31,731 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:31,731 INFO L85 PathProgramCache]: Analyzing trace with hash 1486200132, now seen corresponding path program 1 times [2024-11-08 00:35:31,731 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:31,731 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1884314428] [2024-11-08 00:35:31,731 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:31,731 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:31,736 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:31,752 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:31,752 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:31,752 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1884314428] [2024-11-08 00:35:31,752 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1884314428] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:31,752 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:31,752 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:31,752 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [486383130] [2024-11-08 00:35:31,752 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:31,807 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:35:31,807 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:35:31,807 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:35:31,807 INFO L87 Difference]: Start difference. First operand 147451 states and 192474 transitions. cyclomatic complexity: 45055 Second operand has 3 states, 3 states have (on average 35.666666666666664) internal successors, (107), 3 states have internal predecessors, (107), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:32,227 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:35:32,227 INFO L93 Difference]: Finished difference Result 173751 states and 224990 transitions. [2024-11-08 00:35:32,227 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 173751 states and 224990 transitions. [2024-11-08 00:35:33,107 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 86088 [2024-11-08 00:35:33,399 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 173751 states to 173751 states and 224990 transitions. [2024-11-08 00:35:33,399 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 86826 [2024-11-08 00:35:33,439 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 86826 [2024-11-08 00:35:33,439 INFO L73 IsDeterministic]: Start isDeterministic. Operand 173751 states and 224990 transitions. [2024-11-08 00:35:33,460 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-08 00:35:33,460 INFO L218 hiAutomatonCegarLoop]: Abstraction has 173751 states and 224990 transitions. [2024-11-08 00:35:33,553 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 173751 states and 224990 transitions. [2024-11-08 00:35:34,978 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 173751 to 173751. [2024-11-08 00:35:35,125 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 173751 states, 173751 states have (on average 1.2948990221639012) internal successors, (224990), 173750 states have internal predecessors, (224990), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:35,840 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 173751 states to 173751 states and 224990 transitions. [2024-11-08 00:35:35,841 INFO L240 hiAutomatonCegarLoop]: Abstraction has 173751 states and 224990 transitions. [2024-11-08 00:35:35,841 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:35:35,841 INFO L425 stractBuchiCegarLoop]: Abstraction has 173751 states and 224990 transitions. [2024-11-08 00:35:35,841 INFO L332 stractBuchiCegarLoop]: ======== Iteration 33 ============ [2024-11-08 00:35:35,841 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 173751 states and 224990 transitions. [2024-11-08 00:35:36,125 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 86088 [2024-11-08 00:35:36,126 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:35:36,126 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:35:36,126 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:36,126 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:36,127 INFO L745 eck$LassoCheckResult]: Stem: 1961984#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 1961985#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1962281#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1962282#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1961558#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 1961559#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1962275#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1962276#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1962118#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1961671#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1961672#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1961522#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1961523#L684 assume !(0 == ~M_E~0); 1962567#L684-2 assume !(0 == ~T1_E~0); 1962185#L689-1 assume !(0 == ~T2_E~0); 1962186#L694-1 assume !(0 == ~T3_E~0); 1962183#L699-1 assume !(0 == ~T4_E~0); 1962184#L704-1 assume !(0 == ~T5_E~0); 1962086#L709-1 assume !(0 == ~T6_E~0); 1961938#L714-1 assume !(0 == ~E_M~0); 1961939#L719-1 assume !(0 == ~E_1~0); 1962473#L724-1 assume !(0 == ~E_2~0); 1961467#L729-1 assume !(0 == ~E_3~0); 1961468#L734-1 assume !(0 == ~E_4~0); 1962663#L739-1 assume !(0 == ~E_5~0); 1961860#L744-1 assume !(0 == ~E_6~0); 1961861#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1961384#L334 assume !(1 == ~m_pc~0); 1961385#L334-2 is_master_triggered_~__retres1~0#1 := 0; 1962063#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1962913#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1961804#L849 assume !(0 != activate_threads_~tmp~1#1); 1961805#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1961665#L353 assume !(1 == ~t1_pc~0); 1961666#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1962283#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1961411#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1961412#L857 assume !(0 != activate_threads_~tmp___0~0#1); 1961560#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1961561#L372 assume !(1 == ~t2_pc~0); 1961780#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1961822#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1962284#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1962285#L865 assume !(0 != activate_threads_~tmp___1~0#1); 1961363#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1961364#L391 assume !(1 == ~t3_pc~0); 1961215#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1961216#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1961266#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1961267#L873 assume !(0 != activate_threads_~tmp___2~0#1); 1961814#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1961815#L410 assume !(1 == ~t4_pc~0); 1962314#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1962315#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1961590#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1961591#L881 assume !(0 != activate_threads_~tmp___3~0#1); 1961834#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1961835#L429 assume !(1 == ~t5_pc~0); 1961477#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1961478#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1962914#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1962325#L889 assume !(0 != activate_threads_~tmp___4~0#1); 1962326#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1961803#L448 assume !(1 == ~t6_pc~0); 1961631#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1961632#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1962260#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1962261#L897 assume !(0 != activate_threads_~tmp___5~0#1); 1962736#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1962860#L762 assume !(1 == ~M_E~0); 1961900#L762-2 assume !(1 == ~T1_E~0); 1961901#L767-1 assume !(1 == ~T2_E~0); 1962748#L772-1 assume !(1 == ~T3_E~0); 1962402#L777-1 assume !(1 == ~T4_E~0); 1962150#L782-1 assume !(1 == ~T5_E~0); 1961526#L787-1 assume !(1 == ~T6_E~0); 1961524#L792-1 assume !(1 == ~E_M~0); 1961525#L797-1 assume !(1 == ~E_1~0); 1961602#L802-1 assume !(1 == ~E_2~0); 1962072#L807-1 assume !(1 == ~E_3~0); 1962073#L812-1 assume !(1 == ~E_4~0); 1962655#L817-1 assume !(1 == ~E_5~0); 1962191#L822-1 assume !(1 == ~E_6~0); 1962192#L827-1 assume { :end_inline_reset_delta_events } true; 1962678#L1053-2 assume !false; 1969105#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1969100#L659-1 [2024-11-08 00:35:36,127 INFO L747 eck$LassoCheckResult]: Loop: 1969100#L659-1 assume !false; 1969098#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1969096#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1969095#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1969094#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1969090#L570 assume 0 != eval_~tmp~0#1; 1969088#L570-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 1969085#L578 assume !(0 != eval_~tmp_ndt_1~0#1); 1969084#L578-2 havoc eval_~tmp_ndt_1~0#1; 1969081#L575-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 1969079#L592 assume !(0 != eval_~tmp_ndt_2~0#1); 1969078#L592-2 havoc eval_~tmp_ndt_2~0#1; 1969076#L589-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 1969029#L606 assume !(0 != eval_~tmp_ndt_3~0#1); 1969075#L606-2 havoc eval_~tmp_ndt_3~0#1; 1969128#L603-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 1969123#L620 assume !(0 != eval_~tmp_ndt_4~0#1); 1969121#L620-2 havoc eval_~tmp_ndt_4~0#1; 1969119#L617-1 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;havoc eval_#t~nondet10#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 1969117#L634 assume !(0 != eval_~tmp_ndt_5~0#1); 1969114#L634-2 havoc eval_~tmp_ndt_5~0#1; 1969111#L631-1 assume !(0 == ~t5_st~0); 1969103#L645-1 assume !(0 == ~t6_st~0); 1969100#L659-1 [2024-11-08 00:35:36,127 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:36,127 INFO L85 PathProgramCache]: Analyzing trace with hash -1771052117, now seen corresponding path program 4 times [2024-11-08 00:35:36,127 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:36,127 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1149319645] [2024-11-08 00:35:36,127 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:36,128 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:36,133 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:35:36,133 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 00:35:36,136 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:35:36,142 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 00:35:36,142 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:36,142 INFO L85 PathProgramCache]: Analyzing trace with hash 650449639, now seen corresponding path program 1 times [2024-11-08 00:35:36,142 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:36,142 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1862979607] [2024-11-08 00:35:36,142 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:36,142 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:36,144 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:35:36,144 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-08 00:35:36,145 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-08 00:35:36,146 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-08 00:35:36,146 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:36,147 INFO L85 PathProgramCache]: Analyzing trace with hash 2116988925, now seen corresponding path program 1 times [2024-11-08 00:35:36,147 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:36,147 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1383404368] [2024-11-08 00:35:36,147 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:36,147 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:36,152 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:36,163 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:36,163 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:36,164 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1383404368] [2024-11-08 00:35:36,164 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1383404368] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:36,164 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:36,164 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:36,164 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1487915422] [2024-11-08 00:35:36,164 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:36,218 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:35:36,219 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:35:36,219 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:35:36,219 INFO L87 Difference]: Start difference. First operand 173751 states and 224990 transitions. cyclomatic complexity: 51271 Second operand has 3 states, 3 states have (on average 36.333333333333336) internal successors, (109), 3 states have internal predecessors, (109), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:37,277 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:35:37,277 INFO L93 Difference]: Finished difference Result 312423 states and 403530 transitions. [2024-11-08 00:35:37,277 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 312423 states and 403530 transitions. [2024-11-08 00:35:38,180 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 154688 [2024-11-08 00:35:39,208 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 312423 states to 312423 states and 403530 transitions. [2024-11-08 00:35:39,208 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 156066 [2024-11-08 00:35:39,286 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 156066 [2024-11-08 00:35:39,286 INFO L73 IsDeterministic]: Start isDeterministic. Operand 312423 states and 403530 transitions. [2024-11-08 00:35:39,287 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-08 00:35:39,287 INFO L218 hiAutomatonCegarLoop]: Abstraction has 312423 states and 403530 transitions. [2024-11-08 00:35:39,441 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 312423 states and 403530 transitions.