./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.13.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 4f9af400 extending candidate: java ['java'] extending candidate: /usr/bin/java ['java', '/usr/bin/java'] extending candidate: /opt/oracle-jdk-bin-*/bin/java ['java', '/usr/bin/java'] extending candidate: /opt/openjdk-*/bin/java ['java', '/usr/bin/java'] extending candidate: /usr/lib/jvm/java-*-openjdk-amd64/bin/java ['java', '/usr/bin/java', '/usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java', '/usr/lib/jvm/java-17-openjdk-amd64/bin/java', '/usr/lib/jvm/java-11-openjdk-amd64/bin/java', '/usr/lib/jvm/java-1.17.0-openjdk-amd64/bin/java'] ['/root/.sdkman/candidates/java/21.0.5-tem/bin/java', '-Dosgi.configuration.area=/storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/config', '-Xmx15G', '-Xms4m', '-jar', '/storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar', '-data', '@noDefault', '-ultimatedata', '/storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data', '-tc', '/storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml', '-i', '../sv-benchmarks/c/systemc/token_ring.13.cil-1.c', '-s', '/storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf', '--cacsl2boogietranslator.entry.function', 'main', '--witnessprinter.witness.directory', '/storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux', '--witnessprinter.witness.filename', 'witness', '--witnessprinter.write.witness.besides.input.file', 'false', '--witnessprinter.graph.data.specification', 'CHECK( init(main()), LTL(F end) )\n\n', '--witnessprinter.graph.data.producer', 'Automizer', '--witnessprinter.graph.data.architecture', '32bit', '--witnessprinter.graph.data.programhash', '1b2c6a3c4af8091017033117c21d8fbc40cee2009788b890a114045d77587077'] Calling Ultimate with: /root/.sdkman/candidates/java/21.0.5-tem/bin/java -Dosgi.configuration.area=/storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.13.cil-1.c -s /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 1b2c6a3c4af8091017033117c21d8fbc40cee2009788b890a114045d77587077 --- Real Ultimate output --- This is Ultimate 0.3.0-?-4f9af40 [2024-11-08 00:35:46,122 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-08 00:35:46,197 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-11-08 00:35:46,205 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-08 00:35:46,207 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-08 00:35:46,230 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-08 00:35:46,232 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-08 00:35:46,232 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-08 00:35:46,233 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-08 00:35:46,233 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-08 00:35:46,234 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-08 00:35:46,234 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-08 00:35:46,234 INFO L153 SettingsManager]: * Use SBE=true [2024-11-08 00:35:46,234 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-11-08 00:35:46,235 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-11-08 00:35:46,235 INFO L153 SettingsManager]: * Use old map elimination=false [2024-11-08 00:35:46,235 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-11-08 00:35:46,235 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-11-08 00:35:46,235 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-11-08 00:35:46,235 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-08 00:35:46,236 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-11-08 00:35:46,236 INFO L153 SettingsManager]: * sizeof long=4 [2024-11-08 00:35:46,236 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-08 00:35:46,236 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-11-08 00:35:46,236 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-08 00:35:46,236 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-11-08 00:35:46,236 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-11-08 00:35:46,236 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-11-08 00:35:46,236 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-11-08 00:35:46,236 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-11-08 00:35:46,236 INFO L153 SettingsManager]: * sizeof long double=12 [2024-11-08 00:35:46,237 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-08 00:35:46,237 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-11-08 00:35:46,237 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-08 00:35:46,237 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-11-08 00:35:46,237 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-08 00:35:46,238 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-08 00:35:46,238 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-11-08 00:35:46,238 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-11-08 00:35:46,238 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 1b2c6a3c4af8091017033117c21d8fbc40cee2009788b890a114045d77587077 [2024-11-08 00:35:46,477 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-08 00:35:46,487 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-08 00:35:46,489 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-08 00:35:46,490 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-08 00:35:46,490 INFO L274 PluginConnector]: CDTParser initialized [2024-11-08 00:35:46,491 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.13.cil-1.c [2024-11-08 00:35:47,764 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-11-08 00:35:48,007 INFO L384 CDTParser]: Found 1 translation units. [2024-11-08 00:35:48,011 INFO L180 CDTParser]: Scanning /storage/repos/ultimate-jdk21/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.13.cil-1.c [2024-11-08 00:35:48,025 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/f55bb2513/22a30bf9efed439d837e1a0bdc003a16/FLAG5d8477f17 [2024-11-08 00:35:48,043 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/f55bb2513/22a30bf9efed439d837e1a0bdc003a16 [2024-11-08 00:35:48,045 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-08 00:35:48,046 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-08 00:35:48,048 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-08 00:35:48,048 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-08 00:35:48,051 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-08 00:35:48,052 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 08.11 12:35:48" (1/1) ... [2024-11-08 00:35:48,053 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@19f43d1d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 12:35:48, skipping insertion in model container [2024-11-08 00:35:48,054 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 08.11 12:35:48" (1/1) ... [2024-11-08 00:35:48,087 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-08 00:35:48,316 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-08 00:35:48,325 INFO L200 MainTranslator]: Completed pre-run [2024-11-08 00:35:48,372 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-08 00:35:48,387 INFO L204 MainTranslator]: Completed translation [2024-11-08 00:35:48,387 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 12:35:48 WrapperNode [2024-11-08 00:35:48,388 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-08 00:35:48,388 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-08 00:35:48,388 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-08 00:35:48,389 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-08 00:35:48,393 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 12:35:48" (1/1) ... [2024-11-08 00:35:48,405 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 12:35:48" (1/1) ... [2024-11-08 00:35:48,512 INFO L138 Inliner]: procedures = 54, calls = 72, calls flagged for inlining = 67, calls inlined = 305, statements flattened = 4696 [2024-11-08 00:35:48,513 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-08 00:35:48,514 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-08 00:35:48,514 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-08 00:35:48,514 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-08 00:35:48,520 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 12:35:48" (1/1) ... [2024-11-08 00:35:48,521 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 12:35:48" (1/1) ... [2024-11-08 00:35:48,534 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 12:35:48" (1/1) ... [2024-11-08 00:35:48,570 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-11-08 00:35:48,571 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 12:35:48" (1/1) ... [2024-11-08 00:35:48,571 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 12:35:48" (1/1) ... [2024-11-08 00:35:48,630 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 12:35:48" (1/1) ... [2024-11-08 00:35:48,658 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 12:35:48" (1/1) ... [2024-11-08 00:35:48,663 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 12:35:48" (1/1) ... [2024-11-08 00:35:48,667 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 12:35:48" (1/1) ... [2024-11-08 00:35:48,675 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-08 00:35:48,676 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-11-08 00:35:48,676 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-11-08 00:35:48,676 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-11-08 00:35:48,677 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 12:35:48" (1/1) ... [2024-11-08 00:35:48,682 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 00:35:48,691 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2024-11-08 00:35:48,703 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 00:35:48,708 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-11-08 00:35:48,725 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-08 00:35:48,726 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-11-08 00:35:48,726 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-08 00:35:48,726 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-08 00:35:48,838 INFO L238 CfgBuilder]: Building ICFG [2024-11-08 00:35:48,839 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-08 00:35:51,642 INFO L? ?]: Removed 1008 outVars from TransFormulas that were not future-live. [2024-11-08 00:35:51,642 INFO L287 CfgBuilder]: Performing block encoding [2024-11-08 00:35:51,701 INFO L311 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-08 00:35:51,701 INFO L316 CfgBuilder]: Removed 16 assume(true) statements. [2024-11-08 00:35:51,701 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 08.11 12:35:51 BoogieIcfgContainer [2024-11-08 00:35:51,702 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-11-08 00:35:51,706 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-11-08 00:35:51,707 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-11-08 00:35:51,714 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-11-08 00:35:51,715 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-08 00:35:51,715 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 08.11 12:35:48" (1/3) ... [2024-11-08 00:35:51,716 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@6ba7c281 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 08.11 12:35:51, skipping insertion in model container [2024-11-08 00:35:51,716 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-08 00:35:51,716 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 12:35:48" (2/3) ... [2024-11-08 00:35:51,716 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@6ba7c281 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 08.11 12:35:51, skipping insertion in model container [2024-11-08 00:35:51,716 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-08 00:35:51,716 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 08.11 12:35:51" (3/3) ... [2024-11-08 00:35:51,721 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.13.cil-1.c [2024-11-08 00:35:51,795 INFO L300 stractBuchiCegarLoop]: Interprodecural is true [2024-11-08 00:35:51,795 INFO L301 stractBuchiCegarLoop]: Hoare is None [2024-11-08 00:35:51,795 INFO L302 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-11-08 00:35:51,795 INFO L303 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-11-08 00:35:51,795 INFO L304 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-11-08 00:35:51,795 INFO L305 stractBuchiCegarLoop]: Difference is false [2024-11-08 00:35:51,795 INFO L306 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-11-08 00:35:51,795 INFO L310 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-11-08 00:35:51,803 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 2047 states, 2046 states have (on average 1.4926686217008798) internal successors, (3054), 2046 states have internal predecessors, (3054), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:51,851 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1868 [2024-11-08 00:35:51,851 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:35:51,851 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:35:51,862 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:51,862 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:51,862 INFO L332 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-11-08 00:35:51,865 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 2047 states, 2046 states have (on average 1.4926686217008798) internal successors, (3054), 2046 states have internal predecessors, (3054), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:51,888 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1868 [2024-11-08 00:35:51,891 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:35:51,891 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:35:51,899 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:51,899 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:51,910 INFO L745 eck$LassoCheckResult]: Stem: 138#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 1967#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 740#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1959#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1864#L914true assume !(1 == ~m_i~0);~m_st~0 := 2; 846#L914-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 455#L919-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1235#L924-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1119#L929-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1871#L934-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1276#L939-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1657#L944-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 312#L949-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 1326#L954-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 1976#L959-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 651#L964-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 1185#L969-1true assume !(1 == ~t12_i~0);~t12_st~0 := 2; 1779#L974-1true assume !(1 == ~t13_i~0);~t13_st~0 := 2; 593#L979-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1903#L1291true assume 0 == ~M_E~0;~M_E~0 := 1; 1867#L1291-2true assume !(0 == ~T1_E~0); 1859#L1296-1true assume !(0 == ~T2_E~0); 700#L1301-1true assume !(0 == ~T3_E~0); 1230#L1306-1true assume !(0 == ~T4_E~0); 1204#L1311-1true assume !(0 == ~T5_E~0); 228#L1316-1true assume !(0 == ~T6_E~0); 1661#L1321-1true assume !(0 == ~T7_E~0); 711#L1326-1true assume 0 == ~T8_E~0;~T8_E~0 := 1; 136#L1331-1true assume !(0 == ~T9_E~0); 3#L1336-1true assume !(0 == ~T10_E~0); 1082#L1341-1true assume !(0 == ~T11_E~0); 33#L1346-1true assume !(0 == ~T12_E~0); 1459#L1351-1true assume !(0 == ~T13_E~0); 195#L1356-1true assume !(0 == ~E_M~0); 1985#L1361-1true assume !(0 == ~E_1~0); 1633#L1366-1true assume 0 == ~E_2~0;~E_2~0 := 1; 219#L1371-1true assume !(0 == ~E_3~0); 1437#L1376-1true assume !(0 == ~E_4~0); 764#L1381-1true assume !(0 == ~E_5~0); 1737#L1386-1true assume !(0 == ~E_6~0); 1896#L1391-1true assume !(0 == ~E_7~0); 1811#L1396-1true assume !(0 == ~E_8~0); 671#L1401-1true assume !(0 == ~E_9~0); 1292#L1406-1true assume 0 == ~E_10~0;~E_10~0 := 1; 917#L1411-1true assume !(0 == ~E_11~0); 1695#L1416-1true assume !(0 == ~E_12~0); 619#L1421-1true assume !(0 == ~E_13~0); 322#L1426-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 769#L640true assume !(1 == ~m_pc~0); 1815#L640-2true is_master_triggered_~__retres1~0#1 := 0; 727#L651true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 623#is_master_triggered_returnLabel#1true activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 643#L1603true assume !(0 != activate_threads_~tmp~1#1); 1277#L1603-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 410#L659true assume 1 == ~t1_pc~0; 473#L660true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1419#L670true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1044#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 486#L1611true assume !(0 != activate_threads_~tmp___0~0#1); 495#L1611-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1601#L678true assume 1 == ~t2_pc~0; 1460#L679true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1715#L689true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 241#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 556#L1619true assume !(0 != activate_threads_~tmp___1~0#1); 696#L1619-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 640#L697true assume !(1 == ~t3_pc~0); 747#L697-2true is_transmit3_triggered_~__retres1~3#1 := 0; 1505#L708true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1026#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 580#L1627true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1927#L1627-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1542#L716true assume 1 == ~t4_pc~0; 1514#L717true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 397#L727true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 64#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 118#L1635true assume !(0 != activate_threads_~tmp___3~0#1); 991#L1635-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1484#L735true assume !(1 == ~t5_pc~0); 104#L735-2true is_transmit5_triggered_~__retres1~5#1 := 0; 338#L746true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1648#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1015#L1643true assume !(0 != activate_threads_~tmp___4~0#1); 693#L1643-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 884#L754true assume 1 == ~t6_pc~0; 529#L755true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 464#L765true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 230#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 447#L1651true assume !(0 != activate_threads_~tmp___5~0#1); 1108#L1651-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1974#L773true assume !(1 == ~t7_pc~0); 904#L773-2true is_transmit7_triggered_~__retres1~7#1 := 0; 729#L784true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1987#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 702#L1659true assume !(0 != activate_threads_~tmp___6~0#1); 757#L1659-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 892#L792true assume 1 == ~t8_pc~0; 1969#L793true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1278#L803true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1571#is_transmit8_triggered_returnLabel#1true activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 694#L1667true assume !(0 != activate_threads_~tmp___7~0#1); 641#L1667-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 813#L811true assume 1 == ~t9_pc~0; 1341#L812true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1710#L822true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 269#is_transmit9_triggered_returnLabel#1true activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 809#L1675true assume !(0 != activate_threads_~tmp___8~0#1); 648#L1675-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1740#L830true assume !(1 == ~t10_pc~0); 2034#L830-2true is_transmit10_triggered_~__retres1~10#1 := 0; 185#L841true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1355#is_transmit10_triggered_returnLabel#1true activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 173#L1683true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1806#L1683-2true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1130#L849true assume 1 == ~t11_pc~0; 1629#L850true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 92#L860true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1461#is_transmit11_triggered_returnLabel#1true activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1149#L1691true assume !(0 != activate_threads_~tmp___10~0#1); 1021#L1691-2true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1813#L868true assume !(1 == ~t12_pc~0); 1391#L868-2true is_transmit12_triggered_~__retres1~12#1 := 0; 576#L879true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 40#is_transmit12_triggered_returnLabel#1true activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1730#L1699true assume !(0 != activate_threads_~tmp___11~0#1); 203#L1699-2true assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1631#L887true assume 1 == ~t13_pc~0; 1031#L888true assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 577#L898true is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1396#is_transmit13_triggered_returnLabel#1true activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 1097#L1707true assume !(0 != activate_threads_~tmp___12~0#1); 57#L1707-2true havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1687#L1439true assume !(1 == ~M_E~0); 689#L1439-2true assume !(1 == ~T1_E~0); 143#L1444-1true assume !(1 == ~T2_E~0); 922#L1449-1true assume 1 == ~T3_E~0;~T3_E~0 := 2; 412#L1454-1true assume !(1 == ~T4_E~0); 1458#L1459-1true assume !(1 == ~T5_E~0); 806#L1464-1true assume !(1 == ~T6_E~0); 868#L1469-1true assume !(1 == ~T7_E~0); 1718#L1474-1true assume !(1 == ~T8_E~0); 620#L1479-1true assume !(1 == ~T9_E~0); 810#L1484-1true assume !(1 == ~T10_E~0); 1249#L1489-1true assume 1 == ~T11_E~0;~T11_E~0 := 2; 542#L1494-1true assume !(1 == ~T12_E~0); 1849#L1499-1true assume !(1 == ~T13_E~0); 661#L1504-1true assume !(1 == ~E_M~0); 1513#L1509-1true assume !(1 == ~E_1~0); 1247#L1514-1true assume !(1 == ~E_2~0); 893#L1519-1true assume !(1 == ~E_3~0); 1968#L1524-1true assume !(1 == ~E_4~0); 1676#L1529-1true assume 1 == ~E_5~0;~E_5~0 := 2; 1780#L1534-1true assume !(1 == ~E_6~0); 54#L1539-1true assume !(1 == ~E_7~0); 267#L1544-1true assume !(1 == ~E_8~0); 1593#L1549-1true assume !(1 == ~E_9~0); 1617#L1554-1true assume !(1 == ~E_10~0); 1589#L1559-1true assume !(1 == ~E_11~0); 1316#L1564-1true assume !(1 == ~E_12~0); 1658#L1569-1true assume 1 == ~E_13~0;~E_13~0 := 2; 1756#L1574-1true assume { :end_inline_reset_delta_events } true; 142#L1940-2true [2024-11-08 00:35:51,919 INFO L747 eck$LassoCheckResult]: Loop: 142#L1940-2true assume !false; 1560#L1941true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1831#L1266-1true assume false; 571#eval_returnLabel#1true havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 359#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 974#L1291-3true assume 0 == ~M_E~0;~M_E~0 := 1; 869#L1291-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 1876#L1296-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 1783#L1301-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 1615#L1306-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 596#L1311-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 161#L1316-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 214#L1321-3true assume !(0 == ~T7_E~0); 684#L1326-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 1578#L1331-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 897#L1336-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 1499#L1341-3true assume 0 == ~T11_E~0;~T11_E~0 := 1; 408#L1346-3true assume 0 == ~T12_E~0;~T12_E~0 := 1; 393#L1351-3true assume 0 == ~T13_E~0;~T13_E~0 := 1; 358#L1356-3true assume 0 == ~E_M~0;~E_M~0 := 1; 748#L1361-3true assume !(0 == ~E_1~0); 777#L1366-3true assume 0 == ~E_2~0;~E_2~0 := 1; 24#L1371-3true assume 0 == ~E_3~0;~E_3~0 := 1; 1286#L1376-3true assume 0 == ~E_4~0;~E_4~0 := 1; 1551#L1381-3true assume 0 == ~E_5~0;~E_5~0 := 1; 1084#L1386-3true assume 0 == ~E_6~0;~E_6~0 := 1; 1685#L1391-3true assume 0 == ~E_7~0;~E_7~0 := 1; 1332#L1396-3true assume 0 == ~E_8~0;~E_8~0 := 1; 1990#L1401-3true assume !(0 == ~E_9~0); 192#L1406-3true assume 0 == ~E_10~0;~E_10~0 := 1; 122#L1411-3true assume 0 == ~E_11~0;~E_11~0 := 1; 1782#L1416-3true assume 0 == ~E_12~0;~E_12~0 := 1; 502#L1421-3true assume 0 == ~E_13~0;~E_13~0 := 1; 1118#L1426-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 574#L640-45true assume 1 == ~m_pc~0; 1144#L641-15true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 247#L651-15true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 939#is_master_triggered_returnLabel#16true activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 22#L1603-45true assume !(0 != activate_threads_~tmp~1#1); 1870#L1603-47true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 60#L659-45true assume 1 == ~t1_pc~0; 1932#L660-15true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1796#L670-15true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1873#is_transmit1_triggered_returnLabel#16true activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1556#L1611-45true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 999#L1611-47true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1525#L678-45true assume !(1 == ~t2_pc~0); 978#L678-47true is_transmit2_triggered_~__retres1~2#1 := 0; 578#L689-15true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 936#is_transmit2_triggered_returnLabel#16true activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1363#L1619-45true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1672#L1619-47true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1609#L697-45true assume !(1 == ~t3_pc~0); 1242#L697-47true is_transmit3_triggered_~__retres1~3#1 := 0; 1863#L708-15true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2007#is_transmit3_triggered_returnLabel#16true activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 905#L1627-45true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 941#L1627-47true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2030#L716-45true assume !(1 == ~t4_pc~0); 1074#L716-47true is_transmit4_triggered_~__retres1~4#1 := 0; 2025#L727-15true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1295#is_transmit4_triggered_returnLabel#16true activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 631#L1635-45true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1508#L1635-47true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 418#L735-45true assume 1 == ~t5_pc~0; 803#L736-15true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1664#L746-15true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2002#is_transmit5_triggered_returnLabel#16true activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1844#L1643-45true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1670#L1643-47true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1654#L754-45true assume !(1 == ~t6_pc~0); 1494#L754-47true is_transmit6_triggered_~__retres1~6#1 := 0; 2008#L765-15true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 668#is_transmit6_triggered_returnLabel#16true activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1980#L1651-45true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 770#L1651-47true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 560#L773-45true assume 1 == ~t7_pc~0; 1175#L774-15true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 948#L784-15true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 738#is_transmit7_triggered_returnLabel#16true activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1395#L1659-45true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 568#L1659-47true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 355#L792-45true assume 1 == ~t8_pc~0; 1507#L793-15true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1196#L803-15true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1725#is_transmit8_triggered_returnLabel#16true activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 70#L1667-45true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 728#L1667-47true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 327#L811-45true assume 1 == ~t9_pc~0; 211#L812-15true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1098#L822-15true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1079#is_transmit9_triggered_returnLabel#16true activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 932#L1675-45true assume !(0 != activate_threads_~tmp___8~0#1); 614#L1675-47true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 477#L830-45true assume !(1 == ~t10_pc~0); 38#L830-47true is_transmit10_triggered_~__retres1~10#1 := 0; 688#L841-15true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1195#is_transmit10_triggered_returnLabel#16true activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 148#L1683-45true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1371#L1683-47true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 31#L849-45true assume 1 == ~t11_pc~0; 739#L850-15true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 255#L860-15true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 177#is_transmit11_triggered_returnLabel#16true activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 25#L1691-45true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 175#L1691-47true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 146#L868-45true assume 1 == ~t12_pc~0; 404#L869-15true assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 115#L879-15true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1123#is_transmit12_triggered_returnLabel#16true activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1929#L1699-45true assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1385#L1699-47true assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1949#L887-45true assume 1 == ~t13_pc~0; 1124#L888-15true assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 1033#L898-15true is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1056#is_transmit13_triggered_returnLabel#16true activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 1957#L1707-45true assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 132#L1707-47true havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1050#L1439-3true assume 1 == ~M_E~0;~M_E~0 := 2; 1025#L1439-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 141#L1444-3true assume !(1 == ~T2_E~0); 221#L1449-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 1614#L1454-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 857#L1459-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 2028#L1464-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 1393#L1469-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 1291#L1474-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 1623#L1479-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 1397#L1484-3true assume !(1 == ~T10_E~0); 600#L1489-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 1177#L1494-3true assume 1 == ~T12_E~0;~T12_E~0 := 2; 1807#L1499-3true assume 1 == ~T13_E~0;~T13_E~0 := 2; 819#L1504-3true assume 1 == ~E_M~0;~E_M~0 := 2; 1311#L1509-3true assume 1 == ~E_1~0;~E_1~0 := 2; 1364#L1514-3true assume 1 == ~E_2~0;~E_2~0 := 2; 1907#L1519-3true assume 1 == ~E_3~0;~E_3~0 := 2; 547#L1524-3true assume !(1 == ~E_4~0); 1443#L1529-3true assume 1 == ~E_5~0;~E_5~0 := 2; 1675#L1534-3true assume 1 == ~E_6~0;~E_6~0 := 2; 754#L1539-3true assume 1 == ~E_7~0;~E_7~0 := 2; 384#L1544-3true assume 1 == ~E_8~0;~E_8~0 := 2; 1407#L1549-3true assume 1 == ~E_9~0;~E_9~0 := 2; 714#L1554-3true assume 1 == ~E_10~0;~E_10~0 := 2; 164#L1559-3true assume 1 == ~E_11~0;~E_11~0 := 2; 1206#L1564-3true assume !(1 == ~E_12~0); 942#L1569-3true assume 1 == ~E_13~0;~E_13~0 := 2; 1169#L1574-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 110#L992-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 160#L1064-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 205#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 113#L1959true assume !(0 == start_simulation_~tmp~3#1); 128#L1959-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 900#L992-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 980#L1064-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 29#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 1429#L1914true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1600#L1921true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1374#stop_simulation_returnLabel#1true start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 1616#L1972true assume !(0 != start_simulation_~tmp___0~1#1); 142#L1940-2true [2024-11-08 00:35:51,930 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:51,930 INFO L85 PathProgramCache]: Analyzing trace with hash 1878318605, now seen corresponding path program 1 times [2024-11-08 00:35:51,939 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:51,940 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1821049130] [2024-11-08 00:35:51,940 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:51,940 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:52,073 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:52,333 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:52,334 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:52,334 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1821049130] [2024-11-08 00:35:52,335 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1821049130] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:52,335 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:52,335 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:52,336 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1702129208] [2024-11-08 00:35:52,336 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:52,339 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:35:52,339 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:52,340 INFO L85 PathProgramCache]: Analyzing trace with hash -462906928, now seen corresponding path program 1 times [2024-11-08 00:35:52,340 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:52,340 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [424082957] [2024-11-08 00:35:52,340 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:52,340 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:52,355 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:52,391 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:52,392 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:52,392 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [424082957] [2024-11-08 00:35:52,392 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [424082957] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:52,392 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:52,392 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-08 00:35:52,393 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2070588668] [2024-11-08 00:35:52,393 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:52,394 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:35:52,395 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:35:52,415 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2024-11-08 00:35:52,415 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2024-11-08 00:35:52,422 INFO L87 Difference]: Start difference. First operand has 2047 states, 2046 states have (on average 1.4926686217008798) internal successors, (3054), 2046 states have internal predecessors, (3054), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 79.5) internal successors, (159), 2 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:52,485 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:35:52,486 INFO L93 Difference]: Finished difference Result 2043 states and 3016 transitions. [2024-11-08 00:35:52,487 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2043 states and 3016 transitions. [2024-11-08 00:35:52,512 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2024-11-08 00:35:52,550 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2043 states to 2037 states and 3010 transitions. [2024-11-08 00:35:52,554 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2037 [2024-11-08 00:35:52,556 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2037 [2024-11-08 00:35:52,557 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2037 states and 3010 transitions. [2024-11-08 00:35:52,563 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:35:52,564 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2037 states and 3010 transitions. [2024-11-08 00:35:52,578 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2037 states and 3010 transitions. [2024-11-08 00:35:52,628 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2037 to 2037. [2024-11-08 00:35:52,631 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2037 states, 2037 states have (on average 1.47766323024055) internal successors, (3010), 2036 states have internal predecessors, (3010), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:52,638 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2037 states to 2037 states and 3010 transitions. [2024-11-08 00:35:52,639 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2037 states and 3010 transitions. [2024-11-08 00:35:52,640 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-11-08 00:35:52,642 INFO L425 stractBuchiCegarLoop]: Abstraction has 2037 states and 3010 transitions. [2024-11-08 00:35:52,642 INFO L332 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-11-08 00:35:52,642 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2037 states and 3010 transitions. [2024-11-08 00:35:52,651 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2024-11-08 00:35:52,651 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:35:52,651 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:35:52,654 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:52,654 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:52,655 INFO L745 eck$LassoCheckResult]: Stem: 4391#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 4392#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 5385#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5386#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6121#L914 assume !(1 == ~m_i~0);~m_st~0 := 2; 5513#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4982#L919-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 4983#L924-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 5787#L929-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5788#L934-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5892#L939-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5893#L944-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4731#L949-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4732#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 5927#L959-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 5283#L964-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 5284#L969-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 5833#L974-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 5197#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5198#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 6122#L1291-2 assume !(0 == ~T1_E~0); 6119#L1296-1 assume !(0 == ~T2_E~0); 5347#L1301-1 assume !(0 == ~T3_E~0); 5348#L1306-1 assume !(0 == ~T4_E~0); 5843#L1311-1 assume !(0 == ~T5_E~0); 4568#L1316-1 assume !(0 == ~T6_E~0); 4569#L1321-1 assume !(0 == ~T7_E~0); 5361#L1326-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4388#L1331-1 assume !(0 == ~T9_E~0); 4101#L1336-1 assume !(0 == ~T10_E~0); 4102#L1341-1 assume !(0 == ~T11_E~0); 4175#L1346-1 assume !(0 == ~T12_E~0); 4176#L1351-1 assume !(0 == ~T13_E~0); 4505#L1356-1 assume !(0 == ~E_M~0); 4506#L1361-1 assume !(0 == ~E_1~0); 6059#L1366-1 assume 0 == ~E_2~0;~E_2~0 := 1; 4552#L1371-1 assume !(0 == ~E_3~0); 4553#L1376-1 assume !(0 == ~E_4~0); 5413#L1381-1 assume !(0 == ~E_5~0); 5414#L1386-1 assume !(0 == ~E_6~0); 6090#L1391-1 assume !(0 == ~E_7~0); 6110#L1396-1 assume !(0 == ~E_8~0); 5315#L1401-1 assume !(0 == ~E_9~0); 5316#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 5603#L1411-1 assume !(0 == ~E_11~0); 5604#L1416-1 assume !(0 == ~E_12~0); 5233#L1421-1 assume !(0 == ~E_13~0); 4752#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4753#L640 assume !(1 == ~m_pc~0); 5282#L640-2 is_master_triggered_~__retres1~0#1 := 0; 5281#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5241#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5242#L1603 assume !(0 != activate_threads_~tmp~1#1); 5270#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4902#L659 assume 1 == ~t1_pc~0; 4903#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5011#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5724#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5033#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 5034#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5050#L678 assume 1 == ~t2_pc~0; 5996#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5997#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4595#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4596#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 5144#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5263#L697 assume !(1 == ~t3_pc~0); 5264#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 5394#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5714#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5177#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5178#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6029#L716 assume 1 == ~t4_pc~0; 6017#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4882#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4248#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4249#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 4356#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5678#L735 assume !(1 == ~t5_pc~0); 4323#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4324#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4779#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 5704#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 5341#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5342#L754 assume 1 == ~t6_pc~0; 5095#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4995#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4572#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4573#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 4969#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5778#L773 assume !(1 == ~t7_pc~0); 4509#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 4508#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5376#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 5351#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 5352#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5405#L792 assume 1 == ~t8_pc~0; 5573#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 5894#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5895#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 5343#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 5266#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5267#L811 assume 1 == ~t9_pc~0; 5476#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 5941#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4651#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4652#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 5278#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 5279#L830 assume !(1 == ~t10_pc~0); 5004#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 4485#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4486#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 4463#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 4464#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 5796#L849 assume 1 == ~t11_pc~0; 5797#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 4302#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4303#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 5807#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 5708#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 5709#L868 assume !(1 == ~t12_pc~0); 5128#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 5127#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4190#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 4191#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 4520#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 4521#L887 assume 1 == ~t13_pc~0; 5716#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 5171#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 5172#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 5772#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 4230#L1707-2 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4231#L1439 assume !(1 == ~M_E~0); 5335#L1439-2 assume !(1 == ~T1_E~0); 4401#L1444-1 assume !(1 == ~T2_E~0); 4402#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4907#L1454-1 assume !(1 == ~T4_E~0); 4908#L1459-1 assume !(1 == ~T5_E~0); 5468#L1464-1 assume !(1 == ~T6_E~0); 5469#L1469-1 assume !(1 == ~T7_E~0); 5542#L1474-1 assume !(1 == ~T8_E~0); 5234#L1479-1 assume !(1 == ~T9_E~0); 5235#L1484-1 assume !(1 == ~T10_E~0); 5472#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 5117#L1494-1 assume !(1 == ~T12_E~0); 5118#L1499-1 assume !(1 == ~T13_E~0); 5300#L1504-1 assume !(1 == ~E_M~0); 5301#L1509-1 assume !(1 == ~E_1~0); 5879#L1514-1 assume !(1 == ~E_2~0); 5575#L1519-1 assume !(1 == ~E_3~0); 5576#L1524-1 assume !(1 == ~E_4~0); 6074#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 6075#L1534-1 assume !(1 == ~E_6~0); 4224#L1539-1 assume !(1 == ~E_7~0); 4225#L1544-1 assume !(1 == ~E_8~0); 4648#L1549-1 assume !(1 == ~E_9~0); 6047#L1554-1 assume !(1 == ~E_10~0); 6044#L1559-1 assume !(1 == ~E_11~0); 5919#L1564-1 assume !(1 == ~E_12~0); 5920#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 6069#L1574-1 assume { :end_inline_reset_delta_events } true; 4399#L1940-2 [2024-11-08 00:35:52,655 INFO L747 eck$LassoCheckResult]: Loop: 4399#L1940-2 assume !false; 4400#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4943#L1266-1 assume !false; 6113#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 4964#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4678#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 5878#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 5887#L1079 assume !(0 != eval_~tmp~0#1); 5161#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4816#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4817#L1291-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5543#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5544#L1296-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6100#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6055#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5201#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4437#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4438#L1321-3 assume !(0 == ~T7_E~0); 4542#L1326-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 5330#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 5581#L1336-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 5582#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 4899#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 4876#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 4814#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4815#L1361-3 assume !(0 == ~E_1~0); 5395#L1366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4153#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4154#L1376-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5899#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5758#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5759#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5933#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 5934#L1401-3 assume !(0 == ~E_9~0); 4500#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 4364#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 4365#L1416-3 assume 0 == ~E_12~0;~E_12~0 := 1; 5058#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 5059#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5166#L640-45 assume 1 == ~m_pc~0; 5168#L641-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4608#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4609#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4149#L1603-45 assume !(0 != activate_threads_~tmp~1#1); 4150#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4238#L659-45 assume !(1 == ~t1_pc~0); 4240#L659-47 is_transmit1_triggered_~__retres1~1#1 := 0; 4692#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6104#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6034#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5687#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5688#L678-45 assume 1 == ~t2_pc~0; 5639#L679-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5173#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5174#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5621#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5950#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6053#L697-45 assume 1 == ~t3_pc~0; 5434#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5435#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6120#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5587#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5588#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5622#L716-45 assume 1 == ~t4_pc~0; 5246#L717-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5248#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5905#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5253#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5254#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4917#L735-45 assume 1 == ~t5_pc~0; 4918#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5466#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6071#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 6117#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6073#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6067#L754-45 assume 1 == ~t6_pc~0; 5417#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5418#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5311#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 5312#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5422#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5149#L773-45 assume !(1 == ~t7_pc~0); 4688#L773-47 is_transmit7_triggered_~__retres1~7#1 := 0; 4689#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5383#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 5384#L1659-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 5157#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4808#L792-45 assume 1 == ~t8_pc~0; 4809#L793-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 5837#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5838#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 4259#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4260#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4758#L811-45 assume 1 == ~t9_pc~0; 4535#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4536#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5755#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 5618#L1675-45 assume !(0 != activate_threads_~tmp___8~0#1); 5225#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 5016#L830-45 assume 1 == ~t10_pc~0; 5017#L831-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 4186#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5334#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 4410#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 4411#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 4169#L849-45 assume !(1 == ~t11_pc~0); 4170#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 4626#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4467#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 4155#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 4156#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4405#L868-45 assume 1 == ~t12_pc~0; 4406#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 4349#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4350#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 5790#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 5963#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 5964#L887-45 assume !(1 == ~t13_pc~0); 4412#L887-47 is_transmit13_triggered_~__retres1~13#1 := 0; 4413#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 5718#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 5737#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 4379#L1707-47 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4380#L1439-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5713#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4397#L1444-3 assume !(1 == ~T2_E~0); 4398#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4556#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5524#L1459-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5525#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5965#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5902#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 5903#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 5967#L1484-3 assume !(1 == ~T10_E~0); 5207#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 5208#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 5830#L1499-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 5483#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5484#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5915#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5951#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5124#L1524-3 assume !(1 == ~E_4~0); 5125#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5989#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5402#L1539-3 assume 1 == ~E_7~0;~E_7~0 := 2; 4859#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4860#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 5365#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 4444#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 4445#L1564-3 assume !(1 == ~E_12~0); 5623#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 5624#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 4336#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4110#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 4436#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 4343#L1959 assume !(0 == start_simulation_~tmp~3#1); 4345#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 4375#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4329#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 4164#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 4165#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5983#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5958#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 5959#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 4399#L1940-2 [2024-11-08 00:35:52,656 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:52,656 INFO L85 PathProgramCache]: Analyzing trace with hash 1878318605, now seen corresponding path program 2 times [2024-11-08 00:35:52,656 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:52,656 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [115898124] [2024-11-08 00:35:52,656 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:52,657 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:52,675 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:52,741 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:52,741 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:52,741 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [115898124] [2024-11-08 00:35:52,741 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [115898124] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:52,741 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:52,741 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:52,742 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [821120208] [2024-11-08 00:35:52,742 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:52,742 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:35:52,742 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:52,742 INFO L85 PathProgramCache]: Analyzing trace with hash -1337622148, now seen corresponding path program 1 times [2024-11-08 00:35:52,743 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:52,743 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1985566087] [2024-11-08 00:35:52,743 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:52,743 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:52,779 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:52,852 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:52,852 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:52,852 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1985566087] [2024-11-08 00:35:52,852 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1985566087] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:52,853 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:52,853 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:52,853 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [172773375] [2024-11-08 00:35:52,853 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:52,853 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:35:52,853 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:35:52,854 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:35:52,854 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:35:52,854 INFO L87 Difference]: Start difference. First operand 2037 states and 3010 transitions. cyclomatic complexity: 974 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:52,900 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:35:52,901 INFO L93 Difference]: Finished difference Result 2037 states and 3009 transitions. [2024-11-08 00:35:52,901 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2037 states and 3009 transitions. [2024-11-08 00:35:52,910 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2024-11-08 00:35:52,917 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2037 states to 2037 states and 3009 transitions. [2024-11-08 00:35:52,917 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2037 [2024-11-08 00:35:52,918 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2037 [2024-11-08 00:35:52,919 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2037 states and 3009 transitions. [2024-11-08 00:35:52,925 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:35:52,925 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2037 states and 3009 transitions. [2024-11-08 00:35:52,929 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2037 states and 3009 transitions. [2024-11-08 00:35:52,951 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2037 to 2037. [2024-11-08 00:35:52,954 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2037 states, 2037 states have (on average 1.4771723122238587) internal successors, (3009), 2036 states have internal predecessors, (3009), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:52,959 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2037 states to 2037 states and 3009 transitions. [2024-11-08 00:35:52,959 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2037 states and 3009 transitions. [2024-11-08 00:35:52,961 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:35:52,963 INFO L425 stractBuchiCegarLoop]: Abstraction has 2037 states and 3009 transitions. [2024-11-08 00:35:52,965 INFO L332 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-11-08 00:35:52,965 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2037 states and 3009 transitions. [2024-11-08 00:35:52,972 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2024-11-08 00:35:52,972 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:35:52,972 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:35:52,976 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:52,977 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:52,977 INFO L745 eck$LassoCheckResult]: Stem: 8472#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 8473#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 9466#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9467#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10202#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 9594#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9063#L919-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 9064#L924-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 9868#L929-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 9869#L934-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 9973#L939-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 9974#L944-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8812#L949-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 8813#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 10008#L959-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 9364#L964-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 9365#L969-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 9914#L974-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 9278#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9279#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 10203#L1291-2 assume !(0 == ~T1_E~0); 10200#L1296-1 assume !(0 == ~T2_E~0); 9428#L1301-1 assume !(0 == ~T3_E~0); 9429#L1306-1 assume !(0 == ~T4_E~0); 9924#L1311-1 assume !(0 == ~T5_E~0); 8649#L1316-1 assume !(0 == ~T6_E~0); 8650#L1321-1 assume !(0 == ~T7_E~0); 9442#L1326-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 8469#L1331-1 assume !(0 == ~T9_E~0); 8182#L1336-1 assume !(0 == ~T10_E~0); 8183#L1341-1 assume !(0 == ~T11_E~0); 8256#L1346-1 assume !(0 == ~T12_E~0); 8257#L1351-1 assume !(0 == ~T13_E~0); 8586#L1356-1 assume !(0 == ~E_M~0); 8587#L1361-1 assume !(0 == ~E_1~0); 10140#L1366-1 assume 0 == ~E_2~0;~E_2~0 := 1; 8633#L1371-1 assume !(0 == ~E_3~0); 8634#L1376-1 assume !(0 == ~E_4~0); 9494#L1381-1 assume !(0 == ~E_5~0); 9495#L1386-1 assume !(0 == ~E_6~0); 10171#L1391-1 assume !(0 == ~E_7~0); 10191#L1396-1 assume !(0 == ~E_8~0); 9396#L1401-1 assume !(0 == ~E_9~0); 9397#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 9684#L1411-1 assume !(0 == ~E_11~0); 9685#L1416-1 assume !(0 == ~E_12~0); 9314#L1421-1 assume !(0 == ~E_13~0); 8833#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8834#L640 assume !(1 == ~m_pc~0); 9363#L640-2 is_master_triggered_~__retres1~0#1 := 0; 9362#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9322#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9323#L1603 assume !(0 != activate_threads_~tmp~1#1); 9351#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8983#L659 assume 1 == ~t1_pc~0; 8984#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9092#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9805#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9114#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 9115#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9131#L678 assume 1 == ~t2_pc~0; 10077#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10078#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8676#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8677#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 9225#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9344#L697 assume !(1 == ~t3_pc~0); 9345#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 9475#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9795#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9258#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9259#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10110#L716 assume 1 == ~t4_pc~0; 10098#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8963#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8329#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8330#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 8437#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9759#L735 assume !(1 == ~t5_pc~0); 8404#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 8405#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8860#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 9785#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 9422#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9423#L754 assume 1 == ~t6_pc~0; 9176#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 9076#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8653#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8654#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 9050#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9859#L773 assume !(1 == ~t7_pc~0); 8590#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 8589#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9457#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 9432#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 9433#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9486#L792 assume 1 == ~t8_pc~0; 9654#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 9975#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9976#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 9424#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 9347#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 9348#L811 assume 1 == ~t9_pc~0; 9557#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 10022#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 8732#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 8733#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 9359#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 9360#L830 assume !(1 == ~t10_pc~0); 9085#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 8566#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8567#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 8544#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 8545#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 9877#L849 assume 1 == ~t11_pc~0; 9878#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 8383#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 8384#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 9888#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 9789#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 9790#L868 assume !(1 == ~t12_pc~0); 9209#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 9208#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 8271#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 8272#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 8601#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 8602#L887 assume 1 == ~t13_pc~0; 9797#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 9252#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 9253#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 9853#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 8311#L1707-2 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8312#L1439 assume !(1 == ~M_E~0); 9416#L1439-2 assume !(1 == ~T1_E~0); 8482#L1444-1 assume !(1 == ~T2_E~0); 8483#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8988#L1454-1 assume !(1 == ~T4_E~0); 8989#L1459-1 assume !(1 == ~T5_E~0); 9549#L1464-1 assume !(1 == ~T6_E~0); 9550#L1469-1 assume !(1 == ~T7_E~0); 9623#L1474-1 assume !(1 == ~T8_E~0); 9315#L1479-1 assume !(1 == ~T9_E~0); 9316#L1484-1 assume !(1 == ~T10_E~0); 9553#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 9198#L1494-1 assume !(1 == ~T12_E~0); 9199#L1499-1 assume !(1 == ~T13_E~0); 9381#L1504-1 assume !(1 == ~E_M~0); 9382#L1509-1 assume !(1 == ~E_1~0); 9960#L1514-1 assume !(1 == ~E_2~0); 9656#L1519-1 assume !(1 == ~E_3~0); 9657#L1524-1 assume !(1 == ~E_4~0); 10155#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 10156#L1534-1 assume !(1 == ~E_6~0); 8305#L1539-1 assume !(1 == ~E_7~0); 8306#L1544-1 assume !(1 == ~E_8~0); 8729#L1549-1 assume !(1 == ~E_9~0); 10128#L1554-1 assume !(1 == ~E_10~0); 10125#L1559-1 assume !(1 == ~E_11~0); 10000#L1564-1 assume !(1 == ~E_12~0); 10001#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 10150#L1574-1 assume { :end_inline_reset_delta_events } true; 8480#L1940-2 [2024-11-08 00:35:52,978 INFO L747 eck$LassoCheckResult]: Loop: 8480#L1940-2 assume !false; 8481#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9024#L1266-1 assume !false; 10194#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 9045#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 8759#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 9959#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 9968#L1079 assume !(0 != eval_~tmp~0#1); 9242#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8897#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8898#L1291-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9624#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9625#L1296-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10181#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 10136#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9282#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8518#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8519#L1321-3 assume !(0 == ~T7_E~0); 8623#L1326-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 9411#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 9662#L1336-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 9663#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 8980#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 8957#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 8895#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 8896#L1361-3 assume !(0 == ~E_1~0); 9476#L1366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8234#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8235#L1376-3 assume 0 == ~E_4~0;~E_4~0 := 1; 9980#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9839#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9840#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 10014#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 10015#L1401-3 assume !(0 == ~E_9~0); 8581#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 8445#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 8446#L1416-3 assume 0 == ~E_12~0;~E_12~0 := 1; 9139#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 9140#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9247#L640-45 assume !(1 == ~m_pc~0); 9248#L640-47 is_master_triggered_~__retres1~0#1 := 0; 8689#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8690#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8230#L1603-45 assume !(0 != activate_threads_~tmp~1#1); 8231#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8319#L659-45 assume 1 == ~t1_pc~0; 8320#L660-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8773#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10185#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10115#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 9768#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9769#L678-45 assume 1 == ~t2_pc~0; 9720#L679-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9254#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9255#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9702#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 10031#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10134#L697-45 assume 1 == ~t3_pc~0; 9515#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9516#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10201#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9668#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9669#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9703#L716-45 assume !(1 == ~t4_pc~0); 9328#L716-47 is_transmit4_triggered_~__retres1~4#1 := 0; 9329#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9986#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 9334#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9335#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8998#L735-45 assume 1 == ~t5_pc~0; 8999#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9547#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10152#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 10198#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 10154#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10148#L754-45 assume 1 == ~t6_pc~0; 9498#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 9499#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9392#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 9393#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9503#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9230#L773-45 assume !(1 == ~t7_pc~0); 8769#L773-47 is_transmit7_triggered_~__retres1~7#1 := 0; 8770#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9464#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 9465#L1659-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 9238#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8889#L792-45 assume 1 == ~t8_pc~0; 8890#L793-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 9918#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9919#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 8340#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 8341#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8839#L811-45 assume 1 == ~t9_pc~0; 8616#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 8617#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9836#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 9699#L1675-45 assume !(0 != activate_threads_~tmp___8~0#1); 9306#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 9097#L830-45 assume 1 == ~t10_pc~0; 9098#L831-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 8267#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 9415#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 8491#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 8492#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 8250#L849-45 assume !(1 == ~t11_pc~0); 8251#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 8707#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 8548#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 8236#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 8237#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 8486#L868-45 assume 1 == ~t12_pc~0; 8487#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 8430#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 8431#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 9871#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 10044#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 10045#L887-45 assume 1 == ~t13_pc~0; 9872#L888-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 8494#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 9799#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 9818#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 8460#L1707-47 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8461#L1439-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9794#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8478#L1444-3 assume !(1 == ~T2_E~0); 8479#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8637#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9605#L1459-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9606#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10046#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 9983#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 9984#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 10048#L1484-3 assume !(1 == ~T10_E~0); 9288#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 9289#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 9911#L1499-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 9564#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 9565#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9996#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10032#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9205#L1524-3 assume !(1 == ~E_4~0); 9206#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 10070#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 9483#L1539-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8940#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 8941#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 9446#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 8525#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 8526#L1564-3 assume !(1 == ~E_12~0); 9704#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 9705#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 8417#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 8191#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 8517#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 8424#L1959 assume !(0 == start_simulation_~tmp~3#1); 8426#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 8456#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 8410#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 8245#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 8246#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10064#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10039#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 10040#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 8480#L1940-2 [2024-11-08 00:35:52,978 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:52,978 INFO L85 PathProgramCache]: Analyzing trace with hash 1533490443, now seen corresponding path program 1 times [2024-11-08 00:35:52,979 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:52,979 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [8189911] [2024-11-08 00:35:52,979 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:52,979 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:52,996 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:53,069 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:53,069 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:53,070 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [8189911] [2024-11-08 00:35:53,070 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [8189911] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:53,070 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:53,070 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:53,070 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1371851517] [2024-11-08 00:35:53,070 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:53,070 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:35:53,070 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:53,070 INFO L85 PathProgramCache]: Analyzing trace with hash -828534276, now seen corresponding path program 1 times [2024-11-08 00:35:53,071 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:53,071 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [134520173] [2024-11-08 00:35:53,071 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:53,071 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:53,102 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:53,194 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:53,194 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:53,194 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [134520173] [2024-11-08 00:35:53,194 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [134520173] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:53,194 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:53,194 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:53,194 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1031711849] [2024-11-08 00:35:53,194 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:53,194 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:35:53,195 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:35:53,195 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:35:53,195 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:35:53,195 INFO L87 Difference]: Start difference. First operand 2037 states and 3009 transitions. cyclomatic complexity: 973 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:53,229 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:35:53,229 INFO L93 Difference]: Finished difference Result 2037 states and 3008 transitions. [2024-11-08 00:35:53,229 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2037 states and 3008 transitions. [2024-11-08 00:35:53,238 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2024-11-08 00:35:53,245 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2037 states to 2037 states and 3008 transitions. [2024-11-08 00:35:53,246 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2037 [2024-11-08 00:35:53,247 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2037 [2024-11-08 00:35:53,247 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2037 states and 3008 transitions. [2024-11-08 00:35:53,249 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:35:53,250 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2037 states and 3008 transitions. [2024-11-08 00:35:53,252 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2037 states and 3008 transitions. [2024-11-08 00:35:53,268 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2037 to 2037. [2024-11-08 00:35:53,271 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2037 states, 2037 states have (on average 1.4766813942071675) internal successors, (3008), 2036 states have internal predecessors, (3008), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:53,276 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2037 states to 2037 states and 3008 transitions. [2024-11-08 00:35:53,276 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2037 states and 3008 transitions. [2024-11-08 00:35:53,277 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:35:53,278 INFO L425 stractBuchiCegarLoop]: Abstraction has 2037 states and 3008 transitions. [2024-11-08 00:35:53,279 INFO L332 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-11-08 00:35:53,279 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2037 states and 3008 transitions. [2024-11-08 00:35:53,285 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2024-11-08 00:35:53,285 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:35:53,285 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:35:53,288 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:53,288 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:53,288 INFO L745 eck$LassoCheckResult]: Stem: 12553#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 12554#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 13547#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13548#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14283#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 13675#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13144#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 13145#L924-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 13949#L929-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 13950#L934-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 14054#L939-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 14055#L944-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 12893#L949-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 12894#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 14089#L959-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 13445#L964-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 13446#L969-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 13995#L974-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 13359#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13360#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 14284#L1291-2 assume !(0 == ~T1_E~0); 14281#L1296-1 assume !(0 == ~T2_E~0); 13509#L1301-1 assume !(0 == ~T3_E~0); 13510#L1306-1 assume !(0 == ~T4_E~0); 14005#L1311-1 assume !(0 == ~T5_E~0); 12730#L1316-1 assume !(0 == ~T6_E~0); 12731#L1321-1 assume !(0 == ~T7_E~0); 13523#L1326-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 12550#L1331-1 assume !(0 == ~T9_E~0); 12263#L1336-1 assume !(0 == ~T10_E~0); 12264#L1341-1 assume !(0 == ~T11_E~0); 12337#L1346-1 assume !(0 == ~T12_E~0); 12338#L1351-1 assume !(0 == ~T13_E~0); 12667#L1356-1 assume !(0 == ~E_M~0); 12668#L1361-1 assume !(0 == ~E_1~0); 14221#L1366-1 assume 0 == ~E_2~0;~E_2~0 := 1; 12714#L1371-1 assume !(0 == ~E_3~0); 12715#L1376-1 assume !(0 == ~E_4~0); 13575#L1381-1 assume !(0 == ~E_5~0); 13576#L1386-1 assume !(0 == ~E_6~0); 14252#L1391-1 assume !(0 == ~E_7~0); 14272#L1396-1 assume !(0 == ~E_8~0); 13477#L1401-1 assume !(0 == ~E_9~0); 13478#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 13765#L1411-1 assume !(0 == ~E_11~0); 13766#L1416-1 assume !(0 == ~E_12~0); 13395#L1421-1 assume !(0 == ~E_13~0); 12914#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12915#L640 assume !(1 == ~m_pc~0); 13444#L640-2 is_master_triggered_~__retres1~0#1 := 0; 13443#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13403#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13404#L1603 assume !(0 != activate_threads_~tmp~1#1); 13432#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13064#L659 assume 1 == ~t1_pc~0; 13065#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 13173#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13886#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13195#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 13196#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13212#L678 assume 1 == ~t2_pc~0; 14158#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14159#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12757#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12758#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 13306#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13425#L697 assume !(1 == ~t3_pc~0); 13426#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 13556#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13876#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13339#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13340#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14191#L716 assume 1 == ~t4_pc~0; 14179#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13044#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12410#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12411#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 12518#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13840#L735 assume !(1 == ~t5_pc~0); 12485#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 12486#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12941#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 13866#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 13503#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13504#L754 assume 1 == ~t6_pc~0; 13257#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13157#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12734#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 12735#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 13131#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13940#L773 assume !(1 == ~t7_pc~0); 12671#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 12670#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13538#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 13513#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 13514#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 13567#L792 assume 1 == ~t8_pc~0; 13735#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 14056#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14057#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 13505#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 13428#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13429#L811 assume 1 == ~t9_pc~0; 13638#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 14103#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12813#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 12814#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 13440#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13441#L830 assume !(1 == ~t10_pc~0); 13166#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 12647#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 12648#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 12625#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 12626#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 13958#L849 assume 1 == ~t11_pc~0; 13959#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 12464#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 12465#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 13969#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 13870#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 13871#L868 assume !(1 == ~t12_pc~0); 13290#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 13289#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 12352#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 12353#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 12682#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 12683#L887 assume 1 == ~t13_pc~0; 13878#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 13333#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 13334#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 13934#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 12392#L1707-2 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12393#L1439 assume !(1 == ~M_E~0); 13497#L1439-2 assume !(1 == ~T1_E~0); 12563#L1444-1 assume !(1 == ~T2_E~0); 12564#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 13069#L1454-1 assume !(1 == ~T4_E~0); 13070#L1459-1 assume !(1 == ~T5_E~0); 13630#L1464-1 assume !(1 == ~T6_E~0); 13631#L1469-1 assume !(1 == ~T7_E~0); 13704#L1474-1 assume !(1 == ~T8_E~0); 13396#L1479-1 assume !(1 == ~T9_E~0); 13397#L1484-1 assume !(1 == ~T10_E~0); 13634#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 13279#L1494-1 assume !(1 == ~T12_E~0); 13280#L1499-1 assume !(1 == ~T13_E~0); 13462#L1504-1 assume !(1 == ~E_M~0); 13463#L1509-1 assume !(1 == ~E_1~0); 14041#L1514-1 assume !(1 == ~E_2~0); 13737#L1519-1 assume !(1 == ~E_3~0); 13738#L1524-1 assume !(1 == ~E_4~0); 14236#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 14237#L1534-1 assume !(1 == ~E_6~0); 12386#L1539-1 assume !(1 == ~E_7~0); 12387#L1544-1 assume !(1 == ~E_8~0); 12810#L1549-1 assume !(1 == ~E_9~0); 14209#L1554-1 assume !(1 == ~E_10~0); 14206#L1559-1 assume !(1 == ~E_11~0); 14081#L1564-1 assume !(1 == ~E_12~0); 14082#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 14231#L1574-1 assume { :end_inline_reset_delta_events } true; 12561#L1940-2 [2024-11-08 00:35:53,289 INFO L747 eck$LassoCheckResult]: Loop: 12561#L1940-2 assume !false; 12562#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13105#L1266-1 assume !false; 14275#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 13126#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 12840#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 14040#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 14049#L1079 assume !(0 != eval_~tmp~0#1); 13323#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12978#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12979#L1291-3 assume 0 == ~M_E~0;~M_E~0 := 1; 13705#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13706#L1296-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 14262#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14217#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13363#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 12599#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12600#L1321-3 assume !(0 == ~T7_E~0); 12704#L1326-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 13492#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 13743#L1336-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 13744#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 13061#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 13038#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 12976#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 12977#L1361-3 assume !(0 == ~E_1~0); 13557#L1366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12315#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12316#L1376-3 assume 0 == ~E_4~0;~E_4~0 := 1; 14061#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 13920#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 13921#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 14095#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 14096#L1401-3 assume !(0 == ~E_9~0); 12662#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 12526#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 12527#L1416-3 assume 0 == ~E_12~0;~E_12~0 := 1; 13220#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 13221#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13328#L640-45 assume !(1 == ~m_pc~0); 13329#L640-47 is_master_triggered_~__retres1~0#1 := 0; 12770#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12771#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12311#L1603-45 assume !(0 != activate_threads_~tmp~1#1); 12312#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12400#L659-45 assume 1 == ~t1_pc~0; 12401#L660-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12854#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14266#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14196#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 13849#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13850#L678-45 assume 1 == ~t2_pc~0; 13801#L679-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13335#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13336#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 13783#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14112#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14215#L697-45 assume 1 == ~t3_pc~0; 13596#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 13597#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14282#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13749#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13750#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13784#L716-45 assume 1 == ~t4_pc~0; 13408#L717-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13410#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14067#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 13415#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13416#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13079#L735-45 assume 1 == ~t5_pc~0; 13080#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 13628#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14233#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 14279#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 14235#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14229#L754-45 assume 1 == ~t6_pc~0; 13579#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13580#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13473#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 13474#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 13584#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13311#L773-45 assume 1 == ~t7_pc~0; 13312#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12851#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13545#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 13546#L1659-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 13319#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12970#L792-45 assume 1 == ~t8_pc~0; 12971#L793-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 13999#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14000#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 12421#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 12422#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12920#L811-45 assume 1 == ~t9_pc~0; 12697#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12698#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 13917#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 13780#L1675-45 assume !(0 != activate_threads_~tmp___8~0#1); 13387#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13178#L830-45 assume 1 == ~t10_pc~0; 13179#L831-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 12348#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 13496#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 12572#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 12573#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 12331#L849-45 assume !(1 == ~t11_pc~0); 12332#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 12788#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 12629#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 12317#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 12318#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 12567#L868-45 assume 1 == ~t12_pc~0; 12568#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 12511#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 12512#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 13952#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 14125#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 14126#L887-45 assume 1 == ~t13_pc~0; 13953#L888-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 12575#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 13880#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 13899#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 12541#L1707-47 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12542#L1439-3 assume 1 == ~M_E~0;~M_E~0 := 2; 13875#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12559#L1444-3 assume !(1 == ~T2_E~0); 12560#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12718#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 13686#L1459-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 13687#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 14127#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 14064#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 14065#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 14129#L1484-3 assume !(1 == ~T10_E~0); 13369#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 13370#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 13992#L1499-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 13645#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 13646#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 14077#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 14113#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 13286#L1524-3 assume !(1 == ~E_4~0); 13287#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14151#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 13564#L1539-3 assume 1 == ~E_7~0;~E_7~0 := 2; 13021#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 13022#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 13527#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 12606#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 12607#L1564-3 assume !(1 == ~E_12~0); 13785#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 13786#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 12498#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 12272#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 12598#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 12505#L1959 assume !(0 == start_simulation_~tmp~3#1); 12507#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 12537#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 12491#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 12326#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 12327#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 14145#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14120#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 14121#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 12561#L1940-2 [2024-11-08 00:35:53,289 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:53,290 INFO L85 PathProgramCache]: Analyzing trace with hash -992005239, now seen corresponding path program 1 times [2024-11-08 00:35:53,290 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:53,290 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1913028219] [2024-11-08 00:35:53,290 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:53,290 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:53,305 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:53,352 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:53,352 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:53,352 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1913028219] [2024-11-08 00:35:53,352 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1913028219] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:53,352 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:53,352 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:53,352 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [232736818] [2024-11-08 00:35:53,352 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:53,352 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:35:53,353 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:53,353 INFO L85 PathProgramCache]: Analyzing trace with hash 1601605178, now seen corresponding path program 1 times [2024-11-08 00:35:53,353 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:53,355 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1200927356] [2024-11-08 00:35:53,355 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:53,355 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:53,374 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:53,437 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:53,437 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:53,437 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1200927356] [2024-11-08 00:35:53,437 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1200927356] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:53,437 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:53,437 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:53,437 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1675057005] [2024-11-08 00:35:53,438 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:53,438 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:35:53,439 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:35:53,439 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:35:53,439 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:35:53,439 INFO L87 Difference]: Start difference. First operand 2037 states and 3008 transitions. cyclomatic complexity: 972 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:53,467 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:35:53,468 INFO L93 Difference]: Finished difference Result 2037 states and 3007 transitions. [2024-11-08 00:35:53,468 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2037 states and 3007 transitions. [2024-11-08 00:35:53,479 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2024-11-08 00:35:53,486 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2037 states to 2037 states and 3007 transitions. [2024-11-08 00:35:53,486 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2037 [2024-11-08 00:35:53,488 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2037 [2024-11-08 00:35:53,488 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2037 states and 3007 transitions. [2024-11-08 00:35:53,491 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:35:53,491 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2037 states and 3007 transitions. [2024-11-08 00:35:53,494 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2037 states and 3007 transitions. [2024-11-08 00:35:53,511 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2037 to 2037. [2024-11-08 00:35:53,518 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2037 states, 2037 states have (on average 1.4761904761904763) internal successors, (3007), 2036 states have internal predecessors, (3007), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:53,525 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2037 states to 2037 states and 3007 transitions. [2024-11-08 00:35:53,525 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2037 states and 3007 transitions. [2024-11-08 00:35:53,525 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:35:53,527 INFO L425 stractBuchiCegarLoop]: Abstraction has 2037 states and 3007 transitions. [2024-11-08 00:35:53,527 INFO L332 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-11-08 00:35:53,527 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2037 states and 3007 transitions. [2024-11-08 00:35:53,534 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2024-11-08 00:35:53,534 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:35:53,535 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:35:53,537 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:53,537 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:53,537 INFO L745 eck$LassoCheckResult]: Stem: 16634#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 16635#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 17628#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 17629#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 18364#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 17756#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17225#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17226#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 18030#L929-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 18031#L934-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 18135#L939-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 18136#L944-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 16974#L949-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 16975#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 18170#L959-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 17526#L964-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 17527#L969-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 18076#L974-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 17440#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 17441#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 18365#L1291-2 assume !(0 == ~T1_E~0); 18362#L1296-1 assume !(0 == ~T2_E~0); 17590#L1301-1 assume !(0 == ~T3_E~0); 17591#L1306-1 assume !(0 == ~T4_E~0); 18086#L1311-1 assume !(0 == ~T5_E~0); 16811#L1316-1 assume !(0 == ~T6_E~0); 16812#L1321-1 assume !(0 == ~T7_E~0); 17604#L1326-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16631#L1331-1 assume !(0 == ~T9_E~0); 16344#L1336-1 assume !(0 == ~T10_E~0); 16345#L1341-1 assume !(0 == ~T11_E~0); 16418#L1346-1 assume !(0 == ~T12_E~0); 16419#L1351-1 assume !(0 == ~T13_E~0); 16748#L1356-1 assume !(0 == ~E_M~0); 16749#L1361-1 assume !(0 == ~E_1~0); 18302#L1366-1 assume 0 == ~E_2~0;~E_2~0 := 1; 16795#L1371-1 assume !(0 == ~E_3~0); 16796#L1376-1 assume !(0 == ~E_4~0); 17656#L1381-1 assume !(0 == ~E_5~0); 17657#L1386-1 assume !(0 == ~E_6~0); 18333#L1391-1 assume !(0 == ~E_7~0); 18353#L1396-1 assume !(0 == ~E_8~0); 17558#L1401-1 assume !(0 == ~E_9~0); 17559#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 17846#L1411-1 assume !(0 == ~E_11~0); 17847#L1416-1 assume !(0 == ~E_12~0); 17476#L1421-1 assume !(0 == ~E_13~0); 16995#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16996#L640 assume !(1 == ~m_pc~0); 17525#L640-2 is_master_triggered_~__retres1~0#1 := 0; 17524#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17484#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17485#L1603 assume !(0 != activate_threads_~tmp~1#1); 17513#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17145#L659 assume 1 == ~t1_pc~0; 17146#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 17254#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17967#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17276#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 17277#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17293#L678 assume 1 == ~t2_pc~0; 18239#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 18240#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16838#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16839#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 17387#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17506#L697 assume !(1 == ~t3_pc~0); 17507#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 17637#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17957#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17420#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17421#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 18272#L716 assume 1 == ~t4_pc~0; 18260#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 17125#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16491#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 16492#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 16599#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17921#L735 assume !(1 == ~t5_pc~0); 16566#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 16567#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17022#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 17947#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 17584#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17585#L754 assume 1 == ~t6_pc~0; 17338#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 17238#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16815#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 16816#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 17212#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18021#L773 assume !(1 == ~t7_pc~0); 16752#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 16751#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17619#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 17594#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 17595#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17648#L792 assume 1 == ~t8_pc~0; 17816#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 18137#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 18138#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 17586#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 17509#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 17510#L811 assume 1 == ~t9_pc~0; 17719#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 18184#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 16894#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 16895#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 17521#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 17522#L830 assume !(1 == ~t10_pc~0); 17247#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 16728#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 16729#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 16706#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 16707#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 18039#L849 assume 1 == ~t11_pc~0; 18040#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 16545#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 16546#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 18050#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 17951#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 17952#L868 assume !(1 == ~t12_pc~0); 17371#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 17370#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 16433#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 16434#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 16763#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 16764#L887 assume 1 == ~t13_pc~0; 17959#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 17414#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 17415#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 18015#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 16473#L1707-2 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16474#L1439 assume !(1 == ~M_E~0); 17578#L1439-2 assume !(1 == ~T1_E~0); 16644#L1444-1 assume !(1 == ~T2_E~0); 16645#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17150#L1454-1 assume !(1 == ~T4_E~0); 17151#L1459-1 assume !(1 == ~T5_E~0); 17711#L1464-1 assume !(1 == ~T6_E~0); 17712#L1469-1 assume !(1 == ~T7_E~0); 17785#L1474-1 assume !(1 == ~T8_E~0); 17477#L1479-1 assume !(1 == ~T9_E~0); 17478#L1484-1 assume !(1 == ~T10_E~0); 17715#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 17360#L1494-1 assume !(1 == ~T12_E~0); 17361#L1499-1 assume !(1 == ~T13_E~0); 17543#L1504-1 assume !(1 == ~E_M~0); 17544#L1509-1 assume !(1 == ~E_1~0); 18122#L1514-1 assume !(1 == ~E_2~0); 17818#L1519-1 assume !(1 == ~E_3~0); 17819#L1524-1 assume !(1 == ~E_4~0); 18317#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 18318#L1534-1 assume !(1 == ~E_6~0); 16467#L1539-1 assume !(1 == ~E_7~0); 16468#L1544-1 assume !(1 == ~E_8~0); 16891#L1549-1 assume !(1 == ~E_9~0); 18290#L1554-1 assume !(1 == ~E_10~0); 18287#L1559-1 assume !(1 == ~E_11~0); 18162#L1564-1 assume !(1 == ~E_12~0); 18163#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 18312#L1574-1 assume { :end_inline_reset_delta_events } true; 16642#L1940-2 [2024-11-08 00:35:53,538 INFO L747 eck$LassoCheckResult]: Loop: 16642#L1940-2 assume !false; 16643#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 17186#L1266-1 assume !false; 18356#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 17207#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 16921#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 18121#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 18130#L1079 assume !(0 != eval_~tmp~0#1); 17404#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 17059#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 17060#L1291-3 assume 0 == ~M_E~0;~M_E~0 := 1; 17786#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 17787#L1296-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 18343#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 18298#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17444#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 16680#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 16681#L1321-3 assume !(0 == ~T7_E~0); 16785#L1326-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 17573#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 17824#L1336-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 17825#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 17142#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 17119#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 17057#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 17058#L1361-3 assume !(0 == ~E_1~0); 17638#L1366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 16396#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 16397#L1376-3 assume 0 == ~E_4~0;~E_4~0 := 1; 18142#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 18001#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 18002#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 18176#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 18177#L1401-3 assume !(0 == ~E_9~0); 16743#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 16607#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 16608#L1416-3 assume 0 == ~E_12~0;~E_12~0 := 1; 17301#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 17302#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17409#L640-45 assume !(1 == ~m_pc~0); 17410#L640-47 is_master_triggered_~__retres1~0#1 := 0; 16851#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16852#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16392#L1603-45 assume !(0 != activate_threads_~tmp~1#1); 16393#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16481#L659-45 assume 1 == ~t1_pc~0; 16482#L660-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 16935#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18347#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18277#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 17930#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17931#L678-45 assume 1 == ~t2_pc~0; 17882#L679-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 17416#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17417#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17864#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 18193#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18296#L697-45 assume 1 == ~t3_pc~0; 17677#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 17678#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18363#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17830#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17831#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17865#L716-45 assume 1 == ~t4_pc~0; 17489#L717-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 17491#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18148#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 17496#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17497#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17160#L735-45 assume 1 == ~t5_pc~0; 17161#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 17709#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18314#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 18360#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 18316#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18310#L754-45 assume 1 == ~t6_pc~0; 17660#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 17661#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17554#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 17555#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 17665#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17392#L773-45 assume 1 == ~t7_pc~0; 17393#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 16932#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17626#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 17627#L1659-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 17400#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17051#L792-45 assume 1 == ~t8_pc~0; 17052#L793-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 18080#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 18081#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 16502#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 16503#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 17001#L811-45 assume 1 == ~t9_pc~0; 16778#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 16779#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17998#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 17861#L1675-45 assume !(0 != activate_threads_~tmp___8~0#1); 17468#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 17259#L830-45 assume 1 == ~t10_pc~0; 17260#L831-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 16429#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17577#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 16653#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 16654#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 16412#L849-45 assume !(1 == ~t11_pc~0); 16413#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 16869#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 16710#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 16398#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 16399#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 16648#L868-45 assume 1 == ~t12_pc~0; 16649#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 16592#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 16593#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 18033#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 18206#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 18207#L887-45 assume 1 == ~t13_pc~0; 18034#L888-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 16656#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 17961#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 17980#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 16622#L1707-47 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16623#L1439-3 assume 1 == ~M_E~0;~M_E~0 := 2; 17956#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 16640#L1444-3 assume !(1 == ~T2_E~0); 16641#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 16799#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 17767#L1459-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 17768#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 18208#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 18145#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 18146#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 18210#L1484-3 assume !(1 == ~T10_E~0); 17450#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 17451#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 18073#L1499-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 17726#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 17727#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 18158#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 18194#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 17367#L1524-3 assume !(1 == ~E_4~0); 17368#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 18232#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 17645#L1539-3 assume 1 == ~E_7~0;~E_7~0 := 2; 17102#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 17103#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 17608#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 16687#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 16688#L1564-3 assume !(1 == ~E_12~0); 17866#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 17867#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 16579#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 16353#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 16679#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 16586#L1959 assume !(0 == start_simulation_~tmp~3#1); 16588#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 16618#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 16572#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 16407#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 16408#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 18226#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 18201#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 18202#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 16642#L1940-2 [2024-11-08 00:35:53,539 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:53,539 INFO L85 PathProgramCache]: Analyzing trace with hash -380736181, now seen corresponding path program 1 times [2024-11-08 00:35:53,539 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:53,539 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1551287339] [2024-11-08 00:35:53,539 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:53,539 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:53,553 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:53,593 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:53,594 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:53,594 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1551287339] [2024-11-08 00:35:53,594 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1551287339] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:53,594 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:53,594 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:53,594 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2049031700] [2024-11-08 00:35:53,594 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:53,594 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:35:53,595 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:53,595 INFO L85 PathProgramCache]: Analyzing trace with hash 1601605178, now seen corresponding path program 2 times [2024-11-08 00:35:53,595 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:53,595 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1694463341] [2024-11-08 00:35:53,596 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:53,596 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:53,642 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:53,693 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:53,694 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:53,694 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1694463341] [2024-11-08 00:35:53,694 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1694463341] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:53,694 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:53,694 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:53,694 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1244616694] [2024-11-08 00:35:53,694 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:53,695 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:35:53,695 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:35:53,695 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:35:53,695 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:35:53,695 INFO L87 Difference]: Start difference. First operand 2037 states and 3007 transitions. cyclomatic complexity: 971 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:53,721 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:35:53,721 INFO L93 Difference]: Finished difference Result 2037 states and 3006 transitions. [2024-11-08 00:35:53,721 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2037 states and 3006 transitions. [2024-11-08 00:35:53,728 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2024-11-08 00:35:53,735 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2037 states to 2037 states and 3006 transitions. [2024-11-08 00:35:53,735 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2037 [2024-11-08 00:35:53,736 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2037 [2024-11-08 00:35:53,736 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2037 states and 3006 transitions. [2024-11-08 00:35:53,739 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:35:53,739 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2037 states and 3006 transitions. [2024-11-08 00:35:53,741 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2037 states and 3006 transitions. [2024-11-08 00:35:53,757 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2037 to 2037. [2024-11-08 00:35:53,761 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2037 states, 2037 states have (on average 1.475699558173785) internal successors, (3006), 2036 states have internal predecessors, (3006), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:53,766 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2037 states to 2037 states and 3006 transitions. [2024-11-08 00:35:53,766 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2037 states and 3006 transitions. [2024-11-08 00:35:53,766 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:35:53,767 INFO L425 stractBuchiCegarLoop]: Abstraction has 2037 states and 3006 transitions. [2024-11-08 00:35:53,767 INFO L332 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-11-08 00:35:53,767 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2037 states and 3006 transitions. [2024-11-08 00:35:53,774 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2024-11-08 00:35:53,774 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:35:53,774 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:35:53,777 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:53,778 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:53,778 INFO L745 eck$LassoCheckResult]: Stem: 20715#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 20716#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 21709#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 21710#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 22445#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 21837#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21306#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21307#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 22111#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 22112#L934-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 22216#L939-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 22217#L944-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 21055#L949-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 21056#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 22251#L959-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 21607#L964-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 21608#L969-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 22157#L974-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 21521#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 21522#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 22446#L1291-2 assume !(0 == ~T1_E~0); 22443#L1296-1 assume !(0 == ~T2_E~0); 21671#L1301-1 assume !(0 == ~T3_E~0); 21672#L1306-1 assume !(0 == ~T4_E~0); 22167#L1311-1 assume !(0 == ~T5_E~0); 20892#L1316-1 assume !(0 == ~T6_E~0); 20893#L1321-1 assume !(0 == ~T7_E~0); 21685#L1326-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 20712#L1331-1 assume !(0 == ~T9_E~0); 20425#L1336-1 assume !(0 == ~T10_E~0); 20426#L1341-1 assume !(0 == ~T11_E~0); 20499#L1346-1 assume !(0 == ~T12_E~0); 20500#L1351-1 assume !(0 == ~T13_E~0); 20829#L1356-1 assume !(0 == ~E_M~0); 20830#L1361-1 assume !(0 == ~E_1~0); 22383#L1366-1 assume 0 == ~E_2~0;~E_2~0 := 1; 20876#L1371-1 assume !(0 == ~E_3~0); 20877#L1376-1 assume !(0 == ~E_4~0); 21737#L1381-1 assume !(0 == ~E_5~0); 21738#L1386-1 assume !(0 == ~E_6~0); 22414#L1391-1 assume !(0 == ~E_7~0); 22434#L1396-1 assume !(0 == ~E_8~0); 21639#L1401-1 assume !(0 == ~E_9~0); 21640#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 21927#L1411-1 assume !(0 == ~E_11~0); 21928#L1416-1 assume !(0 == ~E_12~0); 21557#L1421-1 assume !(0 == ~E_13~0); 21076#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21077#L640 assume !(1 == ~m_pc~0); 21606#L640-2 is_master_triggered_~__retres1~0#1 := 0; 21605#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21565#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21566#L1603 assume !(0 != activate_threads_~tmp~1#1); 21594#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21226#L659 assume 1 == ~t1_pc~0; 21227#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 21335#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22048#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 21357#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 21358#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21374#L678 assume 1 == ~t2_pc~0; 22320#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 22321#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20919#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 20920#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 21468#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21587#L697 assume !(1 == ~t3_pc~0); 21588#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 21718#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22038#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 21501#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 21502#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22353#L716 assume 1 == ~t4_pc~0; 22341#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21206#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20572#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 20573#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 20680#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22002#L735 assume !(1 == ~t5_pc~0); 20647#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 20648#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21103#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 22028#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 21665#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 21666#L754 assume 1 == ~t6_pc~0; 21419#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 21319#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 20896#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 20897#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 21293#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 22102#L773 assume !(1 == ~t7_pc~0); 20833#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 20832#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 21700#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 21675#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 21676#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21729#L792 assume 1 == ~t8_pc~0; 21897#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 22218#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22219#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 21667#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 21590#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 21591#L811 assume 1 == ~t9_pc~0; 21800#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 22265#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 20975#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 20976#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 21602#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21603#L830 assume !(1 == ~t10_pc~0); 21328#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 20809#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 20810#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 20787#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 20788#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 22120#L849 assume 1 == ~t11_pc~0; 22121#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 20626#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 20627#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 22131#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 22032#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 22033#L868 assume !(1 == ~t12_pc~0); 21452#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 21451#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 20514#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 20515#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 20844#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 20845#L887 assume 1 == ~t13_pc~0; 22040#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 21495#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 21496#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 22096#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 20554#L1707-2 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20555#L1439 assume !(1 == ~M_E~0); 21659#L1439-2 assume !(1 == ~T1_E~0); 20725#L1444-1 assume !(1 == ~T2_E~0); 20726#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 21231#L1454-1 assume !(1 == ~T4_E~0); 21232#L1459-1 assume !(1 == ~T5_E~0); 21792#L1464-1 assume !(1 == ~T6_E~0); 21793#L1469-1 assume !(1 == ~T7_E~0); 21866#L1474-1 assume !(1 == ~T8_E~0); 21558#L1479-1 assume !(1 == ~T9_E~0); 21559#L1484-1 assume !(1 == ~T10_E~0); 21796#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 21441#L1494-1 assume !(1 == ~T12_E~0); 21442#L1499-1 assume !(1 == ~T13_E~0); 21624#L1504-1 assume !(1 == ~E_M~0); 21625#L1509-1 assume !(1 == ~E_1~0); 22203#L1514-1 assume !(1 == ~E_2~0); 21899#L1519-1 assume !(1 == ~E_3~0); 21900#L1524-1 assume !(1 == ~E_4~0); 22398#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 22399#L1534-1 assume !(1 == ~E_6~0); 20548#L1539-1 assume !(1 == ~E_7~0); 20549#L1544-1 assume !(1 == ~E_8~0); 20972#L1549-1 assume !(1 == ~E_9~0); 22371#L1554-1 assume !(1 == ~E_10~0); 22368#L1559-1 assume !(1 == ~E_11~0); 22243#L1564-1 assume !(1 == ~E_12~0); 22244#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 22393#L1574-1 assume { :end_inline_reset_delta_events } true; 20723#L1940-2 [2024-11-08 00:35:53,779 INFO L747 eck$LassoCheckResult]: Loop: 20723#L1940-2 assume !false; 20724#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 21267#L1266-1 assume !false; 22437#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 21288#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 21002#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 22202#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 22211#L1079 assume !(0 != eval_~tmp~0#1); 21485#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 21140#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 21141#L1291-3 assume 0 == ~M_E~0;~M_E~0 := 1; 21867#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 21868#L1296-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 22424#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 22379#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 21525#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 20761#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 20762#L1321-3 assume !(0 == ~T7_E~0); 20866#L1326-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 21654#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 21905#L1336-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 21906#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 21223#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 21200#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 21138#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 21139#L1361-3 assume !(0 == ~E_1~0); 21719#L1366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 20477#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 20478#L1376-3 assume 0 == ~E_4~0;~E_4~0 := 1; 22223#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 22082#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 22083#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 22257#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 22258#L1401-3 assume !(0 == ~E_9~0); 20824#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 20688#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 20689#L1416-3 assume 0 == ~E_12~0;~E_12~0 := 1; 21382#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 21383#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21490#L640-45 assume !(1 == ~m_pc~0); 21491#L640-47 is_master_triggered_~__retres1~0#1 := 0; 20932#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20933#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 20473#L1603-45 assume !(0 != activate_threads_~tmp~1#1); 20474#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20562#L659-45 assume 1 == ~t1_pc~0; 20563#L660-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 21016#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22428#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22358#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 22011#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22012#L678-45 assume 1 == ~t2_pc~0; 21963#L679-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 21497#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21498#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 21945#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 22274#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22377#L697-45 assume !(1 == ~t3_pc~0); 21760#L697-47 is_transmit3_triggered_~__retres1~3#1 := 0; 21759#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22444#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 21911#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 21912#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21946#L716-45 assume 1 == ~t4_pc~0; 21570#L717-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21572#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22229#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21577#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 21578#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 21241#L735-45 assume 1 == ~t5_pc~0; 21242#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 21790#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22395#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 22441#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 22397#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22391#L754-45 assume 1 == ~t6_pc~0; 21741#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 21742#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21635#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 21636#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 21746#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 21473#L773-45 assume 1 == ~t7_pc~0; 21474#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 21013#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 21707#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 21708#L1659-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 21481#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21132#L792-45 assume 1 == ~t8_pc~0; 21133#L793-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 22161#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22162#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 20583#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 20584#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 21082#L811-45 assume 1 == ~t9_pc~0; 20859#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 20860#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 22079#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 21942#L1675-45 assume !(0 != activate_threads_~tmp___8~0#1); 21549#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21340#L830-45 assume 1 == ~t10_pc~0; 21341#L831-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 20510#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 21658#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 20734#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 20735#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 20493#L849-45 assume !(1 == ~t11_pc~0); 20494#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 20950#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 20791#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 20479#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 20480#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 20729#L868-45 assume 1 == ~t12_pc~0; 20730#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 20673#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 20674#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 22114#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 22287#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 22288#L887-45 assume !(1 == ~t13_pc~0); 20736#L887-47 is_transmit13_triggered_~__retres1~13#1 := 0; 20737#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 22042#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 22061#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 20703#L1707-47 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20704#L1439-3 assume 1 == ~M_E~0;~M_E~0 := 2; 22037#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 20721#L1444-3 assume !(1 == ~T2_E~0); 20722#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 20880#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 21848#L1459-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 21849#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 22289#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 22226#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 22227#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 22291#L1484-3 assume !(1 == ~T10_E~0); 21531#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 21532#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 22154#L1499-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 21807#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 21808#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 22239#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 22275#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 21448#L1524-3 assume !(1 == ~E_4~0); 21449#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 22313#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 21726#L1539-3 assume 1 == ~E_7~0;~E_7~0 := 2; 21183#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 21184#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 21689#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 20768#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 20769#L1564-3 assume !(1 == ~E_12~0); 21947#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 21948#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 20660#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 20434#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 20760#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 20667#L1959 assume !(0 == start_simulation_~tmp~3#1); 20669#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 20699#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 20653#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 20488#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 20489#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 22307#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 22282#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 22283#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 20723#L1940-2 [2024-11-08 00:35:53,779 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:53,780 INFO L85 PathProgramCache]: Analyzing trace with hash 1024455497, now seen corresponding path program 1 times [2024-11-08 00:35:53,780 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:53,780 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [458350268] [2024-11-08 00:35:53,780 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:53,780 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:53,792 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:53,825 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:53,825 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:53,825 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [458350268] [2024-11-08 00:35:53,825 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [458350268] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:53,825 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:53,825 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:53,825 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1909235734] [2024-11-08 00:35:53,825 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:53,826 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:35:53,829 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:53,829 INFO L85 PathProgramCache]: Analyzing trace with hash 1079224764, now seen corresponding path program 1 times [2024-11-08 00:35:53,829 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:53,829 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [881464590] [2024-11-08 00:35:53,830 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:53,830 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:53,846 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:53,890 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:53,890 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:53,890 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [881464590] [2024-11-08 00:35:53,891 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [881464590] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:53,891 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:53,891 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:53,891 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1466277542] [2024-11-08 00:35:53,891 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:53,892 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:35:53,892 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:35:53,892 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:35:53,892 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:35:53,892 INFO L87 Difference]: Start difference. First operand 2037 states and 3006 transitions. cyclomatic complexity: 970 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:53,918 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:35:53,918 INFO L93 Difference]: Finished difference Result 2037 states and 3005 transitions. [2024-11-08 00:35:53,918 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2037 states and 3005 transitions. [2024-11-08 00:35:53,926 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2024-11-08 00:35:53,933 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2037 states to 2037 states and 3005 transitions. [2024-11-08 00:35:53,934 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2037 [2024-11-08 00:35:53,935 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2037 [2024-11-08 00:35:53,935 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2037 states and 3005 transitions. [2024-11-08 00:35:53,937 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:35:53,937 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2037 states and 3005 transitions. [2024-11-08 00:35:53,939 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2037 states and 3005 transitions. [2024-11-08 00:35:53,957 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2037 to 2037. [2024-11-08 00:35:53,960 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2037 states, 2037 states have (on average 1.4752086401570939) internal successors, (3005), 2036 states have internal predecessors, (3005), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:53,965 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2037 states to 2037 states and 3005 transitions. [2024-11-08 00:35:53,967 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2037 states and 3005 transitions. [2024-11-08 00:35:53,967 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:35:53,969 INFO L425 stractBuchiCegarLoop]: Abstraction has 2037 states and 3005 transitions. [2024-11-08 00:35:53,969 INFO L332 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-11-08 00:35:53,969 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2037 states and 3005 transitions. [2024-11-08 00:35:53,975 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2024-11-08 00:35:53,975 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:35:53,975 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:35:53,977 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:53,977 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:53,977 INFO L745 eck$LassoCheckResult]: Stem: 24796#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 24797#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 25790#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 25791#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 26526#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 25918#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 25387#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25388#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 26192#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 26193#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 26297#L939-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 26298#L944-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 25136#L949-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 25137#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 26332#L959-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 25688#L964-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 25689#L969-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 26238#L974-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 25602#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 25603#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 26527#L1291-2 assume !(0 == ~T1_E~0); 26524#L1296-1 assume !(0 == ~T2_E~0); 25752#L1301-1 assume !(0 == ~T3_E~0); 25753#L1306-1 assume !(0 == ~T4_E~0); 26248#L1311-1 assume !(0 == ~T5_E~0); 24973#L1316-1 assume !(0 == ~T6_E~0); 24974#L1321-1 assume !(0 == ~T7_E~0); 25766#L1326-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 24793#L1331-1 assume !(0 == ~T9_E~0); 24506#L1336-1 assume !(0 == ~T10_E~0); 24507#L1341-1 assume !(0 == ~T11_E~0); 24580#L1346-1 assume !(0 == ~T12_E~0); 24581#L1351-1 assume !(0 == ~T13_E~0); 24910#L1356-1 assume !(0 == ~E_M~0); 24911#L1361-1 assume !(0 == ~E_1~0); 26464#L1366-1 assume 0 == ~E_2~0;~E_2~0 := 1; 24957#L1371-1 assume !(0 == ~E_3~0); 24958#L1376-1 assume !(0 == ~E_4~0); 25818#L1381-1 assume !(0 == ~E_5~0); 25819#L1386-1 assume !(0 == ~E_6~0); 26495#L1391-1 assume !(0 == ~E_7~0); 26515#L1396-1 assume !(0 == ~E_8~0); 25720#L1401-1 assume !(0 == ~E_9~0); 25721#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 26008#L1411-1 assume !(0 == ~E_11~0); 26009#L1416-1 assume !(0 == ~E_12~0); 25638#L1421-1 assume !(0 == ~E_13~0); 25157#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25158#L640 assume !(1 == ~m_pc~0); 25687#L640-2 is_master_triggered_~__retres1~0#1 := 0; 25686#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25646#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25647#L1603 assume !(0 != activate_threads_~tmp~1#1); 25675#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25307#L659 assume 1 == ~t1_pc~0; 25308#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 25416#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26129#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25438#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 25439#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25455#L678 assume 1 == ~t2_pc~0; 26401#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 26402#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25000#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25001#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 25549#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25668#L697 assume !(1 == ~t3_pc~0); 25669#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 25799#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26119#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 25582#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 25583#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26434#L716 assume 1 == ~t4_pc~0; 26422#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 25287#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24653#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 24654#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 24761#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26083#L735 assume !(1 == ~t5_pc~0); 24728#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 24729#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25184#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 26109#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 25746#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25747#L754 assume 1 == ~t6_pc~0; 25500#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 25400#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 24977#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 24978#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 25374#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 26183#L773 assume !(1 == ~t7_pc~0); 24914#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 24913#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25781#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 25756#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 25757#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25810#L792 assume 1 == ~t8_pc~0; 25978#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 26299#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 26300#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 25748#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 25671#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 25672#L811 assume 1 == ~t9_pc~0; 25881#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 26346#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25056#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 25057#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 25683#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25684#L830 assume !(1 == ~t10_pc~0); 25409#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 24890#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 24891#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 24868#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 24869#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 26201#L849 assume 1 == ~t11_pc~0; 26202#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 24707#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 24708#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 26212#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 26113#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 26114#L868 assume !(1 == ~t12_pc~0); 25533#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 25532#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 24595#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 24596#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 24925#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 24926#L887 assume 1 == ~t13_pc~0; 26121#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 25576#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 25577#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 26177#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 24635#L1707-2 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24636#L1439 assume !(1 == ~M_E~0); 25740#L1439-2 assume !(1 == ~T1_E~0); 24806#L1444-1 assume !(1 == ~T2_E~0); 24807#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 25312#L1454-1 assume !(1 == ~T4_E~0); 25313#L1459-1 assume !(1 == ~T5_E~0); 25873#L1464-1 assume !(1 == ~T6_E~0); 25874#L1469-1 assume !(1 == ~T7_E~0); 25947#L1474-1 assume !(1 == ~T8_E~0); 25639#L1479-1 assume !(1 == ~T9_E~0); 25640#L1484-1 assume !(1 == ~T10_E~0); 25877#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 25522#L1494-1 assume !(1 == ~T12_E~0); 25523#L1499-1 assume !(1 == ~T13_E~0); 25705#L1504-1 assume !(1 == ~E_M~0); 25706#L1509-1 assume !(1 == ~E_1~0); 26284#L1514-1 assume !(1 == ~E_2~0); 25980#L1519-1 assume !(1 == ~E_3~0); 25981#L1524-1 assume !(1 == ~E_4~0); 26479#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 26480#L1534-1 assume !(1 == ~E_6~0); 24629#L1539-1 assume !(1 == ~E_7~0); 24630#L1544-1 assume !(1 == ~E_8~0); 25053#L1549-1 assume !(1 == ~E_9~0); 26452#L1554-1 assume !(1 == ~E_10~0); 26449#L1559-1 assume !(1 == ~E_11~0); 26324#L1564-1 assume !(1 == ~E_12~0); 26325#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 26474#L1574-1 assume { :end_inline_reset_delta_events } true; 24804#L1940-2 [2024-11-08 00:35:53,978 INFO L747 eck$LassoCheckResult]: Loop: 24804#L1940-2 assume !false; 24805#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 25348#L1266-1 assume !false; 26518#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 25369#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 25083#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 26283#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 26292#L1079 assume !(0 != eval_~tmp~0#1); 25566#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25221#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25222#L1291-3 assume 0 == ~M_E~0;~M_E~0 := 1; 25948#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 25949#L1296-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 26505#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 26460#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 25606#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 24842#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 24843#L1321-3 assume !(0 == ~T7_E~0); 24947#L1326-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 25735#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 25986#L1336-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 25987#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 25304#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 25281#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 25219#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 25220#L1361-3 assume !(0 == ~E_1~0); 25800#L1366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 24558#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 24559#L1376-3 assume 0 == ~E_4~0;~E_4~0 := 1; 26304#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 26163#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 26164#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 26338#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 26339#L1401-3 assume !(0 == ~E_9~0); 24905#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 24769#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 24770#L1416-3 assume 0 == ~E_12~0;~E_12~0 := 1; 25463#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 25464#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25571#L640-45 assume !(1 == ~m_pc~0); 25572#L640-47 is_master_triggered_~__retres1~0#1 := 0; 25013#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25014#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24554#L1603-45 assume !(0 != activate_threads_~tmp~1#1); 24555#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24643#L659-45 assume 1 == ~t1_pc~0; 24644#L660-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 25097#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26509#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 26439#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 26092#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26093#L678-45 assume 1 == ~t2_pc~0; 26044#L679-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 25578#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25579#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 26026#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 26355#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26458#L697-45 assume !(1 == ~t3_pc~0); 25841#L697-47 is_transmit3_triggered_~__retres1~3#1 := 0; 25840#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26525#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 25992#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 25993#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26027#L716-45 assume 1 == ~t4_pc~0; 25651#L717-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 25653#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 26310#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25658#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 25659#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25322#L735-45 assume 1 == ~t5_pc~0; 25323#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 25871#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26476#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 26522#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 26478#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26472#L754-45 assume !(1 == ~t6_pc~0); 25824#L754-47 is_transmit6_triggered_~__retres1~6#1 := 0; 25823#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25716#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 25717#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 25827#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25554#L773-45 assume 1 == ~t7_pc~0; 25555#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 25094#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25788#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 25789#L1659-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 25562#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25213#L792-45 assume 1 == ~t8_pc~0; 25214#L793-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 26242#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 26243#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 24664#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 24665#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 25163#L811-45 assume 1 == ~t9_pc~0; 24940#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 24941#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 26160#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 26023#L1675-45 assume !(0 != activate_threads_~tmp___8~0#1); 25630#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25421#L830-45 assume 1 == ~t10_pc~0; 25422#L831-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 24591#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25739#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 24815#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 24816#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 24574#L849-45 assume 1 == ~t11_pc~0; 24576#L850-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 25031#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 24872#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 24560#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 24561#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 24810#L868-45 assume 1 == ~t12_pc~0; 24811#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 24754#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 24755#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 26195#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 26368#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 26369#L887-45 assume !(1 == ~t13_pc~0); 24817#L887-47 is_transmit13_triggered_~__retres1~13#1 := 0; 24818#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 26123#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 26142#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 24784#L1707-47 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24785#L1439-3 assume 1 == ~M_E~0;~M_E~0 := 2; 26118#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 24802#L1444-3 assume !(1 == ~T2_E~0); 24803#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 24961#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 25929#L1459-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 25930#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 26370#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 26307#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 26308#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 26372#L1484-3 assume !(1 == ~T10_E~0); 25612#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 25613#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 26235#L1499-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 25888#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 25889#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 26320#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 26356#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 25529#L1524-3 assume !(1 == ~E_4~0); 25530#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 26394#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 25807#L1539-3 assume 1 == ~E_7~0;~E_7~0 := 2; 25264#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 25265#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 25770#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 24849#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 24850#L1564-3 assume !(1 == ~E_12~0); 26028#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 26029#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 24741#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 24515#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 24841#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 24748#L1959 assume !(0 == start_simulation_~tmp~3#1); 24750#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 24780#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 24734#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 24569#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 24570#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 26388#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 26363#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 26364#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 24804#L1940-2 [2024-11-08 00:35:53,979 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:53,979 INFO L85 PathProgramCache]: Analyzing trace with hash -869878389, now seen corresponding path program 1 times [2024-11-08 00:35:53,979 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:53,979 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [992528924] [2024-11-08 00:35:53,979 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:53,979 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:53,997 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:54,033 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:54,033 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:54,033 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [992528924] [2024-11-08 00:35:54,033 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [992528924] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:54,033 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:54,033 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:54,033 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2044403115] [2024-11-08 00:35:54,033 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:54,034 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:35:54,036 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:54,036 INFO L85 PathProgramCache]: Analyzing trace with hash 723874300, now seen corresponding path program 1 times [2024-11-08 00:35:54,036 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:54,036 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1188315943] [2024-11-08 00:35:54,037 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:54,037 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:54,081 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:54,123 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:54,124 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:54,124 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1188315943] [2024-11-08 00:35:54,124 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1188315943] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:54,124 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:54,124 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:54,124 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1982811326] [2024-11-08 00:35:54,124 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:54,124 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:35:54,124 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:35:54,125 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:35:54,125 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:35:54,125 INFO L87 Difference]: Start difference. First operand 2037 states and 3005 transitions. cyclomatic complexity: 969 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:54,150 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:35:54,150 INFO L93 Difference]: Finished difference Result 2037 states and 3004 transitions. [2024-11-08 00:35:54,150 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2037 states and 3004 transitions. [2024-11-08 00:35:54,157 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2024-11-08 00:35:54,163 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2037 states to 2037 states and 3004 transitions. [2024-11-08 00:35:54,164 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2037 [2024-11-08 00:35:54,165 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2037 [2024-11-08 00:35:54,165 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2037 states and 3004 transitions. [2024-11-08 00:35:54,167 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:35:54,167 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2037 states and 3004 transitions. [2024-11-08 00:35:54,170 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2037 states and 3004 transitions. [2024-11-08 00:35:54,186 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2037 to 2037. [2024-11-08 00:35:54,189 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2037 states, 2037 states have (on average 1.4747177221404026) internal successors, (3004), 2036 states have internal predecessors, (3004), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:54,196 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2037 states to 2037 states and 3004 transitions. [2024-11-08 00:35:54,196 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2037 states and 3004 transitions. [2024-11-08 00:35:54,198 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:35:54,199 INFO L425 stractBuchiCegarLoop]: Abstraction has 2037 states and 3004 transitions. [2024-11-08 00:35:54,199 INFO L332 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-11-08 00:35:54,199 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2037 states and 3004 transitions. [2024-11-08 00:35:54,205 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2024-11-08 00:35:54,205 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:35:54,205 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:35:54,207 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:54,207 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:54,209 INFO L745 eck$LassoCheckResult]: Stem: 28877#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 28878#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 29871#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 29872#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 30607#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 29999#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 29468#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 29469#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 30273#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 30274#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 30378#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 30379#L944-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 29217#L949-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 29218#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 30413#L959-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 29769#L964-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 29770#L969-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 30319#L974-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 29683#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 29684#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 30608#L1291-2 assume !(0 == ~T1_E~0); 30605#L1296-1 assume !(0 == ~T2_E~0); 29833#L1301-1 assume !(0 == ~T3_E~0); 29834#L1306-1 assume !(0 == ~T4_E~0); 30329#L1311-1 assume !(0 == ~T5_E~0); 29054#L1316-1 assume !(0 == ~T6_E~0); 29055#L1321-1 assume !(0 == ~T7_E~0); 29847#L1326-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 28874#L1331-1 assume !(0 == ~T9_E~0); 28587#L1336-1 assume !(0 == ~T10_E~0); 28588#L1341-1 assume !(0 == ~T11_E~0); 28661#L1346-1 assume !(0 == ~T12_E~0); 28662#L1351-1 assume !(0 == ~T13_E~0); 28991#L1356-1 assume !(0 == ~E_M~0); 28992#L1361-1 assume !(0 == ~E_1~0); 30545#L1366-1 assume 0 == ~E_2~0;~E_2~0 := 1; 29038#L1371-1 assume !(0 == ~E_3~0); 29039#L1376-1 assume !(0 == ~E_4~0); 29899#L1381-1 assume !(0 == ~E_5~0); 29900#L1386-1 assume !(0 == ~E_6~0); 30576#L1391-1 assume !(0 == ~E_7~0); 30596#L1396-1 assume !(0 == ~E_8~0); 29801#L1401-1 assume !(0 == ~E_9~0); 29802#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 30089#L1411-1 assume !(0 == ~E_11~0); 30090#L1416-1 assume !(0 == ~E_12~0); 29719#L1421-1 assume !(0 == ~E_13~0); 29238#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29239#L640 assume !(1 == ~m_pc~0); 29768#L640-2 is_master_triggered_~__retres1~0#1 := 0; 29767#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29727#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 29728#L1603 assume !(0 != activate_threads_~tmp~1#1); 29756#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29388#L659 assume 1 == ~t1_pc~0; 29389#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 29497#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30210#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29519#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 29520#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29536#L678 assume 1 == ~t2_pc~0; 30482#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 30483#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29081#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 29082#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 29630#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29749#L697 assume !(1 == ~t3_pc~0); 29750#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 29880#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30200#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29663#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 29664#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30515#L716 assume 1 == ~t4_pc~0; 30503#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 29368#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28734#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 28735#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 28842#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 30164#L735 assume !(1 == ~t5_pc~0); 28809#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 28810#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29265#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 30190#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 29827#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29828#L754 assume 1 == ~t6_pc~0; 29581#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 29481#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29058#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29059#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 29455#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 30264#L773 assume !(1 == ~t7_pc~0); 28995#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 28994#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29862#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 29837#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 29838#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29891#L792 assume 1 == ~t8_pc~0; 30059#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 30380#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 30381#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 29829#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 29752#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29753#L811 assume 1 == ~t9_pc~0; 29962#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 30427#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 29137#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 29138#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 29764#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29765#L830 assume !(1 == ~t10_pc~0); 29490#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 28971#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 28972#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 28949#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 28950#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 30282#L849 assume 1 == ~t11_pc~0; 30283#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 28788#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 28789#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 30293#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 30194#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 30195#L868 assume !(1 == ~t12_pc~0); 29614#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 29613#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 28676#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 28677#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 29006#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 29007#L887 assume 1 == ~t13_pc~0; 30202#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 29657#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 29658#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 30258#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 28716#L1707-2 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28717#L1439 assume !(1 == ~M_E~0); 29821#L1439-2 assume !(1 == ~T1_E~0); 28887#L1444-1 assume !(1 == ~T2_E~0); 28888#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 29393#L1454-1 assume !(1 == ~T4_E~0); 29394#L1459-1 assume !(1 == ~T5_E~0); 29954#L1464-1 assume !(1 == ~T6_E~0); 29955#L1469-1 assume !(1 == ~T7_E~0); 30028#L1474-1 assume !(1 == ~T8_E~0); 29720#L1479-1 assume !(1 == ~T9_E~0); 29721#L1484-1 assume !(1 == ~T10_E~0); 29958#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 29603#L1494-1 assume !(1 == ~T12_E~0); 29604#L1499-1 assume !(1 == ~T13_E~0); 29786#L1504-1 assume !(1 == ~E_M~0); 29787#L1509-1 assume !(1 == ~E_1~0); 30365#L1514-1 assume !(1 == ~E_2~0); 30061#L1519-1 assume !(1 == ~E_3~0); 30062#L1524-1 assume !(1 == ~E_4~0); 30560#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 30561#L1534-1 assume !(1 == ~E_6~0); 28710#L1539-1 assume !(1 == ~E_7~0); 28711#L1544-1 assume !(1 == ~E_8~0); 29134#L1549-1 assume !(1 == ~E_9~0); 30533#L1554-1 assume !(1 == ~E_10~0); 30530#L1559-1 assume !(1 == ~E_11~0); 30405#L1564-1 assume !(1 == ~E_12~0); 30406#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 30555#L1574-1 assume { :end_inline_reset_delta_events } true; 28885#L1940-2 [2024-11-08 00:35:54,210 INFO L747 eck$LassoCheckResult]: Loop: 28885#L1940-2 assume !false; 28886#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 29429#L1266-1 assume !false; 30599#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 29450#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 29164#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 30364#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 30373#L1079 assume !(0 != eval_~tmp~0#1); 29647#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 29302#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 29303#L1291-3 assume 0 == ~M_E~0;~M_E~0 := 1; 30029#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 30030#L1296-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 30586#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 30541#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 29687#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 28923#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 28924#L1321-3 assume !(0 == ~T7_E~0); 29028#L1326-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 29816#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 30067#L1336-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 30068#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 29385#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 29362#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 29300#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 29301#L1361-3 assume !(0 == ~E_1~0); 29881#L1366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 28639#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 28640#L1376-3 assume 0 == ~E_4~0;~E_4~0 := 1; 30385#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 30244#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 30245#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 30419#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 30420#L1401-3 assume !(0 == ~E_9~0); 28986#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 28850#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 28851#L1416-3 assume 0 == ~E_12~0;~E_12~0 := 1; 29544#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 29545#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29652#L640-45 assume !(1 == ~m_pc~0); 29653#L640-47 is_master_triggered_~__retres1~0#1 := 0; 29094#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29095#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 28635#L1603-45 assume !(0 != activate_threads_~tmp~1#1); 28636#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28724#L659-45 assume 1 == ~t1_pc~0; 28725#L660-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 29178#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30590#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 30520#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 30173#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30174#L678-45 assume 1 == ~t2_pc~0; 30125#L679-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 29659#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29660#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 30107#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 30436#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30539#L697-45 assume 1 == ~t3_pc~0; 29920#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 29921#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30606#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 30073#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 30074#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30108#L716-45 assume 1 == ~t4_pc~0; 29732#L717-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 29734#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30391#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 29739#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 29740#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29403#L735-45 assume 1 == ~t5_pc~0; 29404#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 29952#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30557#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 30603#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 30559#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 30553#L754-45 assume !(1 == ~t6_pc~0); 29905#L754-47 is_transmit6_triggered_~__retres1~6#1 := 0; 29904#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29797#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29798#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 29908#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29635#L773-45 assume 1 == ~t7_pc~0; 29636#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 29175#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29869#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 29870#L1659-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 29643#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29294#L792-45 assume !(1 == ~t8_pc~0); 29296#L792-47 is_transmit8_triggered_~__retres1~8#1 := 0; 30323#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 30324#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 28745#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 28746#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29244#L811-45 assume 1 == ~t9_pc~0; 29021#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 29022#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 30241#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 30104#L1675-45 assume !(0 != activate_threads_~tmp___8~0#1); 29711#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29502#L830-45 assume 1 == ~t10_pc~0; 29503#L831-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 28672#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29820#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 28896#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 28897#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 28655#L849-45 assume !(1 == ~t11_pc~0); 28656#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 29112#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 28953#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 28641#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 28642#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 28891#L868-45 assume 1 == ~t12_pc~0; 28892#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 28835#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 28836#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 30276#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 30449#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 30450#L887-45 assume !(1 == ~t13_pc~0); 28898#L887-47 is_transmit13_triggered_~__retres1~13#1 := 0; 28899#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 30204#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 30223#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 28865#L1707-47 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28866#L1439-3 assume 1 == ~M_E~0;~M_E~0 := 2; 30199#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 28883#L1444-3 assume !(1 == ~T2_E~0); 28884#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 29042#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 30010#L1459-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 30011#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 30451#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 30388#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 30389#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 30453#L1484-3 assume !(1 == ~T10_E~0); 29693#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 29694#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 30316#L1499-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 29969#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 29970#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 30401#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 30437#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 29610#L1524-3 assume !(1 == ~E_4~0); 29611#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 30475#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 29888#L1539-3 assume 1 == ~E_7~0;~E_7~0 := 2; 29345#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 29346#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 29851#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 28930#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 28931#L1564-3 assume !(1 == ~E_12~0); 30109#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 30110#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 28822#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 28596#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 28922#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 28829#L1959 assume !(0 == start_simulation_~tmp~3#1); 28831#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 28861#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 28815#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 28650#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 28651#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 30469#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 30444#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 30445#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 28885#L1940-2 [2024-11-08 00:35:54,210 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:54,210 INFO L85 PathProgramCache]: Analyzing trace with hash 1978508041, now seen corresponding path program 1 times [2024-11-08 00:35:54,210 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:54,210 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1755460425] [2024-11-08 00:35:54,210 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:54,211 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:54,222 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:54,251 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:54,251 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:54,251 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1755460425] [2024-11-08 00:35:54,253 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1755460425] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:54,253 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:54,253 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:54,253 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1044135069] [2024-11-08 00:35:54,253 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:54,253 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:35:54,254 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:54,254 INFO L85 PathProgramCache]: Analyzing trace with hash 774135229, now seen corresponding path program 1 times [2024-11-08 00:35:54,254 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:54,254 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2031690212] [2024-11-08 00:35:54,254 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:54,254 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:54,267 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:54,310 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:54,310 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:54,311 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2031690212] [2024-11-08 00:35:54,311 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2031690212] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:54,311 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:54,311 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:54,311 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1644265702] [2024-11-08 00:35:54,311 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:54,311 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:35:54,311 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:35:54,311 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:35:54,311 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:35:54,312 INFO L87 Difference]: Start difference. First operand 2037 states and 3004 transitions. cyclomatic complexity: 968 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:54,337 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:35:54,337 INFO L93 Difference]: Finished difference Result 2037 states and 3003 transitions. [2024-11-08 00:35:54,337 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2037 states and 3003 transitions. [2024-11-08 00:35:54,343 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2024-11-08 00:35:54,349 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2037 states to 2037 states and 3003 transitions. [2024-11-08 00:35:54,349 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2037 [2024-11-08 00:35:54,350 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2037 [2024-11-08 00:35:54,350 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2037 states and 3003 transitions. [2024-11-08 00:35:54,352 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:35:54,352 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2037 states and 3003 transitions. [2024-11-08 00:35:54,354 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2037 states and 3003 transitions. [2024-11-08 00:35:54,372 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2037 to 2037. [2024-11-08 00:35:54,374 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2037 states, 2037 states have (on average 1.4742268041237114) internal successors, (3003), 2036 states have internal predecessors, (3003), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:54,378 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2037 states to 2037 states and 3003 transitions. [2024-11-08 00:35:54,378 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2037 states and 3003 transitions. [2024-11-08 00:35:54,379 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:35:54,381 INFO L425 stractBuchiCegarLoop]: Abstraction has 2037 states and 3003 transitions. [2024-11-08 00:35:54,381 INFO L332 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-11-08 00:35:54,381 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2037 states and 3003 transitions. [2024-11-08 00:35:54,386 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2024-11-08 00:35:54,386 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:35:54,386 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:35:54,388 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:54,388 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:54,388 INFO L745 eck$LassoCheckResult]: Stem: 32958#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 32959#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 33952#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 33953#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 34688#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 34080#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 33549#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 33550#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 34354#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 34355#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 34459#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 34460#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 33298#L949-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 33299#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 34494#L959-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 33850#L964-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 33851#L969-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 34400#L974-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 33764#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 33765#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 34689#L1291-2 assume !(0 == ~T1_E~0); 34686#L1296-1 assume !(0 == ~T2_E~0); 33914#L1301-1 assume !(0 == ~T3_E~0); 33915#L1306-1 assume !(0 == ~T4_E~0); 34410#L1311-1 assume !(0 == ~T5_E~0); 33135#L1316-1 assume !(0 == ~T6_E~0); 33136#L1321-1 assume !(0 == ~T7_E~0); 33928#L1326-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 32955#L1331-1 assume !(0 == ~T9_E~0); 32668#L1336-1 assume !(0 == ~T10_E~0); 32669#L1341-1 assume !(0 == ~T11_E~0); 32742#L1346-1 assume !(0 == ~T12_E~0); 32743#L1351-1 assume !(0 == ~T13_E~0); 33072#L1356-1 assume !(0 == ~E_M~0); 33073#L1361-1 assume !(0 == ~E_1~0); 34626#L1366-1 assume 0 == ~E_2~0;~E_2~0 := 1; 33119#L1371-1 assume !(0 == ~E_3~0); 33120#L1376-1 assume !(0 == ~E_4~0); 33980#L1381-1 assume !(0 == ~E_5~0); 33981#L1386-1 assume !(0 == ~E_6~0); 34657#L1391-1 assume !(0 == ~E_7~0); 34677#L1396-1 assume !(0 == ~E_8~0); 33882#L1401-1 assume !(0 == ~E_9~0); 33883#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 34170#L1411-1 assume !(0 == ~E_11~0); 34171#L1416-1 assume !(0 == ~E_12~0); 33800#L1421-1 assume !(0 == ~E_13~0); 33319#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33320#L640 assume !(1 == ~m_pc~0); 33849#L640-2 is_master_triggered_~__retres1~0#1 := 0; 33848#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33808#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 33809#L1603 assume !(0 != activate_threads_~tmp~1#1); 33837#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33469#L659 assume 1 == ~t1_pc~0; 33470#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 33578#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 34291#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 33600#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 33601#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33617#L678 assume 1 == ~t2_pc~0; 34563#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 34564#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33162#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 33163#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 33711#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33830#L697 assume !(1 == ~t3_pc~0); 33831#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 33961#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34281#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 33744#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 33745#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 34596#L716 assume 1 == ~t4_pc~0; 34584#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 33449#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 32815#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 32816#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 32923#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 34245#L735 assume !(1 == ~t5_pc~0); 32890#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 32891#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 33346#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 34271#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 33908#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 33909#L754 assume 1 == ~t6_pc~0; 33662#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 33562#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33139#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 33140#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 33536#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 34345#L773 assume !(1 == ~t7_pc~0); 33076#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 33075#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 33943#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 33918#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 33919#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 33972#L792 assume 1 == ~t8_pc~0; 34140#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 34461#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 34462#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 33910#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 33833#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 33834#L811 assume 1 == ~t9_pc~0; 34043#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 34508#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 33218#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 33219#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 33845#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 33846#L830 assume !(1 == ~t10_pc~0); 33571#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 33052#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 33053#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 33030#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 33031#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 34363#L849 assume 1 == ~t11_pc~0; 34364#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 32869#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 32870#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 34374#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 34275#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 34276#L868 assume !(1 == ~t12_pc~0); 33695#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 33694#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 32757#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 32758#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 33087#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 33088#L887 assume 1 == ~t13_pc~0; 34283#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 33738#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 33739#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 34339#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 32797#L1707-2 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32798#L1439 assume !(1 == ~M_E~0); 33902#L1439-2 assume !(1 == ~T1_E~0); 32968#L1444-1 assume !(1 == ~T2_E~0); 32969#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 33474#L1454-1 assume !(1 == ~T4_E~0); 33475#L1459-1 assume !(1 == ~T5_E~0); 34035#L1464-1 assume !(1 == ~T6_E~0); 34036#L1469-1 assume !(1 == ~T7_E~0); 34109#L1474-1 assume !(1 == ~T8_E~0); 33801#L1479-1 assume !(1 == ~T9_E~0); 33802#L1484-1 assume !(1 == ~T10_E~0); 34039#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 33684#L1494-1 assume !(1 == ~T12_E~0); 33685#L1499-1 assume !(1 == ~T13_E~0); 33867#L1504-1 assume !(1 == ~E_M~0); 33868#L1509-1 assume !(1 == ~E_1~0); 34446#L1514-1 assume !(1 == ~E_2~0); 34142#L1519-1 assume !(1 == ~E_3~0); 34143#L1524-1 assume !(1 == ~E_4~0); 34641#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 34642#L1534-1 assume !(1 == ~E_6~0); 32791#L1539-1 assume !(1 == ~E_7~0); 32792#L1544-1 assume !(1 == ~E_8~0); 33215#L1549-1 assume !(1 == ~E_9~0); 34614#L1554-1 assume !(1 == ~E_10~0); 34611#L1559-1 assume !(1 == ~E_11~0); 34486#L1564-1 assume !(1 == ~E_12~0); 34487#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 34636#L1574-1 assume { :end_inline_reset_delta_events } true; 32966#L1940-2 [2024-11-08 00:35:54,389 INFO L747 eck$LassoCheckResult]: Loop: 32966#L1940-2 assume !false; 32967#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 33510#L1266-1 assume !false; 34680#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 33531#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 33245#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 34445#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 34454#L1079 assume !(0 != eval_~tmp~0#1); 33728#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 33383#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 33384#L1291-3 assume 0 == ~M_E~0;~M_E~0 := 1; 34110#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 34111#L1296-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 34667#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 34622#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 33768#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 33004#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 33005#L1321-3 assume !(0 == ~T7_E~0); 33109#L1326-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 33897#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 34148#L1336-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 34149#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 33466#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 33443#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 33381#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 33382#L1361-3 assume !(0 == ~E_1~0); 33962#L1366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 32720#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 32721#L1376-3 assume 0 == ~E_4~0;~E_4~0 := 1; 34466#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 34325#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 34326#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 34500#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 34501#L1401-3 assume !(0 == ~E_9~0); 33067#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 32931#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 32932#L1416-3 assume 0 == ~E_12~0;~E_12~0 := 1; 33625#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 33626#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33733#L640-45 assume !(1 == ~m_pc~0); 33734#L640-47 is_master_triggered_~__retres1~0#1 := 0; 33175#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33176#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 32716#L1603-45 assume !(0 != activate_threads_~tmp~1#1); 32717#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 32805#L659-45 assume 1 == ~t1_pc~0; 32806#L660-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 33259#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 34671#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 34601#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 34254#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34255#L678-45 assume 1 == ~t2_pc~0; 34206#L679-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 33740#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33741#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 34188#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 34517#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34620#L697-45 assume 1 == ~t3_pc~0; 34001#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 34002#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34687#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 34154#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 34155#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 34189#L716-45 assume 1 == ~t4_pc~0; 33813#L717-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 33815#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 34472#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 33820#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 33821#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33484#L735-45 assume 1 == ~t5_pc~0; 33485#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 34033#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 34638#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 34684#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 34640#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 34634#L754-45 assume 1 == ~t6_pc~0; 33984#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 33985#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33878#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 33879#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 33989#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33716#L773-45 assume 1 == ~t7_pc~0; 33717#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 33256#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 33950#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 33951#L1659-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 33724#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 33375#L792-45 assume 1 == ~t8_pc~0; 33376#L793-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 34404#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 34405#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 32826#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 32827#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 33325#L811-45 assume !(1 == ~t9_pc~0); 33104#L811-47 is_transmit9_triggered_~__retres1~9#1 := 0; 33103#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 34322#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 34185#L1675-45 assume !(0 != activate_threads_~tmp___8~0#1); 33792#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 33583#L830-45 assume 1 == ~t10_pc~0; 33584#L831-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 32753#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 33901#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 32977#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 32978#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 32736#L849-45 assume !(1 == ~t11_pc~0); 32737#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 33193#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 33034#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 32722#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 32723#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 32972#L868-45 assume 1 == ~t12_pc~0; 32973#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 32916#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 32917#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 34357#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 34530#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 34531#L887-45 assume !(1 == ~t13_pc~0); 32979#L887-47 is_transmit13_triggered_~__retres1~13#1 := 0; 32980#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 34285#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 34304#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 32946#L1707-47 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32947#L1439-3 assume 1 == ~M_E~0;~M_E~0 := 2; 34280#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 32964#L1444-3 assume !(1 == ~T2_E~0); 32965#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 33123#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 34091#L1459-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 34092#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 34532#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 34469#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 34470#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 34534#L1484-3 assume !(1 == ~T10_E~0); 33774#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 33775#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 34397#L1499-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 34050#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 34051#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 34482#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 34518#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 33691#L1524-3 assume !(1 == ~E_4~0); 33692#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 34556#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 33969#L1539-3 assume 1 == ~E_7~0;~E_7~0 := 2; 33426#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 33427#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 33932#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 33011#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 33012#L1564-3 assume !(1 == ~E_12~0); 34190#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 34191#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 32903#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 32677#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 33003#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 32910#L1959 assume !(0 == start_simulation_~tmp~3#1); 32912#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 32942#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 32896#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 32731#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 32732#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 34550#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 34525#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 34526#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 32966#L1940-2 [2024-11-08 00:35:54,389 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:54,389 INFO L85 PathProgramCache]: Analyzing trace with hash -1393291829, now seen corresponding path program 1 times [2024-11-08 00:35:54,389 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:54,389 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [268588106] [2024-11-08 00:35:54,390 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:54,390 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:54,402 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:54,429 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:54,429 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:54,429 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [268588106] [2024-11-08 00:35:54,429 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [268588106] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:54,429 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:54,429 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:54,429 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [857872896] [2024-11-08 00:35:54,430 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:54,430 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:35:54,430 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:54,431 INFO L85 PathProgramCache]: Analyzing trace with hash 2047809084, now seen corresponding path program 1 times [2024-11-08 00:35:54,431 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:54,431 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1437687359] [2024-11-08 00:35:54,463 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:54,463 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:54,476 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:54,518 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:54,518 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:54,518 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1437687359] [2024-11-08 00:35:54,518 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1437687359] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:54,518 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:54,518 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:54,519 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1045627522] [2024-11-08 00:35:54,519 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:54,519 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:35:54,519 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:35:54,519 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:35:54,519 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:35:54,520 INFO L87 Difference]: Start difference. First operand 2037 states and 3003 transitions. cyclomatic complexity: 967 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:54,549 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:35:54,549 INFO L93 Difference]: Finished difference Result 2037 states and 3002 transitions. [2024-11-08 00:35:54,549 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2037 states and 3002 transitions. [2024-11-08 00:35:54,557 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2024-11-08 00:35:54,565 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2037 states to 2037 states and 3002 transitions. [2024-11-08 00:35:54,565 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2037 [2024-11-08 00:35:54,566 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2037 [2024-11-08 00:35:54,566 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2037 states and 3002 transitions. [2024-11-08 00:35:54,569 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:35:54,569 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2037 states and 3002 transitions. [2024-11-08 00:35:54,571 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2037 states and 3002 transitions. [2024-11-08 00:35:54,591 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2037 to 2037. [2024-11-08 00:35:54,593 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2037 states, 2037 states have (on average 1.4737358861070202) internal successors, (3002), 2036 states have internal predecessors, (3002), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:54,598 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2037 states to 2037 states and 3002 transitions. [2024-11-08 00:35:54,598 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2037 states and 3002 transitions. [2024-11-08 00:35:54,599 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:35:54,603 INFO L425 stractBuchiCegarLoop]: Abstraction has 2037 states and 3002 transitions. [2024-11-08 00:35:54,603 INFO L332 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-11-08 00:35:54,603 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2037 states and 3002 transitions. [2024-11-08 00:35:54,609 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2024-11-08 00:35:54,609 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:35:54,609 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:35:54,611 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:54,611 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:54,611 INFO L745 eck$LassoCheckResult]: Stem: 37039#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 37040#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 38033#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 38034#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 38769#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 38161#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 37630#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 37631#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 38435#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 38436#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 38540#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 38541#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 37379#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 37380#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 38575#L959-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 37931#L964-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 37932#L969-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 38481#L974-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 37845#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 37846#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 38770#L1291-2 assume !(0 == ~T1_E~0); 38767#L1296-1 assume !(0 == ~T2_E~0); 37995#L1301-1 assume !(0 == ~T3_E~0); 37996#L1306-1 assume !(0 == ~T4_E~0); 38491#L1311-1 assume !(0 == ~T5_E~0); 37216#L1316-1 assume !(0 == ~T6_E~0); 37217#L1321-1 assume !(0 == ~T7_E~0); 38009#L1326-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 37036#L1331-1 assume !(0 == ~T9_E~0); 36749#L1336-1 assume !(0 == ~T10_E~0); 36750#L1341-1 assume !(0 == ~T11_E~0); 36823#L1346-1 assume !(0 == ~T12_E~0); 36824#L1351-1 assume !(0 == ~T13_E~0); 37153#L1356-1 assume !(0 == ~E_M~0); 37154#L1361-1 assume !(0 == ~E_1~0); 38707#L1366-1 assume 0 == ~E_2~0;~E_2~0 := 1; 37200#L1371-1 assume !(0 == ~E_3~0); 37201#L1376-1 assume !(0 == ~E_4~0); 38061#L1381-1 assume !(0 == ~E_5~0); 38062#L1386-1 assume !(0 == ~E_6~0); 38738#L1391-1 assume !(0 == ~E_7~0); 38758#L1396-1 assume !(0 == ~E_8~0); 37963#L1401-1 assume !(0 == ~E_9~0); 37964#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 38251#L1411-1 assume !(0 == ~E_11~0); 38252#L1416-1 assume !(0 == ~E_12~0); 37881#L1421-1 assume !(0 == ~E_13~0); 37400#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37401#L640 assume !(1 == ~m_pc~0); 37930#L640-2 is_master_triggered_~__retres1~0#1 := 0; 37929#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 37889#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 37890#L1603 assume !(0 != activate_threads_~tmp~1#1); 37918#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 37550#L659 assume 1 == ~t1_pc~0; 37551#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 37659#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 38372#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 37681#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 37682#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 37698#L678 assume 1 == ~t2_pc~0; 38644#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 38645#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 37243#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 37244#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 37792#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 37911#L697 assume !(1 == ~t3_pc~0); 37912#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 38042#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38362#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 37825#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 37826#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 38677#L716 assume 1 == ~t4_pc~0; 38665#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 37530#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36896#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 36897#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 37004#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 38326#L735 assume !(1 == ~t5_pc~0); 36971#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 36972#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 37427#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 38352#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 37989#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 37990#L754 assume 1 == ~t6_pc~0; 37743#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 37643#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 37220#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 37221#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 37617#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 38426#L773 assume !(1 == ~t7_pc~0); 37157#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 37156#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 38024#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 37999#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 38000#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 38053#L792 assume 1 == ~t8_pc~0; 38221#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 38542#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 38543#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 37991#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 37914#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 37915#L811 assume 1 == ~t9_pc~0; 38124#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 38589#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 37299#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 37300#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 37926#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 37927#L830 assume !(1 == ~t10_pc~0); 37652#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 37133#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 37134#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 37111#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 37112#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 38444#L849 assume 1 == ~t11_pc~0; 38445#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 36950#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 36951#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 38455#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 38356#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 38357#L868 assume !(1 == ~t12_pc~0); 37776#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 37775#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 36838#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 36839#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 37168#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 37169#L887 assume 1 == ~t13_pc~0; 38364#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 37819#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 37820#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 38420#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 36878#L1707-2 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36879#L1439 assume !(1 == ~M_E~0); 37983#L1439-2 assume !(1 == ~T1_E~0); 37049#L1444-1 assume !(1 == ~T2_E~0); 37050#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 37555#L1454-1 assume !(1 == ~T4_E~0); 37556#L1459-1 assume !(1 == ~T5_E~0); 38116#L1464-1 assume !(1 == ~T6_E~0); 38117#L1469-1 assume !(1 == ~T7_E~0); 38190#L1474-1 assume !(1 == ~T8_E~0); 37882#L1479-1 assume !(1 == ~T9_E~0); 37883#L1484-1 assume !(1 == ~T10_E~0); 38120#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 37765#L1494-1 assume !(1 == ~T12_E~0); 37766#L1499-1 assume !(1 == ~T13_E~0); 37948#L1504-1 assume !(1 == ~E_M~0); 37949#L1509-1 assume !(1 == ~E_1~0); 38527#L1514-1 assume !(1 == ~E_2~0); 38223#L1519-1 assume !(1 == ~E_3~0); 38224#L1524-1 assume !(1 == ~E_4~0); 38722#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 38723#L1534-1 assume !(1 == ~E_6~0); 36872#L1539-1 assume !(1 == ~E_7~0); 36873#L1544-1 assume !(1 == ~E_8~0); 37296#L1549-1 assume !(1 == ~E_9~0); 38695#L1554-1 assume !(1 == ~E_10~0); 38692#L1559-1 assume !(1 == ~E_11~0); 38567#L1564-1 assume !(1 == ~E_12~0); 38568#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 38717#L1574-1 assume { :end_inline_reset_delta_events } true; 37047#L1940-2 [2024-11-08 00:35:54,612 INFO L747 eck$LassoCheckResult]: Loop: 37047#L1940-2 assume !false; 37048#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 37591#L1266-1 assume !false; 38761#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 37612#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 37326#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 38526#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 38535#L1079 assume !(0 != eval_~tmp~0#1); 37809#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 37464#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 37465#L1291-3 assume 0 == ~M_E~0;~M_E~0 := 1; 38191#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 38192#L1296-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 38748#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 38703#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 37849#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 37085#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 37086#L1321-3 assume !(0 == ~T7_E~0); 37190#L1326-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 37978#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 38229#L1336-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 38230#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 37547#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 37524#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 37462#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 37463#L1361-3 assume !(0 == ~E_1~0); 38043#L1366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 36801#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 36802#L1376-3 assume 0 == ~E_4~0;~E_4~0 := 1; 38547#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 38406#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 38407#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 38581#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 38582#L1401-3 assume !(0 == ~E_9~0); 37148#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 37012#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 37013#L1416-3 assume 0 == ~E_12~0;~E_12~0 := 1; 37706#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 37707#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37814#L640-45 assume !(1 == ~m_pc~0); 37815#L640-47 is_master_triggered_~__retres1~0#1 := 0; 37256#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 37257#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 36797#L1603-45 assume !(0 != activate_threads_~tmp~1#1); 36798#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36886#L659-45 assume 1 == ~t1_pc~0; 36887#L660-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 37340#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 38752#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 38682#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 38335#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38336#L678-45 assume !(1 == ~t2_pc~0); 38288#L678-47 is_transmit2_triggered_~__retres1~2#1 := 0; 37821#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 37822#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 38269#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 38598#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 38701#L697-45 assume 1 == ~t3_pc~0; 38082#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 38083#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38768#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 38235#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 38236#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 38270#L716-45 assume 1 == ~t4_pc~0; 37894#L717-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 37896#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 38553#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 37901#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 37902#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 37565#L735-45 assume 1 == ~t5_pc~0; 37566#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 38114#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 38719#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 38765#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 38721#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 38715#L754-45 assume 1 == ~t6_pc~0; 38065#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 38066#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 37959#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 37960#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 38070#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 37797#L773-45 assume 1 == ~t7_pc~0; 37798#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 37337#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 38031#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 38032#L1659-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 37805#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 37456#L792-45 assume 1 == ~t8_pc~0; 37457#L793-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 38485#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 38486#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 36907#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 36908#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 37406#L811-45 assume !(1 == ~t9_pc~0); 37185#L811-47 is_transmit9_triggered_~__retres1~9#1 := 0; 37184#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 38403#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 38266#L1675-45 assume !(0 != activate_threads_~tmp___8~0#1); 37873#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 37664#L830-45 assume 1 == ~t10_pc~0; 37665#L831-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 36834#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 37982#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 37058#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 37059#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 36817#L849-45 assume !(1 == ~t11_pc~0); 36818#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 37274#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 37115#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 36803#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 36804#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 37053#L868-45 assume 1 == ~t12_pc~0; 37054#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 36997#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 36998#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 38438#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 38611#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 38612#L887-45 assume !(1 == ~t13_pc~0); 37060#L887-47 is_transmit13_triggered_~__retres1~13#1 := 0; 37061#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 38366#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 38385#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 37027#L1707-47 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37028#L1439-3 assume 1 == ~M_E~0;~M_E~0 := 2; 38361#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 37045#L1444-3 assume !(1 == ~T2_E~0); 37046#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 37204#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 38172#L1459-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 38173#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 38613#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 38550#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 38551#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 38615#L1484-3 assume !(1 == ~T10_E~0); 37855#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 37856#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 38478#L1499-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 38131#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 38132#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 38563#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 38599#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 37772#L1524-3 assume !(1 == ~E_4~0); 37773#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 38637#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 38050#L1539-3 assume 1 == ~E_7~0;~E_7~0 := 2; 37507#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 37508#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 38013#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 37092#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 37093#L1564-3 assume !(1 == ~E_12~0); 38271#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 38272#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 36984#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 36758#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 37084#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 36991#L1959 assume !(0 == start_simulation_~tmp~3#1); 36993#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 37023#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 36977#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 36812#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 36813#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 38631#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 38606#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 38607#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 37047#L1940-2 [2024-11-08 00:35:54,612 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:54,613 INFO L85 PathProgramCache]: Analyzing trace with hash -1779154231, now seen corresponding path program 1 times [2024-11-08 00:35:54,613 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:54,613 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1042028794] [2024-11-08 00:35:54,613 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:54,613 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:54,625 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:54,653 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:54,653 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:54,654 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1042028794] [2024-11-08 00:35:54,654 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1042028794] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:54,654 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:54,654 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:54,654 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [361004889] [2024-11-08 00:35:54,654 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:54,654 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:35:54,654 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:54,655 INFO L85 PathProgramCache]: Analyzing trace with hash -1230532739, now seen corresponding path program 1 times [2024-11-08 00:35:54,655 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:54,655 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [942960010] [2024-11-08 00:35:54,655 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:54,655 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:54,669 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:54,709 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:54,709 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:54,709 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [942960010] [2024-11-08 00:35:54,709 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [942960010] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:54,709 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:54,710 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:54,710 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [34327386] [2024-11-08 00:35:54,710 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:54,710 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:35:54,710 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:35:54,710 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:35:54,711 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:35:54,711 INFO L87 Difference]: Start difference. First operand 2037 states and 3002 transitions. cyclomatic complexity: 966 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:54,744 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:35:54,744 INFO L93 Difference]: Finished difference Result 2037 states and 3001 transitions. [2024-11-08 00:35:54,744 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2037 states and 3001 transitions. [2024-11-08 00:35:54,751 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2024-11-08 00:35:54,764 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2037 states to 2037 states and 3001 transitions. [2024-11-08 00:35:54,764 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2037 [2024-11-08 00:35:54,766 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2037 [2024-11-08 00:35:54,766 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2037 states and 3001 transitions. [2024-11-08 00:35:54,769 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:35:54,769 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2037 states and 3001 transitions. [2024-11-08 00:35:54,771 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2037 states and 3001 transitions. [2024-11-08 00:35:54,791 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2037 to 2037. [2024-11-08 00:35:54,794 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2037 states, 2037 states have (on average 1.473244968090329) internal successors, (3001), 2036 states have internal predecessors, (3001), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:54,804 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2037 states to 2037 states and 3001 transitions. [2024-11-08 00:35:54,804 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2037 states and 3001 transitions. [2024-11-08 00:35:54,804 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:35:54,805 INFO L425 stractBuchiCegarLoop]: Abstraction has 2037 states and 3001 transitions. [2024-11-08 00:35:54,805 INFO L332 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-11-08 00:35:54,805 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2037 states and 3001 transitions. [2024-11-08 00:35:54,811 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2024-11-08 00:35:54,812 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:35:54,812 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:35:54,813 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:54,814 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:54,814 INFO L745 eck$LassoCheckResult]: Stem: 41120#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 41121#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 42114#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 42115#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 42850#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 42242#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 41711#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 41712#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 42516#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 42517#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 42621#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 42622#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 41460#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 41461#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 42656#L959-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 42012#L964-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 42013#L969-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 42562#L974-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 41926#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 41927#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 42851#L1291-2 assume !(0 == ~T1_E~0); 42848#L1296-1 assume !(0 == ~T2_E~0); 42076#L1301-1 assume !(0 == ~T3_E~0); 42077#L1306-1 assume !(0 == ~T4_E~0); 42572#L1311-1 assume !(0 == ~T5_E~0); 41297#L1316-1 assume !(0 == ~T6_E~0); 41298#L1321-1 assume !(0 == ~T7_E~0); 42090#L1326-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 41117#L1331-1 assume !(0 == ~T9_E~0); 40830#L1336-1 assume !(0 == ~T10_E~0); 40831#L1341-1 assume !(0 == ~T11_E~0); 40904#L1346-1 assume !(0 == ~T12_E~0); 40905#L1351-1 assume !(0 == ~T13_E~0); 41234#L1356-1 assume !(0 == ~E_M~0); 41235#L1361-1 assume !(0 == ~E_1~0); 42788#L1366-1 assume 0 == ~E_2~0;~E_2~0 := 1; 41281#L1371-1 assume !(0 == ~E_3~0); 41282#L1376-1 assume !(0 == ~E_4~0); 42142#L1381-1 assume !(0 == ~E_5~0); 42143#L1386-1 assume !(0 == ~E_6~0); 42819#L1391-1 assume !(0 == ~E_7~0); 42839#L1396-1 assume !(0 == ~E_8~0); 42044#L1401-1 assume !(0 == ~E_9~0); 42045#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 42332#L1411-1 assume !(0 == ~E_11~0); 42333#L1416-1 assume !(0 == ~E_12~0); 41962#L1421-1 assume !(0 == ~E_13~0); 41481#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 41482#L640 assume !(1 == ~m_pc~0); 42011#L640-2 is_master_triggered_~__retres1~0#1 := 0; 42010#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41970#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 41971#L1603 assume !(0 != activate_threads_~tmp~1#1); 41999#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 41631#L659 assume 1 == ~t1_pc~0; 41632#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 41740#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 42453#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 41762#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 41763#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 41779#L678 assume 1 == ~t2_pc~0; 42725#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 42726#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 41324#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 41325#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 41873#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 41992#L697 assume !(1 == ~t3_pc~0); 41993#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 42123#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 42443#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 41906#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 41907#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 42758#L716 assume 1 == ~t4_pc~0; 42746#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 41611#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 40977#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 40978#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 41085#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 42407#L735 assume !(1 == ~t5_pc~0); 41052#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 41053#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 41508#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 42433#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 42070#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 42071#L754 assume 1 == ~t6_pc~0; 41824#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 41724#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 41301#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 41302#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 41698#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 42507#L773 assume !(1 == ~t7_pc~0); 41238#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 41237#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 42105#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 42080#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 42081#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 42134#L792 assume 1 == ~t8_pc~0; 42302#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 42623#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 42624#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 42072#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 41995#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 41996#L811 assume 1 == ~t9_pc~0; 42205#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 42670#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 41380#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 41381#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 42007#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 42008#L830 assume !(1 == ~t10_pc~0); 41733#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 41214#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 41215#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 41192#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 41193#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 42525#L849 assume 1 == ~t11_pc~0; 42526#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 41031#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 41032#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 42536#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 42437#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 42438#L868 assume !(1 == ~t12_pc~0); 41857#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 41856#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 40919#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 40920#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 41249#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 41250#L887 assume 1 == ~t13_pc~0; 42445#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 41900#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 41901#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 42501#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 40959#L1707-2 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40960#L1439 assume !(1 == ~M_E~0); 42064#L1439-2 assume !(1 == ~T1_E~0); 41130#L1444-1 assume !(1 == ~T2_E~0); 41131#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 41636#L1454-1 assume !(1 == ~T4_E~0); 41637#L1459-1 assume !(1 == ~T5_E~0); 42197#L1464-1 assume !(1 == ~T6_E~0); 42198#L1469-1 assume !(1 == ~T7_E~0); 42271#L1474-1 assume !(1 == ~T8_E~0); 41963#L1479-1 assume !(1 == ~T9_E~0); 41964#L1484-1 assume !(1 == ~T10_E~0); 42201#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 41846#L1494-1 assume !(1 == ~T12_E~0); 41847#L1499-1 assume !(1 == ~T13_E~0); 42029#L1504-1 assume !(1 == ~E_M~0); 42030#L1509-1 assume !(1 == ~E_1~0); 42608#L1514-1 assume !(1 == ~E_2~0); 42304#L1519-1 assume !(1 == ~E_3~0); 42305#L1524-1 assume !(1 == ~E_4~0); 42803#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 42804#L1534-1 assume !(1 == ~E_6~0); 40953#L1539-1 assume !(1 == ~E_7~0); 40954#L1544-1 assume !(1 == ~E_8~0); 41377#L1549-1 assume !(1 == ~E_9~0); 42776#L1554-1 assume !(1 == ~E_10~0); 42773#L1559-1 assume !(1 == ~E_11~0); 42648#L1564-1 assume !(1 == ~E_12~0); 42649#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 42798#L1574-1 assume { :end_inline_reset_delta_events } true; 41128#L1940-2 [2024-11-08 00:35:54,815 INFO L747 eck$LassoCheckResult]: Loop: 41128#L1940-2 assume !false; 41129#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 41672#L1266-1 assume !false; 42842#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 41693#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 41407#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 42607#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 42616#L1079 assume !(0 != eval_~tmp~0#1); 41890#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 41545#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 41546#L1291-3 assume 0 == ~M_E~0;~M_E~0 := 1; 42272#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 42273#L1296-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 42829#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 42784#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 41930#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 41166#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 41167#L1321-3 assume !(0 == ~T7_E~0); 41271#L1326-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 42059#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 42310#L1336-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 42311#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 41628#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 41605#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 41543#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 41544#L1361-3 assume !(0 == ~E_1~0); 42124#L1366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 40882#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 40883#L1376-3 assume 0 == ~E_4~0;~E_4~0 := 1; 42628#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 42487#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 42488#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 42662#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 42663#L1401-3 assume !(0 == ~E_9~0); 41229#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 41093#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 41094#L1416-3 assume 0 == ~E_12~0;~E_12~0 := 1; 41787#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 41788#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 41895#L640-45 assume !(1 == ~m_pc~0); 41896#L640-47 is_master_triggered_~__retres1~0#1 := 0; 41337#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41338#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 40878#L1603-45 assume !(0 != activate_threads_~tmp~1#1); 40879#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 40967#L659-45 assume 1 == ~t1_pc~0; 40968#L660-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 41421#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 42833#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 42763#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 42416#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 42417#L678-45 assume 1 == ~t2_pc~0; 42368#L679-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 41902#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 41903#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 42350#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 42679#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 42782#L697-45 assume 1 == ~t3_pc~0; 42163#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 42164#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 42849#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 42316#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 42317#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 42351#L716-45 assume 1 == ~t4_pc~0; 41975#L717-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 41977#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 42634#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 41982#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 41983#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 41646#L735-45 assume !(1 == ~t5_pc~0); 41648#L735-47 is_transmit5_triggered_~__retres1~5#1 := 0; 42195#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 42800#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 42846#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 42802#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 42796#L754-45 assume 1 == ~t6_pc~0; 42146#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 42147#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 42040#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 42041#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 42151#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 41878#L773-45 assume 1 == ~t7_pc~0; 41879#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 41418#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 42112#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 42113#L1659-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 41886#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 41537#L792-45 assume 1 == ~t8_pc~0; 41538#L793-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 42566#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 42567#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 40988#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 40989#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 41487#L811-45 assume 1 == ~t9_pc~0; 41264#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 41265#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 42484#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 42347#L1675-45 assume !(0 != activate_threads_~tmp___8~0#1); 41954#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 41745#L830-45 assume 1 == ~t10_pc~0; 41746#L831-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 40915#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 42063#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 41139#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 41140#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 40898#L849-45 assume !(1 == ~t11_pc~0); 40899#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 41355#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 41196#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 40884#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 40885#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 41134#L868-45 assume !(1 == ~t12_pc~0); 41136#L868-47 is_transmit12_triggered_~__retres1~12#1 := 0; 41078#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 41079#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 42519#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 42692#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 42693#L887-45 assume !(1 == ~t13_pc~0); 41141#L887-47 is_transmit13_triggered_~__retres1~13#1 := 0; 41142#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 42447#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 42466#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 41108#L1707-47 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41109#L1439-3 assume 1 == ~M_E~0;~M_E~0 := 2; 42442#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 41126#L1444-3 assume !(1 == ~T2_E~0); 41127#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 41285#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 42253#L1459-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 42254#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 42694#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 42631#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 42632#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 42696#L1484-3 assume !(1 == ~T10_E~0); 41936#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 41937#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 42559#L1499-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 42212#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 42213#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 42644#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 42680#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 41853#L1524-3 assume !(1 == ~E_4~0); 41854#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 42718#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 42131#L1539-3 assume 1 == ~E_7~0;~E_7~0 := 2; 41588#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 41589#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 42094#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 41173#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 41174#L1564-3 assume !(1 == ~E_12~0); 42352#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 42353#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 41065#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 40839#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 41165#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 41072#L1959 assume !(0 == start_simulation_~tmp~3#1); 41074#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 41104#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 41058#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 40893#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 40894#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 42712#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 42687#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 42688#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 41128#L1940-2 [2024-11-08 00:35:54,816 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:54,816 INFO L85 PathProgramCache]: Analyzing trace with hash 584687431, now seen corresponding path program 1 times [2024-11-08 00:35:54,816 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:54,816 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2063413369] [2024-11-08 00:35:54,816 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:54,816 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:54,831 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:54,859 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:54,859 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:54,859 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2063413369] [2024-11-08 00:35:54,859 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2063413369] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:54,859 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:54,859 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:54,859 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1362410131] [2024-11-08 00:35:54,860 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:54,860 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:35:54,860 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:54,860 INFO L85 PathProgramCache]: Analyzing trace with hash -692691971, now seen corresponding path program 1 times [2024-11-08 00:35:54,860 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:54,860 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1897016208] [2024-11-08 00:35:54,861 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:54,861 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:54,873 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:54,906 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:54,907 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:54,907 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1897016208] [2024-11-08 00:35:54,907 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1897016208] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:54,907 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:54,907 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:54,908 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1142951516] [2024-11-08 00:35:54,908 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:54,908 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:35:54,908 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:35:54,908 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:35:54,909 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:35:54,909 INFO L87 Difference]: Start difference. First operand 2037 states and 3001 transitions. cyclomatic complexity: 965 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:54,932 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:35:54,932 INFO L93 Difference]: Finished difference Result 2037 states and 3000 transitions. [2024-11-08 00:35:54,932 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2037 states and 3000 transitions. [2024-11-08 00:35:54,938 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2024-11-08 00:35:54,943 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2037 states to 2037 states and 3000 transitions. [2024-11-08 00:35:54,943 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2037 [2024-11-08 00:35:54,944 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2037 [2024-11-08 00:35:54,944 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2037 states and 3000 transitions. [2024-11-08 00:35:54,947 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:35:54,947 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2037 states and 3000 transitions. [2024-11-08 00:35:54,949 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2037 states and 3000 transitions. [2024-11-08 00:35:54,966 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2037 to 2037. [2024-11-08 00:35:54,968 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2037 states, 2037 states have (on average 1.4727540500736378) internal successors, (3000), 2036 states have internal predecessors, (3000), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:54,972 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2037 states to 2037 states and 3000 transitions. [2024-11-08 00:35:54,972 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2037 states and 3000 transitions. [2024-11-08 00:35:54,972 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:35:54,973 INFO L425 stractBuchiCegarLoop]: Abstraction has 2037 states and 3000 transitions. [2024-11-08 00:35:54,973 INFO L332 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-11-08 00:35:54,973 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2037 states and 3000 transitions. [2024-11-08 00:35:54,978 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2024-11-08 00:35:54,978 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:35:54,978 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:35:54,983 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:54,983 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:54,983 INFO L745 eck$LassoCheckResult]: Stem: 45201#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 45202#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 46195#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 46196#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 46931#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 46323#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 45792#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 45793#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 46597#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 46598#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 46702#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 46703#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 45541#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 45542#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 46737#L959-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 46093#L964-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 46094#L969-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 46643#L974-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 46007#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 46008#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 46932#L1291-2 assume !(0 == ~T1_E~0); 46929#L1296-1 assume !(0 == ~T2_E~0); 46157#L1301-1 assume !(0 == ~T3_E~0); 46158#L1306-1 assume !(0 == ~T4_E~0); 46653#L1311-1 assume !(0 == ~T5_E~0); 45378#L1316-1 assume !(0 == ~T6_E~0); 45379#L1321-1 assume !(0 == ~T7_E~0); 46171#L1326-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 45198#L1331-1 assume !(0 == ~T9_E~0); 44911#L1336-1 assume !(0 == ~T10_E~0); 44912#L1341-1 assume !(0 == ~T11_E~0); 44985#L1346-1 assume !(0 == ~T12_E~0); 44986#L1351-1 assume !(0 == ~T13_E~0); 45315#L1356-1 assume !(0 == ~E_M~0); 45316#L1361-1 assume !(0 == ~E_1~0); 46869#L1366-1 assume 0 == ~E_2~0;~E_2~0 := 1; 45362#L1371-1 assume !(0 == ~E_3~0); 45363#L1376-1 assume !(0 == ~E_4~0); 46223#L1381-1 assume !(0 == ~E_5~0); 46224#L1386-1 assume !(0 == ~E_6~0); 46900#L1391-1 assume !(0 == ~E_7~0); 46920#L1396-1 assume !(0 == ~E_8~0); 46125#L1401-1 assume !(0 == ~E_9~0); 46126#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 46413#L1411-1 assume !(0 == ~E_11~0); 46414#L1416-1 assume !(0 == ~E_12~0); 46043#L1421-1 assume !(0 == ~E_13~0); 45562#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 45563#L640 assume !(1 == ~m_pc~0); 46092#L640-2 is_master_triggered_~__retres1~0#1 := 0; 46091#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 46051#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 46052#L1603 assume !(0 != activate_threads_~tmp~1#1); 46080#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 45712#L659 assume 1 == ~t1_pc~0; 45713#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 45821#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 46534#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 45843#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 45844#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 45860#L678 assume 1 == ~t2_pc~0; 46806#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 46807#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 45405#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 45406#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 45954#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 46073#L697 assume !(1 == ~t3_pc~0); 46074#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 46204#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46524#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 45987#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 45988#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 46839#L716 assume 1 == ~t4_pc~0; 46827#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 45692#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 45058#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 45059#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 45166#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 46488#L735 assume !(1 == ~t5_pc~0); 45133#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 45134#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 45589#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 46514#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 46151#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 46152#L754 assume 1 == ~t6_pc~0; 45905#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 45805#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 45382#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 45383#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 45779#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 46588#L773 assume !(1 == ~t7_pc~0); 45319#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 45318#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 46186#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 46161#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 46162#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 46215#L792 assume 1 == ~t8_pc~0; 46383#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 46704#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 46705#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 46153#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 46076#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 46077#L811 assume 1 == ~t9_pc~0; 46286#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 46751#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 45461#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 45462#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 46088#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 46089#L830 assume !(1 == ~t10_pc~0); 45814#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 45295#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 45296#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 45273#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 45274#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 46606#L849 assume 1 == ~t11_pc~0; 46607#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 45112#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 45113#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 46617#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 46518#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 46519#L868 assume !(1 == ~t12_pc~0); 45938#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 45937#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 45000#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 45001#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 45330#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 45331#L887 assume 1 == ~t13_pc~0; 46526#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 45981#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 45982#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 46582#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 45040#L1707-2 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 45041#L1439 assume !(1 == ~M_E~0); 46145#L1439-2 assume !(1 == ~T1_E~0); 45211#L1444-1 assume !(1 == ~T2_E~0); 45212#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 45717#L1454-1 assume !(1 == ~T4_E~0); 45718#L1459-1 assume !(1 == ~T5_E~0); 46278#L1464-1 assume !(1 == ~T6_E~0); 46279#L1469-1 assume !(1 == ~T7_E~0); 46352#L1474-1 assume !(1 == ~T8_E~0); 46044#L1479-1 assume !(1 == ~T9_E~0); 46045#L1484-1 assume !(1 == ~T10_E~0); 46282#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 45927#L1494-1 assume !(1 == ~T12_E~0); 45928#L1499-1 assume !(1 == ~T13_E~0); 46110#L1504-1 assume !(1 == ~E_M~0); 46111#L1509-1 assume !(1 == ~E_1~0); 46689#L1514-1 assume !(1 == ~E_2~0); 46385#L1519-1 assume !(1 == ~E_3~0); 46386#L1524-1 assume !(1 == ~E_4~0); 46884#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 46885#L1534-1 assume !(1 == ~E_6~0); 45034#L1539-1 assume !(1 == ~E_7~0); 45035#L1544-1 assume !(1 == ~E_8~0); 45458#L1549-1 assume !(1 == ~E_9~0); 46857#L1554-1 assume !(1 == ~E_10~0); 46854#L1559-1 assume !(1 == ~E_11~0); 46729#L1564-1 assume !(1 == ~E_12~0); 46730#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 46879#L1574-1 assume { :end_inline_reset_delta_events } true; 45209#L1940-2 [2024-11-08 00:35:54,984 INFO L747 eck$LassoCheckResult]: Loop: 45209#L1940-2 assume !false; 45210#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 45753#L1266-1 assume !false; 46923#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 45774#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 45488#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 46688#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 46697#L1079 assume !(0 != eval_~tmp~0#1); 45971#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 45626#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 45627#L1291-3 assume 0 == ~M_E~0;~M_E~0 := 1; 46353#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 46354#L1296-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 46910#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 46865#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 46011#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 45247#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 45248#L1321-3 assume !(0 == ~T7_E~0); 45352#L1326-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 46140#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 46391#L1336-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 46392#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 45709#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 45686#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 45624#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 45625#L1361-3 assume !(0 == ~E_1~0); 46205#L1366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 44963#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 44964#L1376-3 assume 0 == ~E_4~0;~E_4~0 := 1; 46709#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 46568#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 46569#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 46743#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 46744#L1401-3 assume !(0 == ~E_9~0); 45310#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 45174#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 45175#L1416-3 assume 0 == ~E_12~0;~E_12~0 := 1; 45868#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 45869#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 45976#L640-45 assume !(1 == ~m_pc~0); 45977#L640-47 is_master_triggered_~__retres1~0#1 := 0; 45418#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 45419#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 44959#L1603-45 assume !(0 != activate_threads_~tmp~1#1); 44960#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 45048#L659-45 assume 1 == ~t1_pc~0; 45049#L660-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 45502#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 46914#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 46844#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 46497#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 46498#L678-45 assume 1 == ~t2_pc~0; 46449#L679-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 45983#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 45984#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 46431#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 46760#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 46863#L697-45 assume 1 == ~t3_pc~0; 46244#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 46245#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46930#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 46397#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 46398#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 46432#L716-45 assume 1 == ~t4_pc~0; 46056#L717-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 46058#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 46715#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 46063#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 46064#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 45727#L735-45 assume 1 == ~t5_pc~0; 45728#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 46276#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 46881#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 46927#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 46883#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 46877#L754-45 assume 1 == ~t6_pc~0; 46227#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 46228#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 46121#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 46122#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 46232#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 45959#L773-45 assume 1 == ~t7_pc~0; 45960#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 45499#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 46193#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 46194#L1659-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 45967#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 45618#L792-45 assume 1 == ~t8_pc~0; 45619#L793-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 46647#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 46648#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 45069#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 45070#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 45568#L811-45 assume 1 == ~t9_pc~0; 45345#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 45346#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 46565#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 46428#L1675-45 assume !(0 != activate_threads_~tmp___8~0#1); 46035#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 45826#L830-45 assume 1 == ~t10_pc~0; 45827#L831-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 44996#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 46144#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 45220#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 45221#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 44979#L849-45 assume !(1 == ~t11_pc~0); 44980#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 45436#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 45277#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 44965#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 44966#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 45215#L868-45 assume 1 == ~t12_pc~0; 45216#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 45159#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 45160#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 46600#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 46773#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 46774#L887-45 assume !(1 == ~t13_pc~0); 45222#L887-47 is_transmit13_triggered_~__retres1~13#1 := 0; 45223#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 46528#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 46547#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 45189#L1707-47 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 45190#L1439-3 assume 1 == ~M_E~0;~M_E~0 := 2; 46523#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 45207#L1444-3 assume !(1 == ~T2_E~0); 45208#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 45366#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 46334#L1459-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 46335#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 46775#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 46712#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 46713#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 46777#L1484-3 assume !(1 == ~T10_E~0); 46017#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 46018#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 46640#L1499-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 46293#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 46294#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 46725#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 46761#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 45934#L1524-3 assume !(1 == ~E_4~0); 45935#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 46799#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 46212#L1539-3 assume 1 == ~E_7~0;~E_7~0 := 2; 45669#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 45670#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 46175#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 45254#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 45255#L1564-3 assume !(1 == ~E_12~0); 46433#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 46434#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 45146#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 44920#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 45246#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 45153#L1959 assume !(0 == start_simulation_~tmp~3#1); 45155#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 45185#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 45139#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 44974#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 44975#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 46793#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 46768#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 46769#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 45209#L1940-2 [2024-11-08 00:35:54,984 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:54,984 INFO L85 PathProgramCache]: Analyzing trace with hash 1907866377, now seen corresponding path program 1 times [2024-11-08 00:35:54,984 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:54,984 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1607095053] [2024-11-08 00:35:54,984 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:54,984 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:54,995 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:55,055 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:55,055 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:55,055 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1607095053] [2024-11-08 00:35:55,055 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1607095053] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:55,055 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:55,055 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:55,055 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2032462929] [2024-11-08 00:35:55,055 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:55,055 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:35:55,056 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:55,056 INFO L85 PathProgramCache]: Analyzing trace with hash -291836997, now seen corresponding path program 1 times [2024-11-08 00:35:55,056 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:55,056 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [895708562] [2024-11-08 00:35:55,056 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:55,056 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:55,068 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:55,102 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:55,103 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:55,103 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [895708562] [2024-11-08 00:35:55,103 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [895708562] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:55,103 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:55,103 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:55,103 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1241346037] [2024-11-08 00:35:55,103 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:55,103 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:35:55,103 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:35:55,103 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:35:55,103 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:35:55,104 INFO L87 Difference]: Start difference. First operand 2037 states and 3000 transitions. cyclomatic complexity: 964 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:55,128 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:35:55,129 INFO L93 Difference]: Finished difference Result 2037 states and 2999 transitions. [2024-11-08 00:35:55,129 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2037 states and 2999 transitions. [2024-11-08 00:35:55,135 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2024-11-08 00:35:55,140 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2037 states to 2037 states and 2999 transitions. [2024-11-08 00:35:55,140 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2037 [2024-11-08 00:35:55,141 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2037 [2024-11-08 00:35:55,141 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2037 states and 2999 transitions. [2024-11-08 00:35:55,143 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:35:55,143 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2037 states and 2999 transitions. [2024-11-08 00:35:55,145 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2037 states and 2999 transitions. [2024-11-08 00:35:55,162 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2037 to 2037. [2024-11-08 00:35:55,164 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2037 states, 2037 states have (on average 1.4722631320569466) internal successors, (2999), 2036 states have internal predecessors, (2999), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:55,168 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2037 states to 2037 states and 2999 transitions. [2024-11-08 00:35:55,168 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2037 states and 2999 transitions. [2024-11-08 00:35:55,168 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:35:55,170 INFO L425 stractBuchiCegarLoop]: Abstraction has 2037 states and 2999 transitions. [2024-11-08 00:35:55,170 INFO L332 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-11-08 00:35:55,170 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2037 states and 2999 transitions. [2024-11-08 00:35:55,175 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2024-11-08 00:35:55,176 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:35:55,176 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:35:55,179 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:55,181 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:55,181 INFO L745 eck$LassoCheckResult]: Stem: 49282#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 49283#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 50276#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 50277#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 51012#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 50404#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 49873#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 49874#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 50678#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 50679#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 50783#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 50784#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 49622#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 49623#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 50818#L959-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 50174#L964-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 50175#L969-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 50724#L974-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 50088#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 50089#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 51013#L1291-2 assume !(0 == ~T1_E~0); 51010#L1296-1 assume !(0 == ~T2_E~0); 50238#L1301-1 assume !(0 == ~T3_E~0); 50239#L1306-1 assume !(0 == ~T4_E~0); 50734#L1311-1 assume !(0 == ~T5_E~0); 49459#L1316-1 assume !(0 == ~T6_E~0); 49460#L1321-1 assume !(0 == ~T7_E~0); 50252#L1326-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 49279#L1331-1 assume !(0 == ~T9_E~0); 48992#L1336-1 assume !(0 == ~T10_E~0); 48993#L1341-1 assume !(0 == ~T11_E~0); 49066#L1346-1 assume !(0 == ~T12_E~0); 49067#L1351-1 assume !(0 == ~T13_E~0); 49396#L1356-1 assume !(0 == ~E_M~0); 49397#L1361-1 assume !(0 == ~E_1~0); 50950#L1366-1 assume 0 == ~E_2~0;~E_2~0 := 1; 49443#L1371-1 assume !(0 == ~E_3~0); 49444#L1376-1 assume !(0 == ~E_4~0); 50304#L1381-1 assume !(0 == ~E_5~0); 50305#L1386-1 assume !(0 == ~E_6~0); 50981#L1391-1 assume !(0 == ~E_7~0); 51001#L1396-1 assume !(0 == ~E_8~0); 50206#L1401-1 assume !(0 == ~E_9~0); 50207#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 50494#L1411-1 assume !(0 == ~E_11~0); 50495#L1416-1 assume !(0 == ~E_12~0); 50124#L1421-1 assume !(0 == ~E_13~0); 49643#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 49644#L640 assume !(1 == ~m_pc~0); 50173#L640-2 is_master_triggered_~__retres1~0#1 := 0; 50172#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 50132#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 50133#L1603 assume !(0 != activate_threads_~tmp~1#1); 50161#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 49793#L659 assume 1 == ~t1_pc~0; 49794#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 49902#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 50615#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 49924#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 49925#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 49941#L678 assume 1 == ~t2_pc~0; 50887#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 50888#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 49486#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 49487#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 50035#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 50154#L697 assume !(1 == ~t3_pc~0); 50155#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 50285#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 50605#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 50068#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 50069#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 50920#L716 assume 1 == ~t4_pc~0; 50908#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 49773#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 49139#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 49140#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 49247#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 50569#L735 assume !(1 == ~t5_pc~0); 49214#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 49215#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 49670#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 50595#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 50232#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 50233#L754 assume 1 == ~t6_pc~0; 49986#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 49886#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 49463#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 49464#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 49860#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 50669#L773 assume !(1 == ~t7_pc~0); 49400#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 49399#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 50267#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 50242#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 50243#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 50296#L792 assume 1 == ~t8_pc~0; 50464#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 50785#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 50786#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 50234#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 50157#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 50158#L811 assume 1 == ~t9_pc~0; 50367#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 50832#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 49542#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 49543#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 50169#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 50170#L830 assume !(1 == ~t10_pc~0); 49895#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 49376#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 49377#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 49354#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 49355#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 50687#L849 assume 1 == ~t11_pc~0; 50688#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 49193#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 49194#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 50698#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 50599#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 50600#L868 assume !(1 == ~t12_pc~0); 50019#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 50018#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 49081#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 49082#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 49411#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 49412#L887 assume 1 == ~t13_pc~0; 50607#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 50062#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 50063#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 50663#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 49121#L1707-2 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 49122#L1439 assume !(1 == ~M_E~0); 50226#L1439-2 assume !(1 == ~T1_E~0); 49292#L1444-1 assume !(1 == ~T2_E~0); 49293#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 49798#L1454-1 assume !(1 == ~T4_E~0); 49799#L1459-1 assume !(1 == ~T5_E~0); 50359#L1464-1 assume !(1 == ~T6_E~0); 50360#L1469-1 assume !(1 == ~T7_E~0); 50433#L1474-1 assume !(1 == ~T8_E~0); 50125#L1479-1 assume !(1 == ~T9_E~0); 50126#L1484-1 assume !(1 == ~T10_E~0); 50363#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 50008#L1494-1 assume !(1 == ~T12_E~0); 50009#L1499-1 assume !(1 == ~T13_E~0); 50191#L1504-1 assume !(1 == ~E_M~0); 50192#L1509-1 assume !(1 == ~E_1~0); 50770#L1514-1 assume !(1 == ~E_2~0); 50466#L1519-1 assume !(1 == ~E_3~0); 50467#L1524-1 assume !(1 == ~E_4~0); 50965#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 50966#L1534-1 assume !(1 == ~E_6~0); 49115#L1539-1 assume !(1 == ~E_7~0); 49116#L1544-1 assume !(1 == ~E_8~0); 49539#L1549-1 assume !(1 == ~E_9~0); 50938#L1554-1 assume !(1 == ~E_10~0); 50935#L1559-1 assume !(1 == ~E_11~0); 50810#L1564-1 assume !(1 == ~E_12~0); 50811#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 50960#L1574-1 assume { :end_inline_reset_delta_events } true; 49290#L1940-2 [2024-11-08 00:35:55,182 INFO L747 eck$LassoCheckResult]: Loop: 49290#L1940-2 assume !false; 49291#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 49834#L1266-1 assume !false; 51004#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 49855#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 49569#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 50769#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 50778#L1079 assume !(0 != eval_~tmp~0#1); 50052#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 49707#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 49708#L1291-3 assume 0 == ~M_E~0;~M_E~0 := 1; 50434#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 50435#L1296-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 50991#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 50946#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 50092#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 49328#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 49329#L1321-3 assume !(0 == ~T7_E~0); 49433#L1326-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 50221#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 50472#L1336-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 50473#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 49790#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 49767#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 49705#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 49706#L1361-3 assume !(0 == ~E_1~0); 50286#L1366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 49044#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 49045#L1376-3 assume 0 == ~E_4~0;~E_4~0 := 1; 50790#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 50649#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 50650#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 50824#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 50825#L1401-3 assume !(0 == ~E_9~0); 49391#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 49255#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 49256#L1416-3 assume 0 == ~E_12~0;~E_12~0 := 1; 49949#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 49950#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 50057#L640-45 assume !(1 == ~m_pc~0); 50058#L640-47 is_master_triggered_~__retres1~0#1 := 0; 49499#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 49500#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 49040#L1603-45 assume !(0 != activate_threads_~tmp~1#1); 49041#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 49129#L659-45 assume 1 == ~t1_pc~0; 49130#L660-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 49583#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 50995#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 50925#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 50578#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 50579#L678-45 assume 1 == ~t2_pc~0; 50530#L679-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 50064#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 50065#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 50512#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 50841#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 50944#L697-45 assume 1 == ~t3_pc~0; 50325#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 50326#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 51011#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 50478#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 50479#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 50513#L716-45 assume 1 == ~t4_pc~0; 50137#L717-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 50139#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 50796#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 50144#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 50145#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 49808#L735-45 assume 1 == ~t5_pc~0; 49809#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 50357#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 50962#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 51008#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 50964#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 50958#L754-45 assume 1 == ~t6_pc~0; 50308#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 50309#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 50202#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 50203#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 50313#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 50040#L773-45 assume 1 == ~t7_pc~0; 50041#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 49580#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 50274#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 50275#L1659-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 50048#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 49699#L792-45 assume 1 == ~t8_pc~0; 49700#L793-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 50728#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 50729#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 49150#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 49151#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 49649#L811-45 assume 1 == ~t9_pc~0; 49426#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 49427#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 50646#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 50509#L1675-45 assume !(0 != activate_threads_~tmp___8~0#1); 50116#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 49907#L830-45 assume 1 == ~t10_pc~0; 49908#L831-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 49077#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 50225#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 49301#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 49302#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 49060#L849-45 assume !(1 == ~t11_pc~0); 49061#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 49517#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 49358#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 49046#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 49047#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 49296#L868-45 assume 1 == ~t12_pc~0; 49297#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 49240#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 49241#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 50681#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 50854#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 50855#L887-45 assume !(1 == ~t13_pc~0); 49303#L887-47 is_transmit13_triggered_~__retres1~13#1 := 0; 49304#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 50609#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 50628#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 49270#L1707-47 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 49271#L1439-3 assume 1 == ~M_E~0;~M_E~0 := 2; 50604#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 49288#L1444-3 assume !(1 == ~T2_E~0); 49289#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 49447#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 50415#L1459-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 50416#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 50856#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 50793#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 50794#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 50858#L1484-3 assume !(1 == ~T10_E~0); 50098#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 50099#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 50721#L1499-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 50374#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 50375#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 50806#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 50842#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 50015#L1524-3 assume !(1 == ~E_4~0); 50016#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 50880#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 50293#L1539-3 assume 1 == ~E_7~0;~E_7~0 := 2; 49750#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 49751#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 50256#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 49335#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 49336#L1564-3 assume !(1 == ~E_12~0); 50514#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 50515#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 49227#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 49001#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 49327#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 49234#L1959 assume !(0 == start_simulation_~tmp~3#1); 49236#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 49266#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 49220#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 49055#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 49056#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 50874#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 50849#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 50850#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 49290#L1940-2 [2024-11-08 00:35:55,182 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:55,182 INFO L85 PathProgramCache]: Analyzing trace with hash 10886919, now seen corresponding path program 1 times [2024-11-08 00:35:55,182 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:55,182 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1989049057] [2024-11-08 00:35:55,182 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:55,182 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:55,193 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:55,214 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:55,215 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:55,215 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1989049057] [2024-11-08 00:35:55,215 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1989049057] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:55,215 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:55,215 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:55,215 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1669452302] [2024-11-08 00:35:55,215 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:55,216 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:35:55,216 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:55,216 INFO L85 PathProgramCache]: Analyzing trace with hash -291836997, now seen corresponding path program 2 times [2024-11-08 00:35:55,216 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:55,216 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [907103119] [2024-11-08 00:35:55,216 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:55,216 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:55,228 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:55,260 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:55,260 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:55,260 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [907103119] [2024-11-08 00:35:55,260 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [907103119] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:55,260 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:55,260 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:55,261 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [973508150] [2024-11-08 00:35:55,261 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:55,261 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:35:55,261 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:35:55,261 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:35:55,261 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:35:55,261 INFO L87 Difference]: Start difference. First operand 2037 states and 2999 transitions. cyclomatic complexity: 963 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:55,289 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:35:55,289 INFO L93 Difference]: Finished difference Result 2037 states and 2998 transitions. [2024-11-08 00:35:55,289 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2037 states and 2998 transitions. [2024-11-08 00:35:55,295 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2024-11-08 00:35:55,300 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2037 states to 2037 states and 2998 transitions. [2024-11-08 00:35:55,300 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2037 [2024-11-08 00:35:55,301 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2037 [2024-11-08 00:35:55,301 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2037 states and 2998 transitions. [2024-11-08 00:35:55,304 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:35:55,304 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2037 states and 2998 transitions. [2024-11-08 00:35:55,306 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2037 states and 2998 transitions. [2024-11-08 00:35:55,322 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2037 to 2037. [2024-11-08 00:35:55,324 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2037 states, 2037 states have (on average 1.4717722140402554) internal successors, (2998), 2036 states have internal predecessors, (2998), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:55,328 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2037 states to 2037 states and 2998 transitions. [2024-11-08 00:35:55,328 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2037 states and 2998 transitions. [2024-11-08 00:35:55,329 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:35:55,329 INFO L425 stractBuchiCegarLoop]: Abstraction has 2037 states and 2998 transitions. [2024-11-08 00:35:55,329 INFO L332 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2024-11-08 00:35:55,329 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2037 states and 2998 transitions. [2024-11-08 00:35:55,334 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1862 [2024-11-08 00:35:55,334 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:35:55,334 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:35:55,336 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:55,336 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:55,336 INFO L745 eck$LassoCheckResult]: Stem: 53363#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 53364#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 54357#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 54358#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 55093#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 54485#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 53954#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 53955#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 54759#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 54760#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 54864#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 54865#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 53703#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 53704#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 54899#L959-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 54255#L964-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 54256#L969-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 54805#L974-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 54169#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 54170#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 55094#L1291-2 assume !(0 == ~T1_E~0); 55091#L1296-1 assume !(0 == ~T2_E~0); 54319#L1301-1 assume !(0 == ~T3_E~0); 54320#L1306-1 assume !(0 == ~T4_E~0); 54815#L1311-1 assume !(0 == ~T5_E~0); 53540#L1316-1 assume !(0 == ~T6_E~0); 53541#L1321-1 assume !(0 == ~T7_E~0); 54333#L1326-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 53360#L1331-1 assume !(0 == ~T9_E~0); 53073#L1336-1 assume !(0 == ~T10_E~0); 53074#L1341-1 assume !(0 == ~T11_E~0); 53147#L1346-1 assume !(0 == ~T12_E~0); 53148#L1351-1 assume !(0 == ~T13_E~0); 53477#L1356-1 assume !(0 == ~E_M~0); 53478#L1361-1 assume !(0 == ~E_1~0); 55031#L1366-1 assume 0 == ~E_2~0;~E_2~0 := 1; 53524#L1371-1 assume !(0 == ~E_3~0); 53525#L1376-1 assume !(0 == ~E_4~0); 54385#L1381-1 assume !(0 == ~E_5~0); 54386#L1386-1 assume !(0 == ~E_6~0); 55062#L1391-1 assume !(0 == ~E_7~0); 55082#L1396-1 assume !(0 == ~E_8~0); 54287#L1401-1 assume !(0 == ~E_9~0); 54288#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 54575#L1411-1 assume !(0 == ~E_11~0); 54576#L1416-1 assume !(0 == ~E_12~0); 54205#L1421-1 assume !(0 == ~E_13~0); 53724#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 53725#L640 assume !(1 == ~m_pc~0); 54254#L640-2 is_master_triggered_~__retres1~0#1 := 0; 54253#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 54213#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 54214#L1603 assume !(0 != activate_threads_~tmp~1#1); 54242#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 53874#L659 assume 1 == ~t1_pc~0; 53875#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 53983#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 54696#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 54005#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 54006#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 54022#L678 assume 1 == ~t2_pc~0; 54968#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 54969#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 53567#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 53568#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 54116#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 54235#L697 assume !(1 == ~t3_pc~0); 54236#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 54366#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 54686#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 54149#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 54150#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 55001#L716 assume 1 == ~t4_pc~0; 54989#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 53854#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 53220#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 53221#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 53328#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 54650#L735 assume !(1 == ~t5_pc~0); 53295#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 53296#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 53751#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 54676#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 54313#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 54314#L754 assume 1 == ~t6_pc~0; 54067#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 53967#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 53544#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 53545#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 53941#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 54750#L773 assume !(1 == ~t7_pc~0); 53481#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 53480#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 54348#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 54323#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 54324#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 54377#L792 assume 1 == ~t8_pc~0; 54545#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 54866#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 54867#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 54315#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 54238#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 54239#L811 assume 1 == ~t9_pc~0; 54448#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 54913#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 53623#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 53624#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 54250#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 54251#L830 assume !(1 == ~t10_pc~0); 53976#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 53457#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 53458#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 53435#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 53436#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 54768#L849 assume 1 == ~t11_pc~0; 54769#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 53274#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 53275#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 54779#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 54680#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 54681#L868 assume !(1 == ~t12_pc~0); 54100#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 54099#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 53162#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 53163#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 53492#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 53493#L887 assume 1 == ~t13_pc~0; 54688#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 54143#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 54144#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 54744#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 53202#L1707-2 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 53203#L1439 assume !(1 == ~M_E~0); 54307#L1439-2 assume !(1 == ~T1_E~0); 53373#L1444-1 assume !(1 == ~T2_E~0); 53374#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 53879#L1454-1 assume !(1 == ~T4_E~0); 53880#L1459-1 assume !(1 == ~T5_E~0); 54440#L1464-1 assume !(1 == ~T6_E~0); 54441#L1469-1 assume !(1 == ~T7_E~0); 54514#L1474-1 assume !(1 == ~T8_E~0); 54206#L1479-1 assume !(1 == ~T9_E~0); 54207#L1484-1 assume !(1 == ~T10_E~0); 54444#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 54089#L1494-1 assume !(1 == ~T12_E~0); 54090#L1499-1 assume !(1 == ~T13_E~0); 54272#L1504-1 assume !(1 == ~E_M~0); 54273#L1509-1 assume !(1 == ~E_1~0); 54851#L1514-1 assume !(1 == ~E_2~0); 54547#L1519-1 assume !(1 == ~E_3~0); 54548#L1524-1 assume !(1 == ~E_4~0); 55046#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 55047#L1534-1 assume !(1 == ~E_6~0); 53196#L1539-1 assume !(1 == ~E_7~0); 53197#L1544-1 assume !(1 == ~E_8~0); 53620#L1549-1 assume !(1 == ~E_9~0); 55019#L1554-1 assume !(1 == ~E_10~0); 55016#L1559-1 assume !(1 == ~E_11~0); 54891#L1564-1 assume !(1 == ~E_12~0); 54892#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 55041#L1574-1 assume { :end_inline_reset_delta_events } true; 53371#L1940-2 [2024-11-08 00:35:55,337 INFO L747 eck$LassoCheckResult]: Loop: 53371#L1940-2 assume !false; 53372#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 53915#L1266-1 assume !false; 55085#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 53936#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 53650#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 54850#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 54859#L1079 assume !(0 != eval_~tmp~0#1); 54133#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 53788#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 53789#L1291-3 assume 0 == ~M_E~0;~M_E~0 := 1; 54515#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 54516#L1296-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 55072#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 55027#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 54173#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 53409#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 53410#L1321-3 assume !(0 == ~T7_E~0); 53514#L1326-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 54302#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 54553#L1336-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 54554#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 53871#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 53848#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 53786#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 53787#L1361-3 assume !(0 == ~E_1~0); 54367#L1366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 53125#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 53126#L1376-3 assume 0 == ~E_4~0;~E_4~0 := 1; 54871#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 54730#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 54731#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 54905#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 54906#L1401-3 assume !(0 == ~E_9~0); 53472#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 53336#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 53337#L1416-3 assume 0 == ~E_12~0;~E_12~0 := 1; 54030#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 54031#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 54138#L640-45 assume !(1 == ~m_pc~0); 54139#L640-47 is_master_triggered_~__retres1~0#1 := 0; 53580#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 53581#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 53121#L1603-45 assume !(0 != activate_threads_~tmp~1#1); 53122#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 53210#L659-45 assume 1 == ~t1_pc~0; 53211#L660-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 53664#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 55076#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 55006#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 54659#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 54660#L678-45 assume 1 == ~t2_pc~0; 54611#L679-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 54145#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 54146#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 54593#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 54922#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 55025#L697-45 assume 1 == ~t3_pc~0; 54406#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 54407#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 55092#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 54559#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 54560#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 54594#L716-45 assume 1 == ~t4_pc~0; 54218#L717-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 54220#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 54877#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 54225#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 54226#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 53889#L735-45 assume 1 == ~t5_pc~0; 53890#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 54438#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 55043#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 55089#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 55045#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 55039#L754-45 assume 1 == ~t6_pc~0; 54389#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 54390#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 54283#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 54284#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 54394#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 54121#L773-45 assume 1 == ~t7_pc~0; 54122#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 53661#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 54355#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 54356#L1659-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 54129#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 53780#L792-45 assume 1 == ~t8_pc~0; 53781#L793-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 54809#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 54810#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 53231#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 53232#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 53730#L811-45 assume 1 == ~t9_pc~0; 53507#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 53508#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 54727#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 54590#L1675-45 assume !(0 != activate_threads_~tmp___8~0#1); 54197#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 53988#L830-45 assume 1 == ~t10_pc~0; 53989#L831-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 53158#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 54306#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 53382#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 53383#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 53141#L849-45 assume !(1 == ~t11_pc~0); 53142#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 53598#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 53439#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 53127#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 53128#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 53377#L868-45 assume 1 == ~t12_pc~0; 53378#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 53321#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 53322#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 54762#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 54935#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 54936#L887-45 assume !(1 == ~t13_pc~0); 53384#L887-47 is_transmit13_triggered_~__retres1~13#1 := 0; 53385#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 54690#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 54709#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 53351#L1707-47 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 53352#L1439-3 assume 1 == ~M_E~0;~M_E~0 := 2; 54685#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 53369#L1444-3 assume !(1 == ~T2_E~0); 53370#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 53528#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 54496#L1459-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 54497#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 54937#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 54874#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 54875#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 54939#L1484-3 assume !(1 == ~T10_E~0); 54179#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 54180#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 54802#L1499-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 54455#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 54456#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 54887#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 54923#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 54096#L1524-3 assume !(1 == ~E_4~0); 54097#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 54961#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 54374#L1539-3 assume 1 == ~E_7~0;~E_7~0 := 2; 53831#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 53832#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 54337#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 53416#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 53417#L1564-3 assume !(1 == ~E_12~0); 54595#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 54596#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 53308#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 53082#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 53408#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 53315#L1959 assume !(0 == start_simulation_~tmp~3#1); 53317#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 53347#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 53301#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 53136#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 53137#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 54955#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 54930#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 54931#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 53371#L1940-2 [2024-11-08 00:35:55,337 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:55,337 INFO L85 PathProgramCache]: Analyzing trace with hash -327400631, now seen corresponding path program 1 times [2024-11-08 00:35:55,338 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:55,338 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1773733891] [2024-11-08 00:35:55,338 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:55,338 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:55,349 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:55,390 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:55,390 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:55,390 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1773733891] [2024-11-08 00:35:55,390 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1773733891] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:55,390 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:55,390 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-08 00:35:55,390 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [987278774] [2024-11-08 00:35:55,390 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:55,390 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:35:55,390 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:55,391 INFO L85 PathProgramCache]: Analyzing trace with hash -291836997, now seen corresponding path program 3 times [2024-11-08 00:35:55,391 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:55,391 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [950517752] [2024-11-08 00:35:55,391 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:55,391 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:55,402 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:55,432 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:55,432 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:55,432 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [950517752] [2024-11-08 00:35:55,432 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [950517752] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:55,432 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:55,432 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:55,432 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [734482438] [2024-11-08 00:35:55,433 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:55,433 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:35:55,433 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:35:55,433 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:35:55,433 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:35:55,433 INFO L87 Difference]: Start difference. First operand 2037 states and 2998 transitions. cyclomatic complexity: 962 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:55,510 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:35:55,511 INFO L93 Difference]: Finished difference Result 3799 states and 5574 transitions. [2024-11-08 00:35:55,511 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3799 states and 5574 transitions. [2024-11-08 00:35:55,536 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3624 [2024-11-08 00:35:55,552 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3799 states to 3799 states and 5574 transitions. [2024-11-08 00:35:55,556 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3799 [2024-11-08 00:35:55,559 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3799 [2024-11-08 00:35:55,559 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3799 states and 5574 transitions. [2024-11-08 00:35:55,570 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:35:55,572 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3799 states and 5574 transitions. [2024-11-08 00:35:55,579 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3799 states and 5574 transitions. [2024-11-08 00:35:55,724 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3799 to 3799. [2024-11-08 00:35:55,735 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3799 states, 3799 states have (on average 1.4672282179520926) internal successors, (5574), 3798 states have internal predecessors, (5574), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:55,746 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3799 states to 3799 states and 5574 transitions. [2024-11-08 00:35:55,750 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3799 states and 5574 transitions. [2024-11-08 00:35:55,750 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:35:55,751 INFO L425 stractBuchiCegarLoop]: Abstraction has 3799 states and 5574 transitions. [2024-11-08 00:35:55,754 INFO L332 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2024-11-08 00:35:55,754 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3799 states and 5574 transitions. [2024-11-08 00:35:55,767 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3624 [2024-11-08 00:35:55,767 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:35:55,767 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:35:55,769 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:55,769 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:55,769 INFO L745 eck$LassoCheckResult]: Stem: 59206#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 59207#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 60206#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 60207#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 60959#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 60333#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 59798#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 59799#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 60612#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 60613#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 60719#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 60720#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 59549#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 59550#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 60754#L959-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 60102#L964-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 60103#L969-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 60659#L974-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 60017#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 60018#L1291 assume !(0 == ~M_E~0); 60960#L1291-2 assume !(0 == ~T1_E~0); 60957#L1296-1 assume !(0 == ~T2_E~0); 60166#L1301-1 assume !(0 == ~T3_E~0); 60167#L1306-1 assume !(0 == ~T4_E~0); 60669#L1311-1 assume !(0 == ~T5_E~0); 59383#L1316-1 assume !(0 == ~T6_E~0); 59384#L1321-1 assume !(0 == ~T7_E~0); 60180#L1326-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 59203#L1331-1 assume !(0 == ~T9_E~0); 58916#L1336-1 assume !(0 == ~T10_E~0); 58917#L1341-1 assume !(0 == ~T11_E~0); 58990#L1346-1 assume !(0 == ~T12_E~0); 58991#L1351-1 assume !(0 == ~T13_E~0); 59320#L1356-1 assume !(0 == ~E_M~0); 59321#L1361-1 assume !(0 == ~E_1~0); 60890#L1366-1 assume 0 == ~E_2~0;~E_2~0 := 1; 59367#L1371-1 assume !(0 == ~E_3~0); 59368#L1376-1 assume !(0 == ~E_4~0); 60233#L1381-1 assume !(0 == ~E_5~0); 60234#L1386-1 assume !(0 == ~E_6~0); 60925#L1391-1 assume !(0 == ~E_7~0); 60948#L1396-1 assume !(0 == ~E_8~0); 60134#L1401-1 assume !(0 == ~E_9~0); 60135#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 60423#L1411-1 assume !(0 == ~E_11~0); 60424#L1416-1 assume !(0 == ~E_12~0); 60052#L1421-1 assume !(0 == ~E_13~0); 59569#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 59570#L640 assume !(1 == ~m_pc~0); 60101#L640-2 is_master_triggered_~__retres1~0#1 := 0; 60100#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 60060#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 60061#L1603 assume !(0 != activate_threads_~tmp~1#1); 60089#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 59717#L659 assume 1 == ~t1_pc~0; 59718#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 59828#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 60545#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 59850#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 59851#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 59867#L678 assume 1 == ~t2_pc~0; 60826#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 60827#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 59410#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 59411#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 59963#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 60084#L697 assume !(1 == ~t3_pc~0); 60085#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 60214#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 60535#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 59996#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 59997#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 60859#L716 assume 1 == ~t4_pc~0; 60847#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 59699#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 59065#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 59066#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 59171#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 60500#L735 assume !(1 == ~t5_pc~0); 59138#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 59139#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 59594#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 60525#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 60160#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 60161#L754 assume 1 == ~t6_pc~0; 59914#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 59812#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 59387#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 59388#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 59785#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 60603#L773 assume !(1 == ~t7_pc~0); 59324#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 59323#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 60195#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 60170#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 60171#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 60225#L792 assume 1 == ~t8_pc~0; 60394#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 60721#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 60722#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 60164#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 60087#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 60088#L811 assume 1 == ~t9_pc~0; 60297#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 60768#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 59466#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 59467#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 60097#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 60098#L830 assume !(1 == ~t10_pc~0); 59823#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 59300#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 59301#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 59278#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 59279#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 60620#L849 assume 1 == ~t11_pc~0; 60621#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 59117#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 59118#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 60631#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 60531#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 60532#L868 assume !(1 == ~t12_pc~0); 59947#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 59946#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 59005#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 59006#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 59335#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 59336#L887 assume 1 == ~t13_pc~0; 60537#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 59990#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 59991#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 60594#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 59045#L1707-2 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 59046#L1439 assume !(1 == ~M_E~0); 60156#L1439-2 assume !(1 == ~T1_E~0); 59216#L1444-1 assume !(1 == ~T2_E~0); 59217#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 59723#L1454-1 assume !(1 == ~T4_E~0); 59724#L1459-1 assume !(1 == ~T5_E~0); 60289#L1464-1 assume !(1 == ~T6_E~0); 60290#L1469-1 assume !(1 == ~T7_E~0); 60362#L1474-1 assume !(1 == ~T8_E~0); 60053#L1479-1 assume !(1 == ~T9_E~0); 60054#L1484-1 assume !(1 == ~T10_E~0); 60292#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 59938#L1494-1 assume !(1 == ~T12_E~0); 59939#L1499-1 assume !(1 == ~T13_E~0); 60119#L1504-1 assume !(1 == ~E_M~0); 60120#L1509-1 assume !(1 == ~E_1~0); 60706#L1514-1 assume !(1 == ~E_2~0); 60396#L1519-1 assume !(1 == ~E_3~0); 60397#L1524-1 assume !(1 == ~E_4~0); 60909#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 60910#L1534-1 assume !(1 == ~E_6~0); 59039#L1539-1 assume !(1 == ~E_7~0); 59040#L1544-1 assume !(1 == ~E_8~0); 59465#L1549-1 assume !(1 == ~E_9~0); 60881#L1554-1 assume !(1 == ~E_10~0); 60875#L1559-1 assume !(1 == ~E_11~0); 60746#L1564-1 assume !(1 == ~E_12~0); 60747#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 60901#L1574-1 assume { :end_inline_reset_delta_events } true; 60934#L1940-2 [2024-11-08 00:35:55,770 INFO L747 eck$LassoCheckResult]: Loop: 60934#L1940-2 assume !false; 61001#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 60997#L1266-1 assume !false; 60964#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 59780#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 59494#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 60705#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 60714#L1079 assume !(0 != eval_~tmp~0#1); 59980#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 59631#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 59632#L1291-3 assume !(0 == ~M_E~0); 60478#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 62389#L1296-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 62388#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 62387#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 62386#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 62385#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 62384#L1321-3 assume !(0 == ~T7_E~0); 62383#L1326-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 62382#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 62381#L1336-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 62380#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 62379#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 62378#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 62377#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 62376#L1361-3 assume !(0 == ~E_1~0); 62375#L1366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 62374#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 62373#L1376-3 assume 0 == ~E_4~0;~E_4~0 := 1; 62372#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 62371#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 62370#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 62369#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 62368#L1401-3 assume !(0 == ~E_9~0); 62367#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 62366#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 62365#L1416-3 assume 0 == ~E_12~0;~E_12~0 := 1; 62364#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 62363#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 62362#L640-45 assume 1 == ~m_pc~0; 62360#L641-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 62359#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 62358#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 62357#L1603-45 assume !(0 != activate_threads_~tmp~1#1); 60961#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 59053#L659-45 assume 1 == ~t1_pc~0; 59054#L660-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 59506#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 60942#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 60864#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 60508#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 60509#L678-45 assume 1 == ~t2_pc~0; 60459#L679-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 59992#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 59993#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 60441#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 60777#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 60883#L697-45 assume !(1 == ~t3_pc~0); 60256#L697-47 is_transmit3_triggered_~__retres1~3#1 := 0; 60255#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 60958#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 60407#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 60408#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 60442#L716-45 assume 1 == ~t4_pc~0; 60065#L717-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 60067#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 60732#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 60072#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 60073#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 59732#L735-45 assume 1 == ~t5_pc~0; 59733#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 60286#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 60903#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 60955#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 60907#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 60899#L754-45 assume 1 == ~t6_pc~0; 60237#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 60238#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 60130#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 60131#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 60242#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 59968#L773-45 assume 1 == ~t7_pc~0; 59969#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 59504#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 60203#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 60204#L1659-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 59976#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 59623#L792-45 assume 1 == ~t8_pc~0; 59624#L793-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 60663#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 60664#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 59074#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 59075#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 59573#L811-45 assume 1 == ~t9_pc~0; 59347#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 59348#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 60577#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 60438#L1675-45 assume !(0 != activate_threads_~tmp___8~0#1); 60044#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 59833#L830-45 assume !(1 == ~t10_pc~0); 59000#L830-47 is_transmit10_triggered_~__retres1~10#1 := 0; 59001#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 60153#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 59225#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 59226#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 58984#L849-45 assume !(1 == ~t11_pc~0); 58985#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 59441#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 59282#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 58970#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 58971#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 59220#L868-45 assume 1 == ~t12_pc~0; 59221#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 59164#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 59165#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 60614#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 60790#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 60791#L887-45 assume 1 == ~t13_pc~0; 60615#L888-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 59228#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 60539#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 60559#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 59194#L1707-47 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 59195#L1439-3 assume !(1 == ~M_E~0); 60550#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 62521#L1444-3 assume !(1 == ~T2_E~0); 62520#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 62519#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 62518#L1459-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 62517#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 62516#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 62515#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 62514#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 62513#L1484-3 assume !(1 == ~T10_E~0); 62512#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 62511#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 62510#L1499-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 62509#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 62508#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 62507#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 62506#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 62505#L1524-3 assume !(1 == ~E_4~0); 62504#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 62503#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 62502#L1539-3 assume 1 == ~E_7~0;~E_7~0 := 2; 62501#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 62500#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 60183#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 59259#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 59260#L1564-3 assume !(1 == ~E_12~0); 60670#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 60647#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 60648#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 61481#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 61478#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 61476#L1959 assume !(0 == start_simulation_~tmp~3#1); 61473#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 61058#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 61049#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 61047#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 61045#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 61030#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 61019#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 61012#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 60934#L1940-2 [2024-11-08 00:35:55,770 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:55,770 INFO L85 PathProgramCache]: Analyzing trace with hash -867830137, now seen corresponding path program 1 times [2024-11-08 00:35:55,771 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:55,771 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [882637646] [2024-11-08 00:35:55,771 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:55,771 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:55,779 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:55,823 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:55,823 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:55,823 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [882637646] [2024-11-08 00:35:55,823 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [882637646] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:55,824 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:55,824 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:55,824 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1549114097] [2024-11-08 00:35:55,824 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:55,824 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:35:55,824 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:55,824 INFO L85 PathProgramCache]: Analyzing trace with hash 647178235, now seen corresponding path program 1 times [2024-11-08 00:35:55,824 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:55,825 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [834246910] [2024-11-08 00:35:55,825 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:55,825 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:55,834 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:55,862 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:55,862 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:55,862 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [834246910] [2024-11-08 00:35:55,862 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [834246910] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:55,862 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:55,863 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:55,863 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1680327219] [2024-11-08 00:35:55,863 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:55,863 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:35:55,863 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:35:55,863 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-08 00:35:55,863 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-08 00:35:55,864 INFO L87 Difference]: Start difference. First operand 3799 states and 5574 transitions. cyclomatic complexity: 1776 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:55,952 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:35:55,952 INFO L93 Difference]: Finished difference Result 5553 states and 8132 transitions. [2024-11-08 00:35:55,952 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5553 states and 8132 transitions. [2024-11-08 00:35:55,966 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5358 [2024-11-08 00:35:55,975 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5553 states to 5553 states and 8132 transitions. [2024-11-08 00:35:55,976 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5553 [2024-11-08 00:35:55,979 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5553 [2024-11-08 00:35:55,979 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5553 states and 8132 transitions. [2024-11-08 00:35:55,984 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:35:55,984 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5553 states and 8132 transitions. [2024-11-08 00:35:55,987 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5553 states and 8132 transitions. [2024-11-08 00:35:56,020 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5553 to 3799. [2024-11-08 00:35:56,024 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3799 states, 3799 states have (on average 1.4664385364569623) internal successors, (5571), 3798 states have internal predecessors, (5571), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:56,030 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3799 states to 3799 states and 5571 transitions. [2024-11-08 00:35:56,030 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3799 states and 5571 transitions. [2024-11-08 00:35:56,030 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-08 00:35:56,031 INFO L425 stractBuchiCegarLoop]: Abstraction has 3799 states and 5571 transitions. [2024-11-08 00:35:56,031 INFO L332 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2024-11-08 00:35:56,031 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3799 states and 5571 transitions. [2024-11-08 00:35:56,036 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3624 [2024-11-08 00:35:56,036 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:35:56,036 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:35:56,038 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:56,038 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:56,038 INFO L745 eck$LassoCheckResult]: Stem: 68568#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 68569#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 69564#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 69565#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 70302#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 69691#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 69159#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 69160#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 69966#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 69967#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 70071#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 70072#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 68911#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 68912#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 70106#L959-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 69461#L964-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 69462#L969-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 70011#L974-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 69376#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 69377#L1291 assume !(0 == ~M_E~0); 70303#L1291-2 assume !(0 == ~T1_E~0); 70300#L1296-1 assume !(0 == ~T2_E~0); 69525#L1301-1 assume !(0 == ~T3_E~0); 69526#L1306-1 assume !(0 == ~T4_E~0); 70021#L1311-1 assume !(0 == ~T5_E~0); 68745#L1316-1 assume !(0 == ~T6_E~0); 68746#L1321-1 assume !(0 == ~T7_E~0); 69539#L1326-1 assume !(0 == ~T8_E~0); 68565#L1331-1 assume !(0 == ~T9_E~0); 68278#L1336-1 assume !(0 == ~T10_E~0); 68279#L1341-1 assume !(0 == ~T11_E~0); 68352#L1346-1 assume !(0 == ~T12_E~0); 68353#L1351-1 assume !(0 == ~T13_E~0); 68682#L1356-1 assume !(0 == ~E_M~0); 68683#L1361-1 assume !(0 == ~E_1~0); 70240#L1366-1 assume 0 == ~E_2~0;~E_2~0 := 1; 68729#L1371-1 assume !(0 == ~E_3~0); 68730#L1376-1 assume !(0 == ~E_4~0); 69591#L1381-1 assume !(0 == ~E_5~0); 69592#L1386-1 assume !(0 == ~E_6~0); 70271#L1391-1 assume !(0 == ~E_7~0); 70291#L1396-1 assume !(0 == ~E_8~0); 69493#L1401-1 assume !(0 == ~E_9~0); 69494#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 69781#L1411-1 assume !(0 == ~E_11~0); 69782#L1416-1 assume !(0 == ~E_12~0); 69411#L1421-1 assume !(0 == ~E_13~0); 68933#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 68934#L640 assume !(1 == ~m_pc~0); 69460#L640-2 is_master_triggered_~__retres1~0#1 := 0; 69459#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 69419#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 69420#L1603 assume !(0 != activate_threads_~tmp~1#1); 69448#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 69079#L659 assume 1 == ~t1_pc~0; 69080#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 69189#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 69902#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 69211#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 69212#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 69228#L678 assume 1 == ~t2_pc~0; 70175#L679 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 70176#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 68772#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 68773#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 69322#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 69443#L697 assume !(1 == ~t3_pc~0); 69444#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 69572#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 69892#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 69355#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 69356#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 70209#L716 assume 1 == ~t4_pc~0; 70197#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 69061#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 68427#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 68428#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 68533#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 69857#L735 assume !(1 == ~t5_pc~0); 68500#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 68501#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 68956#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 69882#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 69519#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 69520#L754 assume 1 == ~t6_pc~0; 69275#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 69173#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 68749#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 68750#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 69146#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 69957#L773 assume !(1 == ~t7_pc~0); 68686#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 68685#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 69554#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 69529#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 69530#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 69583#L792 assume 1 == ~t8_pc~0; 69752#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 70073#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 70074#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 69523#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 69446#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 69447#L811 assume 1 == ~t9_pc~0; 69655#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 70120#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 68828#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 68829#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 69456#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 69457#L830 assume !(1 == ~t10_pc~0); 69184#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 68662#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 68663#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 68640#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 68641#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 69974#L849 assume 1 == ~t11_pc~0; 69975#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 68479#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 68480#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 69985#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 69888#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 69889#L868 assume !(1 == ~t12_pc~0); 69306#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 69305#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 68367#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 68368#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 68697#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 68698#L887 assume 1 == ~t13_pc~0; 69894#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 69349#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 69350#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 69950#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 68407#L1707-2 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 68408#L1439 assume !(1 == ~M_E~0); 69515#L1439-2 assume !(1 == ~T1_E~0); 68578#L1444-1 assume !(1 == ~T2_E~0); 68579#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 69085#L1454-1 assume !(1 == ~T4_E~0); 69086#L1459-1 assume !(1 == ~T5_E~0); 69647#L1464-1 assume !(1 == ~T6_E~0); 69648#L1469-1 assume !(1 == ~T7_E~0); 69723#L1474-1 assume !(1 == ~T8_E~0); 69412#L1479-1 assume !(1 == ~T9_E~0); 69413#L1484-1 assume !(1 == ~T10_E~0); 69650#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 69297#L1494-1 assume !(1 == ~T12_E~0); 69298#L1499-1 assume !(1 == ~T13_E~0); 69478#L1504-1 assume !(1 == ~E_M~0); 69479#L1509-1 assume !(1 == ~E_1~0); 70057#L1514-1 assume !(1 == ~E_2~0); 69754#L1519-1 assume !(1 == ~E_3~0); 69755#L1524-1 assume !(1 == ~E_4~0); 70255#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 70256#L1534-1 assume !(1 == ~E_6~0); 68401#L1539-1 assume !(1 == ~E_7~0); 68402#L1544-1 assume !(1 == ~E_8~0); 68827#L1549-1 assume !(1 == ~E_9~0); 70232#L1554-1 assume !(1 == ~E_10~0); 70226#L1559-1 assume !(1 == ~E_11~0); 70098#L1564-1 assume !(1 == ~E_12~0); 70099#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 70250#L1574-1 assume { :end_inline_reset_delta_events } true; 68576#L1940-2 [2024-11-08 00:35:56,039 INFO L747 eck$LassoCheckResult]: Loop: 68576#L1940-2 assume !false; 68577#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 69120#L1266-1 assume !false; 70294#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 69141#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 68856#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 70056#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 70065#L1079 assume !(0 != eval_~tmp~0#1); 69339#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 68993#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 68994#L1291-3 assume !(0 == ~M_E~0); 69720#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 69721#L1296-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 70281#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 70236#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 69379#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 68614#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 68615#L1321-3 assume !(0 == ~T7_E~0); 68719#L1326-3 assume !(0 == ~T8_E~0); 69508#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 69759#L1336-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 69760#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 69076#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 69053#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 68991#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 68992#L1361-3 assume !(0 == ~E_1~0); 69573#L1366-3 assume 0 == ~E_2~0;~E_2~0 := 1; 68330#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 68331#L1376-3 assume 0 == ~E_4~0;~E_4~0 := 1; 70078#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 69936#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 69937#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 70112#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 70113#L1401-3 assume !(0 == ~E_9~0); 68679#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 68541#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 68542#L1416-3 assume 0 == ~E_12~0;~E_12~0 := 1; 69236#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 69237#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 69344#L640-45 assume !(1 == ~m_pc~0); 69345#L640-47 is_master_triggered_~__retres1~0#1 := 0; 68785#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 68786#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 68326#L1603-45 assume !(0 != activate_threads_~tmp~1#1); 68327#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 68415#L659-45 assume !(1 == ~t1_pc~0); 68417#L659-47 is_transmit1_triggered_~__retres1~1#1 := 0; 68872#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 70285#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 70214#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 69865#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 69866#L678-45 assume 1 == ~t2_pc~0; 69817#L679-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 69351#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 69352#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 69799#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 70129#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 70234#L697-45 assume 1 == ~t3_pc~0; 69612#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 69613#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 70301#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 69765#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 69766#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 69800#L716-45 assume !(1 == ~t4_pc~0); 69425#L716-47 is_transmit4_triggered_~__retres1~4#1 := 0; 69426#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 70084#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 69431#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 69432#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 69094#L735-45 assume 1 == ~t5_pc~0; 69095#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 69644#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 70252#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 70298#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 70254#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 70248#L754-45 assume 1 == ~t6_pc~0; 69595#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 69596#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 69489#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 69490#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 69600#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 69328#L773-45 assume 1 == ~t7_pc~0; 69329#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 68867#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 69561#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 69562#L1659-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 69335#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 68984#L792-45 assume 1 == ~t8_pc~0; 68985#L793-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 70015#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 70016#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 68436#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 68437#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 68935#L811-45 assume 1 == ~t9_pc~0; 68709#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 68710#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 69933#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 69796#L1675-45 assume !(0 != activate_threads_~tmp___8~0#1); 69403#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 69194#L830-45 assume 1 == ~t10_pc~0; 69195#L831-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 68363#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 69512#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 68587#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 68588#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 68346#L849-45 assume !(1 == ~t11_pc~0); 68347#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 68803#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 68642#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 68332#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 68333#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 68582#L868-45 assume 1 == ~t12_pc~0; 68583#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 68526#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 68527#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 69968#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 70142#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 70143#L887-45 assume 1 == ~t13_pc~0; 69969#L888-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 68590#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 69896#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 69915#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 68556#L1707-47 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 68557#L1439-3 assume !(1 == ~M_E~0); 69891#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 68574#L1444-3 assume !(1 == ~T2_E~0); 68575#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 68733#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 69702#L1459-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 69703#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 70144#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 70081#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 70082#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 70146#L1484-3 assume !(1 == ~T10_E~0); 69384#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 69385#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 70008#L1499-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 69661#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 69662#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 70094#L1514-3 assume 1 == ~E_2~0;~E_2~0 := 2; 70130#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 69302#L1524-3 assume !(1 == ~E_4~0); 69303#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 70168#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 69580#L1539-3 assume 1 == ~E_7~0;~E_7~0 := 2; 69036#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 69037#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 69542#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 68621#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 68622#L1564-3 assume !(1 == ~E_12~0); 69801#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 69802#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 68513#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 68287#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 68610#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 68520#L1959 assume !(0 == start_simulation_~tmp~3#1); 68522#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 68550#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 68506#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 68341#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 68342#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 70161#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 70136#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 70137#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 68576#L1940-2 [2024-11-08 00:35:56,039 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:56,039 INFO L85 PathProgramCache]: Analyzing trace with hash 1809696709, now seen corresponding path program 1 times [2024-11-08 00:35:56,039 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:56,039 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [886258101] [2024-11-08 00:35:56,039 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:56,039 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:56,049 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:56,083 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:56,084 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:56,084 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [886258101] [2024-11-08 00:35:56,084 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [886258101] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:56,084 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:56,084 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-08 00:35:56,084 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [285295976] [2024-11-08 00:35:56,084 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:56,084 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:35:56,085 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:56,085 INFO L85 PathProgramCache]: Analyzing trace with hash 1930683898, now seen corresponding path program 1 times [2024-11-08 00:35:56,085 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:56,085 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1414325541] [2024-11-08 00:35:56,085 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:56,085 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:56,096 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:56,138 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:56,139 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:56,139 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1414325541] [2024-11-08 00:35:56,139 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1414325541] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:56,139 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:56,140 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:56,140 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [222807627] [2024-11-08 00:35:56,140 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:56,140 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:35:56,140 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:35:56,140 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:35:56,140 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:35:56,141 INFO L87 Difference]: Start difference. First operand 3799 states and 5571 transitions. cyclomatic complexity: 1773 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:56,252 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:35:56,252 INFO L93 Difference]: Finished difference Result 3799 states and 5533 transitions. [2024-11-08 00:35:56,252 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3799 states and 5533 transitions. [2024-11-08 00:35:56,260 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3624 [2024-11-08 00:35:56,266 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3799 states to 3799 states and 5533 transitions. [2024-11-08 00:35:56,266 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3799 [2024-11-08 00:35:56,268 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3799 [2024-11-08 00:35:56,269 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3799 states and 5533 transitions. [2024-11-08 00:35:56,272 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:35:56,272 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3799 states and 5533 transitions. [2024-11-08 00:35:56,274 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3799 states and 5533 transitions. [2024-11-08 00:35:56,300 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3799 to 3799. [2024-11-08 00:35:56,304 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3799 states, 3799 states have (on average 1.4564359041853119) internal successors, (5533), 3798 states have internal predecessors, (5533), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:56,310 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3799 states to 3799 states and 5533 transitions. [2024-11-08 00:35:56,310 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3799 states and 5533 transitions. [2024-11-08 00:35:56,311 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:35:56,311 INFO L425 stractBuchiCegarLoop]: Abstraction has 3799 states and 5533 transitions. [2024-11-08 00:35:56,311 INFO L332 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2024-11-08 00:35:56,311 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3799 states and 5533 transitions. [2024-11-08 00:35:56,317 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3624 [2024-11-08 00:35:56,317 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:35:56,317 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:35:56,318 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:56,319 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:56,319 INFO L745 eck$LassoCheckResult]: Stem: 76171#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 76172#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 77170#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 77171#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 77923#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 77297#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 76762#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 76763#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 77574#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 77575#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 77679#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 77680#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 76513#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 76514#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 77715#L959-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 77066#L964-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 77067#L969-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 77620#L974-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 76982#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 76983#L1291 assume !(0 == ~M_E~0); 77924#L1291-2 assume !(0 == ~T1_E~0); 77921#L1296-1 assume !(0 == ~T2_E~0); 77131#L1301-1 assume !(0 == ~T3_E~0); 77132#L1306-1 assume !(0 == ~T4_E~0); 77630#L1311-1 assume !(0 == ~T5_E~0); 76347#L1316-1 assume !(0 == ~T6_E~0); 76348#L1321-1 assume !(0 == ~T7_E~0); 77145#L1326-1 assume !(0 == ~T8_E~0); 76168#L1331-1 assume !(0 == ~T9_E~0); 75883#L1336-1 assume !(0 == ~T10_E~0); 75884#L1341-1 assume !(0 == ~T11_E~0); 75956#L1346-1 assume !(0 == ~T12_E~0); 75957#L1351-1 assume !(0 == ~T13_E~0); 76284#L1356-1 assume !(0 == ~E_M~0); 76285#L1361-1 assume !(0 == ~E_1~0); 77852#L1366-1 assume !(0 == ~E_2~0); 76331#L1371-1 assume !(0 == ~E_3~0); 76332#L1376-1 assume !(0 == ~E_4~0); 77197#L1381-1 assume !(0 == ~E_5~0); 77198#L1386-1 assume !(0 == ~E_6~0); 77886#L1391-1 assume !(0 == ~E_7~0); 77912#L1396-1 assume !(0 == ~E_8~0); 77098#L1401-1 assume !(0 == ~E_9~0); 77099#L1406-1 assume 0 == ~E_10~0;~E_10~0 := 1; 77388#L1411-1 assume !(0 == ~E_11~0); 77389#L1416-1 assume !(0 == ~E_12~0); 77017#L1421-1 assume !(0 == ~E_13~0); 76535#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 76536#L640 assume !(1 == ~m_pc~0); 77065#L640-2 is_master_triggered_~__retres1~0#1 := 0; 77064#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 77025#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 77026#L1603 assume !(0 != activate_threads_~tmp~1#1); 77053#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 76682#L659 assume 1 == ~t1_pc~0; 76683#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 76792#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 77509#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 76814#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 76815#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 76831#L678 assume !(1 == ~t2_pc~0); 77789#L678-2 is_transmit2_triggered_~__retres1~2#1 := 0; 77883#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 76374#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 76375#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 76928#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 77048#L697 assume !(1 == ~t3_pc~0); 77049#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 77178#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 77499#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 76961#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 76962#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 77821#L716 assume 1 == ~t4_pc~0; 77808#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 76664#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 76031#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 76032#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 76136#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 77464#L735 assume !(1 == ~t5_pc~0); 76104#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 76105#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 76558#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 77489#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 77124#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 77125#L754 assume 1 == ~t6_pc~0; 76878#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 76776#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 76351#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 76352#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 76749#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 77565#L773 assume !(1 == ~t7_pc~0); 76288#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 76287#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 77160#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 77135#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 77136#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 77189#L792 assume 1 == ~t8_pc~0; 77359#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 77681#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 77682#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 77128#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 77051#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 77052#L811 assume 1 == ~t9_pc~0; 77261#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 77729#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 76430#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 76431#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 77061#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 77062#L830 assume !(1 == ~t10_pc~0); 76787#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 76264#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 76265#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 76242#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 76243#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 77582#L849 assume 1 == ~t11_pc~0; 77583#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 76083#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 76084#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 77594#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 77495#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 77496#L868 assume !(1 == ~t12_pc~0); 76912#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 76911#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 75971#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 75972#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 76299#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 76300#L887 assume 1 == ~t13_pc~0; 77501#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 76955#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 76956#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 77558#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 76011#L1707-2 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 76012#L1439 assume !(1 == ~M_E~0); 77120#L1439-2 assume !(1 == ~T1_E~0); 76181#L1444-1 assume !(1 == ~T2_E~0); 76182#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 76688#L1454-1 assume !(1 == ~T4_E~0); 76689#L1459-1 assume !(1 == ~T5_E~0); 77253#L1464-1 assume !(1 == ~T6_E~0); 77254#L1469-1 assume !(1 == ~T7_E~0); 77329#L1474-1 assume !(1 == ~T8_E~0); 77018#L1479-1 assume !(1 == ~T9_E~0); 77019#L1484-1 assume !(1 == ~T10_E~0); 77256#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 76903#L1494-1 assume !(1 == ~T12_E~0); 76904#L1499-1 assume !(1 == ~T13_E~0); 77083#L1504-1 assume !(1 == ~E_M~0); 77084#L1509-1 assume !(1 == ~E_1~0); 77666#L1514-1 assume !(1 == ~E_2~0); 77361#L1519-1 assume !(1 == ~E_3~0); 77362#L1524-1 assume !(1 == ~E_4~0); 77868#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 77869#L1534-1 assume !(1 == ~E_6~0); 76005#L1539-1 assume !(1 == ~E_7~0); 76006#L1544-1 assume !(1 == ~E_8~0); 76429#L1549-1 assume !(1 == ~E_9~0); 77844#L1554-1 assume !(1 == ~E_10~0); 77838#L1559-1 assume !(1 == ~E_11~0); 77707#L1564-1 assume !(1 == ~E_12~0); 77708#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 77862#L1574-1 assume { :end_inline_reset_delta_events } true; 76179#L1940-2 [2024-11-08 00:35:56,319 INFO L747 eck$LassoCheckResult]: Loop: 76179#L1940-2 assume !false; 76180#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 76723#L1266-1 assume !false; 77915#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 76744#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 76458#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 77665#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 77674#L1079 assume !(0 != eval_~tmp~0#1); 76945#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 76595#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 76596#L1291-3 assume !(0 == ~M_E~0); 77326#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 77327#L1296-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 77902#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 77848#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 76985#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 76216#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 76217#L1321-3 assume !(0 == ~T7_E~0); 76321#L1326-3 assume !(0 == ~T8_E~0); 77113#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 77366#L1336-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 77367#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 76679#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 76656#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 76593#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 76594#L1361-3 assume !(0 == ~E_1~0); 77179#L1366-3 assume !(0 == ~E_2~0); 75934#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 75935#L1376-3 assume 0 == ~E_4~0;~E_4~0 := 1; 77686#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 77544#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 77545#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 77721#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 77722#L1401-3 assume !(0 == ~E_9~0); 76279#L1406-3 assume 0 == ~E_10~0;~E_10~0 := 1; 76144#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 76145#L1416-3 assume 0 == ~E_12~0;~E_12~0 := 1; 76839#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 76840#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 76950#L640-45 assume !(1 == ~m_pc~0); 76951#L640-47 is_master_triggered_~__retres1~0#1 := 0; 76387#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 76388#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 75930#L1603-45 assume !(0 != activate_threads_~tmp~1#1); 75931#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 76019#L659-45 assume !(1 == ~t1_pc~0); 76021#L659-47 is_transmit1_triggered_~__retres1~1#1 := 0; 76474#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 77906#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 77827#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 77472#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 77473#L678-45 assume !(1 == ~t2_pc~0); 77426#L678-47 is_transmit2_triggered_~__retres1~2#1 := 0; 76957#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 76958#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 77406#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 77739#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 77846#L697-45 assume 1 == ~t3_pc~0; 77218#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 77219#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 77922#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 77372#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 77373#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 77407#L716-45 assume !(1 == ~t4_pc~0); 77031#L716-47 is_transmit4_triggered_~__retres1~4#1 := 0; 77032#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 77693#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 77036#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 77037#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 76697#L735-45 assume !(1 == ~t5_pc~0); 76699#L735-47 is_transmit5_triggered_~__retres1~5#1 := 0; 77250#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 77864#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 77919#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 77866#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 77860#L754-45 assume 1 == ~t6_pc~0; 77201#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 77202#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 77094#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 77095#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 77206#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 76934#L773-45 assume !(1 == ~t7_pc~0); 76468#L773-47 is_transmit7_triggered_~__retres1~7#1 := 0; 76469#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 77167#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 77168#L1659-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 76941#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 76587#L792-45 assume !(1 == ~t8_pc~0); 76589#L792-47 is_transmit8_triggered_~__retres1~8#1 := 0; 77624#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 77625#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 76040#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 76041#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 76537#L811-45 assume 1 == ~t9_pc~0; 76311#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 76312#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 77541#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 77403#L1675-45 assume !(0 != activate_threads_~tmp___8~0#1); 77009#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 76796#L830-45 assume 1 == ~t10_pc~0; 76797#L831-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 75967#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 77117#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 76190#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 76191#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 75947#L849-45 assume 1 == ~t11_pc~0; 75949#L850-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 76405#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 76244#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 75936#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 75937#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 76185#L868-45 assume !(1 == ~t12_pc~0); 76187#L868-47 is_transmit12_triggered_~__retres1~12#1 := 0; 76129#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 76130#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 77576#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 77752#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 77753#L887-45 assume !(1 == ~t13_pc~0); 76192#L887-47 is_transmit13_triggered_~__retres1~13#1 := 0; 76193#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 77503#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 77522#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 76159#L1707-47 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 76160#L1439-3 assume !(1 == ~M_E~0); 77498#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 76177#L1444-3 assume !(1 == ~T2_E~0); 76178#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 76335#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 77308#L1459-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 77309#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 77754#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 77690#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 77691#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 77756#L1484-3 assume !(1 == ~T10_E~0); 76990#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 76991#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 77617#L1499-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 77267#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 77268#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 77703#L1514-3 assume !(1 == ~E_2~0); 77740#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 76908#L1524-3 assume !(1 == ~E_4~0); 76909#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 77780#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 77186#L1539-3 assume 1 == ~E_7~0;~E_7~0 := 2; 76639#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 76640#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 77148#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 76223#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 76224#L1564-3 assume !(1 == ~E_12~0); 77408#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 77409#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 76117#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 75892#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 76212#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 76123#L1959 assume !(0 == start_simulation_~tmp~3#1); 76125#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 76153#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 76110#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 75945#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 75946#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 77773#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 77746#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 77747#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 76179#L1940-2 [2024-11-08 00:35:56,320 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:56,320 INFO L85 PathProgramCache]: Analyzing trace with hash 350046660, now seen corresponding path program 1 times [2024-11-08 00:35:56,320 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:56,320 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [539221464] [2024-11-08 00:35:56,320 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:56,320 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:56,331 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:56,385 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:56,385 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:56,385 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [539221464] [2024-11-08 00:35:56,385 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [539221464] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:56,385 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:56,385 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:56,386 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1860442625] [2024-11-08 00:35:56,386 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:56,386 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:35:56,386 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:56,386 INFO L85 PathProgramCache]: Analyzing trace with hash 741514239, now seen corresponding path program 1 times [2024-11-08 00:35:56,386 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:56,386 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1985182148] [2024-11-08 00:35:56,386 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:56,386 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:56,400 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:56,429 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:56,429 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:56,429 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1985182148] [2024-11-08 00:35:56,429 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1985182148] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:56,429 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:56,429 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:56,429 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [281768120] [2024-11-08 00:35:56,429 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:56,429 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:35:56,430 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:35:56,430 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-08 00:35:56,430 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-08 00:35:56,430 INFO L87 Difference]: Start difference. First operand 3799 states and 5533 transitions. cyclomatic complexity: 1735 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:56,565 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:35:56,566 INFO L93 Difference]: Finished difference Result 5438 states and 7902 transitions. [2024-11-08 00:35:56,566 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5438 states and 7902 transitions. [2024-11-08 00:35:56,577 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5258 [2024-11-08 00:35:56,586 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5438 states to 5438 states and 7902 transitions. [2024-11-08 00:35:56,586 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5438 [2024-11-08 00:35:56,589 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5438 [2024-11-08 00:35:56,589 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5438 states and 7902 transitions. [2024-11-08 00:35:56,593 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:35:56,594 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5438 states and 7902 transitions. [2024-11-08 00:35:56,596 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5438 states and 7902 transitions. [2024-11-08 00:35:56,625 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5438 to 3799. [2024-11-08 00:35:56,629 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3799 states, 3799 states have (on average 1.4556462226901816) internal successors, (5530), 3798 states have internal predecessors, (5530), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:56,634 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3799 states to 3799 states and 5530 transitions. [2024-11-08 00:35:56,634 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3799 states and 5530 transitions. [2024-11-08 00:35:56,635 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-08 00:35:56,635 INFO L425 stractBuchiCegarLoop]: Abstraction has 3799 states and 5530 transitions. [2024-11-08 00:35:56,635 INFO L332 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2024-11-08 00:35:56,635 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3799 states and 5530 transitions. [2024-11-08 00:35:56,640 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3624 [2024-11-08 00:35:56,641 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:35:56,641 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:35:56,642 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:56,643 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:56,643 INFO L745 eck$LassoCheckResult]: Stem: 85418#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 85419#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 86416#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 86417#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 87178#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 86544#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 86010#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 86011#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 86825#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 86826#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 86935#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 86936#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 85761#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 85762#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 86970#L959-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 86312#L964-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 86313#L969-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 86872#L974-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 86228#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 86229#L1291 assume !(0 == ~M_E~0); 87179#L1291-2 assume !(0 == ~T1_E~0); 87176#L1296-1 assume !(0 == ~T2_E~0); 86377#L1301-1 assume !(0 == ~T3_E~0); 86378#L1306-1 assume !(0 == ~T4_E~0); 86882#L1311-1 assume !(0 == ~T5_E~0); 85594#L1316-1 assume !(0 == ~T6_E~0); 85595#L1321-1 assume !(0 == ~T7_E~0); 86391#L1326-1 assume !(0 == ~T8_E~0); 85415#L1331-1 assume !(0 == ~T9_E~0); 85130#L1336-1 assume !(0 == ~T10_E~0); 85131#L1341-1 assume !(0 == ~T11_E~0); 85203#L1346-1 assume !(0 == ~T12_E~0); 85204#L1351-1 assume !(0 == ~T13_E~0); 85531#L1356-1 assume !(0 == ~E_M~0); 85532#L1361-1 assume !(0 == ~E_1~0); 87108#L1366-1 assume !(0 == ~E_2~0); 85578#L1371-1 assume !(0 == ~E_3~0); 85579#L1376-1 assume !(0 == ~E_4~0); 86444#L1381-1 assume !(0 == ~E_5~0); 86445#L1386-1 assume !(0 == ~E_6~0); 87142#L1391-1 assume !(0 == ~E_7~0); 87165#L1396-1 assume !(0 == ~E_8~0); 86344#L1401-1 assume !(0 == ~E_9~0); 86345#L1406-1 assume !(0 == ~E_10~0); 86638#L1411-1 assume !(0 == ~E_11~0); 86639#L1416-1 assume !(0 == ~E_12~0); 86263#L1421-1 assume !(0 == ~E_13~0); 85783#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 85784#L640 assume !(1 == ~m_pc~0); 86311#L640-2 is_master_triggered_~__retres1~0#1 := 0; 86310#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 86271#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 86272#L1603 assume !(0 != activate_threads_~tmp~1#1); 86299#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 85930#L659 assume 1 == ~t1_pc~0; 85931#L660 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 86041#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 86761#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 86063#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 86064#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 86080#L678 assume !(1 == ~t2_pc~0); 87043#L678-2 is_transmit2_triggered_~__retres1~2#1 := 0; 87139#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 85621#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 85622#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 86174#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 86294#L697 assume !(1 == ~t3_pc~0); 86295#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 86424#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 86749#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 86207#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 86208#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 87075#L716 assume 1 == ~t4_pc~0; 87063#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 85912#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 85278#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 85279#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 85383#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 86714#L735 assume !(1 == ~t5_pc~0); 85351#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 85352#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 85806#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 86739#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 86370#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 86371#L754 assume 1 == ~t6_pc~0; 86127#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 86024#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 85598#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 85599#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 85997#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 86816#L773 assume !(1 == ~t7_pc~0); 85535#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 85534#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 86406#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 86381#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 86382#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 86436#L792 assume 1 == ~t8_pc~0; 86609#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 86937#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 86938#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 86374#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 86297#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 86298#L811 assume 1 == ~t9_pc~0; 86508#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 86984#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 85677#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 85678#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 86307#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 86308#L830 assume !(1 == ~t10_pc~0); 86035#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 85511#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 85512#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 85489#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 85490#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 86834#L849 assume 1 == ~t11_pc~0; 86835#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 85330#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 85331#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 86846#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 86745#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 86746#L868 assume !(1 == ~t12_pc~0); 86158#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 86157#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 85218#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 85219#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 85546#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 85547#L887 assume 1 == ~t13_pc~0; 86751#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 86201#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 86202#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 86809#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 85258#L1707-2 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 85259#L1439 assume !(1 == ~M_E~0); 86366#L1439-2 assume !(1 == ~T1_E~0); 85428#L1444-1 assume !(1 == ~T2_E~0); 85429#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 85936#L1454-1 assume !(1 == ~T4_E~0); 85937#L1459-1 assume !(1 == ~T5_E~0); 86500#L1464-1 assume !(1 == ~T6_E~0); 86501#L1469-1 assume !(1 == ~T7_E~0); 86580#L1474-1 assume !(1 == ~T8_E~0); 86264#L1479-1 assume !(1 == ~T9_E~0); 86265#L1484-1 assume !(1 == ~T10_E~0); 86503#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 86149#L1494-1 assume !(1 == ~T12_E~0); 86150#L1499-1 assume !(1 == ~T13_E~0); 86329#L1504-1 assume !(1 == ~E_M~0); 86330#L1509-1 assume !(1 == ~E_1~0); 86921#L1514-1 assume !(1 == ~E_2~0); 86611#L1519-1 assume !(1 == ~E_3~0); 86612#L1524-1 assume !(1 == ~E_4~0); 87125#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 87126#L1534-1 assume !(1 == ~E_6~0); 85252#L1539-1 assume !(1 == ~E_7~0); 85253#L1544-1 assume !(1 == ~E_8~0); 85676#L1549-1 assume !(1 == ~E_9~0); 87098#L1554-1 assume !(1 == ~E_10~0); 87092#L1559-1 assume !(1 == ~E_11~0); 86962#L1564-1 assume !(1 == ~E_12~0); 86963#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 87118#L1574-1 assume { :end_inline_reset_delta_events } true; 85426#L1940-2 [2024-11-08 00:35:56,643 INFO L747 eck$LassoCheckResult]: Loop: 85426#L1940-2 assume !false; 85427#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 85971#L1266-1 assume !false; 87169#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 85992#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 85705#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 86920#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 86929#L1079 assume !(0 != eval_~tmp~0#1); 86191#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 85843#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 85844#L1291-3 assume !(0 == ~M_E~0); 86577#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 86578#L1296-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 87152#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 87104#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 86231#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 85463#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 85464#L1321-3 assume !(0 == ~T7_E~0); 85568#L1326-3 assume !(0 == ~T8_E~0); 86359#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 86616#L1336-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 86617#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 85927#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 85904#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 85841#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 85842#L1361-3 assume !(0 == ~E_1~0); 86425#L1366-3 assume !(0 == ~E_2~0); 85181#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 85182#L1376-3 assume 0 == ~E_4~0;~E_4~0 := 1; 86942#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 86795#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 86796#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 86976#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 86977#L1401-3 assume !(0 == ~E_9~0); 85528#L1406-3 assume !(0 == ~E_10~0); 85391#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 85392#L1416-3 assume 0 == ~E_12~0;~E_12~0 := 1; 86088#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 86089#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 86196#L640-45 assume !(1 == ~m_pc~0); 86197#L640-47 is_master_triggered_~__retres1~0#1 := 0; 85634#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 85635#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 85177#L1603-45 assume !(0 != activate_threads_~tmp~1#1); 85178#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 85266#L659-45 assume 1 == ~t1_pc~0; 85267#L660-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 85721#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 87156#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 87080#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 86722#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 86723#L678-45 assume !(1 == ~t2_pc~0); 86676#L678-47 is_transmit2_triggered_~__retres1~2#1 := 0; 86203#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 86204#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 86656#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 86993#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 87100#L697-45 assume 1 == ~t3_pc~0; 86466#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 86467#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 87177#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 86622#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 86623#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 86657#L716-45 assume !(1 == ~t4_pc~0); 86277#L716-47 is_transmit4_triggered_~__retres1~4#1 := 0; 86278#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 86949#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 86282#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 86283#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 85945#L735-45 assume !(1 == ~t5_pc~0); 85947#L735-47 is_transmit5_triggered_~__retres1~5#1 := 0; 86497#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 87121#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 87174#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 87124#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 87116#L754-45 assume 1 == ~t6_pc~0; 86448#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 86449#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 86340#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 86341#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 86453#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 86179#L773-45 assume !(1 == ~t7_pc~0); 85714#L773-47 is_transmit7_triggered_~__retres1~7#1 := 0; 85715#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 86413#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 86414#L1659-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 86187#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 85835#L792-45 assume !(1 == ~t8_pc~0); 85837#L792-47 is_transmit8_triggered_~__retres1~8#1 := 0; 86876#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 86877#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 85287#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 85288#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 85785#L811-45 assume 1 == ~t9_pc~0; 85558#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 85559#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 86792#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 86653#L1675-45 assume !(0 != activate_threads_~tmp___8~0#1); 86255#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 86046#L830-45 assume !(1 == ~t10_pc~0); 85213#L830-47 is_transmit10_triggered_~__retres1~10#1 := 0; 85214#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 86363#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 85437#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 85438#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 85197#L849-45 assume 1 == ~t11_pc~0; 85199#L850-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 85652#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 85491#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 85183#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 85184#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 85432#L868-45 assume 1 == ~t12_pc~0; 85433#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 85376#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 85377#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 86828#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 87006#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 87007#L887-45 assume 1 == ~t13_pc~0; 86829#L888-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 85440#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 86753#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 86774#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 85406#L1707-47 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 85407#L1439-3 assume !(1 == ~M_E~0); 86748#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 85424#L1444-3 assume !(1 == ~T2_E~0); 85425#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 85582#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 86556#L1459-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 86557#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 87008#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 86945#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 86946#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 87010#L1484-3 assume !(1 == ~T10_E~0); 86236#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 86237#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 86869#L1499-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 86514#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 86515#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 86958#L1514-3 assume !(1 == ~E_2~0); 86994#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 86154#L1524-3 assume !(1 == ~E_4~0); 86155#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 87034#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 86432#L1539-3 assume 1 == ~E_7~0;~E_7~0 := 2; 85887#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 85888#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 86394#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 85470#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 85471#L1564-3 assume !(1 == ~E_12~0); 86658#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 86659#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 85364#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 85139#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 85459#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 85370#L1959 assume !(0 == start_simulation_~tmp~3#1); 85372#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 85400#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 85357#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 85192#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 85193#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 87028#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 87000#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 87001#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 85426#L1940-2 [2024-11-08 00:35:56,644 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:56,644 INFO L85 PathProgramCache]: Analyzing trace with hash -1492429054, now seen corresponding path program 1 times [2024-11-08 00:35:56,644 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:56,644 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1149202571] [2024-11-08 00:35:56,644 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:56,644 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:56,653 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:56,685 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:56,686 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:56,686 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1149202571] [2024-11-08 00:35:56,686 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1149202571] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:56,686 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:56,686 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-08 00:35:56,686 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2117895780] [2024-11-08 00:35:56,686 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:56,686 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:35:56,686 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:56,687 INFO L85 PathProgramCache]: Analyzing trace with hash 1091666107, now seen corresponding path program 1 times [2024-11-08 00:35:56,687 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:56,687 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1839714596] [2024-11-08 00:35:56,687 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:56,687 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:56,697 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:56,727 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:56,727 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:56,727 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1839714596] [2024-11-08 00:35:56,727 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1839714596] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:56,727 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:56,727 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:56,727 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1309839543] [2024-11-08 00:35:56,727 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:56,727 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:35:56,728 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:35:56,728 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:35:56,728 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:35:56,728 INFO L87 Difference]: Start difference. First operand 3799 states and 5530 transitions. cyclomatic complexity: 1732 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:56,865 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:35:56,865 INFO L93 Difference]: Finished difference Result 7191 states and 10414 transitions. [2024-11-08 00:35:56,865 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7191 states and 10414 transitions. [2024-11-08 00:35:56,887 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 7013 [2024-11-08 00:35:56,909 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7191 states to 7191 states and 10414 transitions. [2024-11-08 00:35:56,909 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7191 [2024-11-08 00:35:56,915 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7191 [2024-11-08 00:35:56,915 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7191 states and 10414 transitions. [2024-11-08 00:35:56,925 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:35:56,925 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7191 states and 10414 transitions. [2024-11-08 00:35:56,931 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7191 states and 10414 transitions. [2024-11-08 00:35:57,022 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7191 to 7187. [2024-11-08 00:35:57,032 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7187 states, 7187 states have (on average 1.448448587727842) internal successors, (10410), 7186 states have internal predecessors, (10410), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:57,049 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7187 states to 7187 states and 10410 transitions. [2024-11-08 00:35:57,049 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7187 states and 10410 transitions. [2024-11-08 00:35:57,050 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:35:57,050 INFO L425 stractBuchiCegarLoop]: Abstraction has 7187 states and 10410 transitions. [2024-11-08 00:35:57,050 INFO L332 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2024-11-08 00:35:57,050 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7187 states and 10410 transitions. [2024-11-08 00:35:57,071 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 7009 [2024-11-08 00:35:57,071 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:35:57,071 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:35:57,073 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:57,073 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:57,074 INFO L745 eck$LassoCheckResult]: Stem: 96415#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 96416#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 97448#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 97449#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 98498#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 97601#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 97014#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 97015#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 97942#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 97943#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 98106#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 98107#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 96756#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 96757#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 98152#L959-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 97332#L964-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 97333#L969-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 98016#L974-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 97237#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 97238#L1291 assume !(0 == ~M_E~0); 98500#L1291-2 assume !(0 == ~T1_E~0); 98493#L1296-1 assume !(0 == ~T2_E~0); 97402#L1301-1 assume !(0 == ~T3_E~0); 97403#L1306-1 assume !(0 == ~T4_E~0); 98035#L1311-1 assume !(0 == ~T5_E~0); 96592#L1316-1 assume !(0 == ~T6_E~0); 96593#L1321-1 assume !(0 == ~T7_E~0); 97418#L1326-1 assume !(0 == ~T8_E~0); 96412#L1331-1 assume !(0 == ~T9_E~0); 96127#L1336-1 assume !(0 == ~T10_E~0); 96128#L1341-1 assume !(0 == ~T11_E~0); 96200#L1346-1 assume !(0 == ~T12_E~0); 96201#L1351-1 assume !(0 == ~T13_E~0); 96528#L1356-1 assume !(0 == ~E_M~0); 96529#L1361-1 assume !(0 == ~E_1~0); 98374#L1366-1 assume !(0 == ~E_2~0); 96576#L1371-1 assume !(0 == ~E_3~0); 96577#L1376-1 assume !(0 == ~E_4~0); 97481#L1381-1 assume !(0 == ~E_5~0); 97482#L1386-1 assume !(0 == ~E_6~0); 98438#L1391-1 assume !(0 == ~E_7~0); 98468#L1396-1 assume !(0 == ~E_8~0); 97368#L1401-1 assume !(0 == ~E_9~0); 97369#L1406-1 assume !(0 == ~E_10~0); 97701#L1411-1 assume !(0 == ~E_11~0); 97702#L1416-1 assume !(0 == ~E_12~0); 97278#L1421-1 assume !(0 == ~E_13~0); 96777#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 96778#L640 assume !(1 == ~m_pc~0); 97331#L640-2 is_master_triggered_~__retres1~0#1 := 0; 97330#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 97286#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 97287#L1603 assume !(0 != activate_threads_~tmp~1#1); 97317#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 96933#L659 assume !(1 == ~t1_pc~0); 96934#L659-2 is_transmit1_triggered_~__retres1~1#1 := 0; 98221#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 97858#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 97065#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 97066#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 97082#L678 assume !(1 == ~t2_pc~0); 98260#L678-2 is_transmit2_triggered_~__retres1~2#1 := 0; 98429#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 96619#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 96620#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 97183#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 97310#L697 assume !(1 == ~t3_pc~0); 97311#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 97459#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 97844#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 97217#L1627 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 97218#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 98310#L716 assume 1 == ~t4_pc~0; 98289#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 96913#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 96272#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 96273#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 96380#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 97795#L735 assume !(1 == ~t5_pc~0); 96348#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 96349#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 96807#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 97829#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 97395#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 97396#L754 assume 1 == ~t6_pc~0; 97131#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 97028#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 96596#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 96597#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 97001#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 97932#L773 assume !(1 == ~t7_pc~0); 96532#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 96531#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 97438#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 97406#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 97407#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 97471#L792 assume 1 == ~t8_pc~0; 97667#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 98108#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 98109#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 97397#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 97313#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 97314#L811 assume 1 == ~t9_pc~0; 97556#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 98166#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 96675#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 96676#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 97327#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 97328#L830 assume !(1 == ~t10_pc~0); 97037#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 96508#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 96509#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 96487#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 96488#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 97956#L849 assume 1 == ~t11_pc~0; 97957#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 96327#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 96328#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 97975#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 97836#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 97837#L868 assume !(1 == ~t12_pc~0); 97167#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 97166#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 96215#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 96216#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 96543#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 96544#L887 assume 1 == ~t13_pc~0; 97847#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 97211#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 97212#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 97920#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 96255#L1707-2 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 96256#L1439 assume !(1 == ~M_E~0); 97389#L1439-2 assume !(1 == ~T1_E~0); 96425#L1444-1 assume !(1 == ~T2_E~0); 96426#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 96937#L1454-1 assume !(1 == ~T4_E~0); 96938#L1459-1 assume !(1 == ~T5_E~0); 97548#L1464-1 assume !(1 == ~T6_E~0); 97549#L1469-1 assume !(1 == ~T7_E~0); 97633#L1474-1 assume !(1 == ~T8_E~0); 97279#L1479-1 assume !(1 == ~T9_E~0); 97280#L1484-1 assume !(1 == ~T10_E~0); 97552#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 97154#L1494-1 assume !(1 == ~T12_E~0); 97155#L1499-1 assume !(1 == ~T13_E~0); 97350#L1504-1 assume !(1 == ~E_M~0); 97351#L1509-1 assume !(1 == ~E_1~0); 98083#L1514-1 assume !(1 == ~E_2~0); 97669#L1519-1 assume !(1 == ~E_3~0); 97670#L1524-1 assume !(1 == ~E_4~0); 98405#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 98406#L1534-1 assume !(1 == ~E_6~0); 96249#L1539-1 assume !(1 == ~E_7~0); 96250#L1544-1 assume !(1 == ~E_8~0); 96672#L1549-1 assume !(1 == ~E_9~0); 98347#L1554-1 assume !(1 == ~E_10~0); 98345#L1559-1 assume !(1 == ~E_11~0); 98141#L1564-1 assume !(1 == ~E_12~0); 98142#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 98399#L1574-1 assume { :end_inline_reset_delta_events } true; 98445#L1940-2 [2024-11-08 00:35:57,074 INFO L747 eck$LassoCheckResult]: Loop: 98445#L1940-2 assume !false; 100333#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 100330#L1266-1 assume !false; 100329#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 100322#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 98081#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 98082#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 98093#L1079 assume !(0 != eval_~tmp~0#1); 97200#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 97201#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 97774#L1291-3 assume !(0 == ~M_E~0); 97634#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 97635#L1296-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 98457#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 98359#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 97242#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 96460#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 96461#L1321-3 assume !(0 == ~T7_E~0); 96565#L1326-3 assume !(0 == ~T8_E~0); 97383#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 97676#L1336-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 97677#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 96930#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 96907#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 96843#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 96844#L1361-3 assume !(0 == ~E_1~0); 97460#L1366-3 assume !(0 == ~E_2~0); 96178#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 96179#L1376-3 assume 0 == ~E_4~0;~E_4~0 := 1; 98115#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 97906#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 97907#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 98158#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 98159#L1401-3 assume !(0 == ~E_9~0); 96523#L1406-3 assume !(0 == ~E_10~0); 96388#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 96389#L1416-3 assume 0 == ~E_12~0;~E_12~0 := 1; 97090#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 97091#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 97206#L640-45 assume !(1 == ~m_pc~0); 97207#L640-47 is_master_triggered_~__retres1~0#1 := 0; 96632#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 96633#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 96174#L1603-45 assume !(0 != activate_threads_~tmp~1#1); 96175#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 96263#L659-45 assume !(1 == ~t1_pc~0); 96264#L659-47 is_transmit1_triggered_~__retres1~1#1 := 0; 96718#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 98462#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 98320#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 97806#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 97807#L678-45 assume !(1 == ~t2_pc~0); 97751#L678-47 is_transmit2_triggered_~__retres1~2#1 := 0; 97213#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 97214#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 97728#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 98178#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 98356#L697-45 assume 1 == ~t3_pc~0; 97505#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 97506#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 98497#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 97683#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 97684#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 97731#L716-45 assume !(1 == ~t4_pc~0); 97293#L716-47 is_transmit4_triggered_~__retres1~4#1 := 0; 97294#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 98123#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 97298#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 97299#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 96947#L735-45 assume !(1 == ~t5_pc~0); 96949#L735-47 is_transmit5_triggered_~__retres1~5#1 := 0; 97545#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 98401#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 98489#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 98403#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 98393#L754-45 assume 1 == ~t6_pc~0; 97485#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 97486#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 97364#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 97365#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 97490#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 97188#L773-45 assume 1 == ~t7_pc~0; 97189#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 96713#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 97446#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 97447#L1659-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 97196#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 96836#L792-45 assume 1 == ~t8_pc~0; 96837#L793-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 98025#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 98026#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 96284#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 96285#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 96784#L811-45 assume !(1 == ~t9_pc~0); 96560#L811-47 is_transmit9_triggered_~__retres1~9#1 := 0; 96559#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 97898#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 97725#L1675-45 assume !(0 != activate_threads_~tmp___8~0#1); 97269#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 97270#L830-45 assume !(1 == ~t10_pc~0); 101037#L830-47 is_transmit10_triggered_~__retres1~10#1 := 0; 101034#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 101032#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 101031#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 101030#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 101029#L849-45 assume !(1 == ~t11_pc~0); 101027#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 101024#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 101023#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 101022#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 101021#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 101019#L868-45 assume 1 == ~t12_pc~0; 101015#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 101013#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 101011#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 101009#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 101007#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 101005#L887-45 assume 1 == ~t13_pc~0; 101001#L888-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 100998#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 97874#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 97875#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 98543#L1707-47 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 97864#L1439-3 assume !(1 == ~M_E~0); 97865#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 101604#L1444-3 assume !(1 == ~T2_E~0); 101603#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 101602#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 101601#L1459-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 101600#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 101599#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 101598#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 101597#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 101596#L1484-3 assume !(1 == ~T10_E~0); 101595#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 101594#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 101593#L1499-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 101592#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 101591#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 101590#L1514-3 assume !(1 == ~E_2~0); 101589#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 101588#L1524-3 assume !(1 == ~E_4~0); 101587#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 101586#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 101585#L1539-3 assume 1 == ~E_7~0;~E_7~0 := 2; 101584#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 101583#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 101582#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 101581#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 101580#L1564-3 assume !(1 == ~E_12~0); 101579#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 101578#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 100371#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 100362#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 100361#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 100360#L1959 assume !(0 == start_simulation_~tmp~3#1); 100358#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 100347#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 100339#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 100338#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 100337#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 100336#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 100335#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 100334#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 98445#L1940-2 [2024-11-08 00:35:57,075 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:57,075 INFO L85 PathProgramCache]: Analyzing trace with hash -121367293, now seen corresponding path program 1 times [2024-11-08 00:35:57,075 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:57,075 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1089649739] [2024-11-08 00:35:57,075 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:57,075 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:57,088 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:57,147 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:57,147 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:57,147 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1089649739] [2024-11-08 00:35:57,147 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1089649739] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:57,148 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:57,148 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-08 00:35:57,148 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [146949250] [2024-11-08 00:35:57,148 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:57,148 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:35:57,148 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:57,149 INFO L85 PathProgramCache]: Analyzing trace with hash -77619972, now seen corresponding path program 1 times [2024-11-08 00:35:57,149 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:57,149 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1271701231] [2024-11-08 00:35:57,149 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:57,149 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:57,162 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:57,198 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:57,199 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:57,199 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1271701231] [2024-11-08 00:35:57,199 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1271701231] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:57,199 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:57,199 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:57,199 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [532922313] [2024-11-08 00:35:57,199 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:57,200 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:35:57,200 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:35:57,200 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-08 00:35:57,200 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-08 00:35:57,200 INFO L87 Difference]: Start difference. First operand 7187 states and 10410 transitions. cyclomatic complexity: 3225 Second operand has 5 states, 5 states have (on average 32.2) internal successors, (161), 5 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:57,479 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:35:57,479 INFO L93 Difference]: Finished difference Result 7370 states and 10593 transitions. [2024-11-08 00:35:57,479 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7370 states and 10593 transitions. [2024-11-08 00:35:57,508 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 7189 [2024-11-08 00:35:57,530 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7370 states to 7370 states and 10593 transitions. [2024-11-08 00:35:57,530 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7370 [2024-11-08 00:35:57,539 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7370 [2024-11-08 00:35:57,539 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7370 states and 10593 transitions. [2024-11-08 00:35:57,552 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:35:57,552 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7370 states and 10593 transitions. [2024-11-08 00:35:57,561 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7370 states and 10593 transitions. [2024-11-08 00:35:57,647 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7370 to 7370. [2024-11-08 00:35:57,658 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7370 states, 7370 states have (on average 1.4373134328358208) internal successors, (10593), 7369 states have internal predecessors, (10593), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:57,674 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7370 states to 7370 states and 10593 transitions. [2024-11-08 00:35:57,675 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7370 states and 10593 transitions. [2024-11-08 00:35:57,675 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-08 00:35:57,675 INFO L425 stractBuchiCegarLoop]: Abstraction has 7370 states and 10593 transitions. [2024-11-08 00:35:57,675 INFO L332 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2024-11-08 00:35:57,675 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7370 states and 10593 transitions. [2024-11-08 00:35:57,697 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 7189 [2024-11-08 00:35:57,698 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:35:57,698 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:35:57,700 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:57,700 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:57,701 INFO L745 eck$LassoCheckResult]: Stem: 110983#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 110984#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 112007#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 112008#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 112937#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 112145#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 111583#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 111584#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 112459#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 112460#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 112602#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 112603#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 111328#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 111329#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 112645#L959-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 111895#L964-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 111896#L969-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 112520#L974-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 111806#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 111807#L1291 assume !(0 == ~M_E~0); 112940#L1291-2 assume !(0 == ~T1_E~0); 112935#L1296-1 assume !(0 == ~T2_E~0); 111965#L1301-1 assume !(0 == ~T3_E~0); 111966#L1306-1 assume !(0 == ~T4_E~0); 112532#L1311-1 assume !(0 == ~T5_E~0); 111163#L1316-1 assume !(0 == ~T6_E~0); 111164#L1321-1 assume !(0 == ~T7_E~0); 111980#L1326-1 assume !(0 == ~T8_E~0); 110980#L1331-1 assume !(0 == ~T9_E~0); 110693#L1336-1 assume !(0 == ~T10_E~0); 110694#L1341-1 assume !(0 == ~T11_E~0); 110766#L1346-1 assume !(0 == ~T12_E~0); 110767#L1351-1 assume !(0 == ~T13_E~0); 111098#L1356-1 assume !(0 == ~E_M~0); 111099#L1361-1 assume !(0 == ~E_1~0); 112839#L1366-1 assume !(0 == ~E_2~0); 111146#L1371-1 assume !(0 == ~E_3~0); 111147#L1376-1 assume !(0 == ~E_4~0); 112036#L1381-1 assume !(0 == ~E_5~0); 112037#L1386-1 assume !(0 == ~E_6~0); 112887#L1391-1 assume !(0 == ~E_7~0); 112921#L1396-1 assume !(0 == ~E_8~0); 111930#L1401-1 assume !(0 == ~E_9~0); 111931#L1406-1 assume !(0 == ~E_10~0); 112239#L1411-1 assume !(0 == ~E_11~0); 112240#L1416-1 assume !(0 == ~E_12~0); 111846#L1421-1 assume !(0 == ~E_13~0); 111349#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 111350#L640 assume !(1 == ~m_pc~0); 111894#L640-2 is_master_triggered_~__retres1~0#1 := 0; 111893#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 111853#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 111854#L1603 assume !(0 != activate_threads_~tmp~1#1); 111882#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 111503#L659 assume !(1 == ~t1_pc~0); 111504#L659-2 is_transmit1_triggered_~__retres1~1#1 := 0; 112719#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 112373#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 111636#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 111637#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 111653#L678 assume !(1 == ~t2_pc~0); 112750#L678-2 is_transmit2_triggered_~__retres1~2#1 := 0; 112881#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 111190#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 111191#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 111750#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 111875#L697 assume !(1 == ~t3_pc~0); 111876#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 112016#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 112361#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 111785#L1627 assume !(0 != activate_threads_~tmp___2~0#1); 111786#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 112802#L716 assume 1 == ~t4_pc~0; 112783#L717 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 111482#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 110839#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 110840#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 110947#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 112323#L735 assume !(1 == ~t5_pc~0); 110915#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 110916#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 111378#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 112351#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 111958#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 111959#L754 assume 1 == ~t6_pc~0; 111700#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 111597#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 111167#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 111168#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 111570#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 112447#L773 assume !(1 == ~t7_pc~0); 111102#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 111101#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 111998#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 111969#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 111970#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 112027#L792 assume 1 == ~t8_pc~0; 112208#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 112604#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 112605#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 111960#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 111878#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 111879#L811 assume 1 == ~t9_pc~0; 112105#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 112661#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 111247#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 111248#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 111890#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 111891#L830 assume !(1 == ~t10_pc~0); 111606#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 111078#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 111079#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 111057#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 111058#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 112470#L849 assume 1 == ~t11_pc~0; 112471#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 110894#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 110895#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 112486#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 112355#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 112356#L868 assume !(1 == ~t12_pc~0); 111734#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 111733#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 110781#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 110782#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 111113#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 111114#L887 assume 1 == ~t13_pc~0; 112363#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 111779#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 111780#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 112437#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 110822#L1707-2 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 110823#L1439 assume !(1 == ~M_E~0); 111952#L1439-2 assume !(1 == ~T1_E~0); 110993#L1444-1 assume !(1 == ~T2_E~0); 110994#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 111507#L1454-1 assume !(1 == ~T4_E~0); 111508#L1459-1 assume !(1 == ~T5_E~0); 112097#L1464-1 assume !(1 == ~T6_E~0); 112098#L1469-1 assume !(1 == ~T7_E~0); 112176#L1474-1 assume !(1 == ~T8_E~0); 111847#L1479-1 assume !(1 == ~T9_E~0); 111848#L1484-1 assume !(1 == ~T10_E~0); 112101#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 111723#L1494-1 assume !(1 == ~T12_E~0); 111724#L1499-1 assume !(1 == ~T13_E~0); 111913#L1504-1 assume !(1 == ~E_M~0); 111914#L1509-1 assume !(1 == ~E_1~0); 112582#L1514-1 assume !(1 == ~E_2~0); 112210#L1519-1 assume !(1 == ~E_3~0); 112211#L1524-1 assume !(1 == ~E_4~0); 112861#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 112862#L1534-1 assume !(1 == ~E_6~0); 110815#L1539-1 assume !(1 == ~E_7~0); 110816#L1544-1 assume !(1 == ~E_8~0); 111244#L1549-1 assume !(1 == ~E_9~0); 112822#L1554-1 assume !(1 == ~E_10~0); 112820#L1559-1 assume !(1 == ~E_11~0); 112635#L1564-1 assume !(1 == ~E_12~0); 112636#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 112852#L1574-1 assume { :end_inline_reset_delta_events } true; 112894#L1940-2 [2024-11-08 00:35:57,701 INFO L747 eck$LassoCheckResult]: Loop: 112894#L1940-2 assume !false; 114379#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 114377#L1266-1 assume !false; 114376#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 111563#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 111274#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 112597#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 112598#L1079 assume !(0 != eval_~tmp~0#1); 114346#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 114347#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 112301#L1291-3 assume !(0 == ~M_E~0); 112302#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 117743#L1296-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 117742#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 117741#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 117740#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 117739#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 117738#L1321-3 assume !(0 == ~T7_E~0); 117737#L1326-3 assume !(0 == ~T8_E~0); 117735#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 117733#L1336-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 117732#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 117731#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 117730#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 117729#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 117728#L1361-3 assume !(0 == ~E_1~0); 117727#L1366-3 assume !(0 == ~E_2~0); 117726#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 117725#L1376-3 assume 0 == ~E_4~0;~E_4~0 := 1; 117724#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 117723#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 117722#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 117721#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 117720#L1401-3 assume !(0 == ~E_9~0); 117719#L1406-3 assume !(0 == ~E_10~0); 117718#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 117717#L1416-3 assume 0 == ~E_12~0;~E_12~0 := 1; 117716#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 117715#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 117714#L640-45 assume !(1 == ~m_pc~0); 117713#L640-47 is_master_triggered_~__retres1~0#1 := 0; 117711#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 117710#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 110740#L1603-45 assume !(0 != activate_threads_~tmp~1#1); 110741#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 110830#L659-45 assume !(1 == ~t1_pc~0); 110831#L659-47 is_transmit1_triggered_~__retres1~1#1 := 0; 111290#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 112912#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 112807#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 112332#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 112333#L678-45 assume !(1 == ~t2_pc~0); 112283#L678-47 is_transmit2_triggered_~__retres1~2#1 := 0; 111781#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 111782#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 112262#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 112676#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 112832#L697-45 assume 1 == ~t3_pc~0; 112058#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 112059#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 118060#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 118059#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 112224#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 112264#L716-45 assume !(1 == ~t4_pc~0); 111859#L716-47 is_transmit4_triggered_~__retres1~4#1 := 0; 111860#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 112617#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 111864#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 111865#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 111517#L735-45 assume !(1 == ~t5_pc~0); 111519#L735-47 is_transmit5_triggered_~__retres1~5#1 := 0; 112093#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 112855#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 112933#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 112860#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 112850#L754-45 assume 1 == ~t6_pc~0; 112041#L755-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 112042#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 111926#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 111927#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 112046#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 111755#L773-45 assume !(1 == ~t7_pc~0); 111284#L773-47 is_transmit7_triggered_~__retres1~7#1 := 0; 111285#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 112005#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 112006#L1659-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 111763#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 111764#L792-45 assume !(1 == ~t8_pc~0); 112773#L792-47 is_transmit8_triggered_~__retres1~8#1 := 0; 112774#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 112886#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 110851#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 110852#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 117411#L811-45 assume !(1 == ~t9_pc~0); 117408#L811-47 is_transmit9_triggered_~__retres1~9#1 := 0; 117405#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 117401#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 117400#L1675-45 assume !(0 != activate_threads_~tmp___8~0#1); 117341#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 117340#L830-45 assume 1 == ~t10_pc~0; 112663#L831-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 110777#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 111951#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 111002#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 111003#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 110760#L849-45 assume !(1 == ~t11_pc~0); 110761#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 111221#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 111061#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 110746#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 110747#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 110997#L868-45 assume !(1 == ~t12_pc~0); 110999#L868-47 is_transmit12_triggered_~__retres1~12#1 := 0; 110940#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 110941#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 112463#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 112694#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 112695#L887-45 assume 1 == ~t13_pc~0; 112464#L888-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 111005#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 112365#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 112389#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 110971#L1707-47 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 110972#L1439-3 assume !(1 == ~M_E~0); 112380#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 117463#L1444-3 assume !(1 == ~T2_E~0); 111150#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 111151#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 112157#L1459-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 112158#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 117460#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 117459#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 117458#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 117457#L1484-3 assume !(1 == ~T10_E~0); 117456#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 117455#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 117454#L1499-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 112113#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 112114#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 112630#L1514-3 assume !(1 == ~E_2~0); 112677#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 111730#L1524-3 assume !(1 == ~E_4~0); 111731#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 112736#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 112024#L1539-3 assume 1 == ~E_7~0;~E_7~0 := 2; 111459#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 111460#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 111984#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 111035#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 111036#L1564-3 assume !(1 == ~E_12~0); 112265#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 112266#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 110928#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 110702#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 111027#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 111117#L1959 assume !(0 == start_simulation_~tmp~3#1); 110966#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 110967#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 114388#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 114387#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 114386#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 114385#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 114384#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 114380#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 112894#L1940-2 [2024-11-08 00:35:57,702 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:57,702 INFO L85 PathProgramCache]: Analyzing trace with hash -2061949307, now seen corresponding path program 1 times [2024-11-08 00:35:57,702 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:57,702 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [206389488] [2024-11-08 00:35:57,702 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:57,702 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:57,716 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:57,764 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:57,764 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:57,764 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [206389488] [2024-11-08 00:35:57,764 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [206389488] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:57,765 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:57,765 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-08 00:35:57,765 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [540102860] [2024-11-08 00:35:57,765 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:57,765 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:35:57,766 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:57,766 INFO L85 PathProgramCache]: Analyzing trace with hash 323464510, now seen corresponding path program 1 times [2024-11-08 00:35:57,766 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:57,766 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1253586590] [2024-11-08 00:35:57,766 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:57,766 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:57,779 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:57,816 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:57,816 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:57,816 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1253586590] [2024-11-08 00:35:57,816 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1253586590] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:57,816 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:57,816 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:57,816 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [538369790] [2024-11-08 00:35:57,817 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:57,817 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:35:57,817 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:35:57,817 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:35:57,817 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:35:57,818 INFO L87 Difference]: Start difference. First operand 7370 states and 10593 transitions. cyclomatic complexity: 3225 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:57,942 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:35:57,942 INFO L93 Difference]: Finished difference Result 14092 states and 20169 transitions. [2024-11-08 00:35:57,942 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 14092 states and 20169 transitions. [2024-11-08 00:35:58,005 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 13900 [2024-11-08 00:35:58,052 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 14092 states to 14092 states and 20169 transitions. [2024-11-08 00:35:58,052 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14092 [2024-11-08 00:35:58,066 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14092 [2024-11-08 00:35:58,066 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14092 states and 20169 transitions. [2024-11-08 00:35:58,081 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:35:58,081 INFO L218 hiAutomatonCegarLoop]: Abstraction has 14092 states and 20169 transitions. [2024-11-08 00:35:58,094 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14092 states and 20169 transitions. [2024-11-08 00:35:58,293 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14092 to 14084. [2024-11-08 00:35:58,307 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14084 states, 14084 states have (on average 1.4314825333712013) internal successors, (20161), 14083 states have internal predecessors, (20161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:58,330 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14084 states to 14084 states and 20161 transitions. [2024-11-08 00:35:58,330 INFO L240 hiAutomatonCegarLoop]: Abstraction has 14084 states and 20161 transitions. [2024-11-08 00:35:58,331 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:35:58,331 INFO L425 stractBuchiCegarLoop]: Abstraction has 14084 states and 20161 transitions. [2024-11-08 00:35:58,331 INFO L332 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2024-11-08 00:35:58,331 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14084 states and 20161 transitions. [2024-11-08 00:35:58,364 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 13892 [2024-11-08 00:35:58,365 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:35:58,365 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:35:58,366 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:58,366 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:58,367 INFO L745 eck$LassoCheckResult]: Stem: 132456#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 132457#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 133511#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 133512#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 134610#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 133659#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 133067#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 133068#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 133999#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 134000#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 134163#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 134164#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 132802#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 132803#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 134216#L959-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 133392#L964-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 133393#L969-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 134069#L974-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 133301#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 133302#L1291 assume !(0 == ~M_E~0); 134612#L1291-2 assume !(0 == ~T1_E~0); 134606#L1296-1 assume !(0 == ~T2_E~0); 133461#L1301-1 assume !(0 == ~T3_E~0); 133462#L1306-1 assume !(0 == ~T4_E~0); 134087#L1311-1 assume !(0 == ~T5_E~0); 132636#L1316-1 assume !(0 == ~T6_E~0); 132637#L1321-1 assume !(0 == ~T7_E~0); 133481#L1326-1 assume !(0 == ~T8_E~0); 132453#L1331-1 assume !(0 == ~T9_E~0); 132162#L1336-1 assume !(0 == ~T10_E~0); 132163#L1341-1 assume !(0 == ~T11_E~0); 132234#L1346-1 assume !(0 == ~T12_E~0); 132235#L1351-1 assume !(0 == ~T13_E~0); 132569#L1356-1 assume !(0 == ~E_M~0); 132570#L1361-1 assume !(0 == ~E_1~0); 134454#L1366-1 assume !(0 == ~E_2~0); 132619#L1371-1 assume !(0 == ~E_3~0); 132620#L1376-1 assume !(0 == ~E_4~0); 133543#L1381-1 assume !(0 == ~E_5~0); 133544#L1386-1 assume !(0 == ~E_6~0); 134522#L1391-1 assume !(0 == ~E_7~0); 134575#L1396-1 assume !(0 == ~E_8~0); 133428#L1401-1 assume !(0 == ~E_9~0); 133429#L1406-1 assume !(0 == ~E_10~0); 133755#L1411-1 assume !(0 == ~E_11~0); 133756#L1416-1 assume !(0 == ~E_12~0); 133340#L1421-1 assume !(0 == ~E_13~0); 132825#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 132826#L640 assume !(1 == ~m_pc~0); 133391#L640-2 is_master_triggered_~__retres1~0#1 := 0; 133390#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 133348#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 133349#L1603 assume !(0 != activate_threads_~tmp~1#1); 133379#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 132983#L659 assume !(1 == ~t1_pc~0); 132984#L659-2 is_transmit1_triggered_~__retres1~1#1 := 0; 134296#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 133910#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 133120#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 133121#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 133138#L678 assume !(1 == ~t2_pc~0); 134336#L678-2 is_transmit2_triggered_~__retres1~2#1 := 0; 134511#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 132664#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 132665#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 133245#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 133372#L697 assume !(1 == ~t3_pc~0); 133373#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 133521#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 133893#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 133280#L1627 assume !(0 != activate_threads_~tmp___2~0#1); 133281#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 134401#L716 assume !(1 == ~t4_pc~0); 133830#L716-2 is_transmit4_triggered_~__retres1~4#1 := 0; 132961#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 132309#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 132310#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 132419#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 133846#L735 assume !(1 == ~t5_pc~0); 132386#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 132387#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 132853#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 133879#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 133454#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 133455#L754 assume 1 == ~t6_pc~0; 133187#L755 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 133082#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 132640#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 132641#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 133054#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 133989#L773 assume !(1 == ~t7_pc~0); 132573#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 132572#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 133500#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 133465#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 133466#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 133532#L792 assume 1 == ~t8_pc~0; 133724#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 134165#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 134166#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 133456#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 133375#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 133376#L811 assume 1 == ~t9_pc~0; 133615#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 134232#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 132720#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 132721#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 133387#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 133388#L830 assume !(1 == ~t10_pc~0); 133091#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 132549#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 132550#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 132528#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 132529#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 134011#L849 assume 1 == ~t11_pc~0; 134012#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 132364#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 132365#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 134032#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 133889#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 133890#L868 assume !(1 == ~t12_pc~0); 133229#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 133228#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 132249#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 132250#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 132585#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 132586#L887 assume 1 == ~t13_pc~0; 133899#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 133274#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 133275#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 133976#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 132291#L1707-2 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 132292#L1439 assume !(1 == ~M_E~0); 133448#L1439-2 assume !(1 == ~T1_E~0); 132466#L1444-1 assume !(1 == ~T2_E~0); 132467#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 132987#L1454-1 assume !(1 == ~T4_E~0); 132988#L1459-1 assume !(1 == ~T5_E~0); 133605#L1464-1 assume !(1 == ~T6_E~0); 133606#L1469-1 assume !(1 == ~T7_E~0); 133691#L1474-1 assume !(1 == ~T8_E~0); 133341#L1479-1 assume !(1 == ~T9_E~0); 133342#L1484-1 assume !(1 == ~T10_E~0); 133610#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 133215#L1494-1 assume !(1 == ~T12_E~0); 133216#L1499-1 assume !(1 == ~T13_E~0); 133411#L1504-1 assume !(1 == ~E_M~0); 133412#L1509-1 assume !(1 == ~E_1~0); 134140#L1514-1 assume !(1 == ~E_2~0); 133726#L1519-1 assume !(1 == ~E_3~0); 133727#L1524-1 assume !(1 == ~E_4~0); 134485#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 134486#L1534-1 assume !(1 == ~E_6~0); 132284#L1539-1 assume !(1 == ~E_7~0); 132285#L1544-1 assume !(1 == ~E_8~0); 132717#L1549-1 assume !(1 == ~E_9~0); 134434#L1554-1 assume !(1 == ~E_10~0); 134428#L1559-1 assume !(1 == ~E_11~0); 134201#L1564-1 assume !(1 == ~E_12~0); 134202#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 134472#L1574-1 assume { :end_inline_reset_delta_events } true; 134537#L1940-2 [2024-11-08 00:35:58,367 INFO L747 eck$LassoCheckResult]: Loop: 134537#L1940-2 assume !false; 138644#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 134234#L1266-1 assume !false; 138639#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 138640#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 138613#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 138614#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 138608#L1079 assume !(0 != eval_~tmp~0#1); 138610#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 139103#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 139101#L1291-3 assume !(0 == ~M_E~0); 139099#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 139097#L1296-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 139095#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 139093#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 139091#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 139089#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 139087#L1321-3 assume !(0 == ~T7_E~0); 139085#L1326-3 assume !(0 == ~T8_E~0); 139083#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 139081#L1336-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 139079#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 139077#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 139075#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 139073#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 139071#L1361-3 assume !(0 == ~E_1~0); 139069#L1366-3 assume !(0 == ~E_2~0); 139067#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 139065#L1376-3 assume 0 == ~E_4~0;~E_4~0 := 1; 139063#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 139061#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 139059#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 139057#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 139055#L1401-3 assume !(0 == ~E_9~0); 139053#L1406-3 assume !(0 == ~E_10~0); 139051#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 139049#L1416-3 assume 0 == ~E_12~0;~E_12~0 := 1; 139047#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 139045#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 139043#L640-45 assume 1 == ~m_pc~0; 139040#L641-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 139037#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 139035#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 139033#L1603-45 assume !(0 != activate_threads_~tmp~1#1); 139031#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 139029#L659-45 assume !(1 == ~t1_pc~0); 139027#L659-47 is_transmit1_triggered_~__retres1~1#1 := 0; 139025#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 139023#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 139021#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 139019#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 139017#L678-45 assume !(1 == ~t2_pc~0); 139013#L678-47 is_transmit2_triggered_~__retres1~2#1 := 0; 139011#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 139009#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 139007#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 139005#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 139003#L697-45 assume 1 == ~t3_pc~0; 139000#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 138996#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 138992#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 138988#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 138985#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 138983#L716-45 assume !(1 == ~t4_pc~0); 138981#L716-47 is_transmit4_triggered_~__retres1~4#1 := 0; 138979#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 138977#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 138975#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 138973#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 138971#L735-45 assume 1 == ~t5_pc~0; 138968#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 138965#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 138963#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 138961#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 138959#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 138957#L754-45 assume !(1 == ~t6_pc~0); 138954#L754-47 is_transmit6_triggered_~__retres1~6#1 := 0; 138951#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 138949#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 138947#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 138945#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 138943#L773-45 assume 1 == ~t7_pc~0; 138940#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 138937#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 138935#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 138933#L1659-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 138931#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 138929#L792-45 assume !(1 == ~t8_pc~0); 138926#L792-47 is_transmit8_triggered_~__retres1~8#1 := 0; 138923#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 138921#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 138919#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 138917#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 138915#L811-45 assume 1 == ~t9_pc~0; 138912#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 138909#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 138907#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 138905#L1675-45 assume !(0 != activate_threads_~tmp___8~0#1); 138903#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 138901#L830-45 assume 1 == ~t10_pc~0; 138898#L831-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 138895#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 138893#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 138891#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 138889#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 138887#L849-45 assume !(1 == ~t11_pc~0); 138884#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 138881#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 138879#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 138877#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 138875#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 138873#L868-45 assume 1 == ~t12_pc~0; 138870#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 138867#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 138865#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 138863#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 138861#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 138859#L887-45 assume !(1 == ~t13_pc~0); 138856#L887-47 is_transmit13_triggered_~__retres1~13#1 := 0; 138853#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 138851#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 138849#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 138847#L1707-47 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 138845#L1439-3 assume !(1 == ~M_E~0); 138844#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 139509#L1444-3 assume !(1 == ~T2_E~0); 139508#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 139507#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 139506#L1459-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 139505#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 139504#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 139503#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 139502#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 139501#L1484-3 assume !(1 == ~T10_E~0); 139500#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 139499#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 139498#L1499-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 139497#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 139496#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 139495#L1514-3 assume !(1 == ~E_2~0); 139494#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 139493#L1524-3 assume !(1 == ~E_4~0); 139492#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 139491#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 139490#L1539-3 assume 1 == ~E_7~0;~E_7~0 := 2; 139489#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 139488#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 139487#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 139486#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 139485#L1564-3 assume !(1 == ~E_12~0); 139484#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 139483#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 139476#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 139468#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 139467#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 139466#L1959 assume !(0 == start_simulation_~tmp~3#1); 139464#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 138675#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 138668#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 138661#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 138658#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 138655#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 138656#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 138648#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 134537#L1940-2 [2024-11-08 00:35:58,367 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:58,368 INFO L85 PathProgramCache]: Analyzing trace with hash 846336710, now seen corresponding path program 1 times [2024-11-08 00:35:58,368 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:58,368 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1847528729] [2024-11-08 00:35:58,368 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:58,368 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:58,378 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:58,409 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:58,409 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:58,410 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1847528729] [2024-11-08 00:35:58,410 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1847528729] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:58,410 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:58,410 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-08 00:35:58,410 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1497104471] [2024-11-08 00:35:58,410 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:58,410 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:35:58,410 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:58,411 INFO L85 PathProgramCache]: Analyzing trace with hash -1715844229, now seen corresponding path program 1 times [2024-11-08 00:35:58,411 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:58,411 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1581272721] [2024-11-08 00:35:58,411 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:58,411 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:58,420 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:58,447 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:58,447 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:58,447 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1581272721] [2024-11-08 00:35:58,447 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1581272721] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:58,448 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:58,448 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:58,448 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [758673109] [2024-11-08 00:35:58,448 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:58,448 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:35:58,448 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:35:58,448 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:35:58,448 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:35:58,449 INFO L87 Difference]: Start difference. First operand 14084 states and 20161 transitions. cyclomatic complexity: 6081 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:58,580 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:35:58,580 INFO L93 Difference]: Finished difference Result 27059 states and 38586 transitions. [2024-11-08 00:35:58,580 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 27059 states and 38586 transitions. [2024-11-08 00:35:58,679 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 26836 [2024-11-08 00:35:58,755 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 27059 states to 27059 states and 38586 transitions. [2024-11-08 00:35:58,756 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27059 [2024-11-08 00:35:58,778 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 27059 [2024-11-08 00:35:58,778 INFO L73 IsDeterministic]: Start isDeterministic. Operand 27059 states and 38586 transitions. [2024-11-08 00:35:58,802 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:35:58,803 INFO L218 hiAutomatonCegarLoop]: Abstraction has 27059 states and 38586 transitions. [2024-11-08 00:35:58,828 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27059 states and 38586 transitions. [2024-11-08 00:35:59,031 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27059 to 27043. [2024-11-08 00:35:59,063 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 27043 states, 27043 states have (on average 1.4262470879710092) internal successors, (38570), 27042 states have internal predecessors, (38570), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:59,103 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27043 states to 27043 states and 38570 transitions. [2024-11-08 00:35:59,103 INFO L240 hiAutomatonCegarLoop]: Abstraction has 27043 states and 38570 transitions. [2024-11-08 00:35:59,103 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:35:59,104 INFO L425 stractBuchiCegarLoop]: Abstraction has 27043 states and 38570 transitions. [2024-11-08 00:35:59,104 INFO L332 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2024-11-08 00:35:59,104 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 27043 states and 38570 transitions. [2024-11-08 00:35:59,172 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 26820 [2024-11-08 00:35:59,172 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:35:59,172 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:35:59,174 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:59,174 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:59,175 INFO L745 eck$LassoCheckResult]: Stem: 173599#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 173600#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 174616#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 174617#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 175516#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 174753#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 174196#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 174197#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 175069#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 175070#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 175196#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 175197#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 173940#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 173941#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 175235#L959-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 174508#L964-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 174509#L969-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 175131#L974-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 174421#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 174422#L1291 assume !(0 == ~M_E~0); 175517#L1291-2 assume !(0 == ~T1_E~0); 175514#L1296-1 assume !(0 == ~T2_E~0); 174576#L1301-1 assume !(0 == ~T3_E~0); 174577#L1306-1 assume !(0 == ~T4_E~0); 175142#L1311-1 assume !(0 == ~T5_E~0); 173775#L1316-1 assume !(0 == ~T6_E~0); 173776#L1321-1 assume !(0 == ~T7_E~0); 174591#L1326-1 assume !(0 == ~T8_E~0); 173596#L1331-1 assume !(0 == ~T9_E~0); 173312#L1336-1 assume !(0 == ~T10_E~0); 173313#L1341-1 assume !(0 == ~T11_E~0); 173383#L1346-1 assume !(0 == ~T12_E~0); 173384#L1351-1 assume !(0 == ~T13_E~0); 173711#L1356-1 assume !(0 == ~E_M~0); 173712#L1361-1 assume !(0 == ~E_1~0); 175416#L1366-1 assume !(0 == ~E_2~0); 173759#L1371-1 assume !(0 == ~E_3~0); 173760#L1376-1 assume !(0 == ~E_4~0); 174647#L1381-1 assume !(0 == ~E_5~0); 174648#L1386-1 assume !(0 == ~E_6~0); 175466#L1391-1 assume !(0 == ~E_7~0); 175500#L1396-1 assume !(0 == ~E_8~0); 174540#L1401-1 assume !(0 == ~E_9~0); 174541#L1406-1 assume !(0 == ~E_10~0); 174850#L1411-1 assume !(0 == ~E_11~0); 174851#L1416-1 assume !(0 == ~E_12~0); 174458#L1421-1 assume !(0 == ~E_13~0); 173963#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 173964#L640 assume !(1 == ~m_pc~0); 174506#L640-2 is_master_triggered_~__retres1~0#1 := 0; 174505#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 174465#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 174466#L1603 assume !(0 != activate_threads_~tmp~1#1); 174494#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 174117#L659 assume !(1 == ~t1_pc~0); 174118#L659-2 is_transmit1_triggered_~__retres1~1#1 := 0; 175294#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 174984#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 174249#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 174250#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 174266#L678 assume !(1 == ~t2_pc~0); 175327#L678-2 is_transmit2_triggered_~__retres1~2#1 := 0; 175454#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 173801#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 173802#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 174363#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 174487#L697 assume !(1 == ~t3_pc~0); 174488#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 174627#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 175563#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 174398#L1627 assume !(0 != activate_threads_~tmp___2~0#1); 174399#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 175372#L716 assume !(1 == ~t4_pc~0); 174918#L716-2 is_transmit4_triggered_~__retres1~4#1 := 0; 174095#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 173455#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 173456#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 173562#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 174931#L735 assume !(1 == ~t5_pc~0); 173530#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 173531#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 173990#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 174959#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 174568#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 174569#L754 assume !(1 == ~t6_pc~0); 174807#L754-2 is_transmit6_triggered_~__retres1~6#1 := 0; 174212#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 173779#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 173780#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 174180#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 175057#L773 assume !(1 == ~t7_pc~0); 173715#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 173714#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 174607#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 174580#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 174581#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 174639#L792 assume 1 == ~t8_pc~0; 174817#L793 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 175198#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 175199#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 174570#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 174490#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 174491#L811 assume 1 == ~t9_pc~0; 174712#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 175249#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 173858#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 173859#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 174502#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 174503#L830 assume !(1 == ~t10_pc~0); 174221#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 173692#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 173693#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 173671#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 173672#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 175080#L849 assume 1 == ~t11_pc~0; 175081#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 173509#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 173510#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 175100#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 174963#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 174964#L868 assume !(1 == ~t12_pc~0); 174347#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 174346#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 173398#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 173399#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 173727#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 173728#L887 assume 1 == ~t13_pc~0; 174972#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 174392#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 174393#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 175047#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 173438#L1707-2 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 173439#L1439 assume !(1 == ~M_E~0); 174562#L1439-2 assume !(1 == ~T1_E~0); 173609#L1444-1 assume !(1 == ~T2_E~0); 173610#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 174121#L1454-1 assume !(1 == ~T4_E~0); 174122#L1459-1 assume !(1 == ~T5_E~0); 174704#L1464-1 assume !(1 == ~T6_E~0); 174705#L1469-1 assume !(1 == ~T7_E~0); 174785#L1474-1 assume !(1 == ~T8_E~0); 174459#L1479-1 assume !(1 == ~T9_E~0); 174460#L1484-1 assume !(1 == ~T10_E~0); 174708#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 174336#L1494-1 assume !(1 == ~T12_E~0); 174337#L1499-1 assume !(1 == ~T13_E~0); 174525#L1504-1 assume !(1 == ~E_M~0); 174526#L1509-1 assume !(1 == ~E_1~0); 175180#L1514-1 assume !(1 == ~E_2~0); 174819#L1519-1 assume !(1 == ~E_3~0); 174820#L1524-1 assume !(1 == ~E_4~0); 175435#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 175436#L1534-1 assume !(1 == ~E_6~0); 173432#L1539-1 assume !(1 == ~E_7~0); 173433#L1544-1 assume !(1 == ~E_8~0); 173855#L1549-1 assume !(1 == ~E_9~0); 175399#L1554-1 assume !(1 == ~E_10~0); 175395#L1559-1 assume !(1 == ~E_11~0); 175226#L1564-1 assume !(1 == ~E_12~0); 175227#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 175427#L1574-1 assume { :end_inline_reset_delta_events } true; 175474#L1940-2 [2024-11-08 00:35:59,175 INFO L747 eck$LassoCheckResult]: Loop: 175474#L1940-2 assume !false; 190055#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 190051#L1266-1 assume !false; 190050#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 190041#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 190032#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 190030#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 190028#L1079 assume !(0 != eval_~tmp~0#1); 190025#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 190023#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 190021#L1291-3 assume !(0 == ~M_E~0); 190019#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 190017#L1296-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 190015#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 190012#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 190010#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 190008#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 190006#L1321-3 assume !(0 == ~T7_E~0); 190004#L1326-3 assume !(0 == ~T8_E~0); 190002#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 189999#L1336-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 189997#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 189995#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 189993#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 189991#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 189989#L1361-3 assume !(0 == ~E_1~0); 189986#L1366-3 assume !(0 == ~E_2~0); 189984#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 189982#L1376-3 assume 0 == ~E_4~0;~E_4~0 := 1; 189980#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 189978#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 189976#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 189973#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 189971#L1401-3 assume !(0 == ~E_9~0); 189969#L1406-3 assume !(0 == ~E_10~0); 189967#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 189965#L1416-3 assume 0 == ~E_12~0;~E_12~0 := 1; 189963#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 189960#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 189958#L640-45 assume 1 == ~m_pc~0; 189955#L641-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 189953#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 189951#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 189949#L1603-45 assume !(0 != activate_threads_~tmp~1#1); 189946#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 189944#L659-45 assume !(1 == ~t1_pc~0); 189942#L659-47 is_transmit1_triggered_~__retres1~1#1 := 0; 189940#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 189938#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 189937#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 189936#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 189935#L678-45 assume !(1 == ~t2_pc~0); 189933#L678-47 is_transmit2_triggered_~__retres1~2#1 := 0; 189932#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 189931#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 189930#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 189929#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 189928#L697-45 assume !(1 == ~t3_pc~0); 189926#L697-47 is_transmit3_triggered_~__retres1~3#1 := 0; 189924#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 189922#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 189921#L1627-45 assume !(0 != activate_threads_~tmp___2~0#1); 189919#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 189918#L716-45 assume !(1 == ~t4_pc~0); 189917#L716-47 is_transmit4_triggered_~__retres1~4#1 := 0; 189916#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 189915#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 189914#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 189913#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 189912#L735-45 assume 1 == ~t5_pc~0; 189910#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 189909#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 189908#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 189907#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 189906#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 189904#L754-45 assume !(1 == ~t6_pc~0); 189902#L754-47 is_transmit6_triggered_~__retres1~6#1 := 0; 189900#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 189898#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 189895#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 189893#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 189891#L773-45 assume 1 == ~t7_pc~0; 189888#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 189886#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 189884#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 189882#L1659-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 189880#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 189878#L792-45 assume !(1 == ~t8_pc~0); 189875#L792-47 is_transmit8_triggered_~__retres1~8#1 := 0; 189873#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 189871#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 189868#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 189866#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 189864#L811-45 assume !(1 == ~t9_pc~0); 189862#L811-47 is_transmit9_triggered_~__retres1~9#1 := 0; 189859#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 189857#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 189854#L1675-45 assume !(0 != activate_threads_~tmp___8~0#1); 189852#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 189850#L830-45 assume 1 == ~t10_pc~0; 189847#L831-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 189845#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 189843#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 189840#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 189838#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 189836#L849-45 assume 1 == ~t11_pc~0; 189834#L850-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 189831#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 189829#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 189826#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 189824#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 189822#L868-45 assume 1 == ~t12_pc~0; 189819#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 189817#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 189815#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 189812#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 189810#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 189808#L887-45 assume 1 == ~t13_pc~0; 189806#L888-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 189803#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 189801#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 189798#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 189796#L1707-47 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 189794#L1439-3 assume !(1 == ~M_E~0); 184823#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 189791#L1444-3 assume !(1 == ~T2_E~0); 189789#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 189786#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 189784#L1459-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 189782#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 189780#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 189778#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 189775#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 189773#L1484-3 assume !(1 == ~T10_E~0); 189771#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 189769#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 189767#L1499-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 189765#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 189763#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 189761#L1514-3 assume !(1 == ~E_2~0); 189759#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 189757#L1524-3 assume !(1 == ~E_4~0); 189755#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 189753#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 189751#L1539-3 assume 1 == ~E_7~0;~E_7~0 := 2; 189749#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 189747#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 189745#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 189743#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 186311#L1564-3 assume !(1 == ~E_12~0); 186309#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 186308#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 186117#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 186106#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 186102#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 181339#L1959 assume !(0 == start_simulation_~tmp~3#1); 181340#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 190082#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 190073#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 190071#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 190070#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 190067#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 190063#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 190059#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 175474#L1940-2 [2024-11-08 00:35:59,175 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:59,176 INFO L85 PathProgramCache]: Analyzing trace with hash -995977081, now seen corresponding path program 1 times [2024-11-08 00:35:59,176 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:59,176 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [848322419] [2024-11-08 00:35:59,176 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:59,176 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:59,186 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:59,357 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:59,358 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:59,358 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [848322419] [2024-11-08 00:35:59,358 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [848322419] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:59,358 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:59,358 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-08 00:35:59,358 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1563866792] [2024-11-08 00:35:59,358 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:59,358 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:35:59,359 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:59,359 INFO L85 PathProgramCache]: Analyzing trace with hash -1408724739, now seen corresponding path program 1 times [2024-11-08 00:35:59,359 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:59,359 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1726333419] [2024-11-08 00:35:59,359 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:59,359 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:59,368 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:59,394 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:59,394 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:59,394 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1726333419] [2024-11-08 00:35:59,394 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1726333419] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:59,394 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:59,394 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:59,394 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [197833989] [2024-11-08 00:35:59,394 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:59,395 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:35:59,395 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:35:59,395 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:35:59,395 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:35:59,395 INFO L87 Difference]: Start difference. First operand 27043 states and 38570 transitions. cyclomatic complexity: 11535 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:59,585 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:35:59,585 INFO L93 Difference]: Finished difference Result 52062 states and 73987 transitions. [2024-11-08 00:35:59,585 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 52062 states and 73987 transitions. [2024-11-08 00:35:59,792 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 51760 [2024-11-08 00:35:59,951 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 52062 states to 52062 states and 73987 transitions. [2024-11-08 00:35:59,951 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 52062 [2024-11-08 00:35:59,988 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 52062 [2024-11-08 00:35:59,989 INFO L73 IsDeterministic]: Start isDeterministic. Operand 52062 states and 73987 transitions. [2024-11-08 00:36:00,027 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:36:00,027 INFO L218 hiAutomatonCegarLoop]: Abstraction has 52062 states and 73987 transitions. [2024-11-08 00:36:00,069 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 52062 states and 73987 transitions. [2024-11-08 00:36:00,964 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 52062 to 52030. [2024-11-08 00:36:01,018 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 52030 states, 52030 states have (on average 1.4213915049010186) internal successors, (73955), 52029 states have internal predecessors, (73955), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:36:01,115 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 52030 states to 52030 states and 73955 transitions. [2024-11-08 00:36:01,116 INFO L240 hiAutomatonCegarLoop]: Abstraction has 52030 states and 73955 transitions. [2024-11-08 00:36:01,116 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:36:01,116 INFO L425 stractBuchiCegarLoop]: Abstraction has 52030 states and 73955 transitions. [2024-11-08 00:36:01,116 INFO L332 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2024-11-08 00:36:01,117 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 52030 states and 73955 transitions. [2024-11-08 00:36:01,421 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 51728 [2024-11-08 00:36:01,421 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:36:01,421 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:36:01,423 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:36:01,423 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:36:01,424 INFO L745 eck$LassoCheckResult]: Stem: 252711#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 252712#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 253724#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 253725#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 254587#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 253857#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 253309#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 253310#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 254162#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 254163#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 254291#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 254292#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 253056#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 253057#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 254327#L959-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 253618#L964-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 253619#L969-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 254219#L974-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 253531#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 253532#L1291 assume !(0 == ~M_E~0); 254588#L1291-2 assume !(0 == ~T1_E~0); 254584#L1296-1 assume !(0 == ~T2_E~0); 253684#L1301-1 assume !(0 == ~T3_E~0); 253685#L1306-1 assume !(0 == ~T4_E~0); 254232#L1311-1 assume !(0 == ~T5_E~0); 252890#L1316-1 assume !(0 == ~T6_E~0); 252891#L1321-1 assume !(0 == ~T7_E~0); 253699#L1326-1 assume !(0 == ~T8_E~0); 252708#L1331-1 assume !(0 == ~T9_E~0); 252424#L1336-1 assume !(0 == ~T10_E~0); 252425#L1341-1 assume !(0 == ~T11_E~0); 252495#L1346-1 assume !(0 == ~T12_E~0); 252496#L1351-1 assume !(0 == ~T13_E~0); 252825#L1356-1 assume !(0 == ~E_M~0); 252826#L1361-1 assume !(0 == ~E_1~0); 254506#L1366-1 assume !(0 == ~E_2~0); 252874#L1371-1 assume !(0 == ~E_3~0); 252875#L1376-1 assume !(0 == ~E_4~0); 253752#L1381-1 assume !(0 == ~E_5~0); 253753#L1386-1 assume !(0 == ~E_6~0); 254544#L1391-1 assume !(0 == ~E_7~0); 254570#L1396-1 assume !(0 == ~E_8~0); 253650#L1401-1 assume !(0 == ~E_9~0); 253651#L1406-1 assume !(0 == ~E_10~0); 253953#L1411-1 assume !(0 == ~E_11~0); 253954#L1416-1 assume !(0 == ~E_12~0); 253568#L1421-1 assume !(0 == ~E_13~0); 253076#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 253077#L640 assume !(1 == ~m_pc~0); 253617#L640-2 is_master_triggered_~__retres1~0#1 := 0; 253616#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 253576#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 253577#L1603 assume !(0 != activate_threads_~tmp~1#1); 253604#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 253232#L659 assume !(1 == ~t1_pc~0); 253233#L659-2 is_transmit1_triggered_~__retres1~1#1 := 0; 254382#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 254084#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 253362#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 253363#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 253380#L678 assume !(1 == ~t2_pc~0); 254405#L678-2 is_transmit2_triggered_~__retres1~2#1 := 0; 254540#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 252918#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 252919#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 253477#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 253597#L697 assume !(1 == ~t3_pc~0); 253598#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 253733#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 254631#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 253511#L1627 assume !(0 != activate_threads_~tmp___2~0#1); 253512#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 254457#L716 assume !(1 == ~t4_pc~0); 254018#L716-2 is_transmit4_triggered_~__retres1~4#1 := 0; 253210#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 252568#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 252569#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 252675#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 254032#L735 assume !(1 == ~t5_pc~0); 252643#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 252644#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 253105#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 254060#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 253677#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 253678#L754 assume !(1 == ~t6_pc~0); 253914#L754-2 is_transmit6_triggered_~__retres1~6#1 := 0; 253324#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 252894#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 252895#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 253296#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 254153#L773 assume !(1 == ~t7_pc~0); 252829#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 252828#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 253714#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 253688#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 253689#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 253744#L792 assume !(1 == ~t8_pc~0); 253924#L792-2 is_transmit8_triggered_~__retres1~8#1 := 0; 254293#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 254294#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 253679#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 253600#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 253601#L811 assume 1 == ~t9_pc~0; 253818#L812 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 254342#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 252974#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 252975#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 253613#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 253614#L830 assume !(1 == ~t10_pc~0); 253333#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 252804#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 252805#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 252782#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 252783#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 254172#L849 assume 1 == ~t11_pc~0; 254173#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 252622#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 252623#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 254190#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 254064#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 254065#L868 assume !(1 == ~t12_pc~0); 253461#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 253460#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 252510#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 252511#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 252841#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 252842#L887 assume 1 == ~t13_pc~0; 254075#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 253505#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 253506#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 254144#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 252550#L1707-2 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 252551#L1439 assume !(1 == ~M_E~0); 253671#L1439-2 assume !(1 == ~T1_E~0); 252721#L1444-1 assume !(1 == ~T2_E~0); 252722#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 253236#L1454-1 assume !(1 == ~T4_E~0); 253237#L1459-1 assume !(1 == ~T5_E~0); 253810#L1464-1 assume !(1 == ~T6_E~0); 253811#L1469-1 assume !(1 == ~T7_E~0); 253890#L1474-1 assume !(1 == ~T8_E~0); 253569#L1479-1 assume !(1 == ~T9_E~0); 253570#L1484-1 assume !(1 == ~T10_E~0); 253814#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 253449#L1494-1 assume !(1 == ~T12_E~0); 253450#L1499-1 assume !(1 == ~T13_E~0); 253635#L1504-1 assume !(1 == ~E_M~0); 253636#L1509-1 assume !(1 == ~E_1~0); 254272#L1514-1 assume !(1 == ~E_2~0); 253925#L1519-1 assume !(1 == ~E_3~0); 253926#L1524-1 assume !(1 == ~E_4~0); 254525#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 254526#L1534-1 assume !(1 == ~E_6~0); 252544#L1539-1 assume !(1 == ~E_7~0); 252545#L1544-1 assume !(1 == ~E_8~0); 252971#L1549-1 assume !(1 == ~E_9~0); 254484#L1554-1 assume !(1 == ~E_10~0); 254480#L1559-1 assume !(1 == ~E_11~0); 254319#L1564-1 assume !(1 == ~E_12~0); 254320#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 254519#L1574-1 assume { :end_inline_reset_delta_events } true; 254552#L1940-2 [2024-11-08 00:36:01,424 INFO L747 eck$LassoCheckResult]: Loop: 254552#L1940-2 assume !false; 279422#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 279410#L1266-1 assume !false; 279362#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 279104#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 279088#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 279080#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 279070#L1079 assume !(0 != eval_~tmp~0#1); 279071#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 281761#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 281754#L1291-3 assume !(0 == ~M_E~0); 281748#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 281741#L1296-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 281734#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 281727#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 281720#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 281713#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 281707#L1321-3 assume !(0 == ~T7_E~0); 281701#L1326-3 assume !(0 == ~T8_E~0); 281695#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 281687#L1336-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 281681#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 281675#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 281670#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 281664#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 281659#L1361-3 assume !(0 == ~E_1~0); 281653#L1366-3 assume !(0 == ~E_2~0); 281646#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 281639#L1376-3 assume 0 == ~E_4~0;~E_4~0 := 1; 281633#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 281627#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 281621#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 281613#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 281607#L1401-3 assume !(0 == ~E_9~0); 281600#L1406-3 assume !(0 == ~E_10~0); 281594#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 281587#L1416-3 assume 0 == ~E_12~0;~E_12~0 := 1; 281580#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 281569#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 281562#L640-45 assume 1 == ~m_pc~0; 281553#L641-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 281546#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 281539#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 281532#L1603-45 assume !(0 != activate_threads_~tmp~1#1); 281523#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 281515#L659-45 assume !(1 == ~t1_pc~0); 281506#L659-47 is_transmit1_triggered_~__retres1~1#1 := 0; 281498#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 281489#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 281483#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 281475#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 281468#L678-45 assume !(1 == ~t2_pc~0); 281461#L678-47 is_transmit2_triggered_~__retres1~2#1 := 0; 281455#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 281448#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 281443#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 281436#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 281431#L697-45 assume 1 == ~t3_pc~0; 281425#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 281419#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 281412#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 281402#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 279961#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 279958#L716-45 assume !(1 == ~t4_pc~0); 279956#L716-47 is_transmit4_triggered_~__retres1~4#1 := 0; 279954#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 279952#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 279950#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 279948#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 279946#L735-45 assume 1 == ~t5_pc~0; 279943#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 279941#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 279939#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 279937#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 279935#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 279932#L754-45 assume !(1 == ~t6_pc~0); 279930#L754-47 is_transmit6_triggered_~__retres1~6#1 := 0; 279928#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 279926#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 279924#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 279922#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 279920#L773-45 assume 1 == ~t7_pc~0; 279916#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 279914#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 279912#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 279910#L1659-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 279907#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 279905#L792-45 assume !(1 == ~t8_pc~0); 279903#L792-47 is_transmit8_triggered_~__retres1~8#1 := 0; 279901#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 279899#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 279897#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 279894#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 279892#L811-45 assume 1 == ~t9_pc~0; 279889#L812-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 279887#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 279885#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 279883#L1675-45 assume !(0 != activate_threads_~tmp___8~0#1); 279880#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 279878#L830-45 assume !(1 == ~t10_pc~0); 279876#L830-47 is_transmit10_triggered_~__retres1~10#1 := 0; 279873#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 279871#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 279869#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 279866#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 279864#L849-45 assume !(1 == ~t11_pc~0); 279861#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 279859#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 279857#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 279855#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 279852#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 279850#L868-45 assume 1 == ~t12_pc~0; 279847#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 279845#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 279843#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 279842#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 279841#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 279840#L887-45 assume !(1 == ~t13_pc~0); 279837#L887-47 is_transmit13_triggered_~__retres1~13#1 := 0; 279835#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 279833#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 279831#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 279829#L1707-47 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 279827#L1439-3 assume !(1 == ~M_E~0); 279823#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 279821#L1444-3 assume !(1 == ~T2_E~0); 279819#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 279817#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 279815#L1459-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 279813#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 279811#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 279809#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 279807#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 279805#L1484-3 assume !(1 == ~T10_E~0); 279803#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 279801#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 279799#L1499-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 279797#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 279795#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 279793#L1514-3 assume !(1 == ~E_2~0); 279791#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 279789#L1524-3 assume !(1 == ~E_4~0); 279787#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 279785#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 279783#L1539-3 assume 1 == ~E_7~0;~E_7~0 := 2; 279781#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 279779#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 279777#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 279775#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 279772#L1564-3 assume !(1 == ~E_12~0); 279770#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 279768#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 279728#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 279719#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 279717#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 279715#L1959 assume !(0 == start_simulation_~tmp~3#1); 279713#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 279482#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 279473#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 279471#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 279469#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 279467#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 279464#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 279462#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 254552#L1940-2 [2024-11-08 00:36:01,425 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:36:01,425 INFO L85 PathProgramCache]: Analyzing trace with hash -618334264, now seen corresponding path program 1 times [2024-11-08 00:36:01,425 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:36:01,425 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1064398519] [2024-11-08 00:36:01,425 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:36:01,425 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:36:01,435 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:36:01,465 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:36:01,466 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:36:01,466 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1064398519] [2024-11-08 00:36:01,466 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1064398519] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:36:01,466 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:36:01,466 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-08 00:36:01,466 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2057548308] [2024-11-08 00:36:01,466 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:36:01,467 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:36:01,467 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:36:01,467 INFO L85 PathProgramCache]: Analyzing trace with hash -1338201412, now seen corresponding path program 1 times [2024-11-08 00:36:01,467 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:36:01,467 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [204134327] [2024-11-08 00:36:01,467 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:36:01,467 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:36:01,478 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:36:01,581 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:36:01,581 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:36:01,581 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [204134327] [2024-11-08 00:36:01,582 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [204134327] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:36:01,582 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:36:01,582 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:36:01,582 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [595600278] [2024-11-08 00:36:01,582 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:36:01,582 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:36:01,582 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:36:01,582 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:36:01,582 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:36:01,582 INFO L87 Difference]: Start difference. First operand 52030 states and 73955 transitions. cyclomatic complexity: 21941 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:36:02,068 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:36:02,068 INFO L93 Difference]: Finished difference Result 100221 states and 141968 transitions. [2024-11-08 00:36:02,068 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 100221 states and 141968 transitions. [2024-11-08 00:36:02,641 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 99728 [2024-11-08 00:36:02,885 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 100221 states to 100221 states and 141968 transitions. [2024-11-08 00:36:02,885 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 100221 [2024-11-08 00:36:02,944 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 100221 [2024-11-08 00:36:02,945 INFO L73 IsDeterministic]: Start isDeterministic. Operand 100221 states and 141968 transitions. [2024-11-08 00:36:03,027 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:36:03,027 INFO L218 hiAutomatonCegarLoop]: Abstraction has 100221 states and 141968 transitions. [2024-11-08 00:36:03,093 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 100221 states and 141968 transitions. [2024-11-08 00:36:03,914 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 100221 to 100157. [2024-11-08 00:36:04,009 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 100157 states, 100157 states have (on average 1.4168155995087712) internal successors, (141904), 100156 states have internal predecessors, (141904), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:36:04,341 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 100157 states to 100157 states and 141904 transitions. [2024-11-08 00:36:04,342 INFO L240 hiAutomatonCegarLoop]: Abstraction has 100157 states and 141904 transitions. [2024-11-08 00:36:04,342 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:36:04,342 INFO L425 stractBuchiCegarLoop]: Abstraction has 100157 states and 141904 transitions. [2024-11-08 00:36:04,342 INFO L332 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2024-11-08 00:36:04,342 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 100157 states and 141904 transitions. [2024-11-08 00:36:04,583 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 99664 [2024-11-08 00:36:04,584 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:36:04,584 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:36:04,585 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:36:04,585 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:36:04,586 INFO L745 eck$LassoCheckResult]: Stem: 404971#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 404972#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 405994#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 405995#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 406933#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 406128#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 405573#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 405574#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 406454#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 406455#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 406586#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 406587#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 405313#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 405314#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 406623#L959-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 405886#L964-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 405887#L969-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 406515#L974-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 405798#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 405799#L1291 assume !(0 == ~M_E~0); 406934#L1291-2 assume !(0 == ~T1_E~0); 406931#L1296-1 assume !(0 == ~T2_E~0); 405952#L1301-1 assume !(0 == ~T3_E~0); 405953#L1306-1 assume !(0 == ~T4_E~0); 406529#L1311-1 assume !(0 == ~T5_E~0); 405146#L1316-1 assume !(0 == ~T6_E~0); 405147#L1321-1 assume !(0 == ~T7_E~0); 405966#L1326-1 assume !(0 == ~T8_E~0); 404968#L1331-1 assume !(0 == ~T9_E~0); 404682#L1336-1 assume !(0 == ~T10_E~0); 404683#L1341-1 assume !(0 == ~T11_E~0); 404754#L1346-1 assume !(0 == ~T12_E~0); 404755#L1351-1 assume !(0 == ~T13_E~0); 405084#L1356-1 assume !(0 == ~E_M~0); 405085#L1361-1 assume !(0 == ~E_1~0); 406824#L1366-1 assume !(0 == ~E_2~0); 405130#L1371-1 assume !(0 == ~E_3~0); 405131#L1376-1 assume !(0 == ~E_4~0); 406022#L1381-1 assume !(0 == ~E_5~0); 406023#L1386-1 assume !(0 == ~E_6~0); 406875#L1391-1 assume !(0 == ~E_7~0); 406911#L1396-1 assume !(0 == ~E_8~0); 405918#L1401-1 assume !(0 == ~E_9~0); 405919#L1406-1 assume !(0 == ~E_10~0); 406222#L1411-1 assume !(0 == ~E_11~0); 406223#L1416-1 assume !(0 == ~E_12~0); 405835#L1421-1 assume !(0 == ~E_13~0); 405334#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 405335#L640 assume !(1 == ~m_pc~0); 405885#L640-2 is_master_triggered_~__retres1~0#1 := 0; 405884#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 405843#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 405844#L1603 assume !(0 != activate_threads_~tmp~1#1); 405872#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 405496#L659 assume !(1 == ~t1_pc~0); 405497#L659-2 is_transmit1_triggered_~__retres1~1#1 := 0; 406692#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 406366#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 405628#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 405629#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 405646#L678 assume !(1 == ~t2_pc~0); 406720#L678-2 is_transmit2_triggered_~__retres1~2#1 := 0; 406864#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 405173#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 405174#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 405743#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 405865#L697 assume !(1 == ~t3_pc~0); 405866#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 406003#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 406989#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 405778#L1627 assume !(0 != activate_threads_~tmp___2~0#1); 405779#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 406774#L716 assume !(1 == ~t4_pc~0); 406296#L716-2 is_transmit4_triggered_~__retres1~4#1 := 0; 405473#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 404827#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 404828#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 404934#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 406310#L735 assume !(1 == ~t5_pc~0); 404902#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 404903#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 405365#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 406343#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 405945#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 405946#L754 assume !(1 == ~t6_pc~0); 406183#L754-2 is_transmit6_triggered_~__retres1~6#1 := 0; 405587#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 405150#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 405151#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 405560#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 406438#L773 assume !(1 == ~t7_pc~0); 405088#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 405087#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 405984#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 405956#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 405957#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 406014#L792 assume !(1 == ~t8_pc~0); 406193#L792-2 is_transmit8_triggered_~__retres1~8#1 := 0; 406588#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 406589#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 405947#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 405868#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 405869#L811 assume !(1 == ~t9_pc~0); 406087#L811-2 is_transmit9_triggered_~__retres1~9#1 := 0; 406674#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 405229#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 405230#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 405881#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 405882#L830 assume !(1 == ~t10_pc~0); 405597#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 405064#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 405065#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 405041#L1683 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 405042#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 406465#L849 assume 1 == ~t11_pc~0; 406466#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 404881#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 404882#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 406482#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 406347#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 406348#L868 assume !(1 == ~t12_pc~0); 405727#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 405726#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 404769#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 404770#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 405099#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 405100#L887 assume 1 == ~t13_pc~0; 406356#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 405772#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 405773#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 406427#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 404809#L1707-2 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 404810#L1439 assume !(1 == ~M_E~0); 405939#L1439-2 assume !(1 == ~T1_E~0); 404981#L1444-1 assume !(1 == ~T2_E~0); 404982#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 405500#L1454-1 assume !(1 == ~T4_E~0); 405501#L1459-1 assume !(1 == ~T5_E~0); 406079#L1464-1 assume !(1 == ~T6_E~0); 406080#L1469-1 assume !(1 == ~T7_E~0); 406161#L1474-1 assume !(1 == ~T8_E~0); 405836#L1479-1 assume !(1 == ~T9_E~0); 405837#L1484-1 assume !(1 == ~T10_E~0); 406083#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 405715#L1494-1 assume !(1 == ~T12_E~0); 405716#L1499-1 assume !(1 == ~T13_E~0); 405903#L1504-1 assume !(1 == ~E_M~0); 405904#L1509-1 assume !(1 == ~E_1~0); 406568#L1514-1 assume !(1 == ~E_2~0); 406194#L1519-1 assume !(1 == ~E_3~0); 406195#L1524-1 assume !(1 == ~E_4~0); 406849#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 406850#L1534-1 assume !(1 == ~E_6~0); 404803#L1539-1 assume !(1 == ~E_7~0); 404804#L1544-1 assume !(1 == ~E_8~0); 405226#L1549-1 assume !(1 == ~E_9~0); 406801#L1554-1 assume !(1 == ~E_10~0); 406798#L1559-1 assume !(1 == ~E_11~0); 406614#L1564-1 assume !(1 == ~E_12~0); 406615#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 406838#L1574-1 assume { :end_inline_reset_delta_events } true; 406885#L1940-2 [2024-11-08 00:36:04,586 INFO L747 eck$LassoCheckResult]: Loop: 406885#L1940-2 assume !false; 414839#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 414831#L1266-1 assume !false; 414827#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 414647#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 414632#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 414623#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 414614#L1079 assume !(0 != eval_~tmp~0#1); 414615#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 417983#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 417981#L1291-3 assume !(0 == ~M_E~0); 417979#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 417977#L1296-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 417975#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 417972#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 417970#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 417968#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 417966#L1321-3 assume !(0 == ~T7_E~0); 417964#L1326-3 assume !(0 == ~T8_E~0); 417962#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 417960#L1336-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 417958#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 417956#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 417954#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 417952#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 417950#L1361-3 assume !(0 == ~E_1~0); 417948#L1366-3 assume !(0 == ~E_2~0); 417926#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 417916#L1376-3 assume 0 == ~E_4~0;~E_4~0 := 1; 417905#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 417895#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 417757#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 417699#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 417684#L1401-3 assume !(0 == ~E_9~0); 417673#L1406-3 assume !(0 == ~E_10~0); 417664#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 417660#L1416-3 assume 0 == ~E_12~0;~E_12~0 := 1; 417657#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 416461#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 416392#L640-45 assume 1 == ~m_pc~0; 416384#L641-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 416376#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 416368#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 416360#L1603-45 assume !(0 != activate_threads_~tmp~1#1); 416353#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 416346#L659-45 assume !(1 == ~t1_pc~0); 416339#L659-47 is_transmit1_triggered_~__retres1~1#1 := 0; 416332#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 416325#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 416319#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 416314#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 416163#L678-45 assume !(1 == ~t2_pc~0); 416160#L678-47 is_transmit2_triggered_~__retres1~2#1 := 0; 416158#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 416156#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 416154#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 416152#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 416149#L697-45 assume 1 == ~t3_pc~0; 416147#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 416148#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 416169#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 416138#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 416136#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 416133#L716-45 assume !(1 == ~t4_pc~0); 416131#L716-47 is_transmit4_triggered_~__retres1~4#1 := 0; 416129#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 416127#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 416125#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 416123#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 416122#L735-45 assume 1 == ~t5_pc~0; 416119#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 416117#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 416115#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 416113#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 416111#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 416109#L754-45 assume !(1 == ~t6_pc~0); 416107#L754-47 is_transmit6_triggered_~__retres1~6#1 := 0; 416105#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 416103#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 416101#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 416099#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 416097#L773-45 assume 1 == ~t7_pc~0; 416094#L774-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 416092#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 416090#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 416088#L1659-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 416086#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 416084#L792-45 assume !(1 == ~t8_pc~0); 416082#L792-47 is_transmit8_triggered_~__retres1~8#1 := 0; 416080#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 416078#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 416076#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 416074#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 416072#L811-45 assume !(1 == ~t9_pc~0); 416070#L811-47 is_transmit9_triggered_~__retres1~9#1 := 0; 416068#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 416066#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 416064#L1675-45 assume !(0 != activate_threads_~tmp___8~0#1); 416062#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 416060#L830-45 assume 1 == ~t10_pc~0; 416012#L831-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 416004#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 415997#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 415987#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 415965#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 415962#L849-45 assume !(1 == ~t11_pc~0); 415959#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 415957#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 415955#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 415953#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 415951#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 415949#L868-45 assume 1 == ~t12_pc~0; 415946#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 415944#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 415943#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 415940#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 415938#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 415936#L887-45 assume 1 == ~t13_pc~0; 415934#L888-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 415931#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 415929#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 415927#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 415896#L1707-47 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 415888#L1439-3 assume !(1 == ~M_E~0); 415878#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 415871#L1444-3 assume !(1 == ~T2_E~0); 415862#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 415853#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 415846#L1459-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 415838#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 415831#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 415823#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 415814#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 415807#L1484-3 assume !(1 == ~T10_E~0); 415800#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 415793#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 415785#L1499-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 415776#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 415767#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 415760#L1514-3 assume !(1 == ~E_2~0); 415755#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 415750#L1524-3 assume !(1 == ~E_4~0); 415743#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 415738#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 415733#L1539-3 assume 1 == ~E_7~0;~E_7~0 := 2; 415726#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 415719#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 415712#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 415705#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 415699#L1564-3 assume !(1 == ~E_12~0); 415695#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 415690#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 415512#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 415498#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 415491#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 415486#L1959 assume !(0 == start_simulation_~tmp~3#1); 415483#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 414934#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 414925#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 414922#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 414920#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 414919#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 414871#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 414859#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 406885#L1940-2 [2024-11-08 00:36:04,587 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:36:04,587 INFO L85 PathProgramCache]: Analyzing trace with hash -1649665079, now seen corresponding path program 1 times [2024-11-08 00:36:04,587 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:36:04,587 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1402899373] [2024-11-08 00:36:04,587 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:36:04,587 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:36:04,598 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:36:04,792 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:36:04,792 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:36:04,793 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1402899373] [2024-11-08 00:36:04,793 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1402899373] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:36:04,793 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:36:04,793 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-08 00:36:04,793 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1356695752] [2024-11-08 00:36:04,793 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:36:04,793 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:36:04,794 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:36:04,794 INFO L85 PathProgramCache]: Analyzing trace with hash -1777723269, now seen corresponding path program 1 times [2024-11-08 00:36:04,794 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:36:04,794 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [386720383] [2024-11-08 00:36:04,794 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:36:04,794 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:36:04,805 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:36:04,837 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:36:04,837 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:36:04,837 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [386720383] [2024-11-08 00:36:04,837 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [386720383] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:36:04,837 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:36:04,837 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:36:04,837 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [332432496] [2024-11-08 00:36:04,838 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:36:04,838 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:36:04,838 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:36:04,838 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-08 00:36:04,838 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-08 00:36:04,838 INFO L87 Difference]: Start difference. First operand 100157 states and 141904 transitions. cyclomatic complexity: 41779 Second operand has 5 states, 5 states have (on average 32.2) internal successors, (161), 5 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:36:05,398 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:36:05,399 INFO L93 Difference]: Finished difference Result 102656 states and 144403 transitions. [2024-11-08 00:36:05,400 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 102656 states and 144403 transitions. [2024-11-08 00:36:05,850 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 102160 [2024-11-08 00:36:06,650 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 102656 states to 102656 states and 144403 transitions. [2024-11-08 00:36:06,651 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 102656 [2024-11-08 00:36:06,702 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 102656 [2024-11-08 00:36:06,702 INFO L73 IsDeterministic]: Start isDeterministic. Operand 102656 states and 144403 transitions. [2024-11-08 00:36:06,750 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:36:06,750 INFO L218 hiAutomatonCegarLoop]: Abstraction has 102656 states and 144403 transitions. [2024-11-08 00:36:06,814 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 102656 states and 144403 transitions. [2024-11-08 00:36:07,653 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 102656 to 102656. [2024-11-08 00:36:07,742 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 102656 states, 102656 states have (on average 1.4066688746882794) internal successors, (144403), 102655 states have internal predecessors, (144403), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:36:07,898 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 102656 states to 102656 states and 144403 transitions. [2024-11-08 00:36:07,898 INFO L240 hiAutomatonCegarLoop]: Abstraction has 102656 states and 144403 transitions. [2024-11-08 00:36:07,898 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-08 00:36:07,899 INFO L425 stractBuchiCegarLoop]: Abstraction has 102656 states and 144403 transitions. [2024-11-08 00:36:07,899 INFO L332 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2024-11-08 00:36:07,899 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 102656 states and 144403 transitions. [2024-11-08 00:36:08,161 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 102160 [2024-11-08 00:36:08,161 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:36:08,161 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:36:08,163 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:36:08,163 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:36:08,163 INFO L745 eck$LassoCheckResult]: Stem: 607793#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 607794#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 608814#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 608815#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 609709#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 608947#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 608395#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 608396#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 609266#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 609267#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 609394#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 609395#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 608137#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 608138#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 609431#L959-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 608706#L964-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 608707#L969-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 609322#L974-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 608620#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 608621#L1291 assume !(0 == ~M_E~0); 609710#L1291-2 assume !(0 == ~T1_E~0); 609706#L1296-1 assume !(0 == ~T2_E~0); 608771#L1301-1 assume !(0 == ~T3_E~0); 608772#L1306-1 assume !(0 == ~T4_E~0); 609336#L1311-1 assume !(0 == ~T5_E~0); 607968#L1316-1 assume !(0 == ~T6_E~0); 607969#L1321-1 assume !(0 == ~T7_E~0); 608785#L1326-1 assume !(0 == ~T8_E~0); 607790#L1331-1 assume !(0 == ~T9_E~0); 607504#L1336-1 assume !(0 == ~T10_E~0); 607505#L1341-1 assume !(0 == ~T11_E~0); 607575#L1346-1 assume !(0 == ~T12_E~0); 607576#L1351-1 assume !(0 == ~T13_E~0); 607904#L1356-1 assume !(0 == ~E_M~0); 607905#L1361-1 assume !(0 == ~E_1~0); 609616#L1366-1 assume !(0 == ~E_2~0); 607952#L1371-1 assume !(0 == ~E_3~0); 607953#L1376-1 assume !(0 == ~E_4~0); 608842#L1381-1 assume !(0 == ~E_5~0); 608843#L1386-1 assume !(0 == ~E_6~0); 609657#L1391-1 assume !(0 == ~E_7~0); 609691#L1396-1 assume !(0 == ~E_8~0); 608738#L1401-1 assume !(0 == ~E_9~0); 608739#L1406-1 assume !(0 == ~E_10~0); 609043#L1411-1 assume !(0 == ~E_11~0); 609044#L1416-1 assume !(0 == ~E_12~0); 608657#L1421-1 assume !(0 == ~E_13~0); 608161#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 608162#L640 assume !(1 == ~m_pc~0); 608705#L640-2 is_master_triggered_~__retres1~0#1 := 0; 608704#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 608665#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 608666#L1603 assume !(0 != activate_threads_~tmp~1#1); 608693#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 608315#L659 assume !(1 == ~t1_pc~0); 608316#L659-2 is_transmit1_triggered_~__retres1~1#1 := 0; 609496#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 609183#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 608449#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 608450#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 608467#L678 assume !(1 == ~t2_pc~0); 609522#L678-2 is_transmit2_triggered_~__retres1~2#1 := 0; 609652#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 607996#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 607997#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 608565#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 608688#L697 assume !(1 == ~t3_pc~0); 608689#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 608822#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 609750#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 608599#L1627 assume !(0 != activate_threads_~tmp___2~0#1); 608600#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 609565#L716 assume !(1 == ~t4_pc~0); 609111#L716-2 is_transmit4_triggered_~__retres1~4#1 := 0; 608294#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 607650#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 607651#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 607756#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 609126#L735 assume !(1 == ~t5_pc~0); 607724#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 607725#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 608187#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 609157#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 608764#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 608765#L754 assume !(1 == ~t6_pc~0); 609003#L754-2 is_transmit6_triggered_~__retres1~6#1 := 0; 608409#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 607972#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 607973#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 608380#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 609257#L773 assume !(1 == ~t7_pc~0); 607908#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 607907#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 608803#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 608775#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 608776#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 608834#L792 assume !(1 == ~t8_pc~0); 609014#L792-2 is_transmit8_triggered_~__retres1~8#1 := 0; 609396#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 609397#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 608768#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 608691#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 608692#L811 assume !(1 == ~t9_pc~0); 608908#L811-2 is_transmit9_triggered_~__retres1~9#1 := 0; 609479#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 608052#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 608053#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 608701#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 608702#L830 assume !(1 == ~t10_pc~0); 608420#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 609745#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 609452#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 607862#L1683 assume !(0 != activate_threads_~tmp___9~0#1); 607863#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 609276#L849 assume 1 == ~t11_pc~0; 609277#L850 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 607703#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 607704#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 609292#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 609164#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 609165#L868 assume !(1 == ~t12_pc~0); 608549#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 608548#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 607590#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 607591#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 607920#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 607921#L887 assume 1 == ~t13_pc~0; 609172#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 608593#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 608594#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 609248#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 607630#L1707-2 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 607631#L1439 assume !(1 == ~M_E~0); 608760#L1439-2 assume !(1 == ~T1_E~0); 607803#L1444-1 assume !(1 == ~T2_E~0); 607804#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 608320#L1454-1 assume !(1 == ~T4_E~0); 608321#L1459-1 assume !(1 == ~T5_E~0); 608900#L1464-1 assume !(1 == ~T6_E~0); 608901#L1469-1 assume !(1 == ~T7_E~0); 608983#L1474-1 assume !(1 == ~T8_E~0); 608658#L1479-1 assume !(1 == ~T9_E~0); 608659#L1484-1 assume !(1 == ~T10_E~0); 608903#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 608540#L1494-1 assume !(1 == ~T12_E~0); 608541#L1499-1 assume !(1 == ~T13_E~0); 608723#L1504-1 assume !(1 == ~E_M~0); 608724#L1509-1 assume !(1 == ~E_1~0); 609374#L1514-1 assume !(1 == ~E_2~0); 609015#L1519-1 assume !(1 == ~E_3~0); 609016#L1524-1 assume !(1 == ~E_4~0); 609636#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 609637#L1534-1 assume !(1 == ~E_6~0); 607624#L1539-1 assume !(1 == ~E_7~0); 607625#L1544-1 assume !(1 == ~E_8~0); 608051#L1549-1 assume !(1 == ~E_9~0); 609604#L1554-1 assume !(1 == ~E_10~0); 609597#L1559-1 assume !(1 == ~E_11~0); 609423#L1564-1 assume !(1 == ~E_12~0); 609424#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 609628#L1574-1 assume { :end_inline_reset_delta_events } true; 609666#L1940-2 [2024-11-08 00:36:08,163 INFO L747 eck$LassoCheckResult]: Loop: 609666#L1940-2 assume !false; 614911#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 614906#L1266-1 assume !false; 614904#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 614884#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 614875#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 614873#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 614871#L1079 assume !(0 != eval_~tmp~0#1); 614867#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 614865#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 614863#L1291-3 assume !(0 == ~M_E~0); 614862#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 614859#L1296-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 614856#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 614852#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 614848#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 614844#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 614840#L1321-3 assume !(0 == ~T7_E~0); 614836#L1326-3 assume !(0 == ~T8_E~0); 614832#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 614828#L1336-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 614827#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 614826#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 614825#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 614824#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 614823#L1361-3 assume !(0 == ~E_1~0); 614822#L1366-3 assume !(0 == ~E_2~0); 614821#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 614819#L1376-3 assume 0 == ~E_4~0;~E_4~0 := 1; 614818#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 614817#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 614816#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 614815#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 614813#L1401-3 assume !(0 == ~E_9~0); 614812#L1406-3 assume !(0 == ~E_10~0); 614811#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 614810#L1416-3 assume 0 == ~E_12~0;~E_12~0 := 1; 614809#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 614808#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 614807#L640-45 assume 1 == ~m_pc~0; 614805#L641-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 614803#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 614802#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 614801#L1603-45 assume !(0 != activate_threads_~tmp~1#1); 614800#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 614799#L659-45 assume !(1 == ~t1_pc~0); 614798#L659-47 is_transmit1_triggered_~__retres1~1#1 := 0; 614796#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 614795#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 614794#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 614793#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 614792#L678-45 assume !(1 == ~t2_pc~0); 614790#L678-47 is_transmit2_triggered_~__retres1~2#1 := 0; 614788#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 614785#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 614783#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 614781#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 614779#L697-45 assume 1 == ~t3_pc~0; 614777#L698-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 614778#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 614797#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 614768#L1627-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 614766#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 614764#L716-45 assume !(1 == ~t4_pc~0); 614762#L716-47 is_transmit4_triggered_~__retres1~4#1 := 0; 614759#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 614757#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 614755#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 614753#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 614751#L735-45 assume !(1 == ~t5_pc~0); 614749#L735-47 is_transmit5_triggered_~__retres1~5#1 := 0; 614744#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 614742#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 614740#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 614738#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 614735#L754-45 assume !(1 == ~t6_pc~0); 614733#L754-47 is_transmit6_triggered_~__retres1~6#1 := 0; 614731#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 614729#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 614727#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 614725#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 614723#L773-45 assume !(1 == ~t7_pc~0); 614721#L773-47 is_transmit7_triggered_~__retres1~7#1 := 0; 614718#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 614715#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 614713#L1659-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 614711#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 614709#L792-45 assume !(1 == ~t8_pc~0); 614707#L792-47 is_transmit8_triggered_~__retres1~8#1 := 0; 614705#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 614703#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 614701#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 614699#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 614697#L811-45 assume !(1 == ~t9_pc~0); 614695#L811-47 is_transmit9_triggered_~__retres1~9#1 := 0; 614693#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 614690#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 614688#L1675-45 assume !(0 != activate_threads_~tmp___8~0#1); 614686#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 614684#L830-45 assume !(1 == ~t10_pc~0); 614680#L830-47 is_transmit10_triggered_~__retres1~10#1 := 0; 614678#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 614676#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 614674#L1683-45 assume !(0 != activate_threads_~tmp___9~0#1); 614671#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 614669#L849-45 assume 1 == ~t11_pc~0; 614667#L850-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 614664#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 614662#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 614660#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 614658#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 614656#L868-45 assume 1 == ~t12_pc~0; 614653#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 614652#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 614648#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 614646#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 614644#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 614642#L887-45 assume 1 == ~t13_pc~0; 614639#L888-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 614636#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 614634#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 614631#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 614629#L1707-47 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 614627#L1439-3 assume !(1 == ~M_E~0); 614280#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 614624#L1444-3 assume !(1 == ~T2_E~0); 614622#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 614619#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 614617#L1459-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 614615#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 614613#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 614611#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 614609#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 614606#L1484-3 assume !(1 == ~T10_E~0); 614604#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 614602#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 614600#L1499-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 614598#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 614597#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 614593#L1514-3 assume !(1 == ~E_2~0); 614591#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 614589#L1524-3 assume !(1 == ~E_4~0); 614588#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 614585#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 614581#L1539-3 assume 1 == ~E_7~0;~E_7~0 := 2; 614577#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 614573#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 614572#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 614571#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 614570#L1564-3 assume !(1 == ~E_12~0); 614569#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 614568#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 614561#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 614553#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 614552#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 614549#L1959 assume !(0 == start_simulation_~tmp~3#1); 614550#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 614935#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 614926#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 614924#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 614922#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 614919#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 614917#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 614915#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 609666#L1940-2 [2024-11-08 00:36:08,164 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:36:08,164 INFO L85 PathProgramCache]: Analyzing trace with hash -1665183797, now seen corresponding path program 1 times [2024-11-08 00:36:08,164 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:36:08,164 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1993318057] [2024-11-08 00:36:08,164 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:36:08,164 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:36:08,173 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:36:08,209 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:36:08,209 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:36:08,210 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1993318057] [2024-11-08 00:36:08,210 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1993318057] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:36:08,210 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:36:08,210 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:36:08,210 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1788602201] [2024-11-08 00:36:08,210 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:36:08,210 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:36:08,210 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:36:08,211 INFO L85 PathProgramCache]: Analyzing trace with hash 65600831, now seen corresponding path program 1 times [2024-11-08 00:36:08,211 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:36:08,211 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2122598647] [2024-11-08 00:36:08,211 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:36:08,211 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:36:08,219 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:36:08,515 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:36:08,515 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:36:08,515 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2122598647] [2024-11-08 00:36:08,515 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2122598647] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:36:08,515 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:36:08,515 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:36:08,515 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [686966672] [2024-11-08 00:36:08,515 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:36:08,516 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:36:08,516 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:36:08,516 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-08 00:36:08,516 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-08 00:36:08,516 INFO L87 Difference]: Start difference. First operand 102656 states and 144403 transitions. cyclomatic complexity: 41779 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:36:09,747 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:36:09,747 INFO L93 Difference]: Finished difference Result 284539 states and 397897 transitions. [2024-11-08 00:36:09,748 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 284539 states and 397897 transitions. [2024-11-08 00:36:11,061 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 282896 [2024-11-08 00:36:12,034 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 284539 states to 284539 states and 397897 transitions. [2024-11-08 00:36:12,035 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 284539 [2024-11-08 00:36:12,172 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 284539 [2024-11-08 00:36:12,173 INFO L73 IsDeterministic]: Start isDeterministic. Operand 284539 states and 397897 transitions. [2024-11-08 00:36:12,307 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:36:12,307 INFO L218 hiAutomatonCegarLoop]: Abstraction has 284539 states and 397897 transitions. [2024-11-08 00:36:12,468 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 284539 states and 397897 transitions. [2024-11-08 00:36:14,202 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 284539 to 282747. [2024-11-08 00:36:14,440 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 282747 states, 282747 states have (on average 1.3991059144747777) internal successors, (395593), 282746 states have internal predecessors, (395593), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:36:15,460 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 282747 states to 282747 states and 395593 transitions. [2024-11-08 00:36:15,460 INFO L240 hiAutomatonCegarLoop]: Abstraction has 282747 states and 395593 transitions. [2024-11-08 00:36:15,461 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-08 00:36:15,461 INFO L425 stractBuchiCegarLoop]: Abstraction has 282747 states and 395593 transitions. [2024-11-08 00:36:15,461 INFO L332 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2024-11-08 00:36:15,461 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 282747 states and 395593 transitions. [2024-11-08 00:36:16,313 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 281488 [2024-11-08 00:36:16,313 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:36:16,314 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:36:16,315 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:36:16,315 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:36:16,316 INFO L745 eck$LassoCheckResult]: Stem: 994997#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 994998#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 996020#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 996021#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 996924#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 996158#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 995590#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 995591#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 996476#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 996477#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 996607#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 996608#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 995338#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 995339#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 996644#L959-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 995911#L964-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 995912#L969-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 996535#L974-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 995820#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 995821#L1291 assume !(0 == ~M_E~0); 996925#L1291-2 assume !(0 == ~T1_E~0); 996922#L1296-1 assume !(0 == ~T2_E~0); 995977#L1301-1 assume !(0 == ~T3_E~0); 995978#L1306-1 assume !(0 == ~T4_E~0); 996545#L1311-1 assume !(0 == ~T5_E~0); 995173#L1316-1 assume !(0 == ~T6_E~0); 995174#L1321-1 assume !(0 == ~T7_E~0); 995992#L1326-1 assume !(0 == ~T8_E~0); 994994#L1331-1 assume !(0 == ~T9_E~0); 994709#L1336-1 assume !(0 == ~T10_E~0); 994710#L1341-1 assume !(0 == ~T11_E~0); 994781#L1346-1 assume !(0 == ~T12_E~0); 994782#L1351-1 assume !(0 == ~T13_E~0); 995110#L1356-1 assume !(0 == ~E_M~0); 995111#L1361-1 assume !(0 == ~E_1~0); 996815#L1366-1 assume !(0 == ~E_2~0); 995157#L1371-1 assume !(0 == ~E_3~0); 995158#L1376-1 assume !(0 == ~E_4~0); 996050#L1381-1 assume !(0 == ~E_5~0); 996051#L1386-1 assume !(0 == ~E_6~0); 996863#L1391-1 assume !(0 == ~E_7~0); 996903#L1396-1 assume !(0 == ~E_8~0); 995943#L1401-1 assume !(0 == ~E_9~0); 995944#L1406-1 assume !(0 == ~E_10~0); 996254#L1411-1 assume !(0 == ~E_11~0); 996255#L1416-1 assume !(0 == ~E_12~0); 995860#L1421-1 assume !(0 == ~E_13~0); 995359#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 995360#L640 assume !(1 == ~m_pc~0); 995910#L640-2 is_master_triggered_~__retres1~0#1 := 0; 995909#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 995868#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 995869#L1603 assume !(0 != activate_threads_~tmp~1#1); 995898#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 995510#L659 assume !(1 == ~t1_pc~0); 995511#L659-2 is_transmit1_triggered_~__retres1~1#1 := 0; 996707#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 996399#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 995642#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 995643#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 995660#L678 assume !(1 == ~t2_pc~0); 996729#L678-2 is_transmit2_triggered_~__retres1~2#1 := 0; 996857#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 995202#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 995203#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 995761#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 995892#L697 assume !(1 == ~t3_pc~0); 995893#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 996031#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 996383#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 995799#L1627 assume !(0 != activate_threads_~tmp___2~0#1); 995800#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 996772#L716 assume !(1 == ~t4_pc~0); 996328#L716-2 is_transmit4_triggered_~__retres1~4#1 := 0; 995489#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 994855#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 994856#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 994962#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 996342#L735 assume !(1 == ~t5_pc~0); 994931#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 994932#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 995386#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 996372#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 995969#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 995970#L754 assume !(1 == ~t6_pc~0); 996211#L754-2 is_transmit6_triggered_~__retres1~6#1 := 0; 995603#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 995177#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 995178#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 995577#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 996465#L773 assume !(1 == ~t7_pc~0); 995114#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 995113#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 996008#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 995981#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 995982#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 996042#L792 assume !(1 == ~t8_pc~0); 996222#L792-2 is_transmit8_triggered_~__retres1~8#1 := 0; 996609#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 996610#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 995971#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 995894#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 995895#L811 assume !(1 == ~t9_pc~0); 996119#L811-2 is_transmit9_triggered_~__retres1~9#1 := 0; 996690#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 995257#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 995258#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 995906#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 995907#L830 assume !(1 == ~t10_pc~0); 995613#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 995090#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 995091#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 995068#L1683 assume !(0 != activate_threads_~tmp___9~0#1); 995069#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 996488#L849 assume !(1 == ~t11_pc~0); 996489#L849-2 is_transmit11_triggered_~__retres1~11#1 := 0; 994910#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 994911#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 996503#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 996377#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 996378#L868 assume !(1 == ~t12_pc~0); 995745#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 995744#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 994796#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 994797#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 995125#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 995126#L887 assume 1 == ~t13_pc~0; 996385#L888 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 995793#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 995794#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 996458#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 994837#L1707-2 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 994838#L1439 assume !(1 == ~M_E~0); 995963#L1439-2 assume !(1 == ~T1_E~0); 995007#L1444-1 assume !(1 == ~T2_E~0); 995008#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 995514#L1454-1 assume !(1 == ~T4_E~0); 995515#L1459-1 assume !(1 == ~T5_E~0); 996112#L1464-1 assume !(1 == ~T6_E~0); 996113#L1469-1 assume !(1 == ~T7_E~0); 996189#L1474-1 assume !(1 == ~T8_E~0); 995861#L1479-1 assume !(1 == ~T9_E~0); 995862#L1484-1 assume !(1 == ~T10_E~0); 996116#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 995734#L1494-1 assume !(1 == ~T12_E~0); 995735#L1499-1 assume !(1 == ~T13_E~0); 995928#L1504-1 assume !(1 == ~E_M~0); 995929#L1509-1 assume !(1 == ~E_1~0); 996591#L1514-1 assume !(1 == ~E_2~0); 996223#L1519-1 assume !(1 == ~E_3~0); 996224#L1524-1 assume !(1 == ~E_4~0); 996837#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 996838#L1534-1 assume !(1 == ~E_6~0); 994831#L1539-1 assume !(1 == ~E_7~0); 994832#L1544-1 assume !(1 == ~E_8~0); 995254#L1549-1 assume !(1 == ~E_9~0); 996799#L1554-1 assume !(1 == ~E_10~0); 996793#L1559-1 assume !(1 == ~E_11~0); 996635#L1564-1 assume !(1 == ~E_12~0); 996636#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 996830#L1574-1 assume { :end_inline_reset_delta_events } true; 996878#L1940-2 [2024-11-08 00:36:16,316 INFO L747 eck$LassoCheckResult]: Loop: 996878#L1940-2 assume !false; 1100871#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1100867#L1266-1 assume !false; 1100866#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1100859#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1100851#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1100850#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1100848#L1079 assume !(0 != eval_~tmp~0#1); 1100847#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1100846#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1100845#L1291-3 assume !(0 == ~M_E~0); 1100844#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1100843#L1296-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1100842#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1100841#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1100840#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1100839#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1100838#L1321-3 assume !(0 == ~T7_E~0); 1100837#L1326-3 assume !(0 == ~T8_E~0); 1100836#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1100835#L1336-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 1100834#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1100833#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 1100832#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 1100831#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1100830#L1361-3 assume !(0 == ~E_1~0); 1100829#L1366-3 assume !(0 == ~E_2~0); 1100828#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1100827#L1376-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1100826#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1100825#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1100824#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1100823#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1100822#L1401-3 assume !(0 == ~E_9~0); 1100821#L1406-3 assume !(0 == ~E_10~0); 1100820#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1100819#L1416-3 assume 0 == ~E_12~0;~E_12~0 := 1; 1100818#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 1100817#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1100816#L640-45 assume 1 == ~m_pc~0; 1100814#L641-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1100813#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1100812#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1100811#L1603-45 assume !(0 != activate_threads_~tmp~1#1); 1100810#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1100809#L659-45 assume !(1 == ~t1_pc~0); 1100808#L659-47 is_transmit1_triggered_~__retres1~1#1 := 0; 1100806#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1100803#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1100800#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1100796#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1100793#L678-45 assume !(1 == ~t2_pc~0); 1100789#L678-47 is_transmit2_triggered_~__retres1~2#1 := 0; 1100786#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1100782#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1100779#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1100776#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1100773#L697-45 assume !(1 == ~t3_pc~0); 1100770#L697-47 is_transmit3_triggered_~__retres1~3#1 := 0; 1100766#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1100763#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1100759#L1627-45 assume !(0 != activate_threads_~tmp___2~0#1); 1100756#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1100753#L716-45 assume !(1 == ~t4_pc~0); 1100750#L716-47 is_transmit4_triggered_~__retres1~4#1 := 0; 1100747#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1100744#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1100741#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1100738#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1100735#L735-45 assume 1 == ~t5_pc~0; 1100731#L736-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1100728#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1100725#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1100722#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1100719#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1100716#L754-45 assume !(1 == ~t6_pc~0); 1100713#L754-47 is_transmit6_triggered_~__retres1~6#1 := 0; 1100710#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1100706#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1100702#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1100696#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1100692#L773-45 assume !(1 == ~t7_pc~0); 1100688#L773-47 is_transmit7_triggered_~__retres1~7#1 := 0; 1100683#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1100679#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1100675#L1659-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1100671#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1100667#L792-45 assume !(1 == ~t8_pc~0); 1100663#L792-47 is_transmit8_triggered_~__retres1~8#1 := 0; 1100659#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1100654#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1100649#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1100644#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1100640#L811-45 assume !(1 == ~t9_pc~0); 1100636#L811-47 is_transmit9_triggered_~__retres1~9#1 := 0; 1100632#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1100628#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1100624#L1675-45 assume !(0 != activate_threads_~tmp___8~0#1); 1100620#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1100616#L830-45 assume 1 == ~t10_pc~0; 1100611#L831-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1100606#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1100601#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1100595#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1100590#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1100585#L849-45 assume !(1 == ~t11_pc~0); 1100580#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 1100575#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1100569#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1100563#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1100555#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1100548#L868-45 assume 1 == ~t12_pc~0; 1100541#L869-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 1100535#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1100530#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1100525#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1100520#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1100515#L887-45 assume !(1 == ~t13_pc~0); 1100509#L887-47 is_transmit13_triggered_~__retres1~13#1 := 0; 1100504#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1100498#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 1100493#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 1100486#L1707-47 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1100481#L1439-3 assume !(1 == ~M_E~0); 1097768#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1100472#L1444-3 assume !(1 == ~T2_E~0); 1100466#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1100461#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1100455#L1459-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1100450#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1100445#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1100438#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1100433#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1100413#L1484-3 assume !(1 == ~T10_E~0); 1100408#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1100404#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1100399#L1499-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 1100394#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1100391#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1100388#L1514-3 assume !(1 == ~E_2~0); 1100383#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1100378#L1524-3 assume !(1 == ~E_4~0); 1100372#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1100367#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1100363#L1539-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1100359#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1100354#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1100350#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1100346#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1100343#L1564-3 assume !(1 == ~E_12~0); 1100339#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 1100333#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1097944#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1097935#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1097933#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 1097930#L1959 assume !(0 == start_simulation_~tmp~3#1); 1097931#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1100944#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1100928#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1100917#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 1100909#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1100899#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1100889#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 1100883#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 996878#L1940-2 [2024-11-08 00:36:16,317 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:36:16,317 INFO L85 PathProgramCache]: Analyzing trace with hash 736341324, now seen corresponding path program 1 times [2024-11-08 00:36:16,317 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:36:16,317 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1156488053] [2024-11-08 00:36:16,317 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:36:16,317 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:36:16,331 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:36:16,828 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:36:16,828 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:36:16,828 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1156488053] [2024-11-08 00:36:16,828 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1156488053] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:36:16,828 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:36:16,828 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-08 00:36:16,829 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1580784620] [2024-11-08 00:36:16,829 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:36:16,829 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:36:16,829 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:36:16,829 INFO L85 PathProgramCache]: Analyzing trace with hash -1438678144, now seen corresponding path program 1 times [2024-11-08 00:36:16,830 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:36:16,830 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [615947411] [2024-11-08 00:36:16,830 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:36:16,830 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:36:16,839 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:36:16,859 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:36:16,860 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:36:16,860 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [615947411] [2024-11-08 00:36:16,860 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [615947411] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:36:16,860 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:36:16,860 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:36:16,860 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1324804607] [2024-11-08 00:36:16,860 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:36:16,861 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:36:16,861 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:36:16,861 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:36:16,861 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:36:16,861 INFO L87 Difference]: Start difference. First operand 282747 states and 395593 transitions. cyclomatic complexity: 112910 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:36:18,873 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:36:18,873 INFO L93 Difference]: Finished difference Result 543530 states and 758262 transitions. [2024-11-08 00:36:18,873 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 543530 states and 758262 transitions. [2024-11-08 00:36:21,826 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 540800 [2024-11-08 00:36:23,858 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 543530 states to 543530 states and 758262 transitions. [2024-11-08 00:36:23,859 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 543530 [2024-11-08 00:36:24,218 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 543530 [2024-11-08 00:36:24,218 INFO L73 IsDeterministic]: Start isDeterministic. Operand 543530 states and 758262 transitions. [2024-11-08 00:36:24,555 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:36:24,555 INFO L218 hiAutomatonCegarLoop]: Abstraction has 543530 states and 758262 transitions. [2024-11-08 00:36:25,275 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 543530 states and 758262 transitions. [2024-11-08 00:36:29,671 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 543530 to 543146. [2024-11-08 00:36:30,241 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 543146 states, 543146 states have (on average 1.3953485803080572) internal successors, (757878), 543145 states have internal predecessors, (757878), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:36:32,820 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 543146 states to 543146 states and 757878 transitions. [2024-11-08 00:36:32,821 INFO L240 hiAutomatonCegarLoop]: Abstraction has 543146 states and 757878 transitions. [2024-11-08 00:36:32,821 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:36:32,821 INFO L425 stractBuchiCegarLoop]: Abstraction has 543146 states and 757878 transitions. [2024-11-08 00:36:32,821 INFO L332 stractBuchiCegarLoop]: ======== Iteration 27 ============ [2024-11-08 00:36:32,823 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 543146 states and 757878 transitions. [2024-11-08 00:36:34,031 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 540416 [2024-11-08 00:36:34,031 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:36:34,031 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:36:34,032 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:36:34,032 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:36:34,033 INFO L745 eck$LassoCheckResult]: Stem: 1821281#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 1821282#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 1822322#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1822323#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1823268#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 1822462#L914-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1821889#L919-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1821890#L924-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1822781#L929-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1822782#L934-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1822913#L939-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1822914#L944-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1821621#L949-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1821622#L954-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1822951#L959-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1822212#L964-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1822213#L969-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 1822847#L974-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 1822122#L979-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1822123#L1291 assume !(0 == ~M_E~0); 1823269#L1291-2 assume !(0 == ~T1_E~0); 1823265#L1296-1 assume !(0 == ~T2_E~0); 1822278#L1301-1 assume !(0 == ~T3_E~0); 1822279#L1306-1 assume !(0 == ~T4_E~0); 1822856#L1311-1 assume !(0 == ~T5_E~0); 1821457#L1316-1 assume !(0 == ~T6_E~0); 1821458#L1321-1 assume !(0 == ~T7_E~0); 1822293#L1326-1 assume !(0 == ~T8_E~0); 1821278#L1331-1 assume !(0 == ~T9_E~0); 1820993#L1336-1 assume !(0 == ~T10_E~0); 1820994#L1341-1 assume !(0 == ~T11_E~0); 1821065#L1346-1 assume !(0 == ~T12_E~0); 1821066#L1351-1 assume !(0 == ~T13_E~0); 1821392#L1356-1 assume !(0 == ~E_M~0); 1821393#L1361-1 assume !(0 == ~E_1~0); 1823151#L1366-1 assume !(0 == ~E_2~0); 1821441#L1371-1 assume !(0 == ~E_3~0); 1821442#L1376-1 assume !(0 == ~E_4~0); 1822353#L1381-1 assume !(0 == ~E_5~0); 1822354#L1386-1 assume !(0 == ~E_6~0); 1823208#L1391-1 assume !(0 == ~E_7~0); 1823245#L1396-1 assume !(0 == ~E_8~0); 1822245#L1401-1 assume !(0 == ~E_9~0); 1822246#L1406-1 assume !(0 == ~E_10~0); 1822558#L1411-1 assume !(0 == ~E_11~0); 1822559#L1416-1 assume !(0 == ~E_12~0); 1822161#L1421-1 assume !(0 == ~E_13~0); 1821643#L1426-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1821644#L640 assume !(1 == ~m_pc~0); 1822211#L640-2 is_master_triggered_~__retres1~0#1 := 0; 1822210#L651 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1822169#is_master_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1822170#L1603 assume !(0 != activate_threads_~tmp~1#1); 1822198#L1603-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1821806#L659 assume !(1 == ~t1_pc~0); 1821807#L659-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1823020#L670 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1822704#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1821942#L1611 assume !(0 != activate_threads_~tmp___0~0#1); 1821943#L1611-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1821960#L678 assume !(1 == ~t2_pc~0); 1823050#L678-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1823199#L689 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1821484#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1821485#L1619 assume !(0 != activate_threads_~tmp___1~0#1); 1822065#L1619-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1822192#L697 assume !(1 == ~t3_pc~0); 1822193#L697-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1822333#L708 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1822690#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1822102#L1627 assume !(0 != activate_threads_~tmp___2~0#1); 1822103#L1627-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1823104#L716 assume !(1 == ~t4_pc~0); 1822630#L716-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1821783#L727 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1821138#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1821139#L1635 assume !(0 != activate_threads_~tmp___3~0#1); 1821246#L1635-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1822645#L735 assume !(1 == ~t5_pc~0); 1821214#L735-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1821215#L746 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1821674#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1822678#L1643 assume !(0 != activate_threads_~tmp___4~0#1); 1822271#L1643-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1822272#L754 assume !(1 == ~t6_pc~0); 1822517#L754-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1821903#L765 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1821461#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1821462#L1651 assume !(0 != activate_threads_~tmp___5~0#1); 1821876#L1651-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1822770#L773 assume !(1 == ~t7_pc~0); 1821396#L773-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1821395#L784 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1822310#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1822282#L1659 assume !(0 != activate_threads_~tmp___6~0#1); 1822283#L1659-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1822344#L792 assume !(1 == ~t8_pc~0); 1822528#L792-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1822915#L803 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1822916#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1822273#L1667 assume !(0 != activate_threads_~tmp___7~0#1); 1822194#L1667-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1822195#L811 assume !(1 == ~t9_pc~0); 1822423#L811-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1822999#L822 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1821539#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1821540#L1675 assume !(0 != activate_threads_~tmp___8~0#1); 1822207#L1675-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1822208#L830 assume !(1 == ~t10_pc~0); 1821914#L830-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1821373#L841 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1821374#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1821352#L1683 assume !(0 != activate_threads_~tmp___9~0#1); 1821353#L1683-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1822794#L849 assume !(1 == ~t11_pc~0); 1822795#L849-2 is_transmit11_triggered_~__retres1~11#1 := 0; 1821193#L860 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1821194#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1822808#L1691 assume !(0 != activate_threads_~tmp___10~0#1); 1822684#L1691-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1822685#L868 assume !(1 == ~t12_pc~0); 1822048#L868-2 is_transmit12_triggered_~__retres1~12#1 := 0; 1822047#L879 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1821080#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1821081#L1699 assume !(0 != activate_threads_~tmp___11~0#1); 1821408#L1699-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1821409#L887 assume !(1 == ~t13_pc~0); 1822700#L887-2 is_transmit13_triggered_~__retres1~13#1 := 0; 1822096#L898 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1822097#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 1822763#L1707 assume !(0 != activate_threads_~tmp___12~0#1); 1821121#L1707-2 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1821122#L1439 assume !(1 == ~M_E~0); 1822265#L1439-2 assume !(1 == ~T1_E~0); 1821291#L1444-1 assume !(1 == ~T2_E~0); 1821292#L1449-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1821810#L1454-1 assume !(1 == ~T4_E~0); 1821811#L1459-1 assume !(1 == ~T5_E~0); 1822414#L1464-1 assume !(1 == ~T6_E~0); 1822415#L1469-1 assume !(1 == ~T7_E~0); 1822494#L1474-1 assume !(1 == ~T8_E~0); 1822162#L1479-1 assume !(1 == ~T9_E~0); 1822163#L1484-1 assume !(1 == ~T10_E~0); 1822419#L1489-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1822036#L1494-1 assume !(1 == ~T12_E~0); 1822037#L1499-1 assume !(1 == ~T13_E~0); 1822229#L1504-1 assume !(1 == ~E_M~0); 1822230#L1509-1 assume !(1 == ~E_1~0); 1822898#L1514-1 assume !(1 == ~E_2~0); 1822529#L1519-1 assume !(1 == ~E_3~0); 1822530#L1524-1 assume !(1 == ~E_4~0); 1823177#L1529-1 assume 1 == ~E_5~0;~E_5~0 := 2; 1823178#L1534-1 assume !(1 == ~E_6~0); 1821115#L1539-1 assume !(1 == ~E_7~0); 1821116#L1544-1 assume !(1 == ~E_8~0); 1821536#L1549-1 assume !(1 == ~E_9~0); 1823131#L1554-1 assume !(1 == ~E_10~0); 1823126#L1559-1 assume !(1 == ~E_11~0); 1822941#L1564-1 assume !(1 == ~E_12~0); 1822942#L1569-1 assume 1 == ~E_13~0;~E_13~0 := 2; 1823167#L1574-1 assume { :end_inline_reset_delta_events } true; 1823219#L1940-2 [2024-11-08 00:36:34,033 INFO L747 eck$LassoCheckResult]: Loop: 1823219#L1940-2 assume !false; 2082690#L1941 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2082684#L1266-1 assume !false; 2082682#L1075 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 2082666#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 2082657#L1064 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 2082654#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 2082652#L1079 assume !(0 != eval_~tmp~0#1); 2082653#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2083069#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2083067#L1291-3 assume !(0 == ~M_E~0); 2083065#L1291-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2083063#L1296-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2083061#L1301-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2083058#L1306-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2083056#L1311-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2083054#L1316-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2083052#L1321-3 assume !(0 == ~T7_E~0); 2083050#L1326-3 assume !(0 == ~T8_E~0); 2083048#L1331-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 2083046#L1336-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 2083044#L1341-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 2083042#L1346-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 2083040#L1351-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 2083038#L1356-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2083035#L1361-3 assume !(0 == ~E_1~0); 2083033#L1366-3 assume !(0 == ~E_2~0); 2083031#L1371-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2083029#L1376-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2083027#L1381-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2083025#L1386-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2083023#L1391-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2083021#L1396-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2083019#L1401-3 assume !(0 == ~E_9~0); 2083017#L1406-3 assume !(0 == ~E_10~0); 2083015#L1411-3 assume 0 == ~E_11~0;~E_11~0 := 1; 2083013#L1416-3 assume 0 == ~E_12~0;~E_12~0 := 1; 2083011#L1421-3 assume 0 == ~E_13~0;~E_13~0 := 1; 2083009#L1426-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2083007#L640-45 assume !(1 == ~m_pc~0); 2083005#L640-47 is_master_triggered_~__retres1~0#1 := 0; 2083002#L651-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2083000#is_master_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2082998#L1603-45 assume !(0 != activate_threads_~tmp~1#1); 2082995#L1603-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2082993#L659-45 assume !(1 == ~t1_pc~0); 2082991#L659-47 is_transmit1_triggered_~__retres1~1#1 := 0; 2082989#L670-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2082987#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2082985#L1611-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2082983#L1611-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2082981#L678-45 assume !(1 == ~t2_pc~0); 2082978#L678-47 is_transmit2_triggered_~__retres1~2#1 := 0; 2082976#L689-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2082974#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2082972#L1619-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2082969#L1619-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2082967#L697-45 assume !(1 == ~t3_pc~0); 2082965#L697-47 is_transmit3_triggered_~__retres1~3#1 := 0; 2082963#L708-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2082961#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2082959#L1627-45 assume !(0 != activate_threads_~tmp___2~0#1); 2082957#L1627-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2082955#L716-45 assume !(1 == ~t4_pc~0); 2082953#L716-47 is_transmit4_triggered_~__retres1~4#1 := 0; 2082951#L727-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2082949#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2082947#L1635-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2082945#L1635-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2082943#L735-45 assume !(1 == ~t5_pc~0); 2082941#L735-47 is_transmit5_triggered_~__retres1~5#1 := 0; 2082938#L746-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2082936#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 2082932#L1643-45 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2082930#L1643-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2082928#L754-45 assume !(1 == ~t6_pc~0); 2082926#L754-47 is_transmit6_triggered_~__retres1~6#1 := 0; 2082923#L765-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2082921#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 2082919#L1651-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2082917#L1651-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2082915#L773-45 assume !(1 == ~t7_pc~0); 2082913#L773-47 is_transmit7_triggered_~__retres1~7#1 := 0; 2082910#L784-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2082908#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 2082906#L1659-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2082903#L1659-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2082901#L792-45 assume !(1 == ~t8_pc~0); 2082899#L792-47 is_transmit8_triggered_~__retres1~8#1 := 0; 2082897#L803-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2082895#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 2082893#L1667-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 2082891#L1667-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2082889#L811-45 assume !(1 == ~t9_pc~0); 2082887#L811-47 is_transmit9_triggered_~__retres1~9#1 := 0; 2082885#L822-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2082883#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 2082882#L1675-45 assume !(0 != activate_threads_~tmp___8~0#1); 2082881#L1675-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 2082880#L830-45 assume 1 == ~t10_pc~0; 2082879#L831-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 2082877#L841-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 2082875#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 2082872#L1683-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 2082871#L1683-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 2082870#L849-45 assume !(1 == ~t11_pc~0); 2082869#L849-47 is_transmit11_triggered_~__retres1~11#1 := 0; 2082868#L860-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 2082867#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 2082864#L1691-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 2082863#L1691-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 2082857#L868-45 assume !(1 == ~t12_pc~0); 2082855#L868-47 is_transmit12_triggered_~__retres1~12#1 := 0; 2082852#L879-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 2082850#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 2082847#L1699-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 2082845#L1699-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 2082843#L887-45 assume !(1 == ~t13_pc~0); 2082841#L887-47 is_transmit13_triggered_~__retres1~13#1 := 0; 2082839#L898-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 2082837#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 2082835#L1707-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 2082833#L1707-47 havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2082831#L1439-3 assume !(1 == ~M_E~0); 2082827#L1439-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2082825#L1444-3 assume !(1 == ~T2_E~0); 2082822#L1449-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2082820#L1454-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2082818#L1459-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2082816#L1464-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2082814#L1469-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2082812#L1474-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2082810#L1479-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 2082808#L1484-3 assume !(1 == ~T10_E~0); 2082806#L1489-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 2082804#L1494-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 2082802#L1499-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 2082800#L1504-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2082798#L1509-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2082796#L1514-3 assume !(1 == ~E_2~0); 2082794#L1519-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2082792#L1524-3 assume !(1 == ~E_4~0); 2082790#L1529-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2082788#L1534-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2082786#L1539-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2082783#L1544-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2082781#L1549-3 assume 1 == ~E_9~0;~E_9~0 := 2; 2082779#L1554-3 assume 1 == ~E_10~0;~E_10~0 := 2; 2082777#L1559-3 assume 1 == ~E_11~0;~E_11~0 := 2; 2082775#L1564-3 assume !(1 == ~E_12~0); 2082773#L1569-3 assume 1 == ~E_13~0;~E_13~0 := 2; 2082771#L1574-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 2082753#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 2082744#L1064-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 2082742#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 2082739#L1959 assume !(0 == start_simulation_~tmp~3#1); 2082736#L1959-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 2082712#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 2082703#L1064-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 2082701#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 2082699#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2082697#L1921 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2082695#stop_simulation_returnLabel#1 start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 2082693#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 1823219#L1940-2 [2024-11-08 00:36:34,033 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:36:34,034 INFO L85 PathProgramCache]: Analyzing trace with hash 1787790413, now seen corresponding path program 1 times [2024-11-08 00:36:34,034 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:36:34,034 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1782561206] [2024-11-08 00:36:34,034 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:36:34,034 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:36:34,042 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:36:34,080 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:36:34,080 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:36:34,080 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1782561206] [2024-11-08 00:36:34,080 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1782561206] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:36:34,080 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:36:34,080 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:36:34,080 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [505280442] [2024-11-08 00:36:34,080 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:36:34,081 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:36:34,081 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:36:34,081 INFO L85 PathProgramCache]: Analyzing trace with hash 675976067, now seen corresponding path program 1 times [2024-11-08 00:36:34,081 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:36:34,081 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1538132468] [2024-11-08 00:36:34,081 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:36:34,082 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:36:34,089 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:36:34,107 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:36:34,107 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:36:34,107 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1538132468] [2024-11-08 00:36:34,107 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1538132468] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:36:34,107 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:36:34,107 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:36:34,107 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [517419222] [2024-11-08 00:36:34,107 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:36:34,108 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:36:34,108 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:36:34,108 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-08 00:36:34,108 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-08 00:36:34,108 INFO L87 Difference]: Start difference. First operand 543146 states and 757878 transitions. cyclomatic complexity: 214860 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)