./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.13.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 4f9af400 extending candidate: java ['java'] extending candidate: /usr/bin/java ['java', '/usr/bin/java'] extending candidate: /opt/oracle-jdk-bin-*/bin/java ['java', '/usr/bin/java'] extending candidate: /opt/openjdk-*/bin/java ['java', '/usr/bin/java'] extending candidate: /usr/lib/jvm/java-*-openjdk-amd64/bin/java ['java', '/usr/bin/java', '/usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java', '/usr/lib/jvm/java-17-openjdk-amd64/bin/java', '/usr/lib/jvm/java-11-openjdk-amd64/bin/java', '/usr/lib/jvm/java-1.17.0-openjdk-amd64/bin/java'] ['/root/.sdkman/candidates/java/21.0.5-tem/bin/java', '-Dosgi.configuration.area=/storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/config', '-Xmx15G', '-Xms4m', '-jar', '/storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar', '-data', '@noDefault', '-ultimatedata', '/storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data', '-tc', '/storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml', '-i', '../sv-benchmarks/c/systemc/token_ring.13.cil-2.c', '-s', '/storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf', '--cacsl2boogietranslator.entry.function', 'main', '--witnessprinter.witness.directory', '/storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux', '--witnessprinter.witness.filename', 'witness', '--witnessprinter.write.witness.besides.input.file', 'false', '--witnessprinter.graph.data.specification', 'CHECK( init(main()), LTL(F end) )\n\n', '--witnessprinter.graph.data.producer', 'Automizer', '--witnessprinter.graph.data.architecture', '32bit', '--witnessprinter.graph.data.programhash', '0dcd4461cca64e9ab41b6ad7ff4c6eaa4177bddcca1c612fa1571b77ac664a95'] Calling Ultimate with: /root/.sdkman/candidates/java/21.0.5-tem/bin/java -Dosgi.configuration.area=/storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.13.cil-2.c -s /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 0dcd4461cca64e9ab41b6ad7ff4c6eaa4177bddcca1c612fa1571b77ac664a95 --- Real Ultimate output --- This is Ultimate 0.3.0-?-4f9af40 [2024-11-08 00:35:49,938 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-08 00:35:50,008 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-11-08 00:35:50,013 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-08 00:35:50,013 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-08 00:35:50,029 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-08 00:35:50,029 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-08 00:35:50,029 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-08 00:35:50,029 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-08 00:35:50,029 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-08 00:35:50,030 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-08 00:35:50,030 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-08 00:35:50,030 INFO L153 SettingsManager]: * Use SBE=true [2024-11-08 00:35:50,030 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-11-08 00:35:50,030 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-11-08 00:35:50,030 INFO L153 SettingsManager]: * Use old map elimination=false [2024-11-08 00:35:50,030 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-11-08 00:35:50,030 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-11-08 00:35:50,030 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-11-08 00:35:50,030 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-08 00:35:50,031 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-11-08 00:35:50,031 INFO L153 SettingsManager]: * sizeof long=4 [2024-11-08 00:35:50,031 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-08 00:35:50,031 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-11-08 00:35:50,031 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-08 00:35:50,031 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-11-08 00:35:50,031 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-11-08 00:35:50,031 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-11-08 00:35:50,031 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-11-08 00:35:50,031 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-11-08 00:35:50,031 INFO L153 SettingsManager]: * sizeof long double=12 [2024-11-08 00:35:50,031 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-08 00:35:50,032 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-11-08 00:35:50,032 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-08 00:35:50,032 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-11-08 00:35:50,032 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-08 00:35:50,032 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-08 00:35:50,032 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-11-08 00:35:50,032 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-11-08 00:35:50,032 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 0dcd4461cca64e9ab41b6ad7ff4c6eaa4177bddcca1c612fa1571b77ac664a95 [2024-11-08 00:35:50,245 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-08 00:35:50,251 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-08 00:35:50,253 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-08 00:35:50,254 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-08 00:35:50,254 INFO L274 PluginConnector]: CDTParser initialized [2024-11-08 00:35:50,255 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.13.cil-2.c [2024-11-08 00:35:51,348 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-11-08 00:35:51,588 INFO L384 CDTParser]: Found 1 translation units. [2024-11-08 00:35:51,589 INFO L180 CDTParser]: Scanning /storage/repos/ultimate-jdk21/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.13.cil-2.c [2024-11-08 00:35:51,605 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/71f4969b1/d169fbb9ea8742a2b3e921a0665c6d58/FLAGd227b2c9a [2024-11-08 00:35:51,919 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/71f4969b1/d169fbb9ea8742a2b3e921a0665c6d58 [2024-11-08 00:35:51,920 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-08 00:35:51,921 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-08 00:35:51,922 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-08 00:35:51,922 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-08 00:35:51,925 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-08 00:35:51,925 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 08.11 12:35:51" (1/1) ... [2024-11-08 00:35:51,926 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@581e19a0 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 12:35:51, skipping insertion in model container [2024-11-08 00:35:51,926 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 08.11 12:35:51" (1/1) ... [2024-11-08 00:35:51,960 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-08 00:35:52,130 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-08 00:35:52,142 INFO L200 MainTranslator]: Completed pre-run [2024-11-08 00:35:52,200 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-08 00:35:52,217 INFO L204 MainTranslator]: Completed translation [2024-11-08 00:35:52,218 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 12:35:52 WrapperNode [2024-11-08 00:35:52,218 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-08 00:35:52,218 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-08 00:35:52,218 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-08 00:35:52,219 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-08 00:35:52,223 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 12:35:52" (1/1) ... [2024-11-08 00:35:52,234 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 12:35:52" (1/1) ... [2024-11-08 00:35:52,306 INFO L138 Inliner]: procedures = 54, calls = 71, calls flagged for inlining = 66, calls inlined = 303, statements flattened = 4682 [2024-11-08 00:35:52,307 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-08 00:35:52,307 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-08 00:35:52,307 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-08 00:35:52,307 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-08 00:35:52,314 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 12:35:52" (1/1) ... [2024-11-08 00:35:52,314 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 12:35:52" (1/1) ... [2024-11-08 00:35:52,327 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 12:35:52" (1/1) ... [2024-11-08 00:35:52,356 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-11-08 00:35:52,356 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 12:35:52" (1/1) ... [2024-11-08 00:35:52,356 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 12:35:52" (1/1) ... [2024-11-08 00:35:52,417 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 12:35:52" (1/1) ... [2024-11-08 00:35:52,439 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 12:35:52" (1/1) ... [2024-11-08 00:35:52,444 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 12:35:52" (1/1) ... [2024-11-08 00:35:52,452 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 12:35:52" (1/1) ... [2024-11-08 00:35:52,467 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-08 00:35:52,469 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-11-08 00:35:52,469 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-11-08 00:35:52,469 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-11-08 00:35:52,470 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 12:35:52" (1/1) ... [2024-11-08 00:35:52,475 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-08 00:35:52,484 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2024-11-08 00:35:52,498 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-08 00:35:52,501 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-11-08 00:35:52,519 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-08 00:35:52,519 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-11-08 00:35:52,520 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-08 00:35:52,520 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-08 00:35:52,631 INFO L238 CfgBuilder]: Building ICFG [2024-11-08 00:35:52,632 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-08 00:35:54,794 INFO L? ?]: Removed 1004 outVars from TransFormulas that were not future-live. [2024-11-08 00:35:54,795 INFO L287 CfgBuilder]: Performing block encoding [2024-11-08 00:35:54,836 INFO L311 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-08 00:35:54,836 INFO L316 CfgBuilder]: Removed 16 assume(true) statements. [2024-11-08 00:35:54,837 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 08.11 12:35:54 BoogieIcfgContainer [2024-11-08 00:35:54,837 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-11-08 00:35:54,837 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-11-08 00:35:54,837 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-11-08 00:35:54,844 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-11-08 00:35:54,844 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-08 00:35:54,845 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 08.11 12:35:51" (1/3) ... [2024-11-08 00:35:54,845 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@af38c5e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 08.11 12:35:54, skipping insertion in model container [2024-11-08 00:35:54,845 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-08 00:35:54,845 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.11 12:35:52" (2/3) ... [2024-11-08 00:35:54,845 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@af38c5e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 08.11 12:35:54, skipping insertion in model container [2024-11-08 00:35:54,845 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-08 00:35:54,845 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 08.11 12:35:54" (3/3) ... [2024-11-08 00:35:54,846 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.13.cil-2.c [2024-11-08 00:35:54,906 INFO L300 stractBuchiCegarLoop]: Interprodecural is true [2024-11-08 00:35:54,906 INFO L301 stractBuchiCegarLoop]: Hoare is None [2024-11-08 00:35:54,906 INFO L302 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-11-08 00:35:54,906 INFO L303 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-11-08 00:35:54,906 INFO L304 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-11-08 00:35:54,906 INFO L305 stractBuchiCegarLoop]: Difference is false [2024-11-08 00:35:54,906 INFO L306 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-11-08 00:35:54,906 INFO L310 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-11-08 00:35:54,914 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 2039 states, 2038 states have (on average 1.4921491658488715) internal successors, (3041), 2038 states have internal predecessors, (3041), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:54,967 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1860 [2024-11-08 00:35:54,968 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:35:54,968 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:35:54,977 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:54,977 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:54,977 INFO L332 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-11-08 00:35:54,981 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 2039 states, 2038 states have (on average 1.4921491658488715) internal successors, (3041), 2038 states have internal predecessors, (3041), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:55,004 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1860 [2024-11-08 00:35:55,004 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:35:55,004 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:35:55,011 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:55,011 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:55,021 INFO L745 eck$LassoCheckResult]: Stem: 154#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 1954#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 758#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1947#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1875#L902true assume !(1 == ~m_i~0);~m_st~0 := 2; 471#L902-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 1625#L907-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 514#L912-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1555#L917-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 840#L922-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 994#L927-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 494#L932-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 379#L937-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 1485#L942-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 668#L947-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 1544#L952-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 586#L957-1true assume !(1 == ~t12_i~0);~t12_st~0 := 2; 915#L962-1true assume !(1 == ~t13_i~0);~t13_st~0 := 2; 364#L967-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1972#L1279true assume 0 == ~M_E~0;~M_E~0 := 1; 1556#L1279-2true assume !(0 == ~T1_E~0); 164#L1284-1true assume !(0 == ~T2_E~0); 1785#L1289-1true assume !(0 == ~T3_E~0); 583#L1294-1true assume !(0 == ~T4_E~0); 591#L1299-1true assume !(0 == ~T5_E~0); 1865#L1304-1true assume !(0 == ~T6_E~0); 1912#L1309-1true assume !(0 == ~T7_E~0); 1881#L1314-1true assume 0 == ~T8_E~0;~T8_E~0 := 1; 126#L1319-1true assume !(0 == ~T9_E~0); 1114#L1324-1true assume !(0 == ~T10_E~0); 214#L1329-1true assume !(0 == ~T11_E~0); 1377#L1334-1true assume !(0 == ~T12_E~0); 1814#L1339-1true assume !(0 == ~T13_E~0); 1534#L1344-1true assume !(0 == ~E_M~0); 1970#L1349-1true assume !(0 == ~E_1~0); 724#L1354-1true assume 0 == ~E_2~0;~E_2~0 := 1; 1119#L1359-1true assume !(0 == ~E_3~0); 1791#L1364-1true assume !(0 == ~E_4~0); 282#L1369-1true assume !(0 == ~E_5~0); 1093#L1374-1true assume !(0 == ~E_6~0); 729#L1379-1true assume !(0 == ~E_7~0); 791#L1384-1true assume !(0 == ~E_8~0); 2016#L1389-1true assume !(0 == ~E_9~0); 1412#L1394-1true assume 0 == ~E_10~0;~E_10~0 := 1; 1880#L1399-1true assume !(0 == ~E_11~0); 1643#L1404-1true assume !(0 == ~E_12~0); 334#L1409-1true assume !(0 == ~E_13~0); 1618#L1414-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1963#L628true assume !(1 == ~m_pc~0); 1420#L628-2true is_master_triggered_~__retres1~0#1 := 0; 944#L639true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 634#is_master_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1660#L1591true assume !(0 != activate_threads_~tmp~1#1); 1897#L1591-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 617#L647true assume 1 == ~t1_pc~0; 242#L648true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 654#L658true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1065#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1640#L1599true assume !(0 != activate_threads_~tmp___0~0#1); 1511#L1599-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1924#L666true assume 1 == ~t2_pc~0; 163#L667true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 249#L677true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 237#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1538#L1607true assume !(0 != activate_threads_~tmp___1~0#1); 883#L1607-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1866#L685true assume !(1 == ~t3_pc~0); 1034#L685-2true is_transmit3_triggered_~__retres1~3#1 := 0; 1686#L696true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1045#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 765#L1615true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1070#L1615-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 409#L704true assume 1 == ~t4_pc~0; 1246#L705true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 776#L715true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 62#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1786#L1623true assume !(0 != activate_threads_~tmp___3~0#1); 653#L1623-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 762#L723true assume !(1 == ~t5_pc~0); 955#L723-2true is_transmit5_triggered_~__retres1~5#1 := 0; 1113#L734true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1654#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 866#L1631true assume !(0 != activate_threads_~tmp___4~0#1); 887#L1631-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 273#L742true assume 1 == ~t6_pc~0; 967#L743true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 358#L753true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 232#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 111#L1639true assume !(0 != activate_threads_~tmp___5~0#1); 1369#L1639-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 315#L761true assume !(1 == ~t7_pc~0); 323#L761-2true is_transmit7_triggered_~__retres1~7#1 := 0; 247#L772true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1967#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 767#L1647true assume !(0 != activate_threads_~tmp___6~0#1); 1565#L1647-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 122#L780true assume 1 == ~t8_pc~0; 592#L781true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 268#L791true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1606#is_transmit8_triggered_returnLabel#1true activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 736#L1655true assume !(0 != activate_threads_~tmp___7~0#1); 830#L1655-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1403#L799true assume 1 == ~t9_pc~0; 922#L800true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 123#L810true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 265#is_transmit9_triggered_returnLabel#1true activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1008#L1663true assume !(0 != activate_threads_~tmp___8~0#1); 1931#L1663-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 853#L818true assume !(1 == ~t10_pc~0); 25#L818-2true is_transmit10_triggered_~__retres1~10#1 := 0; 916#L829true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1385#is_transmit10_triggered_returnLabel#1true activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 856#L1671true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1099#L1671-2true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 892#L837true assume 1 == ~t11_pc~0; 1808#L838true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1584#L848true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1516#is_transmit11_triggered_returnLabel#1true activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 825#L1679true assume !(0 != activate_threads_~tmp___10~0#1); 1869#L1679-2true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 623#L856true assume !(1 == ~t12_pc~0); 1452#L856-2true is_transmit12_triggered_~__retres1~12#1 := 0; 1253#L867true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 34#is_transmit12_triggered_returnLabel#1true activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1224#L1687true assume !(0 != activate_threads_~tmp___11~0#1); 1800#L1687-2true assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1562#L875true assume 1 == ~t13_pc~0; 589#L876true assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 359#L886true is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1439#is_transmit13_triggered_returnLabel#1true activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 326#L1695true assume !(0 != activate_threads_~tmp___12~0#1); 914#L1695-2true havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1908#L1427true assume !(1 == ~M_E~0); 901#L1427-2true assume !(1 == ~T1_E~0); 308#L1432-1true assume !(1 == ~T2_E~0); 1566#L1437-1true assume 1 == ~T3_E~0;~T3_E~0 := 2; 1129#L1442-1true assume !(1 == ~T4_E~0); 1494#L1447-1true assume !(1 == ~T5_E~0); 962#L1452-1true assume !(1 == ~T6_E~0); 87#L1457-1true assume !(1 == ~T7_E~0); 1158#L1462-1true assume !(1 == ~T8_E~0); 1852#L1467-1true assume !(1 == ~T9_E~0); 1185#L1472-1true assume !(1 == ~T10_E~0); 1381#L1477-1true assume 1 == ~T11_E~0;~T11_E~0 := 2; 912#L1482-1true assume !(1 == ~T12_E~0); 1304#L1487-1true assume !(1 == ~T13_E~0); 254#L1492-1true assume !(1 == ~E_M~0); 666#L1497-1true assume !(1 == ~E_1~0); 459#L1502-1true assume !(1 == ~E_2~0); 1303#L1507-1true assume !(1 == ~E_3~0); 190#L1512-1true assume !(1 == ~E_4~0); 1280#L1517-1true assume 1 == ~E_5~0;~E_5~0 := 2; 1398#L1522-1true assume !(1 == ~E_6~0); 615#L1527-1true assume !(1 == ~E_7~0); 1765#L1532-1true assume !(1 == ~E_8~0); 2028#L1537-1true assume !(1 == ~E_9~0); 781#L1542-1true assume !(1 == ~E_10~0); 638#L1547-1true assume !(1 == ~E_11~0); 1796#L1552-1true assume !(1 == ~E_12~0); 44#L1557-1true assume 1 == ~E_13~0;~E_13~0 := 2; 352#L1562-1true assume { :end_inline_reset_delta_events } true; 759#L1928-2true [2024-11-08 00:35:55,026 INFO L747 eck$LassoCheckResult]: Loop: 759#L1928-2true assume !false; 663#L1929true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 533#L1254-1true assume false; 577#eval_returnLabel#1true havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 338#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1610#L1279-3true assume 0 == ~M_E~0;~M_E~0 := 1; 472#L1279-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 461#L1284-3true assume !(0 == ~T2_E~0); 1665#L1289-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 451#L1294-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 1903#L1299-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 721#L1304-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 1146#L1309-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 383#L1314-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 1984#L1319-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 1212#L1324-3true assume !(0 == ~T10_E~0); 189#L1329-3true assume 0 == ~T11_E~0;~T11_E~0 := 1; 1834#L1334-3true assume 0 == ~T12_E~0;~T12_E~0 := 1; 644#L1339-3true assume 0 == ~T13_E~0;~T13_E~0 := 1; 938#L1344-3true assume 0 == ~E_M~0;~E_M~0 := 1; 889#L1349-3true assume 0 == ~E_1~0;~E_1~0 := 1; 373#L1354-3true assume 0 == ~E_2~0;~E_2~0 := 1; 898#L1359-3true assume 0 == ~E_3~0;~E_3~0 := 1; 1863#L1364-3true assume !(0 == ~E_4~0); 1750#L1369-3true assume 0 == ~E_5~0;~E_5~0 := 1; 1443#L1374-3true assume 0 == ~E_6~0;~E_6~0 := 1; 256#L1379-3true assume 0 == ~E_7~0;~E_7~0 := 1; 1310#L1384-3true assume 0 == ~E_8~0;~E_8~0 := 1; 372#L1389-3true assume 0 == ~E_9~0;~E_9~0 := 1; 555#L1394-3true assume 0 == ~E_10~0;~E_10~0 := 1; 1957#L1399-3true assume 0 == ~E_11~0;~E_11~0 := 1; 1474#L1404-3true assume !(0 == ~E_12~0); 1397#L1409-3true assume 0 == ~E_13~0;~E_13~0 := 1; 1554#L1414-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 801#L628-45true assume 1 == ~m_pc~0; 553#L629-15true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1744#L639-15true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 971#is_master_triggered_returnLabel#16true activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 393#L1591-45true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1667#L1591-47true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 921#L647-45true assume !(1 == ~t1_pc~0); 1404#L647-47true is_transmit1_triggered_~__retres1~1#1 := 0; 735#L658-15true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1867#is_transmit1_triggered_returnLabel#16true activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 218#L1599-45true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1552#L1599-47true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 331#L666-45true assume !(1 == ~t2_pc~0); 630#L666-47true is_transmit2_triggered_~__retres1~2#1 := 0; 1693#L677-15true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 968#is_transmit2_triggered_returnLabel#16true activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1023#L1607-45true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1019#L1607-47true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 96#L685-45true assume 1 == ~t3_pc~0; 730#L686-15true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1537#L696-15true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1990#is_transmit3_triggered_returnLabel#16true activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1275#L1615-45true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1558#L1615-47true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1639#L704-45true assume 1 == ~t4_pc~0; 1316#L705-15true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 492#L715-15true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1317#is_transmit4_triggered_returnLabel#16true activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2031#L1623-45true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1993#L1623-47true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 827#L723-45true assume 1 == ~t5_pc~0; 1827#L724-15true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1706#L734-15true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1983#is_transmit5_triggered_returnLabel#16true activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 381#L1631-45true assume !(0 != activate_threads_~tmp___4~0#1); 1937#L1631-47true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1235#L742-45true assume 1 == ~t6_pc~0; 1845#L743-15true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 897#L753-15true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 685#is_transmit6_triggered_returnLabel#16true activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 926#L1639-45true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1279#L1639-47true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 999#L761-45true assume !(1 == ~t7_pc~0); 1167#L761-47true is_transmit7_triggered_~__retres1~7#1 := 0; 535#L772-15true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 755#is_transmit7_triggered_returnLabel#16true activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 192#L1647-45true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1962#L1647-47true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1401#L780-45true assume 1 == ~t8_pc~0; 396#L781-15true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 197#L791-15true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1736#is_transmit8_triggered_returnLabel#16true activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1764#L1655-45true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 180#L1655-47true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 642#L799-45true assume !(1 == ~t9_pc~0); 298#L799-47true is_transmit9_triggered_~__retres1~9#1 := 0; 2022#L810-15true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1091#is_transmit9_triggered_returnLabel#16true activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 963#L1663-45true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1828#L1663-47true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 152#L818-45true assume 1 == ~t10_pc~0; 1064#L819-15true assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 943#L829-15true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1203#is_transmit10_triggered_returnLabel#16true activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 491#L1671-45true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1056#L1671-47true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1530#L837-45true assume 1 == ~t11_pc~0; 1771#L838-15true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 536#L848-15true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 188#is_transmit11_triggered_returnLabel#16true activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1856#L1679-45true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 224#L1679-47true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 2040#L856-45true assume 1 == ~t12_pc~0; 1549#L857-15true assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 1274#L867-15true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1136#is_transmit12_triggered_returnLabel#16true activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1810#L1687-45true assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 734#L1687-47true assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1282#L875-45true assume 1 == ~t13_pc~0; 709#L876-15true assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 757#L886-15true is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1079#is_transmit13_triggered_returnLabel#16true activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1493#L1695-45true assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 1775#L1695-47true havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1374#L1427-3true assume !(1 == ~M_E~0); 580#L1427-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 1567#L1432-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 1006#L1437-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 723#L1442-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 1024#L1447-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 51#L1452-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 1992#L1457-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 1259#L1462-3true assume !(1 == ~T8_E~0); 1681#L1467-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 1073#L1472-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 1714#L1477-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 173#L1482-3true assume 1 == ~T12_E~0;~T12_E~0 := 2; 246#L1487-3true assume 1 == ~T13_E~0;~T13_E~0 := 2; 1820#L1492-3true assume 1 == ~E_M~0;~E_M~0 := 2; 337#L1497-3true assume 1 == ~E_1~0;~E_1~0 := 2; 1027#L1502-3true assume !(1 == ~E_2~0); 1210#L1507-3true assume 1 == ~E_3~0;~E_3~0 := 2; 1929#L1512-3true assume 1 == ~E_4~0;~E_4~0 := 2; 361#L1517-3true assume 1 == ~E_5~0;~E_5~0 := 2; 194#L1522-3true assume 1 == ~E_6~0;~E_6~0 := 2; 1682#L1527-3true assume 1 == ~E_7~0;~E_7~0 := 2; 176#L1532-3true assume 1 == ~E_8~0;~E_8~0 := 2; 899#L1537-3true assume 1 == ~E_9~0;~E_9~0 := 2; 1581#L1542-3true assume !(1 == ~E_10~0); 1011#L1547-3true assume 1 == ~E_11~0;~E_11~0 := 2; 710#L1552-3true assume 1 == ~E_12~0;~E_12~0 := 2; 1406#L1557-3true assume 1 == ~E_13~0;~E_13~0 := 2; 285#L1562-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1981#L980-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1421#L1052-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 208#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 817#L1947true assume !(0 == start_simulation_~tmp~3#1); 987#L1947-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1134#L980-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1629#L1052-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 29#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 1461#L1902true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1173#L1909true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1411#stop_simulation_returnLabel#1true start_simulation_#t~ret36#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 1720#L1960true assume !(0 != start_simulation_~tmp___0~1#1); 759#L1928-2true [2024-11-08 00:35:55,032 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:55,033 INFO L85 PathProgramCache]: Analyzing trace with hash 1878318605, now seen corresponding path program 1 times [2024-11-08 00:35:55,037 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:55,037 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1215545128] [2024-11-08 00:35:55,038 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:55,038 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:55,119 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:55,303 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:55,303 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:55,303 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1215545128] [2024-11-08 00:35:55,304 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1215545128] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:55,304 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:55,304 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:55,305 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1934457937] [2024-11-08 00:35:55,305 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:55,307 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:35:55,308 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:55,312 INFO L85 PathProgramCache]: Analyzing trace with hash 1758240959, now seen corresponding path program 1 times [2024-11-08 00:35:55,312 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:55,312 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1594033771] [2024-11-08 00:35:55,312 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:55,312 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:55,330 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:55,377 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:55,378 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:55,378 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1594033771] [2024-11-08 00:35:55,378 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1594033771] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:55,378 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:55,378 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-08 00:35:55,378 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [71268723] [2024-11-08 00:35:55,378 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:55,379 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:35:55,382 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:35:55,401 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2024-11-08 00:35:55,401 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2024-11-08 00:35:55,406 INFO L87 Difference]: Start difference. First operand has 2039 states, 2038 states have (on average 1.4921491658488715) internal successors, (3041), 2038 states have internal predecessors, (3041), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 79.5) internal successors, (159), 2 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:55,458 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:35:55,459 INFO L93 Difference]: Finished difference Result 2037 states and 3006 transitions. [2024-11-08 00:35:55,460 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2037 states and 3006 transitions. [2024-11-08 00:35:55,474 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1857 [2024-11-08 00:35:55,492 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2037 states to 2032 states and 3001 transitions. [2024-11-08 00:35:55,493 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2032 [2024-11-08 00:35:55,495 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2032 [2024-11-08 00:35:55,495 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2032 states and 3001 transitions. [2024-11-08 00:35:55,503 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:35:55,503 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2032 states and 3001 transitions. [2024-11-08 00:35:55,517 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2032 states and 3001 transitions. [2024-11-08 00:35:55,568 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2032 to 2032. [2024-11-08 00:35:55,571 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2032 states, 2032 states have (on average 1.4768700787401574) internal successors, (3001), 2031 states have internal predecessors, (3001), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:55,577 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2032 states to 2032 states and 3001 transitions. [2024-11-08 00:35:55,578 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2032 states and 3001 transitions. [2024-11-08 00:35:55,579 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-11-08 00:35:55,581 INFO L425 stractBuchiCegarLoop]: Abstraction has 2032 states and 3001 transitions. [2024-11-08 00:35:55,582 INFO L332 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-11-08 00:35:55,582 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2032 states and 3001 transitions. [2024-11-08 00:35:55,590 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1857 [2024-11-08 00:35:55,590 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:35:55,590 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:35:55,594 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:55,594 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:55,595 INFO L745 eck$LassoCheckResult]: Stem: 4416#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 4417#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 5403#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5404#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6103#L902 assume !(1 == ~m_i~0);~m_st~0 := 2; 4997#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4998#L907-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 5068#L912-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 5069#L917-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5506#L922-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5507#L927-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5032#L932-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4837#L937-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4838#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 5296#L947-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 5297#L952-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 5176#L957-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 5177#L962-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 4811#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4812#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 6027#L1279-2 assume !(0 == ~T1_E~0); 4437#L1284-1 assume !(0 == ~T2_E~0); 4438#L1289-1 assume !(0 == ~T3_E~0); 5173#L1294-1 assume !(0 == ~T4_E~0); 5174#L1299-1 assume !(0 == ~T5_E~0); 5185#L1304-1 assume !(0 == ~T6_E~0); 6102#L1309-1 assume !(0 == ~T7_E~0); 6104#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4361#L1319-1 assume !(0 == ~T9_E~0); 4362#L1324-1 assume !(0 == ~T10_E~0); 4535#L1329-1 assume !(0 == ~T11_E~0); 4536#L1334-1 assume !(0 == ~T12_E~0); 5945#L1339-1 assume !(0 == ~T13_E~0); 6017#L1344-1 assume !(0 == ~E_M~0); 6018#L1349-1 assume !(0 == ~E_1~0); 5362#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 5363#L1359-1 assume !(0 == ~E_3~0); 5770#L1364-1 assume !(0 == ~E_4~0); 4661#L1369-1 assume !(0 == ~E_5~0); 4662#L1374-1 assume !(0 == ~E_6~0); 5369#L1379-1 assume !(0 == ~E_7~0); 5370#L1384-1 assume !(0 == ~E_8~0); 5447#L1389-1 assume !(0 == ~E_9~0); 5964#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 5965#L1399-1 assume !(0 == ~E_11~0); 6058#L1404-1 assume !(0 == ~E_12~0); 4759#L1409-1 assume !(0 == ~E_13~0); 4760#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6053#L628 assume !(1 == ~m_pc~0); 4660#L628-2 is_master_triggered_~__retres1~0#1 := 0; 4659#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5244#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5245#L1591 assume !(0 != activate_threads_~tmp~1#1); 6066#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5225#L647 assume 1 == ~t1_pc~0; 4585#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4586#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5276#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5733#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 6005#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6006#L666 assume 1 == ~t2_pc~0; 4434#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4435#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4576#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4577#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 5558#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5559#L685 assume !(1 == ~t3_pc~0); 5653#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 5652#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5722#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5411#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5412#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4885#L704 assume 1 == ~t4_pc~0; 4886#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5423#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4225#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4226#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 5274#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5275#L723 assume !(1 == ~t5_pc~0); 5407#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 5625#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5763#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5537#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 5538#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4643#L742 assume 1 == ~t6_pc~0; 4644#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4800#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4567#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4330#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 4331#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4721#L761 assume !(1 == ~t7_pc~0); 4722#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 4597#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4598#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 5414#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 5415#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4353#L780 assume 1 == ~t8_pc~0; 4354#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4633#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4634#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 5376#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 5377#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5493#L799 assume 1 == ~t9_pc~0; 5595#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4356#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4357#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 4628#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 5696#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 5519#L818 assume !(1 == ~t10_pc~0); 4140#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 4141#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5588#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 5522#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 5523#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 5565#L837 assume 1 == ~t11_pc~0; 5566#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 5401#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 6009#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 5486#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 5487#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 5233#L856 assume !(1 == ~t12_pc~0); 5234#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 5868#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4158#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 4159#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 5846#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 6030#L875 assume 1 == ~t13_pc~0; 5183#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 4801#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 4802#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 4739#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 4740#L1695-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5587#L1427 assume !(1 == ~M_E~0); 5572#L1427-2 assume !(1 == ~T1_E~0); 4708#L1432-1 assume !(1 == ~T2_E~0); 4709#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5775#L1442-1 assume !(1 == ~T4_E~0); 5776#L1447-1 assume !(1 == ~T5_E~0); 5634#L1452-1 assume !(1 == ~T6_E~0); 4277#L1457-1 assume !(1 == ~T7_E~0); 4278#L1462-1 assume !(1 == ~T8_E~0); 5793#L1467-1 assume !(1 == ~T9_E~0); 5814#L1472-1 assume !(1 == ~T10_E~0); 5815#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 5583#L1482-1 assume !(1 == ~T12_E~0); 5584#L1487-1 assume !(1 == ~T13_E~0); 4608#L1492-1 assume !(1 == ~E_M~0); 4609#L1497-1 assume !(1 == ~E_1~0); 4979#L1502-1 assume !(1 == ~E_2~0); 4980#L1507-1 assume !(1 == ~E_3~0); 4485#L1512-1 assume !(1 == ~E_4~0); 4486#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 5887#L1522-1 assume !(1 == ~E_6~0); 5222#L1527-1 assume !(1 == ~E_7~0); 5223#L1532-1 assume !(1 == ~E_8~0); 6088#L1537-1 assume !(1 == ~E_9~0); 5430#L1542-1 assume !(1 == ~E_10~0); 5251#L1547-1 assume !(1 == ~E_11~0); 5252#L1552-1 assume !(1 == ~E_12~0); 4181#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 4182#L1562-1 assume { :end_inline_reset_delta_events } true; 4791#L1928-2 [2024-11-08 00:35:55,596 INFO L747 eck$LassoCheckResult]: Loop: 4791#L1928-2 assume !false; 5289#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4866#L1254-1 assume !false; 5098#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 4510#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4511#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 4710#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 5873#L1067 assume !(0 != eval_~tmp~0#1); 5163#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4768#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4769#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4999#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4983#L1284-3 assume !(0 == ~T2_E~0); 4984#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4964#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4965#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5357#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5358#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4845#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4846#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 5836#L1324-3 assume !(0 == ~T10_E~0); 4483#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 4484#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 5257#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 5258#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5562#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4829#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4830#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5570#L1364-3 assume !(0 == ~E_4~0); 6087#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5979#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4612#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 4613#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 4827#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 4828#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 5134#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 5989#L1404-3 assume !(0 == ~E_12~0); 5954#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 5955#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5459#L628-45 assume 1 == ~m_pc~0; 5129#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 5131#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5642#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4863#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4864#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5594#L647-45 assume !(1 == ~t1_pc~0); 4433#L647-47 is_transmit1_triggered_~__retres1~1#1 := 0; 4432#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5375#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4541#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4542#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4752#L666-45 assume !(1 == ~t2_pc~0); 4753#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 5243#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5640#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5641#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5706#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4293#L685-45 assume 1 == ~t3_pc~0; 4294#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5371#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6019#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5885#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5886#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6028#L704-45 assume !(1 == ~t4_pc~0); 4160#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 4161#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5029#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5910#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6116#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5488#L723-45 assume !(1 == ~t5_pc~0); 5489#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 5966#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6078#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4841#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 4842#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5856#L742-45 assume 1 == ~t6_pc~0; 5857#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5106#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5316#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 5317#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5599#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5685#L761-45 assume !(1 == ~t7_pc~0); 5686#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 5100#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5101#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4489#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4490#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5958#L780-45 assume 1 == ~t8_pc~0; 4867#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4500#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4501#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 6085#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4469#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4470#L799-45 assume !(1 == ~t9_pc~0); 4688#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 4689#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5751#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 5635#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 5636#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4411#L818-45 assume 1 == ~t10_pc~0; 4412#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 4529#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5612#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 5027#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 5028#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 5731#L837-45 assume !(1 == ~t11_pc~0); 4957#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 4958#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4481#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 4482#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 4550#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4551#L856-45 assume !(1 == ~t12_pc~0); 4552#L856-47 is_transmit12_triggered_~__retres1~12#1 := 0; 4553#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 5782#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 5783#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 5373#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 5374#L875-45 assume 1 == ~t13_pc~0; 5341#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 5342#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 5402#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 5743#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 5999#L1695-47 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5943#L1427-3 assume !(1 == ~M_E~0); 5168#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5169#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5693#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5360#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5361#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4198#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4199#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5871#L1462-3 assume !(1 == ~T8_E~0); 5872#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 5739#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 5740#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 4453#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 4454#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 4596#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4766#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4767#L1502-3 assume !(1 == ~E_2~0); 5713#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5834#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4805#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4493#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4494#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 4460#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4461#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 5571#L1542-3 assume !(1 == ~E_10~0); 5699#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 5344#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 5345#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 4664#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 4665#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4086#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 4523#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 4524#L1947 assume !(0 == start_simulation_~tmp~3#1); 5477#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 5667#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4725#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 4148#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 4149#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5802#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5803#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 5963#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 4791#L1928-2 [2024-11-08 00:35:55,597 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:55,597 INFO L85 PathProgramCache]: Analyzing trace with hash 1878318605, now seen corresponding path program 2 times [2024-11-08 00:35:55,597 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:55,597 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [943649837] [2024-11-08 00:35:55,598 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:55,598 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:55,617 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:55,693 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:55,694 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:55,694 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [943649837] [2024-11-08 00:35:55,694 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [943649837] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:55,694 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:55,694 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:55,694 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [234629519] [2024-11-08 00:35:55,694 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:55,694 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:35:55,695 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:55,695 INFO L85 PathProgramCache]: Analyzing trace with hash 225054192, now seen corresponding path program 1 times [2024-11-08 00:35:55,695 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:55,695 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1524042103] [2024-11-08 00:35:55,695 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:55,695 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:55,734 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:55,822 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:55,822 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:55,822 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1524042103] [2024-11-08 00:35:55,822 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1524042103] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:55,822 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:55,823 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:55,823 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1851806657] [2024-11-08 00:35:55,823 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:55,823 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:35:55,823 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:35:55,823 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:35:55,823 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:35:55,824 INFO L87 Difference]: Start difference. First operand 2032 states and 3001 transitions. cyclomatic complexity: 970 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:55,865 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:35:55,865 INFO L93 Difference]: Finished difference Result 2032 states and 3000 transitions. [2024-11-08 00:35:55,866 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2032 states and 3000 transitions. [2024-11-08 00:35:55,874 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1857 [2024-11-08 00:35:55,881 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2032 states to 2032 states and 3000 transitions. [2024-11-08 00:35:55,881 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2032 [2024-11-08 00:35:55,882 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2032 [2024-11-08 00:35:55,884 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2032 states and 3000 transitions. [2024-11-08 00:35:55,888 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:35:55,888 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2032 states and 3000 transitions. [2024-11-08 00:35:55,891 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2032 states and 3000 transitions. [2024-11-08 00:35:55,912 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2032 to 2032. [2024-11-08 00:35:55,914 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2032 states, 2032 states have (on average 1.4763779527559056) internal successors, (3000), 2031 states have internal predecessors, (3000), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:55,919 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2032 states to 2032 states and 3000 transitions. [2024-11-08 00:35:55,919 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2032 states and 3000 transitions. [2024-11-08 00:35:55,919 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:35:55,921 INFO L425 stractBuchiCegarLoop]: Abstraction has 2032 states and 3000 transitions. [2024-11-08 00:35:55,923 INFO L332 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-11-08 00:35:55,923 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2032 states and 3000 transitions. [2024-11-08 00:35:55,929 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1857 [2024-11-08 00:35:55,929 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:35:55,929 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:35:55,932 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:55,932 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:55,933 INFO L745 eck$LassoCheckResult]: Stem: 8487#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 8488#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 9474#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9475#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10174#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 9068#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9069#L907-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 9139#L912-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 9140#L917-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 9577#L922-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 9578#L927-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 9103#L932-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8908#L937-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 8909#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 9367#L947-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 9368#L952-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 9247#L957-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 9248#L962-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 8882#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8883#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 10098#L1279-2 assume !(0 == ~T1_E~0); 8508#L1284-1 assume !(0 == ~T2_E~0); 8509#L1289-1 assume !(0 == ~T3_E~0); 9244#L1294-1 assume !(0 == ~T4_E~0); 9245#L1299-1 assume !(0 == ~T5_E~0); 9256#L1304-1 assume !(0 == ~T6_E~0); 10173#L1309-1 assume !(0 == ~T7_E~0); 10175#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 8432#L1319-1 assume !(0 == ~T9_E~0); 8433#L1324-1 assume !(0 == ~T10_E~0); 8606#L1329-1 assume !(0 == ~T11_E~0); 8607#L1334-1 assume !(0 == ~T12_E~0); 10016#L1339-1 assume !(0 == ~T13_E~0); 10088#L1344-1 assume !(0 == ~E_M~0); 10089#L1349-1 assume !(0 == ~E_1~0); 9433#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 9434#L1359-1 assume !(0 == ~E_3~0); 9841#L1364-1 assume !(0 == ~E_4~0); 8732#L1369-1 assume !(0 == ~E_5~0); 8733#L1374-1 assume !(0 == ~E_6~0); 9440#L1379-1 assume !(0 == ~E_7~0); 9441#L1384-1 assume !(0 == ~E_8~0); 9518#L1389-1 assume !(0 == ~E_9~0); 10035#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 10036#L1399-1 assume !(0 == ~E_11~0); 10129#L1404-1 assume !(0 == ~E_12~0); 8830#L1409-1 assume !(0 == ~E_13~0); 8831#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10124#L628 assume !(1 == ~m_pc~0); 8731#L628-2 is_master_triggered_~__retres1~0#1 := 0; 8730#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9315#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9316#L1591 assume !(0 != activate_threads_~tmp~1#1); 10137#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9296#L647 assume 1 == ~t1_pc~0; 8656#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8657#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9347#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9804#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 10076#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10077#L666 assume 1 == ~t2_pc~0; 8505#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8506#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8647#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8648#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 9629#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9630#L685 assume !(1 == ~t3_pc~0); 9724#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 9723#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9793#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9482#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9483#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8956#L704 assume 1 == ~t4_pc~0; 8957#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9494#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8296#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8297#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 9345#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9346#L723 assume !(1 == ~t5_pc~0); 9478#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 9696#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9834#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 9608#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 9609#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8714#L742 assume 1 == ~t6_pc~0; 8715#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8871#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8638#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8401#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 8402#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8792#L761 assume !(1 == ~t7_pc~0); 8793#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 8668#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8669#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 9485#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 9486#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8424#L780 assume 1 == ~t8_pc~0; 8425#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8704#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8705#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 9447#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 9448#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 9564#L799 assume 1 == ~t9_pc~0; 9666#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 8427#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 8428#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 8699#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 9767#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 9590#L818 assume !(1 == ~t10_pc~0); 8211#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 8212#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 9659#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 9593#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 9594#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 9636#L837 assume 1 == ~t11_pc~0; 9637#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 9472#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 10080#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 9557#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 9558#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 9304#L856 assume !(1 == ~t12_pc~0); 9305#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 9939#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 8229#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 8230#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 9917#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 10101#L875 assume 1 == ~t13_pc~0; 9254#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 8872#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 8873#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 8810#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 8811#L1695-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9658#L1427 assume !(1 == ~M_E~0); 9643#L1427-2 assume !(1 == ~T1_E~0); 8779#L1432-1 assume !(1 == ~T2_E~0); 8780#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9846#L1442-1 assume !(1 == ~T4_E~0); 9847#L1447-1 assume !(1 == ~T5_E~0); 9705#L1452-1 assume !(1 == ~T6_E~0); 8348#L1457-1 assume !(1 == ~T7_E~0); 8349#L1462-1 assume !(1 == ~T8_E~0); 9864#L1467-1 assume !(1 == ~T9_E~0); 9885#L1472-1 assume !(1 == ~T10_E~0); 9886#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 9654#L1482-1 assume !(1 == ~T12_E~0); 9655#L1487-1 assume !(1 == ~T13_E~0); 8679#L1492-1 assume !(1 == ~E_M~0); 8680#L1497-1 assume !(1 == ~E_1~0); 9050#L1502-1 assume !(1 == ~E_2~0); 9051#L1507-1 assume !(1 == ~E_3~0); 8556#L1512-1 assume !(1 == ~E_4~0); 8557#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 9958#L1522-1 assume !(1 == ~E_6~0); 9293#L1527-1 assume !(1 == ~E_7~0); 9294#L1532-1 assume !(1 == ~E_8~0); 10159#L1537-1 assume !(1 == ~E_9~0); 9501#L1542-1 assume !(1 == ~E_10~0); 9322#L1547-1 assume !(1 == ~E_11~0); 9323#L1552-1 assume !(1 == ~E_12~0); 8252#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 8253#L1562-1 assume { :end_inline_reset_delta_events } true; 8862#L1928-2 [2024-11-08 00:35:55,934 INFO L747 eck$LassoCheckResult]: Loop: 8862#L1928-2 assume !false; 9360#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8937#L1254-1 assume !false; 9169#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 8581#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 8582#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 8781#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 9944#L1067 assume !(0 != eval_~tmp~0#1); 9234#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8839#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8840#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9070#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9054#L1284-3 assume !(0 == ~T2_E~0); 9055#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9035#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9036#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9428#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9429#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8916#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 8917#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 9907#L1324-3 assume !(0 == ~T10_E~0); 8554#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 8555#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 9328#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 9329#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 9633#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8900#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8901#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9641#L1364-3 assume !(0 == ~E_4~0); 10158#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10050#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 8683#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 8684#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 8898#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 8899#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 9205#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 10060#L1404-3 assume !(0 == ~E_12~0); 10025#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 10026#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9530#L628-45 assume 1 == ~m_pc~0; 9200#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 9202#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9713#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8934#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8935#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9665#L647-45 assume 1 == ~t1_pc~0; 8502#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8503#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9446#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8612#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8613#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8823#L666-45 assume !(1 == ~t2_pc~0); 8824#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 9314#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9711#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9712#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9777#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8364#L685-45 assume 1 == ~t3_pc~0; 8365#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9442#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10090#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9956#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9957#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10099#L704-45 assume !(1 == ~t4_pc~0); 8231#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 8232#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9100#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9981#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 10187#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9559#L723-45 assume !(1 == ~t5_pc~0); 9560#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 10037#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10149#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8912#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 8913#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9927#L742-45 assume 1 == ~t6_pc~0; 9928#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 9177#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9387#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 9388#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9670#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9756#L761-45 assume !(1 == ~t7_pc~0); 9757#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 9171#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9172#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8560#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8561#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10029#L780-45 assume 1 == ~t8_pc~0; 8938#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8571#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8572#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 10156#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 8540#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8541#L799-45 assume !(1 == ~t9_pc~0); 8759#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 8760#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9822#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 9706#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 9707#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8482#L818-45 assume 1 == ~t10_pc~0; 8483#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 8600#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 9683#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 9098#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 9099#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 9802#L837-45 assume !(1 == ~t11_pc~0); 9028#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 9029#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 8552#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 8553#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 8621#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 8622#L856-45 assume 1 == ~t12_pc~0; 10097#L857-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 8624#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 9853#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 9854#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 9444#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 9445#L875-45 assume 1 == ~t13_pc~0; 9412#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 9413#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 9473#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 9814#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 10070#L1695-47 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10014#L1427-3 assume !(1 == ~M_E~0); 9239#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9240#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9764#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9431#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9432#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8269#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8270#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 9942#L1462-3 assume !(1 == ~T8_E~0); 9943#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 9810#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 9811#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 8524#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 8525#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 8667#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8837#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8838#L1502-3 assume !(1 == ~E_2~0); 9784#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9905#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8876#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8564#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8565#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8531#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 8532#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 9642#L1542-3 assume !(1 == ~E_10~0); 9770#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 9415#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 9416#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 8735#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 8736#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 8157#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 8594#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 8595#L1947 assume !(0 == start_simulation_~tmp~3#1); 9548#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 9738#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 8796#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 8219#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 8220#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9873#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9874#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 10034#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 8862#L1928-2 [2024-11-08 00:35:55,934 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:55,934 INFO L85 PathProgramCache]: Analyzing trace with hash 1533490443, now seen corresponding path program 1 times [2024-11-08 00:35:55,934 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:55,934 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1454523584] [2024-11-08 00:35:55,935 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:55,935 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:55,952 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:55,986 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:55,986 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:55,986 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1454523584] [2024-11-08 00:35:55,986 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1454523584] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:55,986 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:55,986 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:55,986 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1775182504] [2024-11-08 00:35:55,986 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:55,987 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:35:55,987 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:55,987 INFO L85 PathProgramCache]: Analyzing trace with hash 1923928238, now seen corresponding path program 1 times [2024-11-08 00:35:55,987 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:55,987 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [343334539] [2024-11-08 00:35:55,987 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:55,987 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:56,023 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:56,077 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:56,077 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:56,077 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [343334539] [2024-11-08 00:35:56,077 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [343334539] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:56,077 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:56,078 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:56,078 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [873146508] [2024-11-08 00:35:56,078 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:56,078 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:35:56,078 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:35:56,078 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:35:56,078 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:35:56,078 INFO L87 Difference]: Start difference. First operand 2032 states and 3000 transitions. cyclomatic complexity: 969 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:56,106 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:35:56,107 INFO L93 Difference]: Finished difference Result 2032 states and 2999 transitions. [2024-11-08 00:35:56,107 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2032 states and 2999 transitions. [2024-11-08 00:35:56,114 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1857 [2024-11-08 00:35:56,121 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2032 states to 2032 states and 2999 transitions. [2024-11-08 00:35:56,121 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2032 [2024-11-08 00:35:56,122 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2032 [2024-11-08 00:35:56,123 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2032 states and 2999 transitions. [2024-11-08 00:35:56,125 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:35:56,125 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2032 states and 2999 transitions. [2024-11-08 00:35:56,128 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2032 states and 2999 transitions. [2024-11-08 00:35:56,143 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2032 to 2032. [2024-11-08 00:35:56,146 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2032 states, 2032 states have (on average 1.4758858267716535) internal successors, (2999), 2031 states have internal predecessors, (2999), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:56,150 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2032 states to 2032 states and 2999 transitions. [2024-11-08 00:35:56,151 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2032 states and 2999 transitions. [2024-11-08 00:35:56,152 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:35:56,154 INFO L425 stractBuchiCegarLoop]: Abstraction has 2032 states and 2999 transitions. [2024-11-08 00:35:56,154 INFO L332 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-11-08 00:35:56,154 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2032 states and 2999 transitions. [2024-11-08 00:35:56,160 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1857 [2024-11-08 00:35:56,160 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:35:56,160 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:35:56,161 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:56,162 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:56,162 INFO L745 eck$LassoCheckResult]: Stem: 12558#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 12559#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 13545#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13546#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14245#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 13139#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13140#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 13210#L912-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 13211#L917-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 13648#L922-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 13649#L927-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 13174#L932-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 12979#L937-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 12980#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 13438#L947-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 13439#L952-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 13318#L957-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 13319#L962-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 12953#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12954#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 14169#L1279-2 assume !(0 == ~T1_E~0); 12579#L1284-1 assume !(0 == ~T2_E~0); 12580#L1289-1 assume !(0 == ~T3_E~0); 13315#L1294-1 assume !(0 == ~T4_E~0); 13316#L1299-1 assume !(0 == ~T5_E~0); 13327#L1304-1 assume !(0 == ~T6_E~0); 14244#L1309-1 assume !(0 == ~T7_E~0); 14246#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 12503#L1319-1 assume !(0 == ~T9_E~0); 12504#L1324-1 assume !(0 == ~T10_E~0); 12677#L1329-1 assume !(0 == ~T11_E~0); 12678#L1334-1 assume !(0 == ~T12_E~0); 14087#L1339-1 assume !(0 == ~T13_E~0); 14159#L1344-1 assume !(0 == ~E_M~0); 14160#L1349-1 assume !(0 == ~E_1~0); 13504#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 13505#L1359-1 assume !(0 == ~E_3~0); 13912#L1364-1 assume !(0 == ~E_4~0); 12803#L1369-1 assume !(0 == ~E_5~0); 12804#L1374-1 assume !(0 == ~E_6~0); 13511#L1379-1 assume !(0 == ~E_7~0); 13512#L1384-1 assume !(0 == ~E_8~0); 13589#L1389-1 assume !(0 == ~E_9~0); 14106#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 14107#L1399-1 assume !(0 == ~E_11~0); 14200#L1404-1 assume !(0 == ~E_12~0); 12901#L1409-1 assume !(0 == ~E_13~0); 12902#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14195#L628 assume !(1 == ~m_pc~0); 12802#L628-2 is_master_triggered_~__retres1~0#1 := 0; 12801#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13386#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13387#L1591 assume !(0 != activate_threads_~tmp~1#1); 14208#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13367#L647 assume 1 == ~t1_pc~0; 12727#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12728#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13418#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13875#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 14147#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14148#L666 assume 1 == ~t2_pc~0; 12576#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 12577#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12718#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12719#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 13700#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13701#L685 assume !(1 == ~t3_pc~0); 13795#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 13794#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13864#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 13553#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13554#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13027#L704 assume 1 == ~t4_pc~0; 13028#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13565#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12367#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12368#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 13416#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13417#L723 assume !(1 == ~t5_pc~0); 13549#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 13767#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13905#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 13679#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 13680#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12785#L742 assume 1 == ~t6_pc~0; 12786#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 12942#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12709#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12472#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 12473#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12863#L761 assume !(1 == ~t7_pc~0); 12864#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 12739#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12740#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 13556#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 13557#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12495#L780 assume 1 == ~t8_pc~0; 12496#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 12775#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12776#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 13518#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 13519#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13635#L799 assume 1 == ~t9_pc~0; 13737#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12498#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12499#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 12770#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 13838#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13661#L818 assume !(1 == ~t10_pc~0); 12282#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 12283#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 13730#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 13664#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 13665#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 13707#L837 assume 1 == ~t11_pc~0; 13708#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 13543#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 14151#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 13628#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 13629#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 13375#L856 assume !(1 == ~t12_pc~0); 13376#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 14010#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 12300#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 12301#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 13988#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 14172#L875 assume 1 == ~t13_pc~0; 13325#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 12943#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 12944#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 12881#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 12882#L1695-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13729#L1427 assume !(1 == ~M_E~0); 13714#L1427-2 assume !(1 == ~T1_E~0); 12850#L1432-1 assume !(1 == ~T2_E~0); 12851#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 13917#L1442-1 assume !(1 == ~T4_E~0); 13918#L1447-1 assume !(1 == ~T5_E~0); 13776#L1452-1 assume !(1 == ~T6_E~0); 12419#L1457-1 assume !(1 == ~T7_E~0); 12420#L1462-1 assume !(1 == ~T8_E~0); 13935#L1467-1 assume !(1 == ~T9_E~0); 13956#L1472-1 assume !(1 == ~T10_E~0); 13957#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 13725#L1482-1 assume !(1 == ~T12_E~0); 13726#L1487-1 assume !(1 == ~T13_E~0); 12750#L1492-1 assume !(1 == ~E_M~0); 12751#L1497-1 assume !(1 == ~E_1~0); 13121#L1502-1 assume !(1 == ~E_2~0); 13122#L1507-1 assume !(1 == ~E_3~0); 12627#L1512-1 assume !(1 == ~E_4~0); 12628#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 14029#L1522-1 assume !(1 == ~E_6~0); 13364#L1527-1 assume !(1 == ~E_7~0); 13365#L1532-1 assume !(1 == ~E_8~0); 14230#L1537-1 assume !(1 == ~E_9~0); 13572#L1542-1 assume !(1 == ~E_10~0); 13393#L1547-1 assume !(1 == ~E_11~0); 13394#L1552-1 assume !(1 == ~E_12~0); 12323#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 12324#L1562-1 assume { :end_inline_reset_delta_events } true; 12933#L1928-2 [2024-11-08 00:35:56,163 INFO L747 eck$LassoCheckResult]: Loop: 12933#L1928-2 assume !false; 13431#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13008#L1254-1 assume !false; 13240#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 12652#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 12653#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 12852#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 14015#L1067 assume !(0 != eval_~tmp~0#1); 13305#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12910#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12911#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 13141#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13125#L1284-3 assume !(0 == ~T2_E~0); 13126#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13106#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13107#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13499#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 13500#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 12987#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 12988#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 13978#L1324-3 assume !(0 == ~T10_E~0); 12625#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 12626#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 13399#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 13400#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 13704#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 12971#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12972#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 13712#L1364-3 assume !(0 == ~E_4~0); 14229#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 14121#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12754#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 12755#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12969#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 12970#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 13276#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 14131#L1404-3 assume !(0 == ~E_12~0); 14096#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 14097#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13601#L628-45 assume 1 == ~m_pc~0; 13271#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 13273#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13784#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13005#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 13006#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13736#L647-45 assume 1 == ~t1_pc~0; 12573#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12574#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13517#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12683#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12684#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12894#L666-45 assume 1 == ~t2_pc~0; 12896#L667-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13385#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13782#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13783#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 13848#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12435#L685-45 assume 1 == ~t3_pc~0; 12436#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 13513#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14161#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14027#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 14028#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14170#L704-45 assume 1 == ~t4_pc~0; 14051#L705-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12303#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13171#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14052#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 14258#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13630#L723-45 assume 1 == ~t5_pc~0; 13632#L724-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 14108#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14220#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12983#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 12984#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13998#L742-45 assume 1 == ~t6_pc~0; 13999#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13248#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13458#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 13459#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 13741#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13827#L761-45 assume !(1 == ~t7_pc~0); 13828#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 13242#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13243#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 12631#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 12632#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14100#L780-45 assume 1 == ~t8_pc~0; 13009#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 12642#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12643#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 14227#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 12611#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12612#L799-45 assume 1 == ~t9_pc~0; 13397#L800-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12831#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 13893#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 13777#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 13778#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 12553#L818-45 assume 1 == ~t10_pc~0; 12554#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 12671#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 13754#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 13169#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 13170#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 13873#L837-45 assume !(1 == ~t11_pc~0); 13099#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 13100#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 12623#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 12624#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 12692#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 12693#L856-45 assume !(1 == ~t12_pc~0); 12694#L856-47 is_transmit12_triggered_~__retres1~12#1 := 0; 12695#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 13924#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 13925#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 13515#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 13516#L875-45 assume 1 == ~t13_pc~0; 13483#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 13484#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 13544#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 13885#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 14141#L1695-47 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14085#L1427-3 assume !(1 == ~M_E~0); 13310#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13311#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 13835#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 13502#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 13503#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12340#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12341#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 14013#L1462-3 assume !(1 == ~T8_E~0); 14014#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 13881#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 13882#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 12595#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 12596#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 12738#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12908#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12909#L1502-3 assume !(1 == ~E_2~0); 13855#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 13976#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12947#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12635#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12636#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12602#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 12603#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 13713#L1542-3 assume !(1 == ~E_10~0); 13841#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 13486#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 13487#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 12806#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 12807#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 12228#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 12665#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 12666#L1947 assume !(0 == start_simulation_~tmp~3#1); 13619#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 13809#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 12867#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 12290#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 12291#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 13944#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 13945#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 14105#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 12933#L1928-2 [2024-11-08 00:35:56,163 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:56,163 INFO L85 PathProgramCache]: Analyzing trace with hash -992005239, now seen corresponding path program 1 times [2024-11-08 00:35:56,163 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:56,163 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [71572784] [2024-11-08 00:35:56,164 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:56,164 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:56,176 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:56,227 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:56,227 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:56,227 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [71572784] [2024-11-08 00:35:56,227 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [71572784] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:56,227 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:56,227 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:56,227 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1010654605] [2024-11-08 00:35:56,227 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:56,227 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:35:56,227 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:56,228 INFO L85 PathProgramCache]: Analyzing trace with hash -549053589, now seen corresponding path program 1 times [2024-11-08 00:35:56,228 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:56,228 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [456609282] [2024-11-08 00:35:56,228 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:56,228 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:56,245 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:56,304 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:56,304 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:56,304 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [456609282] [2024-11-08 00:35:56,305 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [456609282] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:56,305 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:56,305 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:56,305 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [395564459] [2024-11-08 00:35:56,305 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:56,305 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:35:56,305 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:35:56,305 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:35:56,305 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:35:56,305 INFO L87 Difference]: Start difference. First operand 2032 states and 2999 transitions. cyclomatic complexity: 968 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:56,332 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:35:56,332 INFO L93 Difference]: Finished difference Result 2032 states and 2998 transitions. [2024-11-08 00:35:56,332 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2032 states and 2998 transitions. [2024-11-08 00:35:56,341 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1857 [2024-11-08 00:35:56,347 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2032 states to 2032 states and 2998 transitions. [2024-11-08 00:35:56,347 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2032 [2024-11-08 00:35:56,348 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2032 [2024-11-08 00:35:56,348 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2032 states and 2998 transitions. [2024-11-08 00:35:56,350 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:35:56,350 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2032 states and 2998 transitions. [2024-11-08 00:35:56,352 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2032 states and 2998 transitions. [2024-11-08 00:35:56,368 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2032 to 2032. [2024-11-08 00:35:56,370 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2032 states, 2032 states have (on average 1.4753937007874016) internal successors, (2998), 2031 states have internal predecessors, (2998), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:56,375 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2032 states to 2032 states and 2998 transitions. [2024-11-08 00:35:56,375 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2032 states and 2998 transitions. [2024-11-08 00:35:56,376 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:35:56,376 INFO L425 stractBuchiCegarLoop]: Abstraction has 2032 states and 2998 transitions. [2024-11-08 00:35:56,376 INFO L332 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-11-08 00:35:56,376 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2032 states and 2998 transitions. [2024-11-08 00:35:56,382 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1857 [2024-11-08 00:35:56,382 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:35:56,382 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:35:56,384 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:56,384 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:56,384 INFO L745 eck$LassoCheckResult]: Stem: 16629#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 16630#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 17616#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 17617#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 18316#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 17210#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17211#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17281#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 17282#L917-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 17719#L922-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 17720#L927-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 17245#L932-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 17050#L937-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 17051#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 17509#L947-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 17510#L952-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 17389#L957-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 17390#L962-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 17024#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 17025#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 18240#L1279-2 assume !(0 == ~T1_E~0); 16650#L1284-1 assume !(0 == ~T2_E~0); 16651#L1289-1 assume !(0 == ~T3_E~0); 17386#L1294-1 assume !(0 == ~T4_E~0); 17387#L1299-1 assume !(0 == ~T5_E~0); 17398#L1304-1 assume !(0 == ~T6_E~0); 18315#L1309-1 assume !(0 == ~T7_E~0); 18317#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16574#L1319-1 assume !(0 == ~T9_E~0); 16575#L1324-1 assume !(0 == ~T10_E~0); 16748#L1329-1 assume !(0 == ~T11_E~0); 16749#L1334-1 assume !(0 == ~T12_E~0); 18158#L1339-1 assume !(0 == ~T13_E~0); 18230#L1344-1 assume !(0 == ~E_M~0); 18231#L1349-1 assume !(0 == ~E_1~0); 17575#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 17576#L1359-1 assume !(0 == ~E_3~0); 17983#L1364-1 assume !(0 == ~E_4~0); 16874#L1369-1 assume !(0 == ~E_5~0); 16875#L1374-1 assume !(0 == ~E_6~0); 17582#L1379-1 assume !(0 == ~E_7~0); 17583#L1384-1 assume !(0 == ~E_8~0); 17660#L1389-1 assume !(0 == ~E_9~0); 18177#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 18178#L1399-1 assume !(0 == ~E_11~0); 18271#L1404-1 assume !(0 == ~E_12~0); 16972#L1409-1 assume !(0 == ~E_13~0); 16973#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18266#L628 assume !(1 == ~m_pc~0); 16873#L628-2 is_master_triggered_~__retres1~0#1 := 0; 16872#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17457#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17458#L1591 assume !(0 != activate_threads_~tmp~1#1); 18279#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17438#L647 assume 1 == ~t1_pc~0; 16798#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 16799#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17489#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17946#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 18218#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18219#L666 assume 1 == ~t2_pc~0; 16647#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 16648#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16789#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16790#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 17771#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17772#L685 assume !(1 == ~t3_pc~0); 17866#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 17865#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17935#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17624#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17625#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17098#L704 assume 1 == ~t4_pc~0; 17099#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 17636#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16438#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 16439#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 17487#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17488#L723 assume !(1 == ~t5_pc~0); 17620#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 17838#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17976#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 17750#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 17751#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16856#L742 assume 1 == ~t6_pc~0; 16857#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 17013#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16780#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 16543#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 16544#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16934#L761 assume !(1 == ~t7_pc~0); 16935#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 16810#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16811#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 17627#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 17628#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16566#L780 assume 1 == ~t8_pc~0; 16567#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16846#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16847#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 17589#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 17590#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 17706#L799 assume 1 == ~t9_pc~0; 17808#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 16569#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 16570#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 16841#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 17909#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 17732#L818 assume !(1 == ~t10_pc~0); 16353#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 16354#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17801#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 17735#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 17736#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 17778#L837 assume 1 == ~t11_pc~0; 17779#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 17614#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 18222#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 17699#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 17700#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 17446#L856 assume !(1 == ~t12_pc~0); 17447#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 18081#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 16371#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 16372#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 18059#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 18243#L875 assume 1 == ~t13_pc~0; 17396#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 17014#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 17015#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 16952#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 16953#L1695-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17800#L1427 assume !(1 == ~M_E~0); 17785#L1427-2 assume !(1 == ~T1_E~0); 16921#L1432-1 assume !(1 == ~T2_E~0); 16922#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17988#L1442-1 assume !(1 == ~T4_E~0); 17989#L1447-1 assume !(1 == ~T5_E~0); 17847#L1452-1 assume !(1 == ~T6_E~0); 16490#L1457-1 assume !(1 == ~T7_E~0); 16491#L1462-1 assume !(1 == ~T8_E~0); 18006#L1467-1 assume !(1 == ~T9_E~0); 18027#L1472-1 assume !(1 == ~T10_E~0); 18028#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 17796#L1482-1 assume !(1 == ~T12_E~0); 17797#L1487-1 assume !(1 == ~T13_E~0); 16821#L1492-1 assume !(1 == ~E_M~0); 16822#L1497-1 assume !(1 == ~E_1~0); 17192#L1502-1 assume !(1 == ~E_2~0); 17193#L1507-1 assume !(1 == ~E_3~0); 16698#L1512-1 assume !(1 == ~E_4~0); 16699#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 18100#L1522-1 assume !(1 == ~E_6~0); 17435#L1527-1 assume !(1 == ~E_7~0); 17436#L1532-1 assume !(1 == ~E_8~0); 18301#L1537-1 assume !(1 == ~E_9~0); 17643#L1542-1 assume !(1 == ~E_10~0); 17464#L1547-1 assume !(1 == ~E_11~0); 17465#L1552-1 assume !(1 == ~E_12~0); 16394#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 16395#L1562-1 assume { :end_inline_reset_delta_events } true; 17004#L1928-2 [2024-11-08 00:35:56,387 INFO L747 eck$LassoCheckResult]: Loop: 17004#L1928-2 assume !false; 17502#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 17079#L1254-1 assume !false; 17311#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 16723#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 16724#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 16923#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 18086#L1067 assume !(0 != eval_~tmp~0#1); 17376#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 16981#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 16982#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 17212#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 17196#L1284-3 assume !(0 == ~T2_E~0); 17197#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 17177#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17178#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 17570#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 17571#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 17058#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 17059#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 18049#L1324-3 assume !(0 == ~T10_E~0); 16696#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 16697#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 17470#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 17471#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 17775#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 17042#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 17043#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 17783#L1364-3 assume !(0 == ~E_4~0); 18300#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 18192#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 16825#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 16826#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 17040#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 17041#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 17347#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 18202#L1404-3 assume !(0 == ~E_12~0); 18167#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 18168#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17672#L628-45 assume 1 == ~m_pc~0; 17342#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 17344#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17855#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17076#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 17077#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17807#L647-45 assume 1 == ~t1_pc~0; 16644#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 16645#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17588#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16754#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 16755#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16965#L666-45 assume !(1 == ~t2_pc~0); 16966#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 17456#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17853#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17854#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 17919#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16506#L685-45 assume 1 == ~t3_pc~0; 16507#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 17584#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18232#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 18098#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 18099#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 18241#L704-45 assume !(1 == ~t4_pc~0); 16373#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 16374#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17242#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 18123#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 18329#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17701#L723-45 assume !(1 == ~t5_pc~0); 17702#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 18179#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18291#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 17054#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 17055#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18069#L742-45 assume 1 == ~t6_pc~0; 18070#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 17319#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17529#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 17530#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 17812#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17898#L761-45 assume !(1 == ~t7_pc~0); 17899#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 17313#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17314#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 16702#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 16703#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18171#L780-45 assume 1 == ~t8_pc~0; 17080#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16713#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16714#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 18298#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 16682#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16683#L799-45 assume !(1 == ~t9_pc~0); 16901#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 16902#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17964#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 17848#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 17849#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 16624#L818-45 assume 1 == ~t10_pc~0; 16625#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 16742#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17825#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 17240#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 17241#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 17944#L837-45 assume !(1 == ~t11_pc~0); 17170#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 17171#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 16694#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 16695#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 16763#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 16764#L856-45 assume !(1 == ~t12_pc~0); 16765#L856-47 is_transmit12_triggered_~__retres1~12#1 := 0; 16766#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 17995#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 17996#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 17586#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 17587#L875-45 assume 1 == ~t13_pc~0; 17554#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 17555#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 17615#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 17956#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 18212#L1695-47 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18156#L1427-3 assume !(1 == ~M_E~0); 17381#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17382#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17906#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17573#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 17574#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 16411#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 16412#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 18084#L1462-3 assume !(1 == ~T8_E~0); 18085#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 17952#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 17953#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 16666#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 16667#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 16809#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 16979#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 16980#L1502-3 assume !(1 == ~E_2~0); 17926#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 18047#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 17018#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 16706#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 16707#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 16673#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 16674#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 17784#L1542-3 assume !(1 == ~E_10~0); 17912#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 17557#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 17558#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 16877#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 16878#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 16299#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 16736#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 16737#L1947 assume !(0 == start_simulation_~tmp~3#1); 17690#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 17880#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 16938#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 16361#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 16362#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 18015#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 18016#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 18176#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 17004#L1928-2 [2024-11-08 00:35:56,387 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:56,388 INFO L85 PathProgramCache]: Analyzing trace with hash -380736181, now seen corresponding path program 1 times [2024-11-08 00:35:56,388 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:56,388 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [260616165] [2024-11-08 00:35:56,388 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:56,388 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:56,428 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:56,467 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:56,467 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:56,467 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [260616165] [2024-11-08 00:35:56,467 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [260616165] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:56,468 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:56,468 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:56,468 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1455002851] [2024-11-08 00:35:56,468 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:56,468 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:35:56,468 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:56,468 INFO L85 PathProgramCache]: Analyzing trace with hash 1650149743, now seen corresponding path program 1 times [2024-11-08 00:35:56,468 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:56,468 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1650412767] [2024-11-08 00:35:56,468 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:56,468 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:56,482 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:56,531 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:56,531 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:56,531 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1650412767] [2024-11-08 00:35:56,531 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1650412767] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:56,531 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:56,531 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:56,531 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1247081628] [2024-11-08 00:35:56,531 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:56,532 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:35:56,532 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:35:56,532 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:35:56,532 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:35:56,532 INFO L87 Difference]: Start difference. First operand 2032 states and 2998 transitions. cyclomatic complexity: 967 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:56,557 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:35:56,557 INFO L93 Difference]: Finished difference Result 2032 states and 2997 transitions. [2024-11-08 00:35:56,557 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2032 states and 2997 transitions. [2024-11-08 00:35:56,563 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1857 [2024-11-08 00:35:56,569 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2032 states to 2032 states and 2997 transitions. [2024-11-08 00:35:56,569 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2032 [2024-11-08 00:35:56,570 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2032 [2024-11-08 00:35:56,570 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2032 states and 2997 transitions. [2024-11-08 00:35:56,572 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:35:56,572 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2032 states and 2997 transitions. [2024-11-08 00:35:56,574 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2032 states and 2997 transitions. [2024-11-08 00:35:56,588 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2032 to 2032. [2024-11-08 00:35:56,590 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2032 states, 2032 states have (on average 1.4749015748031495) internal successors, (2997), 2031 states have internal predecessors, (2997), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:56,594 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2032 states to 2032 states and 2997 transitions. [2024-11-08 00:35:56,594 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2032 states and 2997 transitions. [2024-11-08 00:35:56,594 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:35:56,595 INFO L425 stractBuchiCegarLoop]: Abstraction has 2032 states and 2997 transitions. [2024-11-08 00:35:56,595 INFO L332 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-11-08 00:35:56,595 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2032 states and 2997 transitions. [2024-11-08 00:35:56,600 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1857 [2024-11-08 00:35:56,600 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:35:56,600 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:35:56,601 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:56,601 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:56,602 INFO L745 eck$LassoCheckResult]: Stem: 20700#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 20701#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 21687#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 21688#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 22387#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 21281#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21282#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21352#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21353#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 21790#L922-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 21791#L927-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 21316#L932-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 21121#L937-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 21122#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 21580#L947-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 21581#L952-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 21460#L957-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 21461#L962-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 21095#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 21096#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 22311#L1279-2 assume !(0 == ~T1_E~0); 20721#L1284-1 assume !(0 == ~T2_E~0); 20722#L1289-1 assume !(0 == ~T3_E~0); 21457#L1294-1 assume !(0 == ~T4_E~0); 21458#L1299-1 assume !(0 == ~T5_E~0); 21469#L1304-1 assume !(0 == ~T6_E~0); 22386#L1309-1 assume !(0 == ~T7_E~0); 22388#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 20645#L1319-1 assume !(0 == ~T9_E~0); 20646#L1324-1 assume !(0 == ~T10_E~0); 20819#L1329-1 assume !(0 == ~T11_E~0); 20820#L1334-1 assume !(0 == ~T12_E~0); 22229#L1339-1 assume !(0 == ~T13_E~0); 22301#L1344-1 assume !(0 == ~E_M~0); 22302#L1349-1 assume !(0 == ~E_1~0); 21646#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 21647#L1359-1 assume !(0 == ~E_3~0); 22054#L1364-1 assume !(0 == ~E_4~0); 20945#L1369-1 assume !(0 == ~E_5~0); 20946#L1374-1 assume !(0 == ~E_6~0); 21653#L1379-1 assume !(0 == ~E_7~0); 21654#L1384-1 assume !(0 == ~E_8~0); 21731#L1389-1 assume !(0 == ~E_9~0); 22248#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 22249#L1399-1 assume !(0 == ~E_11~0); 22342#L1404-1 assume !(0 == ~E_12~0); 21043#L1409-1 assume !(0 == ~E_13~0); 21044#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22337#L628 assume !(1 == ~m_pc~0); 20944#L628-2 is_master_triggered_~__retres1~0#1 := 0; 20943#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21528#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 21529#L1591 assume !(0 != activate_threads_~tmp~1#1); 22350#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21509#L647 assume 1 == ~t1_pc~0; 20869#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 20870#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21560#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 22017#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 22289#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22290#L666 assume 1 == ~t2_pc~0; 20718#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 20719#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20860#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20861#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 21842#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21843#L685 assume !(1 == ~t3_pc~0); 21937#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 21936#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22006#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 21695#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 21696#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21169#L704 assume 1 == ~t4_pc~0; 21170#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21707#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20509#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20510#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 21558#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 21559#L723 assume !(1 == ~t5_pc~0); 21691#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 21909#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22047#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21821#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 21822#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 20927#L742 assume 1 == ~t6_pc~0; 20928#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 21084#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 20851#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 20614#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 20615#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 21005#L761 assume !(1 == ~t7_pc~0); 21006#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 20881#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20882#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 21698#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 21699#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20637#L780 assume 1 == ~t8_pc~0; 20638#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 20917#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20918#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 21660#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 21661#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 21777#L799 assume 1 == ~t9_pc~0; 21879#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 20640#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 20641#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 20912#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 21980#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21803#L818 assume !(1 == ~t10_pc~0); 20424#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 20425#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 21872#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 21806#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 21807#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 21849#L837 assume 1 == ~t11_pc~0; 21850#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 21685#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 22293#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 21770#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 21771#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 21517#L856 assume !(1 == ~t12_pc~0); 21518#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 22152#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 20442#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 20443#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 22130#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 22314#L875 assume 1 == ~t13_pc~0; 21467#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 21085#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 21086#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 21023#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 21024#L1695-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21871#L1427 assume !(1 == ~M_E~0); 21856#L1427-2 assume !(1 == ~T1_E~0); 20992#L1432-1 assume !(1 == ~T2_E~0); 20993#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 22059#L1442-1 assume !(1 == ~T4_E~0); 22060#L1447-1 assume !(1 == ~T5_E~0); 21918#L1452-1 assume !(1 == ~T6_E~0); 20561#L1457-1 assume !(1 == ~T7_E~0); 20562#L1462-1 assume !(1 == ~T8_E~0); 22077#L1467-1 assume !(1 == ~T9_E~0); 22098#L1472-1 assume !(1 == ~T10_E~0); 22099#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 21867#L1482-1 assume !(1 == ~T12_E~0); 21868#L1487-1 assume !(1 == ~T13_E~0); 20892#L1492-1 assume !(1 == ~E_M~0); 20893#L1497-1 assume !(1 == ~E_1~0); 21263#L1502-1 assume !(1 == ~E_2~0); 21264#L1507-1 assume !(1 == ~E_3~0); 20769#L1512-1 assume !(1 == ~E_4~0); 20770#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 22171#L1522-1 assume !(1 == ~E_6~0); 21506#L1527-1 assume !(1 == ~E_7~0); 21507#L1532-1 assume !(1 == ~E_8~0); 22372#L1537-1 assume !(1 == ~E_9~0); 21714#L1542-1 assume !(1 == ~E_10~0); 21535#L1547-1 assume !(1 == ~E_11~0); 21536#L1552-1 assume !(1 == ~E_12~0); 20465#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 20466#L1562-1 assume { :end_inline_reset_delta_events } true; 21075#L1928-2 [2024-11-08 00:35:56,602 INFO L747 eck$LassoCheckResult]: Loop: 21075#L1928-2 assume !false; 21573#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 21150#L1254-1 assume !false; 21382#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 20794#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 20795#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 20994#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 22157#L1067 assume !(0 != eval_~tmp~0#1); 21447#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 21052#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 21053#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 21283#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 21267#L1284-3 assume !(0 == ~T2_E~0); 21268#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 21248#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 21249#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 21641#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 21642#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 21129#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 21130#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 22120#L1324-3 assume !(0 == ~T10_E~0); 20767#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 20768#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 21541#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 21542#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 21846#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 21113#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 21114#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 21854#L1364-3 assume !(0 == ~E_4~0); 22371#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 22263#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 20896#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 20897#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 21111#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 21112#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 21418#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 22273#L1404-3 assume !(0 == ~E_12~0); 22238#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 22239#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21743#L628-45 assume 1 == ~m_pc~0; 21413#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 21415#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21926#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 21147#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 21148#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21878#L647-45 assume 1 == ~t1_pc~0; 20715#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 20716#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21659#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 20825#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 20826#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21036#L666-45 assume !(1 == ~t2_pc~0); 21037#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 21527#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21924#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 21925#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 21990#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20577#L685-45 assume 1 == ~t3_pc~0; 20578#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 21655#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22303#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22169#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 22170#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22312#L704-45 assume 1 == ~t4_pc~0; 22193#L705-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 20445#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21313#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 22194#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 22400#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 21772#L723-45 assume !(1 == ~t5_pc~0); 21773#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 22250#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22362#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21125#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 21126#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22140#L742-45 assume 1 == ~t6_pc~0; 22141#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 21390#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21600#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 21601#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 21883#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 21969#L761-45 assume !(1 == ~t7_pc~0); 21970#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 21384#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 21385#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 20773#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 20774#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 22242#L780-45 assume !(1 == ~t8_pc~0); 21152#L780-47 is_transmit8_triggered_~__retres1~8#1 := 0; 20784#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20785#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 22369#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 20753#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 20754#L799-45 assume 1 == ~t9_pc~0; 21539#L800-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 20973#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 22035#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 21919#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 21920#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 20695#L818-45 assume 1 == ~t10_pc~0; 20696#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 20813#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 21896#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 21311#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 21312#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 22015#L837-45 assume !(1 == ~t11_pc~0); 21241#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 21242#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 20765#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 20766#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 20834#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 20835#L856-45 assume !(1 == ~t12_pc~0); 20836#L856-47 is_transmit12_triggered_~__retres1~12#1 := 0; 20837#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 22066#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 22067#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 21657#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 21658#L875-45 assume 1 == ~t13_pc~0; 21625#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 21626#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 21686#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 22027#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 22283#L1695-47 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22227#L1427-3 assume !(1 == ~M_E~0); 21452#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 21453#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 21977#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 21644#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 21645#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 20482#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 20483#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 22155#L1462-3 assume !(1 == ~T8_E~0); 22156#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 22023#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 22024#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 20737#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 20738#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 20880#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 21050#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 21051#L1502-3 assume !(1 == ~E_2~0); 21997#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 22118#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 21089#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 20777#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 20778#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 20744#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 20745#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 21855#L1542-3 assume !(1 == ~E_10~0); 21983#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 21628#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 21629#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 20948#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 20949#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 20370#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 20807#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 20808#L1947 assume !(0 == start_simulation_~tmp~3#1); 21761#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 21951#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 21009#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 20432#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 20433#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 22086#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 22087#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 22247#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 21075#L1928-2 [2024-11-08 00:35:56,602 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:56,602 INFO L85 PathProgramCache]: Analyzing trace with hash 1024455497, now seen corresponding path program 1 times [2024-11-08 00:35:56,602 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:56,602 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [817991118] [2024-11-08 00:35:56,602 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:56,602 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:56,612 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:56,634 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:56,636 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:56,636 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [817991118] [2024-11-08 00:35:56,636 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [817991118] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:56,636 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:56,636 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:56,636 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1905868035] [2024-11-08 00:35:56,636 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:56,637 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:35:56,637 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:56,637 INFO L85 PathProgramCache]: Analyzing trace with hash -1501818386, now seen corresponding path program 1 times [2024-11-08 00:35:56,637 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:56,637 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1636814278] [2024-11-08 00:35:56,637 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:56,637 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:56,649 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:56,684 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:56,685 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:56,685 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1636814278] [2024-11-08 00:35:56,685 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1636814278] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:56,685 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:56,685 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:56,685 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [620828449] [2024-11-08 00:35:56,685 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:56,685 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:35:56,685 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:35:56,686 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:35:56,686 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:35:56,686 INFO L87 Difference]: Start difference. First operand 2032 states and 2997 transitions. cyclomatic complexity: 966 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:56,712 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:35:56,713 INFO L93 Difference]: Finished difference Result 2032 states and 2996 transitions. [2024-11-08 00:35:56,713 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2032 states and 2996 transitions. [2024-11-08 00:35:56,721 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1857 [2024-11-08 00:35:56,727 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2032 states to 2032 states and 2996 transitions. [2024-11-08 00:35:56,728 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2032 [2024-11-08 00:35:56,729 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2032 [2024-11-08 00:35:56,729 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2032 states and 2996 transitions. [2024-11-08 00:35:56,731 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:35:56,731 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2032 states and 2996 transitions. [2024-11-08 00:35:56,733 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2032 states and 2996 transitions. [2024-11-08 00:35:56,774 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2032 to 2032. [2024-11-08 00:35:56,776 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2032 states, 2032 states have (on average 1.4744094488188977) internal successors, (2996), 2031 states have internal predecessors, (2996), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:56,779 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2032 states to 2032 states and 2996 transitions. [2024-11-08 00:35:56,779 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2032 states and 2996 transitions. [2024-11-08 00:35:56,780 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:35:56,780 INFO L425 stractBuchiCegarLoop]: Abstraction has 2032 states and 2996 transitions. [2024-11-08 00:35:56,780 INFO L332 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-11-08 00:35:56,780 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2032 states and 2996 transitions. [2024-11-08 00:35:56,785 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1857 [2024-11-08 00:35:56,785 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:35:56,785 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:35:56,786 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:56,786 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:56,787 INFO L745 eck$LassoCheckResult]: Stem: 24771#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 24772#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 25758#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 25759#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 26458#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 25352#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 25353#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25423#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 25424#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 25861#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 25862#L927-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 25387#L932-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 25192#L937-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 25193#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 25651#L947-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 25652#L952-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 25531#L957-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 25532#L962-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 25166#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 25167#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 26382#L1279-2 assume !(0 == ~T1_E~0); 24792#L1284-1 assume !(0 == ~T2_E~0); 24793#L1289-1 assume !(0 == ~T3_E~0); 25528#L1294-1 assume !(0 == ~T4_E~0); 25529#L1299-1 assume !(0 == ~T5_E~0); 25540#L1304-1 assume !(0 == ~T6_E~0); 26457#L1309-1 assume !(0 == ~T7_E~0); 26459#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 24716#L1319-1 assume !(0 == ~T9_E~0); 24717#L1324-1 assume !(0 == ~T10_E~0); 24890#L1329-1 assume !(0 == ~T11_E~0); 24891#L1334-1 assume !(0 == ~T12_E~0); 26300#L1339-1 assume !(0 == ~T13_E~0); 26372#L1344-1 assume !(0 == ~E_M~0); 26373#L1349-1 assume !(0 == ~E_1~0); 25717#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 25718#L1359-1 assume !(0 == ~E_3~0); 26125#L1364-1 assume !(0 == ~E_4~0); 25016#L1369-1 assume !(0 == ~E_5~0); 25017#L1374-1 assume !(0 == ~E_6~0); 25724#L1379-1 assume !(0 == ~E_7~0); 25725#L1384-1 assume !(0 == ~E_8~0); 25802#L1389-1 assume !(0 == ~E_9~0); 26319#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 26320#L1399-1 assume !(0 == ~E_11~0); 26413#L1404-1 assume !(0 == ~E_12~0); 25114#L1409-1 assume !(0 == ~E_13~0); 25115#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26408#L628 assume !(1 == ~m_pc~0); 25015#L628-2 is_master_triggered_~__retres1~0#1 := 0; 25014#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25599#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 25600#L1591 assume !(0 != activate_threads_~tmp~1#1); 26421#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25580#L647 assume 1 == ~t1_pc~0; 24940#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 24941#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25631#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 26088#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 26360#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26361#L666 assume 1 == ~t2_pc~0; 24789#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 24790#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24931#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 24932#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 25913#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25914#L685 assume !(1 == ~t3_pc~0); 26008#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 26007#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26077#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25766#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 25767#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25240#L704 assume 1 == ~t4_pc~0; 25241#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 25778#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24580#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 24581#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 25629#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25630#L723 assume !(1 == ~t5_pc~0); 25762#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 25980#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26118#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25892#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 25893#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 24998#L742 assume 1 == ~t6_pc~0; 24999#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 25155#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 24922#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 24685#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 24686#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25076#L761 assume !(1 == ~t7_pc~0); 25077#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 24952#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 24953#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 25769#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 25770#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 24708#L780 assume 1 == ~t8_pc~0; 24709#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 24988#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 24989#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 25731#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 25732#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 25848#L799 assume 1 == ~t9_pc~0; 25950#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 24711#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 24712#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 24983#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 26051#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25874#L818 assume !(1 == ~t10_pc~0); 24495#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 24496#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25943#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 25877#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 25878#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 25920#L837 assume 1 == ~t11_pc~0; 25921#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 25756#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 26364#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 25841#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 25842#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 25588#L856 assume !(1 == ~t12_pc~0); 25589#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 26223#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 24513#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 24514#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 26201#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 26385#L875 assume 1 == ~t13_pc~0; 25538#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 25156#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 25157#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 25094#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 25095#L1695-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25942#L1427 assume !(1 == ~M_E~0); 25927#L1427-2 assume !(1 == ~T1_E~0); 25063#L1432-1 assume !(1 == ~T2_E~0); 25064#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 26130#L1442-1 assume !(1 == ~T4_E~0); 26131#L1447-1 assume !(1 == ~T5_E~0); 25989#L1452-1 assume !(1 == ~T6_E~0); 24632#L1457-1 assume !(1 == ~T7_E~0); 24633#L1462-1 assume !(1 == ~T8_E~0); 26148#L1467-1 assume !(1 == ~T9_E~0); 26169#L1472-1 assume !(1 == ~T10_E~0); 26170#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 25938#L1482-1 assume !(1 == ~T12_E~0); 25939#L1487-1 assume !(1 == ~T13_E~0); 24963#L1492-1 assume !(1 == ~E_M~0); 24964#L1497-1 assume !(1 == ~E_1~0); 25334#L1502-1 assume !(1 == ~E_2~0); 25335#L1507-1 assume !(1 == ~E_3~0); 24840#L1512-1 assume !(1 == ~E_4~0); 24841#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 26242#L1522-1 assume !(1 == ~E_6~0); 25577#L1527-1 assume !(1 == ~E_7~0); 25578#L1532-1 assume !(1 == ~E_8~0); 26443#L1537-1 assume !(1 == ~E_9~0); 25785#L1542-1 assume !(1 == ~E_10~0); 25606#L1547-1 assume !(1 == ~E_11~0); 25607#L1552-1 assume !(1 == ~E_12~0); 24536#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 24537#L1562-1 assume { :end_inline_reset_delta_events } true; 25146#L1928-2 [2024-11-08 00:35:56,787 INFO L747 eck$LassoCheckResult]: Loop: 25146#L1928-2 assume !false; 25644#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 25221#L1254-1 assume !false; 25453#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 24865#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 24866#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 25065#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 26228#L1067 assume !(0 != eval_~tmp~0#1); 25518#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25123#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25124#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 25354#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 25338#L1284-3 assume !(0 == ~T2_E~0); 25339#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25319#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 25320#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 25712#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 25713#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 25200#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 25201#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 26191#L1324-3 assume !(0 == ~T10_E~0); 24838#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 24839#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 25612#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 25613#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 25917#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 25184#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 25185#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 25925#L1364-3 assume !(0 == ~E_4~0); 26442#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 26334#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 24967#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 24968#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 25182#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 25183#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 25489#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 26344#L1404-3 assume !(0 == ~E_12~0); 26309#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 26310#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25814#L628-45 assume 1 == ~m_pc~0; 25484#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 25486#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25997#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 25218#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 25219#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25949#L647-45 assume 1 == ~t1_pc~0; 24786#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 24787#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25730#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24896#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 24897#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25107#L666-45 assume !(1 == ~t2_pc~0); 25108#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 25598#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25995#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25996#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 26061#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24648#L685-45 assume 1 == ~t3_pc~0; 24649#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 25726#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26374#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 26240#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 26241#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26383#L704-45 assume !(1 == ~t4_pc~0); 24515#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 24516#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25384#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 26265#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 26471#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25843#L723-45 assume !(1 == ~t5_pc~0); 25844#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 26321#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26433#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25196#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 25197#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26211#L742-45 assume 1 == ~t6_pc~0; 26212#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 25461#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25671#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 25672#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 25954#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 26040#L761-45 assume !(1 == ~t7_pc~0); 26041#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 25455#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25456#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 24844#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 24845#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 26313#L780-45 assume 1 == ~t8_pc~0; 25222#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 24855#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 24856#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 26440#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 24824#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24825#L799-45 assume !(1 == ~t9_pc~0); 25043#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 25044#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 26106#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 25990#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 25991#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 24766#L818-45 assume !(1 == ~t10_pc~0); 24768#L818-47 is_transmit10_triggered_~__retres1~10#1 := 0; 24884#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25967#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 25382#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 25383#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 26086#L837-45 assume !(1 == ~t11_pc~0); 25312#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 25313#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 24836#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 24837#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 24905#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 24906#L856-45 assume !(1 == ~t12_pc~0); 24907#L856-47 is_transmit12_triggered_~__retres1~12#1 := 0; 24908#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 26137#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 26138#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 25728#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 25729#L875-45 assume 1 == ~t13_pc~0; 25696#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 25697#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 25757#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 26098#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 26354#L1695-47 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26298#L1427-3 assume !(1 == ~M_E~0); 25523#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 25524#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 26048#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 25715#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 25716#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 24553#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 24554#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 26226#L1462-3 assume !(1 == ~T8_E~0); 26227#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 26094#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 26095#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 24808#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 24809#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 24951#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 25121#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 25122#L1502-3 assume !(1 == ~E_2~0); 26068#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 26189#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 25160#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 24848#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 24849#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 24815#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 24816#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 25926#L1542-3 assume !(1 == ~E_10~0); 26054#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 25699#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 25700#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 25019#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 25020#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 24441#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 24878#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 24879#L1947 assume !(0 == start_simulation_~tmp~3#1); 25832#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 26022#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 25080#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 24503#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 24504#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 26157#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 26158#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 26318#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 25146#L1928-2 [2024-11-08 00:35:56,787 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:56,788 INFO L85 PathProgramCache]: Analyzing trace with hash -869878389, now seen corresponding path program 1 times [2024-11-08 00:35:56,788 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:56,788 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1925985850] [2024-11-08 00:35:56,788 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:56,788 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:56,797 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:56,821 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:56,822 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:56,822 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1925985850] [2024-11-08 00:35:56,822 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1925985850] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:56,822 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:56,822 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:56,822 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [295893714] [2024-11-08 00:35:56,822 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:56,822 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:35:56,823 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:56,823 INFO L85 PathProgramCache]: Analyzing trace with hash 2027792560, now seen corresponding path program 1 times [2024-11-08 00:35:56,823 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:56,823 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [367542218] [2024-11-08 00:35:56,823 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:56,823 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:56,833 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:56,868 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:56,868 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:56,869 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [367542218] [2024-11-08 00:35:56,869 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [367542218] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:56,869 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:56,869 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:56,869 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [735907764] [2024-11-08 00:35:56,869 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:56,869 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:35:56,869 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:35:56,870 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:35:56,870 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:35:56,870 INFO L87 Difference]: Start difference. First operand 2032 states and 2996 transitions. cyclomatic complexity: 965 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:56,897 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:35:56,897 INFO L93 Difference]: Finished difference Result 2032 states and 2995 transitions. [2024-11-08 00:35:56,897 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2032 states and 2995 transitions. [2024-11-08 00:35:56,904 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1857 [2024-11-08 00:35:56,910 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2032 states to 2032 states and 2995 transitions. [2024-11-08 00:35:56,911 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2032 [2024-11-08 00:35:56,912 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2032 [2024-11-08 00:35:56,912 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2032 states and 2995 transitions. [2024-11-08 00:35:56,914 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:35:56,914 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2032 states and 2995 transitions. [2024-11-08 00:35:56,916 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2032 states and 2995 transitions. [2024-11-08 00:35:56,932 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2032 to 2032. [2024-11-08 00:35:56,935 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2032 states, 2032 states have (on average 1.4739173228346456) internal successors, (2995), 2031 states have internal predecessors, (2995), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:56,939 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2032 states to 2032 states and 2995 transitions. [2024-11-08 00:35:56,939 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2032 states and 2995 transitions. [2024-11-08 00:35:56,940 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:35:56,940 INFO L425 stractBuchiCegarLoop]: Abstraction has 2032 states and 2995 transitions. [2024-11-08 00:35:56,940 INFO L332 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-11-08 00:35:56,940 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2032 states and 2995 transitions. [2024-11-08 00:35:56,945 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1857 [2024-11-08 00:35:56,946 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:35:56,946 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:35:56,947 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:56,947 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:56,948 INFO L745 eck$LassoCheckResult]: Stem: 28842#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 28843#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 29829#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 29830#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 30529#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 29423#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 29424#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 29494#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 29495#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 29932#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 29933#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 29458#L932-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 29263#L937-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 29264#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 29722#L947-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 29723#L952-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 29602#L957-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 29603#L962-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 29237#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 29238#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 30453#L1279-2 assume !(0 == ~T1_E~0); 28863#L1284-1 assume !(0 == ~T2_E~0); 28864#L1289-1 assume !(0 == ~T3_E~0); 29599#L1294-1 assume !(0 == ~T4_E~0); 29600#L1299-1 assume !(0 == ~T5_E~0); 29611#L1304-1 assume !(0 == ~T6_E~0); 30528#L1309-1 assume !(0 == ~T7_E~0); 30530#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 28787#L1319-1 assume !(0 == ~T9_E~0); 28788#L1324-1 assume !(0 == ~T10_E~0); 28961#L1329-1 assume !(0 == ~T11_E~0); 28962#L1334-1 assume !(0 == ~T12_E~0); 30371#L1339-1 assume !(0 == ~T13_E~0); 30443#L1344-1 assume !(0 == ~E_M~0); 30444#L1349-1 assume !(0 == ~E_1~0); 29788#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 29789#L1359-1 assume !(0 == ~E_3~0); 30196#L1364-1 assume !(0 == ~E_4~0); 29087#L1369-1 assume !(0 == ~E_5~0); 29088#L1374-1 assume !(0 == ~E_6~0); 29795#L1379-1 assume !(0 == ~E_7~0); 29796#L1384-1 assume !(0 == ~E_8~0); 29873#L1389-1 assume !(0 == ~E_9~0); 30390#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 30391#L1399-1 assume !(0 == ~E_11~0); 30484#L1404-1 assume !(0 == ~E_12~0); 29185#L1409-1 assume !(0 == ~E_13~0); 29186#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30479#L628 assume !(1 == ~m_pc~0); 29086#L628-2 is_master_triggered_~__retres1~0#1 := 0; 29085#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29670#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29671#L1591 assume !(0 != activate_threads_~tmp~1#1); 30492#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29651#L647 assume 1 == ~t1_pc~0; 29011#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 29012#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29702#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 30159#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 30431#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30432#L666 assume 1 == ~t2_pc~0; 28860#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 28861#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29002#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29003#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 29984#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29985#L685 assume !(1 == ~t3_pc~0); 30079#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 30078#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30148#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 29837#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 29838#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29311#L704 assume 1 == ~t4_pc~0; 29312#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 29849#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28651#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 28652#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 29700#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29701#L723 assume !(1 == ~t5_pc~0); 29833#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 30051#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30189#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 29963#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 29964#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29069#L742 assume 1 == ~t6_pc~0; 29070#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 29226#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 28993#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 28756#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 28757#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29147#L761 assume !(1 == ~t7_pc~0); 29148#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 29023#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29024#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29840#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 29841#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 28779#L780 assume 1 == ~t8_pc~0; 28780#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 29059#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 29060#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 29802#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 29803#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29919#L799 assume 1 == ~t9_pc~0; 30021#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 28782#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 28783#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 29054#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 30122#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29945#L818 assume !(1 == ~t10_pc~0); 28566#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 28567#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 30014#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 29948#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 29949#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 29991#L837 assume 1 == ~t11_pc~0; 29992#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 29827#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 30435#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 29912#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 29913#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 29659#L856 assume !(1 == ~t12_pc~0); 29660#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 30294#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 28584#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 28585#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 30272#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 30456#L875 assume 1 == ~t13_pc~0; 29609#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 29227#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 29228#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 29165#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 29166#L1695-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30013#L1427 assume !(1 == ~M_E~0); 29998#L1427-2 assume !(1 == ~T1_E~0); 29134#L1432-1 assume !(1 == ~T2_E~0); 29135#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 30201#L1442-1 assume !(1 == ~T4_E~0); 30202#L1447-1 assume !(1 == ~T5_E~0); 30060#L1452-1 assume !(1 == ~T6_E~0); 28703#L1457-1 assume !(1 == ~T7_E~0); 28704#L1462-1 assume !(1 == ~T8_E~0); 30219#L1467-1 assume !(1 == ~T9_E~0); 30240#L1472-1 assume !(1 == ~T10_E~0); 30241#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 30009#L1482-1 assume !(1 == ~T12_E~0); 30010#L1487-1 assume !(1 == ~T13_E~0); 29034#L1492-1 assume !(1 == ~E_M~0); 29035#L1497-1 assume !(1 == ~E_1~0); 29405#L1502-1 assume !(1 == ~E_2~0); 29406#L1507-1 assume !(1 == ~E_3~0); 28911#L1512-1 assume !(1 == ~E_4~0); 28912#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 30313#L1522-1 assume !(1 == ~E_6~0); 29648#L1527-1 assume !(1 == ~E_7~0); 29649#L1532-1 assume !(1 == ~E_8~0); 30514#L1537-1 assume !(1 == ~E_9~0); 29856#L1542-1 assume !(1 == ~E_10~0); 29677#L1547-1 assume !(1 == ~E_11~0); 29678#L1552-1 assume !(1 == ~E_12~0); 28607#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 28608#L1562-1 assume { :end_inline_reset_delta_events } true; 29217#L1928-2 [2024-11-08 00:35:56,948 INFO L747 eck$LassoCheckResult]: Loop: 29217#L1928-2 assume !false; 29715#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 29292#L1254-1 assume !false; 29524#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 28936#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 28937#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 29136#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 30299#L1067 assume !(0 != eval_~tmp~0#1); 29589#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 29194#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 29195#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 29425#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 29409#L1284-3 assume !(0 == ~T2_E~0); 29410#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 29390#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 29391#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 29783#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 29784#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 29271#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 29272#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 30262#L1324-3 assume !(0 == ~T10_E~0); 28909#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 28910#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 29683#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 29684#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 29988#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 29255#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 29256#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 29996#L1364-3 assume !(0 == ~E_4~0); 30513#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 30405#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 29038#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 29039#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 29253#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 29254#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 29560#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 30415#L1404-3 assume !(0 == ~E_12~0); 30380#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 30381#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29885#L628-45 assume 1 == ~m_pc~0; 29555#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 29557#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30068#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29289#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 29290#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30020#L647-45 assume 1 == ~t1_pc~0; 28857#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 28858#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29801#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 28967#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 28968#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29178#L666-45 assume !(1 == ~t2_pc~0); 29179#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 29669#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 30066#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 30067#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 30132#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28719#L685-45 assume 1 == ~t3_pc~0; 28720#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 29797#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30445#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 30311#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 30312#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30454#L704-45 assume !(1 == ~t4_pc~0); 28586#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 28587#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29455#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 30336#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 30542#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29914#L723-45 assume !(1 == ~t5_pc~0); 29915#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 30392#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30504#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 29267#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 29268#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 30282#L742-45 assume 1 == ~t6_pc~0; 30283#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 29532#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29742#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29743#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 30025#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 30111#L761-45 assume !(1 == ~t7_pc~0); 30112#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 29526#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29527#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 28915#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 28916#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 30384#L780-45 assume 1 == ~t8_pc~0; 29293#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 28926#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 28927#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 30511#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 28895#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 28896#L799-45 assume 1 == ~t9_pc~0; 29681#L800-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 29115#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 30177#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 30061#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 30062#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 28837#L818-45 assume 1 == ~t10_pc~0; 28838#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 28955#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 30038#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 29453#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 29454#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 30157#L837-45 assume !(1 == ~t11_pc~0); 29383#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 29384#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 28907#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 28908#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 28976#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 28977#L856-45 assume !(1 == ~t12_pc~0); 28978#L856-47 is_transmit12_triggered_~__retres1~12#1 := 0; 28979#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 30208#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 30209#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 29799#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 29800#L875-45 assume 1 == ~t13_pc~0; 29767#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 29768#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 29828#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 30169#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 30425#L1695-47 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30369#L1427-3 assume !(1 == ~M_E~0); 29594#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 29595#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 30119#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 29786#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 29787#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 28624#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 28625#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 30297#L1462-3 assume !(1 == ~T8_E~0); 30298#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 30165#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 30166#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 28879#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 28880#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 29022#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 29192#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 29193#L1502-3 assume !(1 == ~E_2~0); 30139#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 30260#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 29231#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 28919#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 28920#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 28886#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 28887#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 29997#L1542-3 assume !(1 == ~E_10~0); 30125#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 29770#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 29771#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 29090#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 29091#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 28512#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 28949#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 28950#L1947 assume !(0 == start_simulation_~tmp~3#1); 29903#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 30093#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 29151#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 28574#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 28575#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 30228#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 30229#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 30389#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 29217#L1928-2 [2024-11-08 00:35:56,949 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:56,949 INFO L85 PathProgramCache]: Analyzing trace with hash 1978508041, now seen corresponding path program 1 times [2024-11-08 00:35:56,949 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:56,949 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [558458371] [2024-11-08 00:35:56,949 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:56,949 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:56,959 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:56,984 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:56,984 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:56,984 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [558458371] [2024-11-08 00:35:56,985 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [558458371] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:56,985 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:56,985 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:56,985 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [57511846] [2024-11-08 00:35:56,985 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:56,985 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:35:56,985 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:56,985 INFO L85 PathProgramCache]: Analyzing trace with hash -689496338, now seen corresponding path program 1 times [2024-11-08 00:35:56,985 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:56,985 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1209995234] [2024-11-08 00:35:56,986 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:56,986 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:57,002 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:57,042 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:57,042 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:57,042 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1209995234] [2024-11-08 00:35:57,042 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1209995234] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:57,042 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:57,042 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:57,042 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1661436968] [2024-11-08 00:35:57,042 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:57,043 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:35:57,043 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:35:57,043 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:35:57,043 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:35:57,043 INFO L87 Difference]: Start difference. First operand 2032 states and 2995 transitions. cyclomatic complexity: 964 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:57,100 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:35:57,100 INFO L93 Difference]: Finished difference Result 2032 states and 2994 transitions. [2024-11-08 00:35:57,100 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2032 states and 2994 transitions. [2024-11-08 00:35:57,106 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1857 [2024-11-08 00:35:57,113 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2032 states to 2032 states and 2994 transitions. [2024-11-08 00:35:57,113 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2032 [2024-11-08 00:35:57,114 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2032 [2024-11-08 00:35:57,114 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2032 states and 2994 transitions. [2024-11-08 00:35:57,117 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:35:57,117 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2032 states and 2994 transitions. [2024-11-08 00:35:57,119 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2032 states and 2994 transitions. [2024-11-08 00:35:57,138 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2032 to 2032. [2024-11-08 00:35:57,140 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2032 states, 2032 states have (on average 1.4734251968503937) internal successors, (2994), 2031 states have internal predecessors, (2994), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:57,143 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2032 states to 2032 states and 2994 transitions. [2024-11-08 00:35:57,144 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2032 states and 2994 transitions. [2024-11-08 00:35:57,144 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:35:57,144 INFO L425 stractBuchiCegarLoop]: Abstraction has 2032 states and 2994 transitions. [2024-11-08 00:35:57,144 INFO L332 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-11-08 00:35:57,144 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2032 states and 2994 transitions. [2024-11-08 00:35:57,150 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1857 [2024-11-08 00:35:57,150 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:35:57,150 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:35:57,152 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:57,152 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:57,153 INFO L745 eck$LassoCheckResult]: Stem: 32913#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 32914#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 33900#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 33901#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 34600#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 33494#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 33495#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 33565#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 33566#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 34003#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 34004#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 33529#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 33334#L937-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 33335#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 33793#L947-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 33794#L952-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 33673#L957-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 33674#L962-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 33308#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 33309#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 34524#L1279-2 assume !(0 == ~T1_E~0); 32934#L1284-1 assume !(0 == ~T2_E~0); 32935#L1289-1 assume !(0 == ~T3_E~0); 33670#L1294-1 assume !(0 == ~T4_E~0); 33671#L1299-1 assume !(0 == ~T5_E~0); 33682#L1304-1 assume !(0 == ~T6_E~0); 34599#L1309-1 assume !(0 == ~T7_E~0); 34601#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 32858#L1319-1 assume !(0 == ~T9_E~0); 32859#L1324-1 assume !(0 == ~T10_E~0); 33032#L1329-1 assume !(0 == ~T11_E~0); 33033#L1334-1 assume !(0 == ~T12_E~0); 34442#L1339-1 assume !(0 == ~T13_E~0); 34514#L1344-1 assume !(0 == ~E_M~0); 34515#L1349-1 assume !(0 == ~E_1~0); 33859#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 33860#L1359-1 assume !(0 == ~E_3~0); 34267#L1364-1 assume !(0 == ~E_4~0); 33158#L1369-1 assume !(0 == ~E_5~0); 33159#L1374-1 assume !(0 == ~E_6~0); 33866#L1379-1 assume !(0 == ~E_7~0); 33867#L1384-1 assume !(0 == ~E_8~0); 33944#L1389-1 assume !(0 == ~E_9~0); 34461#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 34462#L1399-1 assume !(0 == ~E_11~0); 34555#L1404-1 assume !(0 == ~E_12~0); 33256#L1409-1 assume !(0 == ~E_13~0); 33257#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 34550#L628 assume !(1 == ~m_pc~0); 33157#L628-2 is_master_triggered_~__retres1~0#1 := 0; 33156#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33741#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 33742#L1591 assume !(0 != activate_threads_~tmp~1#1); 34563#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33722#L647 assume 1 == ~t1_pc~0; 33082#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 33083#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33773#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 34230#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 34502#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34503#L666 assume 1 == ~t2_pc~0; 32931#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 32932#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33073#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 33074#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 34055#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34056#L685 assume !(1 == ~t3_pc~0); 34150#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 34149#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34219#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 33908#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 33909#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33382#L704 assume 1 == ~t4_pc~0; 33383#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 33920#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 32722#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 32723#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 33771#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33772#L723 assume !(1 == ~t5_pc~0); 33904#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 34122#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 34260#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 34034#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 34035#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 33140#L742 assume 1 == ~t6_pc~0; 33141#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 33297#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33064#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 32827#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 32828#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33218#L761 assume !(1 == ~t7_pc~0); 33219#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 33094#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 33095#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 33911#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 33912#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 32850#L780 assume 1 == ~t8_pc~0; 32851#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 33130#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 33131#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 33873#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 33874#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 33990#L799 assume 1 == ~t9_pc~0; 34092#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 32853#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 32854#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 33125#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 34193#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 34016#L818 assume !(1 == ~t10_pc~0); 32637#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 32638#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 34085#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 34019#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 34020#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 34062#L837 assume 1 == ~t11_pc~0; 34063#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 33898#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 34506#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 33983#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 33984#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 33730#L856 assume !(1 == ~t12_pc~0); 33731#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 34365#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 32655#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 32656#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 34343#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 34527#L875 assume 1 == ~t13_pc~0; 33680#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 33298#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 33299#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 33236#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 33237#L1695-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 34084#L1427 assume !(1 == ~M_E~0); 34069#L1427-2 assume !(1 == ~T1_E~0); 33205#L1432-1 assume !(1 == ~T2_E~0); 33206#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 34272#L1442-1 assume !(1 == ~T4_E~0); 34273#L1447-1 assume !(1 == ~T5_E~0); 34131#L1452-1 assume !(1 == ~T6_E~0); 32774#L1457-1 assume !(1 == ~T7_E~0); 32775#L1462-1 assume !(1 == ~T8_E~0); 34290#L1467-1 assume !(1 == ~T9_E~0); 34311#L1472-1 assume !(1 == ~T10_E~0); 34312#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 34080#L1482-1 assume !(1 == ~T12_E~0); 34081#L1487-1 assume !(1 == ~T13_E~0); 33105#L1492-1 assume !(1 == ~E_M~0); 33106#L1497-1 assume !(1 == ~E_1~0); 33476#L1502-1 assume !(1 == ~E_2~0); 33477#L1507-1 assume !(1 == ~E_3~0); 32982#L1512-1 assume !(1 == ~E_4~0); 32983#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 34384#L1522-1 assume !(1 == ~E_6~0); 33719#L1527-1 assume !(1 == ~E_7~0); 33720#L1532-1 assume !(1 == ~E_8~0); 34585#L1537-1 assume !(1 == ~E_9~0); 33927#L1542-1 assume !(1 == ~E_10~0); 33748#L1547-1 assume !(1 == ~E_11~0); 33749#L1552-1 assume !(1 == ~E_12~0); 32678#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 32679#L1562-1 assume { :end_inline_reset_delta_events } true; 33288#L1928-2 [2024-11-08 00:35:57,153 INFO L747 eck$LassoCheckResult]: Loop: 33288#L1928-2 assume !false; 33786#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 33363#L1254-1 assume !false; 33595#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 33007#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 33008#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 33207#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 34370#L1067 assume !(0 != eval_~tmp~0#1); 33660#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 33265#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 33266#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 33496#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 33480#L1284-3 assume !(0 == ~T2_E~0); 33481#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 33461#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 33462#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 33854#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 33855#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 33342#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 33343#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 34333#L1324-3 assume !(0 == ~T10_E~0); 32980#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 32981#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 33754#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 33755#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 34059#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 33326#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 33327#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 34067#L1364-3 assume !(0 == ~E_4~0); 34584#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 34476#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 33109#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 33110#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 33324#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 33325#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 33631#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 34486#L1404-3 assume !(0 == ~E_12~0); 34451#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 34452#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33956#L628-45 assume 1 == ~m_pc~0; 33626#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 33628#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 34139#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 33360#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 33361#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 34091#L647-45 assume 1 == ~t1_pc~0; 32928#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 32929#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33872#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 33038#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 33039#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33249#L666-45 assume !(1 == ~t2_pc~0); 33250#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 33740#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 34137#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 34138#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 34203#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 32790#L685-45 assume 1 == ~t3_pc~0; 32791#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 33868#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34516#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 34382#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 34383#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 34525#L704-45 assume !(1 == ~t4_pc~0); 32657#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 32658#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33526#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 34407#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 34613#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33985#L723-45 assume !(1 == ~t5_pc~0); 33986#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 34463#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 34575#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 33338#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 33339#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 34353#L742-45 assume 1 == ~t6_pc~0; 34354#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 33603#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33813#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 33814#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 34096#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 34182#L761-45 assume !(1 == ~t7_pc~0); 34183#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 33597#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 33598#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 32986#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 32987#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 34455#L780-45 assume 1 == ~t8_pc~0; 33364#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 32997#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 32998#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 34582#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 32966#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 32967#L799-45 assume !(1 == ~t9_pc~0); 33185#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 33186#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 34248#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 34132#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 34133#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 32908#L818-45 assume 1 == ~t10_pc~0; 32909#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 33026#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 34109#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 33524#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 33525#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 34228#L837-45 assume 1 == ~t11_pc~0; 34512#L838-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 33455#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 32978#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 32979#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 33047#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 33048#L856-45 assume !(1 == ~t12_pc~0); 33049#L856-47 is_transmit12_triggered_~__retres1~12#1 := 0; 33050#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 34279#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 34280#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 33870#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 33871#L875-45 assume !(1 == ~t13_pc~0); 33840#L875-47 is_transmit13_triggered_~__retres1~13#1 := 0; 33839#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 33899#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 34240#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 34496#L1695-47 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 34440#L1427-3 assume !(1 == ~M_E~0); 33665#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 33666#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 34190#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 33857#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 33858#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 32695#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 32696#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 34368#L1462-3 assume !(1 == ~T8_E~0); 34369#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 34236#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 34237#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 32950#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 32951#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 33093#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 33263#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 33264#L1502-3 assume !(1 == ~E_2~0); 34210#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 34331#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 33302#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 32990#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 32991#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 32957#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 32958#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 34068#L1542-3 assume !(1 == ~E_10~0); 34196#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 33841#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 33842#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 33161#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 33162#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 32583#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 33020#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 33021#L1947 assume !(0 == start_simulation_~tmp~3#1); 33974#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 34164#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 33222#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 32645#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 32646#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 34299#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 34300#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 34460#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 33288#L1928-2 [2024-11-08 00:35:57,153 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:57,154 INFO L85 PathProgramCache]: Analyzing trace with hash -1393291829, now seen corresponding path program 1 times [2024-11-08 00:35:57,154 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:57,154 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1585753359] [2024-11-08 00:35:57,154 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:57,154 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:57,166 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:57,193 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:57,193 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:57,194 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1585753359] [2024-11-08 00:35:57,194 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1585753359] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:57,194 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:57,194 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:57,194 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2102231767] [2024-11-08 00:35:57,194 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:57,194 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:35:57,194 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:57,194 INFO L85 PathProgramCache]: Analyzing trace with hash 788038383, now seen corresponding path program 1 times [2024-11-08 00:35:57,195 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:57,195 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2050926096] [2024-11-08 00:35:57,195 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:57,195 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:57,210 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:57,251 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:57,252 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:57,252 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2050926096] [2024-11-08 00:35:57,252 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2050926096] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:57,252 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:57,252 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:57,252 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1026304691] [2024-11-08 00:35:57,252 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:57,252 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:35:57,252 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:35:57,252 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:35:57,252 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:35:57,253 INFO L87 Difference]: Start difference. First operand 2032 states and 2994 transitions. cyclomatic complexity: 963 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:57,284 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:35:57,284 INFO L93 Difference]: Finished difference Result 2032 states and 2993 transitions. [2024-11-08 00:35:57,284 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2032 states and 2993 transitions. [2024-11-08 00:35:57,291 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1857 [2024-11-08 00:35:57,304 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2032 states to 2032 states and 2993 transitions. [2024-11-08 00:35:57,304 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2032 [2024-11-08 00:35:57,305 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2032 [2024-11-08 00:35:57,306 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2032 states and 2993 transitions. [2024-11-08 00:35:57,308 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:35:57,308 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2032 states and 2993 transitions. [2024-11-08 00:35:57,310 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2032 states and 2993 transitions. [2024-11-08 00:35:57,330 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2032 to 2032. [2024-11-08 00:35:57,332 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2032 states, 2032 states have (on average 1.4729330708661417) internal successors, (2993), 2031 states have internal predecessors, (2993), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:57,340 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2032 states to 2032 states and 2993 transitions. [2024-11-08 00:35:57,340 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2032 states and 2993 transitions. [2024-11-08 00:35:57,341 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:35:57,341 INFO L425 stractBuchiCegarLoop]: Abstraction has 2032 states and 2993 transitions. [2024-11-08 00:35:57,342 INFO L332 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-11-08 00:35:57,342 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2032 states and 2993 transitions. [2024-11-08 00:35:57,347 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1857 [2024-11-08 00:35:57,347 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:35:57,347 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:35:57,349 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:57,349 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:57,350 INFO L745 eck$LassoCheckResult]: Stem: 36984#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 36985#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 37971#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 37972#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 38671#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 37565#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 37566#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 37636#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 37637#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 38074#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 38075#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 37600#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 37405#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 37406#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 37864#L947-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 37865#L952-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 37744#L957-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 37745#L962-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 37379#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 37380#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 38595#L1279-2 assume !(0 == ~T1_E~0); 37005#L1284-1 assume !(0 == ~T2_E~0); 37006#L1289-1 assume !(0 == ~T3_E~0); 37741#L1294-1 assume !(0 == ~T4_E~0); 37742#L1299-1 assume !(0 == ~T5_E~0); 37753#L1304-1 assume !(0 == ~T6_E~0); 38670#L1309-1 assume !(0 == ~T7_E~0); 38672#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 36929#L1319-1 assume !(0 == ~T9_E~0); 36930#L1324-1 assume !(0 == ~T10_E~0); 37103#L1329-1 assume !(0 == ~T11_E~0); 37104#L1334-1 assume !(0 == ~T12_E~0); 38513#L1339-1 assume !(0 == ~T13_E~0); 38585#L1344-1 assume !(0 == ~E_M~0); 38586#L1349-1 assume !(0 == ~E_1~0); 37930#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 37931#L1359-1 assume !(0 == ~E_3~0); 38338#L1364-1 assume !(0 == ~E_4~0); 37229#L1369-1 assume !(0 == ~E_5~0); 37230#L1374-1 assume !(0 == ~E_6~0); 37937#L1379-1 assume !(0 == ~E_7~0); 37938#L1384-1 assume !(0 == ~E_8~0); 38015#L1389-1 assume !(0 == ~E_9~0); 38532#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 38533#L1399-1 assume !(0 == ~E_11~0); 38626#L1404-1 assume !(0 == ~E_12~0); 37327#L1409-1 assume !(0 == ~E_13~0); 37328#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 38621#L628 assume !(1 == ~m_pc~0); 37228#L628-2 is_master_triggered_~__retres1~0#1 := 0; 37227#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 37812#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 37813#L1591 assume !(0 != activate_threads_~tmp~1#1); 38634#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 37793#L647 assume 1 == ~t1_pc~0; 37153#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 37154#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 37844#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 38301#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 38573#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38574#L666 assume 1 == ~t2_pc~0; 37002#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 37003#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 37144#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 37145#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 38126#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 38127#L685 assume !(1 == ~t3_pc~0); 38221#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 38220#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38290#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 37979#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 37980#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 37453#L704 assume 1 == ~t4_pc~0; 37454#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 37991#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36793#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 36794#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 37842#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 37843#L723 assume !(1 == ~t5_pc~0); 37975#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 38193#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 38331#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 38105#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 38106#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 37211#L742 assume 1 == ~t6_pc~0; 37212#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 37368#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 37135#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 36898#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 36899#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 37289#L761 assume !(1 == ~t7_pc~0); 37290#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 37165#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37166#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 37982#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 37983#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 36921#L780 assume 1 == ~t8_pc~0; 36922#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 37201#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 37202#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 37944#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 37945#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 38061#L799 assume 1 == ~t9_pc~0; 38163#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 36924#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 36925#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 37196#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 38264#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 38087#L818 assume !(1 == ~t10_pc~0); 36708#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 36709#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 38156#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 38090#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 38091#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 38133#L837 assume 1 == ~t11_pc~0; 38134#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 37969#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 38577#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 38054#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 38055#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 37801#L856 assume !(1 == ~t12_pc~0); 37802#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 38436#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 36726#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 36727#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 38414#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 38598#L875 assume 1 == ~t13_pc~0; 37751#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 37369#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 37370#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 37307#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 37308#L1695-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 38155#L1427 assume !(1 == ~M_E~0); 38140#L1427-2 assume !(1 == ~T1_E~0); 37276#L1432-1 assume !(1 == ~T2_E~0); 37277#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 38343#L1442-1 assume !(1 == ~T4_E~0); 38344#L1447-1 assume !(1 == ~T5_E~0); 38202#L1452-1 assume !(1 == ~T6_E~0); 36845#L1457-1 assume !(1 == ~T7_E~0); 36846#L1462-1 assume !(1 == ~T8_E~0); 38361#L1467-1 assume !(1 == ~T9_E~0); 38382#L1472-1 assume !(1 == ~T10_E~0); 38383#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 38151#L1482-1 assume !(1 == ~T12_E~0); 38152#L1487-1 assume !(1 == ~T13_E~0); 37176#L1492-1 assume !(1 == ~E_M~0); 37177#L1497-1 assume !(1 == ~E_1~0); 37547#L1502-1 assume !(1 == ~E_2~0); 37548#L1507-1 assume !(1 == ~E_3~0); 37053#L1512-1 assume !(1 == ~E_4~0); 37054#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 38455#L1522-1 assume !(1 == ~E_6~0); 37790#L1527-1 assume !(1 == ~E_7~0); 37791#L1532-1 assume !(1 == ~E_8~0); 38656#L1537-1 assume !(1 == ~E_9~0); 37998#L1542-1 assume !(1 == ~E_10~0); 37819#L1547-1 assume !(1 == ~E_11~0); 37820#L1552-1 assume !(1 == ~E_12~0); 36749#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 36750#L1562-1 assume { :end_inline_reset_delta_events } true; 37359#L1928-2 [2024-11-08 00:35:57,351 INFO L747 eck$LassoCheckResult]: Loop: 37359#L1928-2 assume !false; 37857#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 37434#L1254-1 assume !false; 37666#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 37078#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 37079#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 37278#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 38441#L1067 assume !(0 != eval_~tmp~0#1); 37731#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 37336#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 37337#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 37567#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 37551#L1284-3 assume !(0 == ~T2_E~0); 37552#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 37532#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 37533#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 37925#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 37926#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 37413#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 37414#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 38404#L1324-3 assume !(0 == ~T10_E~0); 37051#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 37052#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 37825#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 37826#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 38130#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 37397#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 37398#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 38138#L1364-3 assume !(0 == ~E_4~0); 38655#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 38547#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 37180#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 37181#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 37395#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 37396#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 37702#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 38557#L1404-3 assume !(0 == ~E_12~0); 38522#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 38523#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 38027#L628-45 assume 1 == ~m_pc~0; 37697#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 37699#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 38210#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 37431#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 37432#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 38162#L647-45 assume 1 == ~t1_pc~0; 36999#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 37000#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 37943#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 37109#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 37110#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 37320#L666-45 assume !(1 == ~t2_pc~0); 37321#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 37811#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 38208#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 38209#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 38274#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36861#L685-45 assume 1 == ~t3_pc~0; 36862#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 37939#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38587#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 38453#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 38454#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 38596#L704-45 assume !(1 == ~t4_pc~0); 36728#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 36729#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 37597#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 38478#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 38684#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 38056#L723-45 assume !(1 == ~t5_pc~0); 38057#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 38534#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 38646#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 37409#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 37410#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 38424#L742-45 assume 1 == ~t6_pc~0; 38425#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 37674#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 37884#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 37885#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 38167#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 38253#L761-45 assume !(1 == ~t7_pc~0); 38254#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 37668#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37669#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 37057#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 37058#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 38526#L780-45 assume 1 == ~t8_pc~0; 37435#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 37068#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 37069#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 38653#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 37037#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 37038#L799-45 assume !(1 == ~t9_pc~0); 37256#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 37257#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 38319#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 38203#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 38204#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 36979#L818-45 assume 1 == ~t10_pc~0; 36980#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 37097#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 38180#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 37595#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 37596#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 38299#L837-45 assume !(1 == ~t11_pc~0); 37525#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 37526#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 37049#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 37050#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 37118#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 37119#L856-45 assume !(1 == ~t12_pc~0); 37120#L856-47 is_transmit12_triggered_~__retres1~12#1 := 0; 37121#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 38350#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 38351#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 37941#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 37942#L875-45 assume 1 == ~t13_pc~0; 37909#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 37910#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 37970#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 38311#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 38567#L1695-47 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 38511#L1427-3 assume !(1 == ~M_E~0); 37736#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 37737#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 38261#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 37928#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 37929#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 36766#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 36767#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 38439#L1462-3 assume !(1 == ~T8_E~0); 38440#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 38307#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 38308#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 37021#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 37022#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 37164#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 37334#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 37335#L1502-3 assume !(1 == ~E_2~0); 38281#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 38402#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 37373#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 37061#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 37062#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 37028#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 37029#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 38139#L1542-3 assume !(1 == ~E_10~0); 38267#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 37912#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 37913#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 37232#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 37233#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 36654#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 37091#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 37092#L1947 assume !(0 == start_simulation_~tmp~3#1); 38045#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 38235#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 37293#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 36716#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 36717#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 38370#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 38371#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 38531#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 37359#L1928-2 [2024-11-08 00:35:57,351 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:57,351 INFO L85 PathProgramCache]: Analyzing trace with hash -1779154231, now seen corresponding path program 1 times [2024-11-08 00:35:57,351 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:57,351 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [960414657] [2024-11-08 00:35:57,352 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:57,352 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:57,364 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:57,389 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:57,389 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:57,389 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [960414657] [2024-11-08 00:35:57,390 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [960414657] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:57,390 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:57,390 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:57,390 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1235438921] [2024-11-08 00:35:57,390 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:57,390 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:35:57,391 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:57,391 INFO L85 PathProgramCache]: Analyzing trace with hash 1650149743, now seen corresponding path program 2 times [2024-11-08 00:35:57,391 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:57,391 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2046339126] [2024-11-08 00:35:57,391 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:57,391 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:57,402 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:57,433 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:57,433 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:57,433 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2046339126] [2024-11-08 00:35:57,433 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2046339126] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:57,433 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:57,433 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:57,433 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [22962001] [2024-11-08 00:35:57,433 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:57,434 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:35:57,434 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:35:57,434 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:35:57,434 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:35:57,435 INFO L87 Difference]: Start difference. First operand 2032 states and 2993 transitions. cyclomatic complexity: 962 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:57,459 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:35:57,459 INFO L93 Difference]: Finished difference Result 2032 states and 2992 transitions. [2024-11-08 00:35:57,459 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2032 states and 2992 transitions. [2024-11-08 00:35:57,464 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1857 [2024-11-08 00:35:57,469 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2032 states to 2032 states and 2992 transitions. [2024-11-08 00:35:57,469 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2032 [2024-11-08 00:35:57,470 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2032 [2024-11-08 00:35:57,470 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2032 states and 2992 transitions. [2024-11-08 00:35:57,472 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:35:57,472 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2032 states and 2992 transitions. [2024-11-08 00:35:57,474 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2032 states and 2992 transitions. [2024-11-08 00:35:57,488 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2032 to 2032. [2024-11-08 00:35:57,494 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2032 states, 2032 states have (on average 1.4724409448818898) internal successors, (2992), 2031 states have internal predecessors, (2992), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:57,498 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2032 states to 2032 states and 2992 transitions. [2024-11-08 00:35:57,498 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2032 states and 2992 transitions. [2024-11-08 00:35:57,499 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:35:57,499 INFO L425 stractBuchiCegarLoop]: Abstraction has 2032 states and 2992 transitions. [2024-11-08 00:35:57,499 INFO L332 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-11-08 00:35:57,499 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2032 states and 2992 transitions. [2024-11-08 00:35:57,505 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1857 [2024-11-08 00:35:57,505 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:35:57,505 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:35:57,506 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:57,506 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:57,506 INFO L745 eck$LassoCheckResult]: Stem: 41055#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 41056#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 42042#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 42043#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 42742#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 41636#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 41637#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 41707#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 41708#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 42145#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 42146#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 41671#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 41476#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 41477#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 41935#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 41936#L952-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 41815#L957-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 41816#L962-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 41450#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 41451#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 42666#L1279-2 assume !(0 == ~T1_E~0); 41076#L1284-1 assume !(0 == ~T2_E~0); 41077#L1289-1 assume !(0 == ~T3_E~0); 41812#L1294-1 assume !(0 == ~T4_E~0); 41813#L1299-1 assume !(0 == ~T5_E~0); 41824#L1304-1 assume !(0 == ~T6_E~0); 42741#L1309-1 assume !(0 == ~T7_E~0); 42743#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 41000#L1319-1 assume !(0 == ~T9_E~0); 41001#L1324-1 assume !(0 == ~T10_E~0); 41174#L1329-1 assume !(0 == ~T11_E~0); 41175#L1334-1 assume !(0 == ~T12_E~0); 42584#L1339-1 assume !(0 == ~T13_E~0); 42656#L1344-1 assume !(0 == ~E_M~0); 42657#L1349-1 assume !(0 == ~E_1~0); 42001#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 42002#L1359-1 assume !(0 == ~E_3~0); 42409#L1364-1 assume !(0 == ~E_4~0); 41300#L1369-1 assume !(0 == ~E_5~0); 41301#L1374-1 assume !(0 == ~E_6~0); 42008#L1379-1 assume !(0 == ~E_7~0); 42009#L1384-1 assume !(0 == ~E_8~0); 42086#L1389-1 assume !(0 == ~E_9~0); 42603#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 42604#L1399-1 assume !(0 == ~E_11~0); 42697#L1404-1 assume !(0 == ~E_12~0); 41398#L1409-1 assume !(0 == ~E_13~0); 41399#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 42692#L628 assume !(1 == ~m_pc~0); 41299#L628-2 is_master_triggered_~__retres1~0#1 := 0; 41298#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41883#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 41884#L1591 assume !(0 != activate_threads_~tmp~1#1); 42705#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 41864#L647 assume 1 == ~t1_pc~0; 41224#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 41225#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 41915#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 42372#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 42644#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 42645#L666 assume 1 == ~t2_pc~0; 41073#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 41074#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 41215#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 41216#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 42197#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 42198#L685 assume !(1 == ~t3_pc~0); 42292#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 42291#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 42361#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 42050#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 42051#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 41524#L704 assume 1 == ~t4_pc~0; 41525#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 42062#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 40864#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 40865#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 41913#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 41914#L723 assume !(1 == ~t5_pc~0); 42046#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 42264#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 42402#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 42176#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 42177#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 41282#L742 assume 1 == ~t6_pc~0; 41283#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 41439#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 41206#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 40969#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 40970#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 41360#L761 assume !(1 == ~t7_pc~0); 41361#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 41236#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 41237#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 42053#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 42054#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 40992#L780 assume 1 == ~t8_pc~0; 40993#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 41272#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 41273#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 42015#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 42016#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 42132#L799 assume 1 == ~t9_pc~0; 42234#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 40995#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 40996#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 41267#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 42335#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 42158#L818 assume !(1 == ~t10_pc~0); 40779#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 40780#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 42227#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 42161#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 42162#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 42204#L837 assume 1 == ~t11_pc~0; 42205#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 42040#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 42648#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 42125#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 42126#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 41872#L856 assume !(1 == ~t12_pc~0); 41873#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 42507#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 40797#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 40798#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 42485#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 42669#L875 assume 1 == ~t13_pc~0; 41822#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 41440#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 41441#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 41378#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 41379#L1695-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 42226#L1427 assume !(1 == ~M_E~0); 42211#L1427-2 assume !(1 == ~T1_E~0); 41347#L1432-1 assume !(1 == ~T2_E~0); 41348#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 42414#L1442-1 assume !(1 == ~T4_E~0); 42415#L1447-1 assume !(1 == ~T5_E~0); 42273#L1452-1 assume !(1 == ~T6_E~0); 40916#L1457-1 assume !(1 == ~T7_E~0); 40917#L1462-1 assume !(1 == ~T8_E~0); 42432#L1467-1 assume !(1 == ~T9_E~0); 42453#L1472-1 assume !(1 == ~T10_E~0); 42454#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 42222#L1482-1 assume !(1 == ~T12_E~0); 42223#L1487-1 assume !(1 == ~T13_E~0); 41247#L1492-1 assume !(1 == ~E_M~0); 41248#L1497-1 assume !(1 == ~E_1~0); 41618#L1502-1 assume !(1 == ~E_2~0); 41619#L1507-1 assume !(1 == ~E_3~0); 41124#L1512-1 assume !(1 == ~E_4~0); 41125#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 42526#L1522-1 assume !(1 == ~E_6~0); 41861#L1527-1 assume !(1 == ~E_7~0); 41862#L1532-1 assume !(1 == ~E_8~0); 42727#L1537-1 assume !(1 == ~E_9~0); 42069#L1542-1 assume !(1 == ~E_10~0); 41890#L1547-1 assume !(1 == ~E_11~0); 41891#L1552-1 assume !(1 == ~E_12~0); 40820#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 40821#L1562-1 assume { :end_inline_reset_delta_events } true; 41430#L1928-2 [2024-11-08 00:35:57,507 INFO L747 eck$LassoCheckResult]: Loop: 41430#L1928-2 assume !false; 41928#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 41505#L1254-1 assume !false; 41737#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 41149#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 41150#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 41349#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 42512#L1067 assume !(0 != eval_~tmp~0#1); 41802#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 41407#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 41408#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 41638#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 41622#L1284-3 assume !(0 == ~T2_E~0); 41623#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 41603#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 41604#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 41996#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 41997#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 41484#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 41485#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 42475#L1324-3 assume !(0 == ~T10_E~0); 41122#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 41123#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 41896#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 41897#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 42201#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 41468#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 41469#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 42209#L1364-3 assume !(0 == ~E_4~0); 42726#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 42618#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 41251#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 41252#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 41466#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 41467#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 41773#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 42628#L1404-3 assume !(0 == ~E_12~0); 42593#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 42594#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 42098#L628-45 assume 1 == ~m_pc~0; 41768#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 41770#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 42281#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 41502#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 41503#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 42233#L647-45 assume !(1 == ~t1_pc~0); 41072#L647-47 is_transmit1_triggered_~__retres1~1#1 := 0; 41071#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 42014#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 41180#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 41181#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 41391#L666-45 assume !(1 == ~t2_pc~0); 41392#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 41882#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 42279#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 42280#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 42345#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 40932#L685-45 assume 1 == ~t3_pc~0; 40933#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 42010#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 42658#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 42524#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 42525#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 42667#L704-45 assume 1 == ~t4_pc~0; 42548#L705-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 40800#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 41668#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 42549#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 42755#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 42127#L723-45 assume !(1 == ~t5_pc~0); 42128#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 42605#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 42717#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 41480#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 41481#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 42495#L742-45 assume 1 == ~t6_pc~0; 42496#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 41745#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 41955#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 41956#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 42238#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 42324#L761-45 assume !(1 == ~t7_pc~0); 42325#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 41739#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 41740#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 41128#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 41129#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 42597#L780-45 assume 1 == ~t8_pc~0; 41506#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 41139#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 41140#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 42724#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 41108#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 41109#L799-45 assume 1 == ~t9_pc~0; 41894#L800-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 41328#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 42390#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 42274#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 42275#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 41050#L818-45 assume 1 == ~t10_pc~0; 41051#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 41168#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 42251#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 41666#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 41667#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 42370#L837-45 assume !(1 == ~t11_pc~0); 41596#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 41597#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 41120#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 41121#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 41189#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 41190#L856-45 assume !(1 == ~t12_pc~0); 41191#L856-47 is_transmit12_triggered_~__retres1~12#1 := 0; 41192#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 42421#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 42422#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 42012#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 42013#L875-45 assume 1 == ~t13_pc~0; 41980#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 41981#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 42041#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 42382#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 42638#L1695-47 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 42582#L1427-3 assume !(1 == ~M_E~0); 41807#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 41808#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 42332#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 41999#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 42000#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 40837#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 40838#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 42510#L1462-3 assume !(1 == ~T8_E~0); 42511#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 42378#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 42379#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 41092#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 41093#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 41235#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 41405#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 41406#L1502-3 assume !(1 == ~E_2~0); 42352#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 42473#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 41444#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 41132#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 41133#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 41099#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 41100#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 42210#L1542-3 assume !(1 == ~E_10~0); 42338#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 41983#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 41984#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 41303#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 41304#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 40725#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 41162#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 41163#L1947 assume !(0 == start_simulation_~tmp~3#1); 42116#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 42306#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 41364#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 40787#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 40788#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 42441#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 42442#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 42602#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 41430#L1928-2 [2024-11-08 00:35:57,507 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:57,507 INFO L85 PathProgramCache]: Analyzing trace with hash 584687431, now seen corresponding path program 1 times [2024-11-08 00:35:57,507 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:57,507 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [770748097] [2024-11-08 00:35:57,508 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:57,508 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:57,521 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:57,545 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:57,545 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:57,545 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [770748097] [2024-11-08 00:35:57,545 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [770748097] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:57,545 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:57,545 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:57,545 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [889329236] [2024-11-08 00:35:57,545 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:57,546 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:35:57,546 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:57,546 INFO L85 PathProgramCache]: Analyzing trace with hash -1084600146, now seen corresponding path program 1 times [2024-11-08 00:35:57,546 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:57,546 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [914921125] [2024-11-08 00:35:57,546 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:57,546 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:57,573 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:57,603 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:57,604 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:57,604 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [914921125] [2024-11-08 00:35:57,604 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [914921125] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:57,604 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:57,604 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:57,604 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [795562531] [2024-11-08 00:35:57,604 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:57,604 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:35:57,604 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:35:57,605 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:35:57,605 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:35:57,605 INFO L87 Difference]: Start difference. First operand 2032 states and 2992 transitions. cyclomatic complexity: 961 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:57,629 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:35:57,629 INFO L93 Difference]: Finished difference Result 2032 states and 2991 transitions. [2024-11-08 00:35:57,629 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2032 states and 2991 transitions. [2024-11-08 00:35:57,635 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1857 [2024-11-08 00:35:57,639 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2032 states to 2032 states and 2991 transitions. [2024-11-08 00:35:57,639 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2032 [2024-11-08 00:35:57,640 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2032 [2024-11-08 00:35:57,640 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2032 states and 2991 transitions. [2024-11-08 00:35:57,642 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:35:57,642 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2032 states and 2991 transitions. [2024-11-08 00:35:57,645 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2032 states and 2991 transitions. [2024-11-08 00:35:57,659 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2032 to 2032. [2024-11-08 00:35:57,665 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2032 states, 2032 states have (on average 1.4719488188976377) internal successors, (2991), 2031 states have internal predecessors, (2991), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:57,669 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2032 states to 2032 states and 2991 transitions. [2024-11-08 00:35:57,669 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2032 states and 2991 transitions. [2024-11-08 00:35:57,669 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:35:57,670 INFO L425 stractBuchiCegarLoop]: Abstraction has 2032 states and 2991 transitions. [2024-11-08 00:35:57,670 INFO L332 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-11-08 00:35:57,670 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2032 states and 2991 transitions. [2024-11-08 00:35:57,674 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1857 [2024-11-08 00:35:57,674 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:35:57,674 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:35:57,676 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:57,676 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:57,676 INFO L745 eck$LassoCheckResult]: Stem: 45126#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 45127#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 46113#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 46114#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 46813#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 45707#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 45708#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 45778#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 45779#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 46216#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 46217#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 45742#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 45547#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 45548#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 46006#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 46007#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 45886#L957-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 45887#L962-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 45521#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 45522#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 46737#L1279-2 assume !(0 == ~T1_E~0); 45147#L1284-1 assume !(0 == ~T2_E~0); 45148#L1289-1 assume !(0 == ~T3_E~0); 45883#L1294-1 assume !(0 == ~T4_E~0); 45884#L1299-1 assume !(0 == ~T5_E~0); 45895#L1304-1 assume !(0 == ~T6_E~0); 46812#L1309-1 assume !(0 == ~T7_E~0); 46814#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 45071#L1319-1 assume !(0 == ~T9_E~0); 45072#L1324-1 assume !(0 == ~T10_E~0); 45245#L1329-1 assume !(0 == ~T11_E~0); 45246#L1334-1 assume !(0 == ~T12_E~0); 46655#L1339-1 assume !(0 == ~T13_E~0); 46727#L1344-1 assume !(0 == ~E_M~0); 46728#L1349-1 assume !(0 == ~E_1~0); 46072#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 46073#L1359-1 assume !(0 == ~E_3~0); 46480#L1364-1 assume !(0 == ~E_4~0); 45371#L1369-1 assume !(0 == ~E_5~0); 45372#L1374-1 assume !(0 == ~E_6~0); 46079#L1379-1 assume !(0 == ~E_7~0); 46080#L1384-1 assume !(0 == ~E_8~0); 46157#L1389-1 assume !(0 == ~E_9~0); 46674#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 46675#L1399-1 assume !(0 == ~E_11~0); 46768#L1404-1 assume !(0 == ~E_12~0); 45469#L1409-1 assume !(0 == ~E_13~0); 45470#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 46763#L628 assume !(1 == ~m_pc~0); 45370#L628-2 is_master_triggered_~__retres1~0#1 := 0; 45369#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 45954#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 45955#L1591 assume !(0 != activate_threads_~tmp~1#1); 46776#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 45935#L647 assume 1 == ~t1_pc~0; 45295#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 45296#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 45986#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 46443#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 46715#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 46716#L666 assume 1 == ~t2_pc~0; 45144#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 45145#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 45286#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 45287#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 46268#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 46269#L685 assume !(1 == ~t3_pc~0); 46363#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 46362#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46432#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 46121#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 46122#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 45595#L704 assume 1 == ~t4_pc~0; 45596#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 46133#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 44935#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 44936#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 45984#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 45985#L723 assume !(1 == ~t5_pc~0); 46117#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 46335#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 46473#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 46247#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 46248#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 45353#L742 assume 1 == ~t6_pc~0; 45354#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 45510#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 45277#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 45040#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 45041#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 45431#L761 assume !(1 == ~t7_pc~0); 45432#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 45307#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 45308#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 46124#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 46125#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 45063#L780 assume 1 == ~t8_pc~0; 45064#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 45343#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 45344#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 46086#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 46087#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 46203#L799 assume 1 == ~t9_pc~0; 46305#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 45066#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 45067#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 45338#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 46406#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 46229#L818 assume !(1 == ~t10_pc~0); 44850#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 44851#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 46298#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 46232#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 46233#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 46275#L837 assume 1 == ~t11_pc~0; 46276#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 46111#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 46719#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 46196#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 46197#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 45943#L856 assume !(1 == ~t12_pc~0); 45944#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 46578#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 44868#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 44869#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 46556#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 46740#L875 assume 1 == ~t13_pc~0; 45893#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 45511#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 45512#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 45449#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 45450#L1695-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 46297#L1427 assume !(1 == ~M_E~0); 46282#L1427-2 assume !(1 == ~T1_E~0); 45418#L1432-1 assume !(1 == ~T2_E~0); 45419#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 46485#L1442-1 assume !(1 == ~T4_E~0); 46486#L1447-1 assume !(1 == ~T5_E~0); 46344#L1452-1 assume !(1 == ~T6_E~0); 44987#L1457-1 assume !(1 == ~T7_E~0); 44988#L1462-1 assume !(1 == ~T8_E~0); 46503#L1467-1 assume !(1 == ~T9_E~0); 46524#L1472-1 assume !(1 == ~T10_E~0); 46525#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 46293#L1482-1 assume !(1 == ~T12_E~0); 46294#L1487-1 assume !(1 == ~T13_E~0); 45318#L1492-1 assume !(1 == ~E_M~0); 45319#L1497-1 assume !(1 == ~E_1~0); 45689#L1502-1 assume !(1 == ~E_2~0); 45690#L1507-1 assume !(1 == ~E_3~0); 45195#L1512-1 assume !(1 == ~E_4~0); 45196#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 46597#L1522-1 assume !(1 == ~E_6~0); 45932#L1527-1 assume !(1 == ~E_7~0); 45933#L1532-1 assume !(1 == ~E_8~0); 46798#L1537-1 assume !(1 == ~E_9~0); 46140#L1542-1 assume !(1 == ~E_10~0); 45961#L1547-1 assume !(1 == ~E_11~0); 45962#L1552-1 assume !(1 == ~E_12~0); 44891#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 44892#L1562-1 assume { :end_inline_reset_delta_events } true; 45501#L1928-2 [2024-11-08 00:35:57,677 INFO L747 eck$LassoCheckResult]: Loop: 45501#L1928-2 assume !false; 45999#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 45576#L1254-1 assume !false; 45808#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 45220#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 45221#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 45420#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 46583#L1067 assume !(0 != eval_~tmp~0#1); 45873#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 45478#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 45479#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 45709#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 45693#L1284-3 assume !(0 == ~T2_E~0); 45694#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 45674#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 45675#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 46067#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 46068#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 45555#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 45556#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 46546#L1324-3 assume !(0 == ~T10_E~0); 45193#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 45194#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 45967#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 45968#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 46272#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 45539#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 45540#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 46280#L1364-3 assume !(0 == ~E_4~0); 46797#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 46689#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 45322#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 45323#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 45537#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 45538#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 45844#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 46699#L1404-3 assume !(0 == ~E_12~0); 46664#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 46665#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 46169#L628-45 assume !(1 == ~m_pc~0); 45840#L628-47 is_master_triggered_~__retres1~0#1 := 0; 45841#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 46352#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 45573#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 45574#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 46304#L647-45 assume 1 == ~t1_pc~0; 45141#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 45142#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 46085#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 45251#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 45252#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 45462#L666-45 assume !(1 == ~t2_pc~0); 45463#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 45953#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 46350#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 46351#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 46416#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 45003#L685-45 assume 1 == ~t3_pc~0; 45004#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 46081#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46729#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 46595#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 46596#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 46738#L704-45 assume !(1 == ~t4_pc~0); 44870#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 44871#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 45739#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 46620#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 46826#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 46198#L723-45 assume !(1 == ~t5_pc~0); 46199#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 46676#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 46788#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 45551#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 45552#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 46566#L742-45 assume 1 == ~t6_pc~0; 46567#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 45816#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 46026#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 46027#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 46309#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 46395#L761-45 assume !(1 == ~t7_pc~0); 46396#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 45810#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 45811#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 45199#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 45200#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 46668#L780-45 assume 1 == ~t8_pc~0; 45577#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 45210#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 45211#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 46795#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 45179#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 45180#L799-45 assume !(1 == ~t9_pc~0); 45398#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 45399#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 46461#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 46345#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 46346#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 45121#L818-45 assume 1 == ~t10_pc~0; 45122#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 45239#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 46322#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 45737#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 45738#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 46441#L837-45 assume !(1 == ~t11_pc~0); 45667#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 45668#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 45191#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 45192#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 45260#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 45261#L856-45 assume 1 == ~t12_pc~0; 46736#L857-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 45263#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 46492#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 46493#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 46083#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 46084#L875-45 assume 1 == ~t13_pc~0; 46051#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 46052#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 46112#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 46453#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 46709#L1695-47 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 46653#L1427-3 assume !(1 == ~M_E~0); 45878#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 45879#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 46403#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 46070#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 46071#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 44908#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 44909#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 46581#L1462-3 assume !(1 == ~T8_E~0); 46582#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 46449#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 46450#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 45163#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 45164#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 45306#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 45476#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 45477#L1502-3 assume !(1 == ~E_2~0); 46423#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 46544#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 45515#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 45203#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 45204#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 45170#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 45171#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 46281#L1542-3 assume !(1 == ~E_10~0); 46409#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 46054#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 46055#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 45374#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 45375#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 44796#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 45233#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 45234#L1947 assume !(0 == start_simulation_~tmp~3#1); 46187#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 46377#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 45435#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 44858#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 44859#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 46512#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 46513#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 46673#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 45501#L1928-2 [2024-11-08 00:35:57,677 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:57,677 INFO L85 PathProgramCache]: Analyzing trace with hash 1907866377, now seen corresponding path program 1 times [2024-11-08 00:35:57,677 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:57,677 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1590609899] [2024-11-08 00:35:57,677 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:57,678 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:57,686 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:57,707 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:57,708 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:57,708 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1590609899] [2024-11-08 00:35:57,708 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1590609899] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:57,708 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:57,708 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:57,708 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1988781701] [2024-11-08 00:35:57,708 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:57,708 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:35:57,708 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:57,709 INFO L85 PathProgramCache]: Analyzing trace with hash 144470127, now seen corresponding path program 1 times [2024-11-08 00:35:57,709 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:57,709 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1339324521] [2024-11-08 00:35:57,709 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:57,709 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:57,719 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:57,748 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:57,748 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:57,748 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1339324521] [2024-11-08 00:35:57,748 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1339324521] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:57,748 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:57,748 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:57,748 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1806952151] [2024-11-08 00:35:57,749 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:57,749 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:35:57,749 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:35:57,749 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:35:57,749 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:35:57,750 INFO L87 Difference]: Start difference. First operand 2032 states and 2991 transitions. cyclomatic complexity: 960 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:57,771 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:35:57,772 INFO L93 Difference]: Finished difference Result 2032 states and 2990 transitions. [2024-11-08 00:35:57,772 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2032 states and 2990 transitions. [2024-11-08 00:35:57,777 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1857 [2024-11-08 00:35:57,781 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2032 states to 2032 states and 2990 transitions. [2024-11-08 00:35:57,781 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2032 [2024-11-08 00:35:57,782 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2032 [2024-11-08 00:35:57,782 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2032 states and 2990 transitions. [2024-11-08 00:35:57,784 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:35:57,784 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2032 states and 2990 transitions. [2024-11-08 00:35:57,786 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2032 states and 2990 transitions. [2024-11-08 00:35:57,799 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2032 to 2032. [2024-11-08 00:35:57,800 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2032 states, 2032 states have (on average 1.4714566929133859) internal successors, (2990), 2031 states have internal predecessors, (2990), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:57,803 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2032 states to 2032 states and 2990 transitions. [2024-11-08 00:35:57,804 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2032 states and 2990 transitions. [2024-11-08 00:35:57,804 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:35:57,804 INFO L425 stractBuchiCegarLoop]: Abstraction has 2032 states and 2990 transitions. [2024-11-08 00:35:57,804 INFO L332 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-11-08 00:35:57,804 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2032 states and 2990 transitions. [2024-11-08 00:35:57,809 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1857 [2024-11-08 00:35:57,809 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:35:57,809 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:35:57,811 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:57,811 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:57,811 INFO L745 eck$LassoCheckResult]: Stem: 49197#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 49198#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 50184#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 50185#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 50884#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 49778#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 49779#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 49849#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 49850#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 50287#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 50288#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 49813#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 49618#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 49619#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 50077#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 50078#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 49957#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 49958#L962-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 49592#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 49593#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 50808#L1279-2 assume !(0 == ~T1_E~0); 49218#L1284-1 assume !(0 == ~T2_E~0); 49219#L1289-1 assume !(0 == ~T3_E~0); 49954#L1294-1 assume !(0 == ~T4_E~0); 49955#L1299-1 assume !(0 == ~T5_E~0); 49966#L1304-1 assume !(0 == ~T6_E~0); 50883#L1309-1 assume !(0 == ~T7_E~0); 50885#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 49142#L1319-1 assume !(0 == ~T9_E~0); 49143#L1324-1 assume !(0 == ~T10_E~0); 49316#L1329-1 assume !(0 == ~T11_E~0); 49317#L1334-1 assume !(0 == ~T12_E~0); 50726#L1339-1 assume !(0 == ~T13_E~0); 50798#L1344-1 assume !(0 == ~E_M~0); 50799#L1349-1 assume !(0 == ~E_1~0); 50143#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 50144#L1359-1 assume !(0 == ~E_3~0); 50551#L1364-1 assume !(0 == ~E_4~0); 49442#L1369-1 assume !(0 == ~E_5~0); 49443#L1374-1 assume !(0 == ~E_6~0); 50150#L1379-1 assume !(0 == ~E_7~0); 50151#L1384-1 assume !(0 == ~E_8~0); 50228#L1389-1 assume !(0 == ~E_9~0); 50745#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 50746#L1399-1 assume !(0 == ~E_11~0); 50839#L1404-1 assume !(0 == ~E_12~0); 49540#L1409-1 assume !(0 == ~E_13~0); 49541#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 50834#L628 assume !(1 == ~m_pc~0); 49441#L628-2 is_master_triggered_~__retres1~0#1 := 0; 49440#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 50025#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 50026#L1591 assume !(0 != activate_threads_~tmp~1#1); 50847#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 50006#L647 assume 1 == ~t1_pc~0; 49366#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 49367#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 50057#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 50514#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 50786#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 50787#L666 assume 1 == ~t2_pc~0; 49215#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 49216#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 49357#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 49358#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 50339#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 50340#L685 assume !(1 == ~t3_pc~0); 50434#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 50433#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 50503#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 50192#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 50193#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 49666#L704 assume 1 == ~t4_pc~0; 49667#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 50204#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 49006#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 49007#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 50055#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 50056#L723 assume !(1 == ~t5_pc~0); 50188#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 50406#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 50544#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 50318#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 50319#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 49424#L742 assume 1 == ~t6_pc~0; 49425#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 49581#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 49348#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 49111#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 49112#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 49502#L761 assume !(1 == ~t7_pc~0); 49503#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 49378#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 49379#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 50195#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 50196#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 49134#L780 assume 1 == ~t8_pc~0; 49135#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 49414#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 49415#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 50157#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 50158#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 50274#L799 assume 1 == ~t9_pc~0; 50376#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 49137#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 49138#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 49409#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 50477#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 50300#L818 assume !(1 == ~t10_pc~0); 48921#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 48922#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 50369#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 50303#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 50304#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 50346#L837 assume 1 == ~t11_pc~0; 50347#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 50182#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 50790#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 50267#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 50268#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 50014#L856 assume !(1 == ~t12_pc~0); 50015#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 50649#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 48939#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 48940#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 50627#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 50811#L875 assume 1 == ~t13_pc~0; 49964#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 49582#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 49583#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 49520#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 49521#L1695-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 50368#L1427 assume !(1 == ~M_E~0); 50353#L1427-2 assume !(1 == ~T1_E~0); 49489#L1432-1 assume !(1 == ~T2_E~0); 49490#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 50556#L1442-1 assume !(1 == ~T4_E~0); 50557#L1447-1 assume !(1 == ~T5_E~0); 50415#L1452-1 assume !(1 == ~T6_E~0); 49058#L1457-1 assume !(1 == ~T7_E~0); 49059#L1462-1 assume !(1 == ~T8_E~0); 50574#L1467-1 assume !(1 == ~T9_E~0); 50595#L1472-1 assume !(1 == ~T10_E~0); 50596#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 50364#L1482-1 assume !(1 == ~T12_E~0); 50365#L1487-1 assume !(1 == ~T13_E~0); 49389#L1492-1 assume !(1 == ~E_M~0); 49390#L1497-1 assume !(1 == ~E_1~0); 49760#L1502-1 assume !(1 == ~E_2~0); 49761#L1507-1 assume !(1 == ~E_3~0); 49266#L1512-1 assume !(1 == ~E_4~0); 49267#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 50668#L1522-1 assume !(1 == ~E_6~0); 50003#L1527-1 assume !(1 == ~E_7~0); 50004#L1532-1 assume !(1 == ~E_8~0); 50869#L1537-1 assume !(1 == ~E_9~0); 50211#L1542-1 assume !(1 == ~E_10~0); 50032#L1547-1 assume !(1 == ~E_11~0); 50033#L1552-1 assume !(1 == ~E_12~0); 48962#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 48963#L1562-1 assume { :end_inline_reset_delta_events } true; 49572#L1928-2 [2024-11-08 00:35:57,811 INFO L747 eck$LassoCheckResult]: Loop: 49572#L1928-2 assume !false; 50070#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 49647#L1254-1 assume !false; 49879#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 49291#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 49292#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 49491#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 50654#L1067 assume !(0 != eval_~tmp~0#1); 49944#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 49549#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 49550#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 49780#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 49764#L1284-3 assume !(0 == ~T2_E~0); 49765#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 49745#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 49746#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 50138#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 50139#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 49626#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 49627#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 50617#L1324-3 assume !(0 == ~T10_E~0); 49264#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 49265#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 50038#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 50039#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 50343#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 49610#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 49611#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 50351#L1364-3 assume !(0 == ~E_4~0); 50868#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 50760#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 49393#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 49394#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 49608#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 49609#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 49915#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 50770#L1404-3 assume !(0 == ~E_12~0); 50735#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 50736#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 50240#L628-45 assume 1 == ~m_pc~0; 49910#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 49912#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 50423#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 49644#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 49645#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 50375#L647-45 assume 1 == ~t1_pc~0; 49212#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 49213#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 50156#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 49322#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 49323#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 49533#L666-45 assume !(1 == ~t2_pc~0); 49534#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 50024#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 50421#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 50422#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 50487#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49074#L685-45 assume 1 == ~t3_pc~0; 49075#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 50152#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 50800#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 50666#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 50667#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 50809#L704-45 assume 1 == ~t4_pc~0; 50690#L705-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 48942#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 49810#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 50691#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 50897#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 50269#L723-45 assume !(1 == ~t5_pc~0); 50270#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 50747#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 50859#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 49622#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 49623#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 50637#L742-45 assume 1 == ~t6_pc~0; 50638#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 49887#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 50097#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 50098#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 50380#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 50466#L761-45 assume !(1 == ~t7_pc~0); 50467#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 49881#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 49882#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 49270#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 49271#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 50739#L780-45 assume 1 == ~t8_pc~0; 49648#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 49281#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 49282#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 50866#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 49250#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 49251#L799-45 assume 1 == ~t9_pc~0; 50036#L800-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 49470#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 50532#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 50416#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 50417#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 49192#L818-45 assume 1 == ~t10_pc~0; 49193#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 49310#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 50393#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 49808#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 49809#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 50512#L837-45 assume !(1 == ~t11_pc~0); 49738#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 49739#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 49262#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 49263#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 49331#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 49332#L856-45 assume !(1 == ~t12_pc~0); 49333#L856-47 is_transmit12_triggered_~__retres1~12#1 := 0; 49334#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 50563#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 50564#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 50154#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 50155#L875-45 assume 1 == ~t13_pc~0; 50122#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 50123#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 50183#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 50524#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 50780#L1695-47 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 50724#L1427-3 assume !(1 == ~M_E~0); 49949#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 49950#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 50474#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 50141#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 50142#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 48979#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 48980#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 50652#L1462-3 assume !(1 == ~T8_E~0); 50653#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 50520#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 50521#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 49234#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 49235#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 49377#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 49547#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 49548#L1502-3 assume !(1 == ~E_2~0); 50494#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 50615#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 49586#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 49274#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 49275#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 49241#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 49242#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 50352#L1542-3 assume !(1 == ~E_10~0); 50480#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 50125#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 50126#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 49445#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 49446#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 48867#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 49304#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 49305#L1947 assume !(0 == start_simulation_~tmp~3#1); 50258#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 50448#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 49506#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 48929#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 48930#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 50583#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 50584#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 50744#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 49572#L1928-2 [2024-11-08 00:35:57,812 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:57,812 INFO L85 PathProgramCache]: Analyzing trace with hash 10886919, now seen corresponding path program 1 times [2024-11-08 00:35:57,812 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:57,812 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [12325926] [2024-11-08 00:35:57,812 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:57,812 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:57,821 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:57,840 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:57,840 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:57,841 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [12325926] [2024-11-08 00:35:57,841 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [12325926] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:57,841 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:57,841 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:57,841 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1922944089] [2024-11-08 00:35:57,841 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:57,841 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:35:57,841 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:57,841 INFO L85 PathProgramCache]: Analyzing trace with hash 340495405, now seen corresponding path program 1 times [2024-11-08 00:35:57,842 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:57,842 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1273264719] [2024-11-08 00:35:57,842 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:57,842 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:57,851 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:57,878 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:57,878 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:57,879 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1273264719] [2024-11-08 00:35:57,879 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1273264719] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:57,879 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:57,879 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:57,879 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1176436805] [2024-11-08 00:35:57,879 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:57,879 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:35:57,879 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:35:57,879 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:35:57,879 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:35:57,879 INFO L87 Difference]: Start difference. First operand 2032 states and 2990 transitions. cyclomatic complexity: 959 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:57,900 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:35:57,900 INFO L93 Difference]: Finished difference Result 2032 states and 2989 transitions. [2024-11-08 00:35:57,900 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2032 states and 2989 transitions. [2024-11-08 00:35:57,904 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1857 [2024-11-08 00:35:57,908 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2032 states to 2032 states and 2989 transitions. [2024-11-08 00:35:57,908 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2032 [2024-11-08 00:35:57,909 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2032 [2024-11-08 00:35:57,909 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2032 states and 2989 transitions. [2024-11-08 00:35:57,912 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:35:57,912 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2032 states and 2989 transitions. [2024-11-08 00:35:57,913 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2032 states and 2989 transitions. [2024-11-08 00:35:57,926 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2032 to 2032. [2024-11-08 00:35:57,928 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2032 states, 2032 states have (on average 1.4709645669291338) internal successors, (2989), 2031 states have internal predecessors, (2989), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:57,931 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2032 states to 2032 states and 2989 transitions. [2024-11-08 00:35:57,931 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2032 states and 2989 transitions. [2024-11-08 00:35:57,931 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:35:57,932 INFO L425 stractBuchiCegarLoop]: Abstraction has 2032 states and 2989 transitions. [2024-11-08 00:35:57,932 INFO L332 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2024-11-08 00:35:57,932 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2032 states and 2989 transitions. [2024-11-08 00:35:57,935 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1857 [2024-11-08 00:35:57,935 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:35:57,935 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:35:57,937 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:57,937 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:57,937 INFO L745 eck$LassoCheckResult]: Stem: 53268#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 53269#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 54255#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 54256#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 54955#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 53849#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 53850#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 53920#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 53921#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 54358#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 54359#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 53884#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 53689#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 53690#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 54148#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 54149#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 54028#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 54029#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 53663#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 53664#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 54879#L1279-2 assume !(0 == ~T1_E~0); 53289#L1284-1 assume !(0 == ~T2_E~0); 53290#L1289-1 assume !(0 == ~T3_E~0); 54025#L1294-1 assume !(0 == ~T4_E~0); 54026#L1299-1 assume !(0 == ~T5_E~0); 54037#L1304-1 assume !(0 == ~T6_E~0); 54954#L1309-1 assume !(0 == ~T7_E~0); 54956#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 53213#L1319-1 assume !(0 == ~T9_E~0); 53214#L1324-1 assume !(0 == ~T10_E~0); 53387#L1329-1 assume !(0 == ~T11_E~0); 53388#L1334-1 assume !(0 == ~T12_E~0); 54797#L1339-1 assume !(0 == ~T13_E~0); 54869#L1344-1 assume !(0 == ~E_M~0); 54870#L1349-1 assume !(0 == ~E_1~0); 54214#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 54215#L1359-1 assume !(0 == ~E_3~0); 54622#L1364-1 assume !(0 == ~E_4~0); 53513#L1369-1 assume !(0 == ~E_5~0); 53514#L1374-1 assume !(0 == ~E_6~0); 54221#L1379-1 assume !(0 == ~E_7~0); 54222#L1384-1 assume !(0 == ~E_8~0); 54299#L1389-1 assume !(0 == ~E_9~0); 54816#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 54817#L1399-1 assume !(0 == ~E_11~0); 54910#L1404-1 assume !(0 == ~E_12~0); 53611#L1409-1 assume !(0 == ~E_13~0); 53612#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 54905#L628 assume !(1 == ~m_pc~0); 53512#L628-2 is_master_triggered_~__retres1~0#1 := 0; 53511#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 54096#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 54097#L1591 assume !(0 != activate_threads_~tmp~1#1); 54918#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 54077#L647 assume 1 == ~t1_pc~0; 53437#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 53438#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 54128#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 54585#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 54857#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 54858#L666 assume 1 == ~t2_pc~0; 53286#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 53287#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 53428#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 53429#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 54410#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 54411#L685 assume !(1 == ~t3_pc~0); 54505#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 54504#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 54574#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 54263#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 54264#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 53737#L704 assume 1 == ~t4_pc~0; 53738#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 54275#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 53077#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 53078#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 54126#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 54127#L723 assume !(1 == ~t5_pc~0); 54259#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 54477#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 54615#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 54389#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 54390#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 53495#L742 assume 1 == ~t6_pc~0; 53496#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 53652#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 53419#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 53182#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 53183#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 53573#L761 assume !(1 == ~t7_pc~0); 53574#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 53449#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 53450#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 54266#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 54267#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 53205#L780 assume 1 == ~t8_pc~0; 53206#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 53485#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 53486#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 54228#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 54229#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 54345#L799 assume 1 == ~t9_pc~0; 54447#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 53208#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 53209#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 53480#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 54548#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 54371#L818 assume !(1 == ~t10_pc~0); 52992#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 52993#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 54440#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 54374#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 54375#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 54417#L837 assume 1 == ~t11_pc~0; 54418#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 54253#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 54861#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 54338#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 54339#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 54085#L856 assume !(1 == ~t12_pc~0); 54086#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 54720#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 53010#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 53011#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 54698#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 54882#L875 assume 1 == ~t13_pc~0; 54035#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 53653#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 53654#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 53591#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 53592#L1695-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 54439#L1427 assume !(1 == ~M_E~0); 54424#L1427-2 assume !(1 == ~T1_E~0); 53560#L1432-1 assume !(1 == ~T2_E~0); 53561#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 54627#L1442-1 assume !(1 == ~T4_E~0); 54628#L1447-1 assume !(1 == ~T5_E~0); 54486#L1452-1 assume !(1 == ~T6_E~0); 53129#L1457-1 assume !(1 == ~T7_E~0); 53130#L1462-1 assume !(1 == ~T8_E~0); 54645#L1467-1 assume !(1 == ~T9_E~0); 54666#L1472-1 assume !(1 == ~T10_E~0); 54667#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 54435#L1482-1 assume !(1 == ~T12_E~0); 54436#L1487-1 assume !(1 == ~T13_E~0); 53460#L1492-1 assume !(1 == ~E_M~0); 53461#L1497-1 assume !(1 == ~E_1~0); 53831#L1502-1 assume !(1 == ~E_2~0); 53832#L1507-1 assume !(1 == ~E_3~0); 53337#L1512-1 assume !(1 == ~E_4~0); 53338#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 54739#L1522-1 assume !(1 == ~E_6~0); 54074#L1527-1 assume !(1 == ~E_7~0); 54075#L1532-1 assume !(1 == ~E_8~0); 54940#L1537-1 assume !(1 == ~E_9~0); 54282#L1542-1 assume !(1 == ~E_10~0); 54103#L1547-1 assume !(1 == ~E_11~0); 54104#L1552-1 assume !(1 == ~E_12~0); 53033#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 53034#L1562-1 assume { :end_inline_reset_delta_events } true; 53643#L1928-2 [2024-11-08 00:35:57,938 INFO L747 eck$LassoCheckResult]: Loop: 53643#L1928-2 assume !false; 54141#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 53718#L1254-1 assume !false; 53950#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 53362#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 53363#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 53562#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 54725#L1067 assume !(0 != eval_~tmp~0#1); 54015#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 53620#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 53621#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 53851#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 53835#L1284-3 assume !(0 == ~T2_E~0); 53836#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 53816#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 53817#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 54209#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 54210#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 53697#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 53698#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 54688#L1324-3 assume !(0 == ~T10_E~0); 53335#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 53336#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 54109#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 54110#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 54414#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 53681#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 53682#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 54422#L1364-3 assume !(0 == ~E_4~0); 54939#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 54831#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 53464#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 53465#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 53679#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 53680#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 53986#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 54841#L1404-3 assume !(0 == ~E_12~0); 54806#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 54807#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 54311#L628-45 assume 1 == ~m_pc~0; 53981#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 53983#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 54494#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 53715#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 53716#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 54446#L647-45 assume 1 == ~t1_pc~0; 53283#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 53284#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 54227#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 53393#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 53394#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 53604#L666-45 assume !(1 == ~t2_pc~0); 53605#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 54095#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 54492#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 54493#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 54558#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 53145#L685-45 assume 1 == ~t3_pc~0; 53146#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 54223#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 54871#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 54737#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 54738#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 54880#L704-45 assume !(1 == ~t4_pc~0); 53012#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 53013#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 53881#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 54762#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 54968#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 54340#L723-45 assume !(1 == ~t5_pc~0); 54341#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 54818#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 54930#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 53693#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 53694#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 54708#L742-45 assume 1 == ~t6_pc~0; 54709#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 53958#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 54168#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 54169#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 54451#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 54537#L761-45 assume !(1 == ~t7_pc~0); 54538#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 53952#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 53953#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 53341#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 53342#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 54810#L780-45 assume 1 == ~t8_pc~0; 53719#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 53352#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 53353#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 54937#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 53321#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 53322#L799-45 assume !(1 == ~t9_pc~0); 53540#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 53541#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 54603#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 54487#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 54488#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 53263#L818-45 assume 1 == ~t10_pc~0; 53264#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 53381#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 54464#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 53879#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 53880#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 54583#L837-45 assume !(1 == ~t11_pc~0); 53809#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 53810#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 53333#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 53334#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 53402#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 53403#L856-45 assume !(1 == ~t12_pc~0); 53404#L856-47 is_transmit12_triggered_~__retres1~12#1 := 0; 53405#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 54634#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 54635#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 54225#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 54226#L875-45 assume 1 == ~t13_pc~0; 54193#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 54194#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 54254#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 54595#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 54851#L1695-47 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 54795#L1427-3 assume !(1 == ~M_E~0); 54020#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 54021#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 54545#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 54212#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 54213#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 53050#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 53051#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 54723#L1462-3 assume !(1 == ~T8_E~0); 54724#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 54591#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 54592#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 53305#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 53306#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 53448#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 53618#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 53619#L1502-3 assume !(1 == ~E_2~0); 54565#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 54686#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 53657#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 53345#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 53346#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 53312#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 53313#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 54423#L1542-3 assume !(1 == ~E_10~0); 54551#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 54196#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 54197#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 53516#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 53517#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 52938#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 53375#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 53376#L1947 assume !(0 == start_simulation_~tmp~3#1); 54329#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 54519#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 53577#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 53000#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 53001#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 54654#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 54655#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 54815#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 53643#L1928-2 [2024-11-08 00:35:57,938 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:57,938 INFO L85 PathProgramCache]: Analyzing trace with hash -327400631, now seen corresponding path program 1 times [2024-11-08 00:35:57,938 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:57,938 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1211168464] [2024-11-08 00:35:57,939 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:57,939 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:57,948 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:57,995 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:57,995 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:57,995 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1211168464] [2024-11-08 00:35:57,996 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1211168464] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:57,996 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:57,996 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-08 00:35:57,996 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1676066465] [2024-11-08 00:35:57,996 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:57,996 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:35:57,996 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:57,996 INFO L85 PathProgramCache]: Analyzing trace with hash 1650149743, now seen corresponding path program 3 times [2024-11-08 00:35:57,997 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:57,997 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [739295262] [2024-11-08 00:35:57,997 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:57,997 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:58,006 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:58,032 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:58,032 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:58,032 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [739295262] [2024-11-08 00:35:58,032 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [739295262] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:58,032 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:58,033 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:58,033 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1109023993] [2024-11-08 00:35:58,033 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:58,033 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:35:58,033 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:35:58,037 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:35:58,037 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:35:58,037 INFO L87 Difference]: Start difference. First operand 2032 states and 2989 transitions. cyclomatic complexity: 958 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:58,103 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:35:58,104 INFO L93 Difference]: Finished difference Result 3789 states and 5556 transitions. [2024-11-08 00:35:58,104 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3789 states and 5556 transitions. [2024-11-08 00:35:58,113 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3614 [2024-11-08 00:35:58,123 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3789 states to 3789 states and 5556 transitions. [2024-11-08 00:35:58,123 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3789 [2024-11-08 00:35:58,125 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3789 [2024-11-08 00:35:58,126 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3789 states and 5556 transitions. [2024-11-08 00:35:58,129 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:35:58,129 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3789 states and 5556 transitions. [2024-11-08 00:35:58,132 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3789 states and 5556 transitions. [2024-11-08 00:35:58,165 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3789 to 3789. [2024-11-08 00:35:58,168 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3789 states, 3789 states have (on average 1.466349960411718) internal successors, (5556), 3788 states have internal predecessors, (5556), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:58,174 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3789 states to 3789 states and 5556 transitions. [2024-11-08 00:35:58,174 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3789 states and 5556 transitions. [2024-11-08 00:35:58,174 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:35:58,175 INFO L425 stractBuchiCegarLoop]: Abstraction has 3789 states and 5556 transitions. [2024-11-08 00:35:58,175 INFO L332 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2024-11-08 00:35:58,175 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3789 states and 5556 transitions. [2024-11-08 00:35:58,181 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3614 [2024-11-08 00:35:58,181 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:35:58,181 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:35:58,183 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:58,183 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:58,183 INFO L745 eck$LassoCheckResult]: Stem: 59096#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 59097#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 60102#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 60103#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 60913#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 59681#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 59682#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 59753#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 59754#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 60214#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 60215#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 59719#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 59520#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 59521#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 59986#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 59987#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 59869#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 59870#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 59494#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 59495#L1279 assume !(0 == ~M_E~0); 60799#L1279-2 assume !(0 == ~T1_E~0); 59117#L1284-1 assume !(0 == ~T2_E~0); 59118#L1289-1 assume !(0 == ~T3_E~0); 59861#L1294-1 assume !(0 == ~T4_E~0); 59862#L1299-1 assume !(0 == ~T5_E~0); 59873#L1304-1 assume !(0 == ~T6_E~0); 60912#L1309-1 assume !(0 == ~T7_E~0); 60914#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 59043#L1319-1 assume !(0 == ~T9_E~0); 59044#L1324-1 assume !(0 == ~T10_E~0); 59217#L1329-1 assume !(0 == ~T11_E~0); 59218#L1334-1 assume !(0 == ~T12_E~0); 60702#L1339-1 assume !(0 == ~T13_E~0); 60785#L1344-1 assume !(0 == ~E_M~0); 60786#L1349-1 assume !(0 == ~E_1~0); 60057#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 60058#L1359-1 assume !(0 == ~E_3~0); 60496#L1364-1 assume !(0 == ~E_4~0); 59343#L1369-1 assume !(0 == ~E_5~0); 59344#L1374-1 assume !(0 == ~E_6~0); 60065#L1379-1 assume !(0 == ~E_7~0); 60066#L1384-1 assume !(0 == ~E_8~0); 60148#L1389-1 assume !(0 == ~E_9~0); 60723#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 60724#L1399-1 assume !(0 == ~E_11~0); 60839#L1404-1 assume !(0 == ~E_12~0); 59442#L1409-1 assume !(0 == ~E_13~0); 59443#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 60832#L628 assume !(1 == ~m_pc~0); 59342#L628-2 is_master_triggered_~__retres1~0#1 := 0; 59341#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 59933#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 59934#L1591 assume !(0 != activate_threads_~tmp~1#1); 60847#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 59913#L647 assume 1 == ~t1_pc~0; 59267#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 59268#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 59966#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 60455#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 60771#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 60772#L666 assume 1 == ~t2_pc~0; 59114#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 59115#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 59260#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 59261#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 60264#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 60265#L685 assume !(1 == ~t3_pc~0); 60369#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 60368#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 60441#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 60111#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 60112#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 59568#L704 assume 1 == ~t4_pc~0; 59569#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 60124#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 58905#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 58906#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 59964#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 59965#L723 assume !(1 == ~t5_pc~0); 60108#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 60342#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 60489#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 60246#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 60247#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 59326#L742 assume 1 == ~t6_pc~0; 59327#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 59483#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 59249#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 59012#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 59013#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 59404#L761 assume !(1 == ~t7_pc~0); 59405#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 59281#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 59282#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 60115#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 60116#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 59033#L780 assume 1 == ~t8_pc~0; 59034#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 59316#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 59317#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 60072#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 60073#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 60201#L799 assume 1 == ~t9_pc~0; 60310#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 59036#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 59037#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 59310#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 60414#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 60225#L818 assume !(1 == ~t10_pc~0); 58820#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 58821#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 60298#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 60228#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 60229#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 60272#L837 assume 1 == ~t11_pc~0; 60273#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 60101#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 60775#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 60191#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 60192#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 59924#L856 assume !(1 == ~t12_pc~0); 59925#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 60606#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 58838#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 58839#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 60585#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 60803#L875 assume 1 == ~t13_pc~0; 59871#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 59484#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 59485#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 59422#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 59423#L1695-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 60297#L1427 assume !(1 == ~M_E~0); 60283#L1427-2 assume !(1 == ~T1_E~0); 59390#L1432-1 assume !(1 == ~T2_E~0); 59391#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 60503#L1442-1 assume !(1 == ~T4_E~0); 60504#L1447-1 assume !(1 == ~T5_E~0); 60351#L1452-1 assume !(1 == ~T6_E~0); 58957#L1457-1 assume !(1 == ~T7_E~0); 58958#L1462-1 assume !(1 == ~T8_E~0); 60524#L1467-1 assume !(1 == ~T9_E~0); 60547#L1472-1 assume !(1 == ~T10_E~0); 60548#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 60293#L1482-1 assume !(1 == ~T12_E~0); 60294#L1487-1 assume !(1 == ~T13_E~0); 59290#L1492-1 assume !(1 == ~E_M~0); 59291#L1497-1 assume !(1 == ~E_1~0); 59663#L1502-1 assume !(1 == ~E_2~0); 59664#L1507-1 assume !(1 == ~E_3~0); 59166#L1512-1 assume !(1 == ~E_4~0); 59167#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 60634#L1522-1 assume !(1 == ~E_6~0); 59911#L1527-1 assume !(1 == ~E_7~0); 59912#L1532-1 assume !(1 == ~E_8~0); 60889#L1537-1 assume !(1 == ~E_9~0); 60131#L1542-1 assume !(1 == ~E_10~0); 59941#L1547-1 assume !(1 == ~E_11~0); 59942#L1552-1 assume !(1 == ~E_12~0); 58863#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 58864#L1562-1 assume { :end_inline_reset_delta_events } true; 59474#L1928-2 [2024-11-08 00:35:58,184 INFO L747 eck$LassoCheckResult]: Loop: 59474#L1928-2 assume !false; 60104#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 59783#L1254-1 assume !false; 59784#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 59191#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 59192#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 60647#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 60648#L1067 assume !(0 != eval_~tmp~0#1); 59855#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 59451#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 59452#L1279-3 assume !(0 == ~M_E~0); 60994#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 59668#L1284-3 assume !(0 == ~T2_E~0); 59669#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 60993#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 60992#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 60048#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 60049#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 59529#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 59530#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 60935#L1324-3 assume !(0 == ~T10_E~0); 60990#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 60989#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 59951#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 59952#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 60325#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 59512#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 59513#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 60279#L1364-3 assume !(0 == ~E_4~0); 60911#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 60739#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 59292#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 59293#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 59510#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 59511#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 59821#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 60930#L1404-3 assume !(0 == ~E_12~0); 60713#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 60714#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 60160#L628-45 assume !(1 == ~m_pc~0); 60161#L628-47 is_master_triggered_~__retres1~0#1 := 0; 60879#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 60880#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 59546#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 59547#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 60304#L647-45 assume 1 == ~t1_pc~0; 59111#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 59112#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 60980#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 60979#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 60796#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 59435#L666-45 assume !(1 == ~t2_pc~0); 59436#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 60861#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 60862#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 60429#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 60430#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 60977#L685-45 assume !(1 == ~t3_pc~0); 60064#L685-47 is_transmit3_triggered_~__retres1~3#1 := 0; 60063#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 60976#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 60630#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 60631#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 60838#L704-45 assume 1 == ~t4_pc~0; 60663#L705-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 58841#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 59714#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 60972#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 60971#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 60193#L723-45 assume !(1 == ~t5_pc~0); 60194#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 60725#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 60968#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 59524#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 59525#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 60924#L742-45 assume 1 == ~t6_pc~0; 60965#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 60277#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 60278#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 60311#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 60312#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 60401#L761-45 assume !(1 == ~t7_pc~0); 60402#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 59786#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 59787#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 60961#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 60960#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 60717#L780-45 assume 1 == ~t8_pc~0; 59550#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 59181#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 59182#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 60887#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 60888#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 59944#L799-45 assume 1 == ~t9_pc~0; 59945#L800-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 59371#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 60941#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 60349#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 60350#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 60953#L818-45 assume 1 == ~t10_pc~0; 60454#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 59209#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 60565#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 59711#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 59712#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 60780#L837-45 assume !(1 == ~t11_pc~0); 60781#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 59788#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 59162#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 59163#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 59232#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 59233#L856-45 assume !(1 == ~t12_pc~0); 60944#L856-47 is_transmit12_triggered_~__retres1~12#1 := 0; 60626#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 60627#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 60947#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 60068#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 60069#L875-45 assume 1 == ~t13_pc~0; 60032#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 60033#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 60465#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 60466#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 60946#L1695-47 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 60700#L1427-3 assume !(1 == ~M_E~0); 59856#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 59857#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 60409#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 60050#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 60051#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 58878#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 58879#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 60610#L1462-3 assume !(1 == ~T8_E~0); 60611#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 60461#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 60462#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 59134#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 59135#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 59278#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 59449#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 59450#L1502-3 assume !(1 == ~E_2~0); 60432#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 60570#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 59488#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 59174#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 59175#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 59141#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 59142#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 60280#L1542-3 assume !(1 == ~E_10~0); 60415#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 60035#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 60036#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 59346#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 59347#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 58766#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 59204#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 59205#L1947 assume !(0 == start_simulation_~tmp~3#1); 60180#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 60383#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 61034#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 61033#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 61032#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 61031#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 61030#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 61029#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 59474#L1928-2 [2024-11-08 00:35:58,184 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:58,184 INFO L85 PathProgramCache]: Analyzing trace with hash -867830137, now seen corresponding path program 1 times [2024-11-08 00:35:58,184 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:58,184 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1412788773] [2024-11-08 00:35:58,184 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:58,185 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:58,193 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:58,246 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:58,246 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:58,246 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1412788773] [2024-11-08 00:35:58,247 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1412788773] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:58,247 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:58,247 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:58,247 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2017241858] [2024-11-08 00:35:58,247 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:58,247 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:35:58,247 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:58,247 INFO L85 PathProgramCache]: Analyzing trace with hash -679170003, now seen corresponding path program 1 times [2024-11-08 00:35:58,247 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:58,248 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2023414670] [2024-11-08 00:35:58,248 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:58,248 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:58,258 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:58,285 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:58,286 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:58,286 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2023414670] [2024-11-08 00:35:58,286 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2023414670] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:58,286 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:58,286 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:58,286 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1788251336] [2024-11-08 00:35:58,286 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:58,287 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:35:58,287 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:35:58,287 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-08 00:35:58,287 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-08 00:35:58,287 INFO L87 Difference]: Start difference. First operand 3789 states and 5556 transitions. cyclomatic complexity: 1768 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:58,370 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:35:58,370 INFO L93 Difference]: Finished difference Result 5538 states and 8105 transitions. [2024-11-08 00:35:58,371 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5538 states and 8105 transitions. [2024-11-08 00:35:58,382 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5343 [2024-11-08 00:35:58,423 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5538 states to 5538 states and 8105 transitions. [2024-11-08 00:35:58,424 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5538 [2024-11-08 00:35:58,427 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5538 [2024-11-08 00:35:58,427 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5538 states and 8105 transitions. [2024-11-08 00:35:58,432 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:35:58,432 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5538 states and 8105 transitions. [2024-11-08 00:35:58,436 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5538 states and 8105 transitions. [2024-11-08 00:35:58,472 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5538 to 3789. [2024-11-08 00:35:58,475 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3789 states, 3789 states have (on average 1.4655581947743468) internal successors, (5553), 3788 states have internal predecessors, (5553), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:58,481 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3789 states to 3789 states and 5553 transitions. [2024-11-08 00:35:58,481 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3789 states and 5553 transitions. [2024-11-08 00:35:58,481 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-08 00:35:58,482 INFO L425 stractBuchiCegarLoop]: Abstraction has 3789 states and 5553 transitions. [2024-11-08 00:35:58,482 INFO L332 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2024-11-08 00:35:58,482 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3789 states and 5553 transitions. [2024-11-08 00:35:58,487 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3614 [2024-11-08 00:35:58,488 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:35:58,488 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:35:58,489 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:58,489 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:58,490 INFO L745 eck$LassoCheckResult]: Stem: 68433#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 68434#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 69424#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 69425#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 70147#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 69015#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 69016#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 69086#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 69087#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 69529#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 69530#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 69052#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 68854#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 68855#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 69315#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 69316#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 69200#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 69201#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 68828#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 68829#L1279 assume !(0 == ~M_E~0); 70057#L1279-2 assume !(0 == ~T1_E~0); 68454#L1284-1 assume !(0 == ~T2_E~0); 68455#L1289-1 assume !(0 == ~T3_E~0); 69192#L1294-1 assume !(0 == ~T4_E~0); 69193#L1299-1 assume !(0 == ~T5_E~0); 69204#L1304-1 assume !(0 == ~T6_E~0); 70144#L1309-1 assume !(0 == ~T7_E~0); 70148#L1314-1 assume !(0 == ~T8_E~0); 68380#L1319-1 assume !(0 == ~T9_E~0); 68381#L1324-1 assume !(0 == ~T10_E~0); 68552#L1329-1 assume !(0 == ~T11_E~0); 68553#L1334-1 assume !(0 == ~T12_E~0); 69972#L1339-1 assume !(0 == ~T13_E~0); 70047#L1344-1 assume !(0 == ~E_M~0); 70048#L1349-1 assume !(0 == ~E_1~0); 69385#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 69386#L1359-1 assume !(0 == ~E_3~0); 69791#L1364-1 assume !(0 == ~E_4~0); 68678#L1369-1 assume !(0 == ~E_5~0); 68679#L1374-1 assume !(0 == ~E_6~0); 69392#L1379-1 assume !(0 == ~E_7~0); 69393#L1384-1 assume !(0 == ~E_8~0); 69468#L1389-1 assume !(0 == ~E_9~0); 69992#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 69993#L1399-1 assume !(0 == ~E_11~0); 70092#L1404-1 assume !(0 == ~E_12~0); 68776#L1409-1 assume !(0 == ~E_13~0); 68777#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 70085#L628 assume !(1 == ~m_pc~0); 68677#L628-2 is_master_triggered_~__retres1~0#1 := 0; 68676#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 69263#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 69264#L1591 assume !(0 != activate_threads_~tmp~1#1); 70101#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 69244#L647 assume 1 == ~t1_pc~0; 68605#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 68606#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 69295#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 69754#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 70035#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 70036#L666 assume 1 == ~t2_pc~0; 68451#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 68452#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 68595#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 68596#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 69579#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 69580#L685 assume !(1 == ~t3_pc~0); 69674#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 69673#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 69743#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 69433#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 69434#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 68902#L704 assume 1 == ~t4_pc~0; 68903#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 69444#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 68242#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 68243#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 69293#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 69294#L723 assume !(1 == ~t5_pc~0); 69429#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 69648#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 69784#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 69561#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 69562#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 68661#L742 assume 1 == ~t6_pc~0; 68662#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 68817#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 68584#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 68349#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 68350#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 68738#L761 assume !(1 == ~t7_pc~0); 68739#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 68616#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 68617#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 69435#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 69436#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 68370#L780 assume 1 == ~t8_pc~0; 68371#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 68651#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 68652#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 69397#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 69398#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 69517#L799 assume 1 == ~t9_pc~0; 69619#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 68373#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 68374#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 68645#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 69719#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 69540#L818 assume !(1 == ~t10_pc~0); 68157#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 68158#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 69611#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 69543#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 69544#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 69586#L837 assume 1 == ~t11_pc~0; 69587#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 69423#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 70039#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 69507#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 69508#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 69255#L856 assume !(1 == ~t12_pc~0); 69256#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 69892#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 68175#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 68176#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 69872#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 70060#L875 assume 1 == ~t13_pc~0; 69202#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 68818#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 68819#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 68756#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 68757#L1695-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 69608#L1427 assume !(1 == ~M_E~0); 69595#L1427-2 assume !(1 == ~T1_E~0); 68725#L1432-1 assume !(1 == ~T2_E~0); 68726#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 69796#L1442-1 assume !(1 == ~T4_E~0); 69797#L1447-1 assume !(1 == ~T5_E~0); 69657#L1452-1 assume !(1 == ~T6_E~0); 68294#L1457-1 assume !(1 == ~T7_E~0); 68295#L1462-1 assume !(1 == ~T8_E~0); 69817#L1467-1 assume !(1 == ~T9_E~0); 69837#L1472-1 assume !(1 == ~T10_E~0); 69838#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 69604#L1482-1 assume !(1 == ~T12_E~0); 69605#L1487-1 assume !(1 == ~T13_E~0); 68625#L1492-1 assume !(1 == ~E_M~0); 68626#L1497-1 assume !(1 == ~E_1~0); 68997#L1502-1 assume !(1 == ~E_2~0); 68998#L1507-1 assume !(1 == ~E_3~0); 68502#L1512-1 assume !(1 == ~E_4~0); 68503#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 69912#L1522-1 assume !(1 == ~E_6~0); 69242#L1527-1 assume !(1 == ~E_7~0); 69243#L1532-1 assume !(1 == ~E_8~0); 70128#L1537-1 assume !(1 == ~E_9~0); 69454#L1542-1 assume !(1 == ~E_10~0); 69271#L1547-1 assume !(1 == ~E_11~0); 69272#L1552-1 assume !(1 == ~E_12~0); 68200#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 68201#L1562-1 assume { :end_inline_reset_delta_events } true; 68808#L1928-2 [2024-11-08 00:35:58,490 INFO L747 eck$LassoCheckResult]: Loop: 68808#L1928-2 assume !false; 69308#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 68883#L1254-1 assume !false; 69116#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 68527#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 68528#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 68727#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 69897#L1067 assume !(0 != eval_~tmp~0#1); 69186#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 68785#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 68786#L1279-3 assume !(0 == ~M_E~0); 69017#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 69001#L1284-3 assume !(0 == ~T2_E~0); 69002#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 68982#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 68983#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 69378#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 69379#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 68863#L1314-3 assume !(0 == ~T8_E~0); 68864#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 69860#L1324-3 assume !(0 == ~T10_E~0); 68500#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 68501#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 69277#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 69278#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 69583#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 68846#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 68847#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 69591#L1364-3 assume !(0 == ~E_4~0); 70127#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 70007#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 68629#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 68630#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 68844#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 68845#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 69152#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 70017#L1404-3 assume !(0 == ~E_12~0); 69982#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 69983#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 69480#L628-45 assume 1 == ~m_pc~0; 69147#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 69149#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 69663#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 68880#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 68881#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 69615#L647-45 assume 1 == ~t1_pc~0; 68448#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 68449#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 69396#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 68558#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 68559#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 68769#L666-45 assume 1 == ~t2_pc~0; 68771#L667-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 69262#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 69661#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 69662#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 69727#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 68310#L685-45 assume 1 == ~t3_pc~0; 68311#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 69391#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 70049#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 69910#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 69911#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 70059#L704-45 assume !(1 == ~t4_pc~0); 68180#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 68181#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 69047#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 69935#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 70160#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 69509#L723-45 assume 1 == ~t5_pc~0; 69511#L724-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 69994#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 70117#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 68858#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 68859#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 69880#L742-45 assume !(1 == ~t6_pc~0); 69124#L742-47 is_transmit6_triggered_~__retres1~6#1 := 0; 69125#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 69335#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 69336#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 69620#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 69707#L761-45 assume 1 == ~t7_pc~0; 69709#L762-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 69118#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 69119#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 68506#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 68507#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 69986#L780-45 assume !(1 == ~t8_pc~0); 68885#L780-47 is_transmit8_triggered_~__retres1~8#1 := 0; 68515#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 68516#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 70125#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 68486#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 68487#L799-45 assume !(1 == ~t9_pc~0); 68704#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 68705#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 69772#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 69655#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 69656#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 68425#L818-45 assume !(1 == ~t10_pc~0); 68427#L818-47 is_transmit10_triggered_~__retres1~10#1 := 0; 68544#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 69633#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 69042#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 69043#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 69752#L837-45 assume 1 == ~t11_pc~0; 70044#L838-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 68975#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 68496#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 68497#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 68567#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 68568#L856-45 assume !(1 == ~t12_pc~0); 68569#L856-47 is_transmit12_triggered_~__retres1~12#1 := 0; 68570#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 69804#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 69805#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 69394#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 69395#L875-45 assume 1 == ~t13_pc~0; 69362#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 69363#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 69421#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 69763#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 70025#L1695-47 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 69970#L1427-3 assume !(1 == ~M_E~0); 69187#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 69188#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 69714#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 69380#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 69381#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 68215#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 68216#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 69895#L1462-3 assume !(1 == ~T8_E~0); 69896#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 69760#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 69761#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 68470#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 68471#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 68613#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 68783#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 68784#L1502-3 assume !(1 == ~E_2~0); 69734#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 69858#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 68822#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 68510#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 68511#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 68477#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 68478#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 69592#L1542-3 assume !(1 == ~E_10~0); 69720#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 69365#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 69366#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 68681#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 68682#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 68103#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 68538#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 68539#L1947 assume !(0 == start_simulation_~tmp~3#1); 69498#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 69688#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 68742#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 68165#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 68166#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 69825#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 69826#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 69990#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 68808#L1928-2 [2024-11-08 00:35:58,490 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:58,491 INFO L85 PathProgramCache]: Analyzing trace with hash 1809696709, now seen corresponding path program 1 times [2024-11-08 00:35:58,491 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:58,491 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1821416921] [2024-11-08 00:35:58,491 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:58,491 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:58,501 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:58,539 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:58,539 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:58,539 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1821416921] [2024-11-08 00:35:58,539 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1821416921] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:58,539 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:58,539 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-08 00:35:58,539 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1544223673] [2024-11-08 00:35:58,539 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:58,540 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:35:58,540 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:58,540 INFO L85 PathProgramCache]: Analyzing trace with hash -1593720982, now seen corresponding path program 1 times [2024-11-08 00:35:58,540 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:58,540 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [702605344] [2024-11-08 00:35:58,540 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:58,540 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:58,551 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:58,592 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:58,592 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:58,592 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [702605344] [2024-11-08 00:35:58,592 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [702605344] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:58,592 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:58,593 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:58,593 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1804697089] [2024-11-08 00:35:58,593 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:58,593 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:35:58,593 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:35:58,593 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:35:58,593 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:35:58,594 INFO L87 Difference]: Start difference. First operand 3789 states and 5553 transitions. cyclomatic complexity: 1765 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:58,656 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:35:58,656 INFO L93 Difference]: Finished difference Result 3789 states and 5515 transitions. [2024-11-08 00:35:58,657 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3789 states and 5515 transitions. [2024-11-08 00:35:58,664 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3614 [2024-11-08 00:35:58,670 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3789 states to 3789 states and 5515 transitions. [2024-11-08 00:35:58,670 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3789 [2024-11-08 00:35:58,672 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3789 [2024-11-08 00:35:58,672 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3789 states and 5515 transitions. [2024-11-08 00:35:58,675 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:35:58,675 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3789 states and 5515 transitions. [2024-11-08 00:35:58,677 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3789 states and 5515 transitions. [2024-11-08 00:35:58,698 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3789 to 3789. [2024-11-08 00:35:58,701 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3789 states, 3789 states have (on average 1.4555291633676433) internal successors, (5515), 3788 states have internal predecessors, (5515), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:58,707 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3789 states to 3789 states and 5515 transitions. [2024-11-08 00:35:58,707 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3789 states and 5515 transitions. [2024-11-08 00:35:58,708 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:35:58,708 INFO L425 stractBuchiCegarLoop]: Abstraction has 3789 states and 5515 transitions. [2024-11-08 00:35:58,708 INFO L332 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2024-11-08 00:35:58,708 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3789 states and 5515 transitions. [2024-11-08 00:35:58,713 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3614 [2024-11-08 00:35:58,713 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:35:58,713 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:35:58,715 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:58,715 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:58,715 INFO L745 eck$LassoCheckResult]: Stem: 76017#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 76018#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 77012#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 77013#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 77785#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 76599#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 76600#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 76671#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 76672#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 77121#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 77122#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 76636#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 76437#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 76438#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 76900#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 76901#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 76785#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 76786#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 76411#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 76412#L1279 assume !(0 == ~M_E~0); 77682#L1279-2 assume !(0 == ~T1_E~0); 76037#L1284-1 assume !(0 == ~T2_E~0); 76038#L1289-1 assume !(0 == ~T3_E~0); 76777#L1294-1 assume !(0 == ~T4_E~0); 76778#L1299-1 assume !(0 == ~T5_E~0); 76789#L1304-1 assume !(0 == ~T6_E~0); 77783#L1309-1 assume !(0 == ~T7_E~0); 77786#L1314-1 assume !(0 == ~T8_E~0); 75964#L1319-1 assume !(0 == ~T9_E~0); 75965#L1324-1 assume !(0 == ~T10_E~0); 76135#L1329-1 assume !(0 == ~T11_E~0); 76136#L1334-1 assume !(0 == ~T12_E~0); 77588#L1339-1 assume !(0 == ~T13_E~0); 77670#L1344-1 assume !(0 == ~E_M~0); 77671#L1349-1 assume !(0 == ~E_1~0); 76970#L1354-1 assume !(0 == ~E_2~0); 76971#L1359-1 assume !(0 == ~E_3~0); 77391#L1364-1 assume !(0 == ~E_4~0); 76261#L1369-1 assume !(0 == ~E_5~0); 76262#L1374-1 assume !(0 == ~E_6~0); 76977#L1379-1 assume !(0 == ~E_7~0); 76978#L1384-1 assume !(0 == ~E_8~0); 77058#L1389-1 assume !(0 == ~E_9~0); 77609#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 77610#L1399-1 assume !(0 == ~E_11~0); 77721#L1404-1 assume !(0 == ~E_12~0); 76359#L1409-1 assume !(0 == ~E_13~0); 76360#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 77713#L628 assume !(1 == ~m_pc~0); 76260#L628-2 is_master_triggered_~__retres1~0#1 := 0; 76259#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 76848#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 76849#L1591 assume !(0 != activate_threads_~tmp~1#1); 77730#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 76829#L647 assume 1 == ~t1_pc~0; 76188#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 76189#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 76880#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 77351#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 77656#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 77657#L666 assume !(1 == ~t2_pc~0); 76036#L666-2 is_transmit2_triggered_~__retres1~2#1 := 0; 76203#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 76177#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 76178#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 77171#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 77172#L685 assume !(1 == ~t3_pc~0); 77267#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 77266#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 77338#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 77022#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 77023#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 76485#L704 assume 1 == ~t4_pc~0; 76486#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 77033#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 75827#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 75828#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 76878#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 76879#L723 assume !(1 == ~t5_pc~0); 77018#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 77241#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 77384#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 77153#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 77154#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 76244#L742 assume 1 == ~t6_pc~0; 76245#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 76400#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 76166#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 75933#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 75934#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 76322#L761 assume !(1 == ~t7_pc~0); 76323#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 76199#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 76200#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 77024#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 77025#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 75954#L780 assume 1 == ~t8_pc~0; 75955#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 76234#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 76235#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 76982#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 76983#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 77108#L799 assume 1 == ~t9_pc~0; 77212#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 75957#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 75958#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 76229#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 77312#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 77132#L818 assume !(1 == ~t10_pc~0); 75742#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 75743#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 77204#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 77135#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 77136#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 77178#L837 assume 1 == ~t11_pc~0; 77179#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 77010#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 77660#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 77098#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 77099#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 76840#L856 assume !(1 == ~t12_pc~0); 76841#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 77493#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 75760#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 75761#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 77473#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 77687#L875 assume 1 == ~t13_pc~0; 76787#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 76401#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 76402#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 76340#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 76341#L1695-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 77201#L1427 assume !(1 == ~M_E~0); 77187#L1427-2 assume !(1 == ~T1_E~0); 76308#L1432-1 assume !(1 == ~T2_E~0); 76309#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 77396#L1442-1 assume !(1 == ~T4_E~0); 77397#L1447-1 assume !(1 == ~T5_E~0); 77250#L1452-1 assume !(1 == ~T6_E~0); 75878#L1457-1 assume !(1 == ~T7_E~0); 75879#L1462-1 assume !(1 == ~T8_E~0); 77416#L1467-1 assume !(1 == ~T9_E~0); 77438#L1472-1 assume !(1 == ~T10_E~0); 77439#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 77197#L1482-1 assume !(1 == ~T12_E~0); 77198#L1487-1 assume !(1 == ~T13_E~0); 76209#L1492-1 assume !(1 == ~E_M~0); 76210#L1497-1 assume !(1 == ~E_1~0); 76581#L1502-1 assume !(1 == ~E_2~0); 76582#L1507-1 assume !(1 == ~E_3~0); 76085#L1512-1 assume !(1 == ~E_4~0); 76086#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 77514#L1522-1 assume !(1 == ~E_6~0); 76827#L1527-1 assume !(1 == ~E_7~0); 76828#L1532-1 assume !(1 == ~E_8~0); 77766#L1537-1 assume !(1 == ~E_9~0); 77043#L1542-1 assume !(1 == ~E_10~0); 76856#L1547-1 assume !(1 == ~E_11~0); 76857#L1552-1 assume !(1 == ~E_12~0); 75785#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 75786#L1562-1 assume { :end_inline_reset_delta_events } true; 76391#L1928-2 [2024-11-08 00:35:58,716 INFO L747 eck$LassoCheckResult]: Loop: 76391#L1928-2 assume !false; 77011#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 76701#L1254-1 assume !false; 76702#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 76110#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 76111#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 77530#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 77531#L1067 assume !(0 != eval_~tmp~0#1); 77811#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 77810#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 77712#L1279-3 assume !(0 == ~M_E~0); 76601#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 76585#L1284-3 assume !(0 == ~T2_E~0); 76586#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 76565#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 76566#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 76963#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 76964#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 76445#L1314-3 assume !(0 == ~T8_E~0); 76446#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 77460#L1324-3 assume !(0 == ~T10_E~0); 76083#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 76084#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 76861#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 76862#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 77175#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 76429#L1354-3 assume !(0 == ~E_2~0); 76430#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 77183#L1364-3 assume !(0 == ~E_4~0); 77763#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 77626#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 76213#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 76214#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 76427#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 76428#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 76738#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 77636#L1404-3 assume !(0 == ~E_12~0); 77599#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 77600#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 77070#L628-45 assume 1 == ~m_pc~0; 76733#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 76735#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 77256#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 76463#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 76464#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 77208#L647-45 assume 1 == ~t1_pc~0; 76032#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 76033#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 76981#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 76140#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 76141#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 76352#L666-45 assume !(1 == ~t2_pc~0); 76353#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 76847#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 77254#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 77255#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 77320#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 75894#L685-45 assume 1 == ~t3_pc~0; 75895#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 76976#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 77672#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 77512#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 77513#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 77683#L704-45 assume !(1 == ~t4_pc~0); 75765#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 75766#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 76631#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 77546#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 77805#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 77100#L723-45 assume !(1 == ~t5_pc~0); 77101#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 77611#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 77745#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 76441#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 76442#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 77481#L742-45 assume !(1 == ~t6_pc~0); 76710#L742-47 is_transmit6_triggered_~__retres1~6#1 := 0; 76711#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 76921#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 76922#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 77213#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 77299#L761-45 assume 1 == ~t7_pc~0; 77301#L762-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 76704#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 76705#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 76089#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 76090#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 77603#L780-45 assume 1 == ~t8_pc~0; 76467#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 76102#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 76103#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 77758#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 76069#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 76070#L799-45 assume !(1 == ~t9_pc~0); 76291#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 76292#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 77372#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 77248#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 77249#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 76012#L818-45 assume 1 == ~t10_pc~0; 76013#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 76131#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 77226#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 76629#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 76630#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 77348#L837-45 assume !(1 == ~t11_pc~0); 76561#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 76562#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 76081#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 76082#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 76152#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 76153#L856-45 assume 1 == ~t12_pc~0; 77681#L857-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 76155#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 77511#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 78077#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 78075#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 78073#L875-45 assume 1 == ~t13_pc~0; 78071#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 78068#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 78066#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 78064#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 78062#L1695-47 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 78060#L1427-3 assume !(1 == ~M_E~0); 77586#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 78057#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 78055#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 78053#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 78051#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 78049#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 78047#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 78045#L1462-3 assume !(1 == ~T8_E~0); 78043#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 78041#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 78039#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 78038#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 78037#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 78036#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 78035#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 78034#L1502-3 assume !(1 == ~E_2~0); 78033#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 78032#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 78031#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 78030#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 78029#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 78028#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 78027#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 78026#L1542-3 assume !(1 == ~E_10~0); 78025#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 78024#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 78023#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 78022#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 77984#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 77976#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 77974#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 77972#L1947 assume !(0 == start_simulation_~tmp~3#1); 77969#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 77403#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 76326#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 75750#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 75751#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 77422#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 77423#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 77607#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 76391#L1928-2 [2024-11-08 00:35:58,716 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:58,716 INFO L85 PathProgramCache]: Analyzing trace with hash 350046660, now seen corresponding path program 1 times [2024-11-08 00:35:58,716 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:58,716 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1143290743] [2024-11-08 00:35:58,716 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:58,716 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:58,725 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:58,775 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:58,775 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:58,775 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1143290743] [2024-11-08 00:35:58,775 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1143290743] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:58,775 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:58,775 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:58,775 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1458270484] [2024-11-08 00:35:58,775 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:58,776 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:35:58,776 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:58,776 INFO L85 PathProgramCache]: Analyzing trace with hash -2132936536, now seen corresponding path program 1 times [2024-11-08 00:35:58,776 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:58,776 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [604137244] [2024-11-08 00:35:58,776 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:58,776 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:58,786 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:58,841 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:58,841 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:58,841 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [604137244] [2024-11-08 00:35:58,841 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [604137244] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:58,841 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:58,841 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:35:58,841 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [160736532] [2024-11-08 00:35:58,841 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:58,841 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:35:58,842 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:35:58,842 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-08 00:35:58,842 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-08 00:35:58,842 INFO L87 Difference]: Start difference. First operand 3789 states and 5515 transitions. cyclomatic complexity: 1727 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:58,993 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:35:58,993 INFO L93 Difference]: Finished difference Result 5423 states and 7875 transitions. [2024-11-08 00:35:58,994 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5423 states and 7875 transitions. [2024-11-08 00:35:59,008 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5243 [2024-11-08 00:35:59,020 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5423 states to 5423 states and 7875 transitions. [2024-11-08 00:35:59,020 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5423 [2024-11-08 00:35:59,023 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5423 [2024-11-08 00:35:59,023 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5423 states and 7875 transitions. [2024-11-08 00:35:59,029 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:35:59,029 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5423 states and 7875 transitions. [2024-11-08 00:35:59,032 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5423 states and 7875 transitions. [2024-11-08 00:35:59,068 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5423 to 3789. [2024-11-08 00:35:59,072 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3789 states, 3789 states have (on average 1.4547373977302718) internal successors, (5512), 3788 states have internal predecessors, (5512), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:59,079 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3789 states to 3789 states and 5512 transitions. [2024-11-08 00:35:59,079 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3789 states and 5512 transitions. [2024-11-08 00:35:59,079 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-08 00:35:59,080 INFO L425 stractBuchiCegarLoop]: Abstraction has 3789 states and 5512 transitions. [2024-11-08 00:35:59,080 INFO L332 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2024-11-08 00:35:59,080 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3789 states and 5512 transitions. [2024-11-08 00:35:59,087 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3614 [2024-11-08 00:35:59,087 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:35:59,087 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:35:59,089 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:59,090 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:59,090 INFO L745 eck$LassoCheckResult]: Stem: 85242#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 85243#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 86248#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 86249#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 87012#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 85830#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 85831#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 85902#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 85903#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 86353#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 86354#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 85868#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 85666#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 85667#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 86134#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 86135#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 86019#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 86020#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 85639#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 85640#L1279 assume !(0 == ~M_E~0); 86911#L1279-2 assume !(0 == ~T1_E~0); 85262#L1284-1 assume !(0 == ~T2_E~0); 85263#L1289-1 assume !(0 == ~T3_E~0); 86011#L1294-1 assume !(0 == ~T4_E~0); 86012#L1299-1 assume !(0 == ~T5_E~0); 86023#L1304-1 assume !(0 == ~T6_E~0); 87011#L1309-1 assume !(0 == ~T7_E~0); 87013#L1314-1 assume !(0 == ~T8_E~0); 85188#L1319-1 assume !(0 == ~T9_E~0); 85189#L1324-1 assume !(0 == ~T10_E~0); 85360#L1329-1 assume !(0 == ~T11_E~0); 85361#L1334-1 assume !(0 == ~T12_E~0); 86817#L1339-1 assume !(0 == ~T13_E~0); 86898#L1344-1 assume !(0 == ~E_M~0); 86899#L1349-1 assume !(0 == ~E_1~0); 86205#L1354-1 assume !(0 == ~E_2~0); 86206#L1359-1 assume !(0 == ~E_3~0); 86629#L1364-1 assume !(0 == ~E_4~0); 85488#L1369-1 assume !(0 == ~E_5~0); 85489#L1374-1 assume !(0 == ~E_6~0); 86212#L1379-1 assume !(0 == ~E_7~0); 86213#L1384-1 assume !(0 == ~E_8~0); 86292#L1389-1 assume !(0 == ~E_9~0); 86840#L1394-1 assume !(0 == ~E_10~0); 86841#L1399-1 assume !(0 == ~E_11~0); 86948#L1404-1 assume !(0 == ~E_12~0); 85586#L1409-1 assume !(0 == ~E_13~0); 85587#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 86940#L628 assume !(1 == ~m_pc~0); 85487#L628-2 is_master_triggered_~__retres1~0#1 := 0; 85486#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 86082#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 86083#L1591 assume !(0 != activate_threads_~tmp~1#1); 86957#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 86063#L647 assume 1 == ~t1_pc~0; 85414#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 85415#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 86114#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 86591#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 86886#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 86887#L666 assume !(1 == ~t2_pc~0); 85261#L666-2 is_transmit2_triggered_~__retres1~2#1 := 0; 85429#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 85404#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 85405#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 86405#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 86406#L685 assume !(1 == ~t3_pc~0); 86505#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 86504#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 86576#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 86257#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 86258#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 85714#L704 assume 1 == ~t4_pc~0; 85715#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 86268#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 85049#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 85050#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 86112#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 86113#L723 assume !(1 == ~t5_pc~0); 86253#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 86476#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 86622#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 86387#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 86388#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 85471#L742 assume 1 == ~t6_pc~0; 85472#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 85628#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 85393#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 85157#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 85158#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 85548#L761 assume !(1 == ~t7_pc~0); 85549#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 85425#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 85426#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 86259#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 86260#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 85178#L780 assume 1 == ~t8_pc~0; 85179#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 85461#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 85462#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 86217#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 86218#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 86341#L799 assume 1 == ~t9_pc~0; 86447#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 85181#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 85182#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 85456#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 86550#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 86364#L818 assume !(1 == ~t10_pc~0); 84964#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 84965#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 86439#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 86367#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 86368#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 86412#L837 assume 1 == ~t11_pc~0; 86413#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 86247#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 86890#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 86331#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 86332#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 86074#L856 assume !(1 == ~t12_pc~0); 86075#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 86737#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 84982#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 84983#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 86716#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 86914#L875 assume 1 == ~t13_pc~0; 86021#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 85629#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 85630#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 85567#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 85568#L1695-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 86434#L1427 assume !(1 == ~M_E~0); 86421#L1427-2 assume !(1 == ~T1_E~0); 85535#L1432-1 assume !(1 == ~T2_E~0); 85536#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 86634#L1442-1 assume !(1 == ~T4_E~0); 86635#L1447-1 assume !(1 == ~T5_E~0); 86485#L1452-1 assume !(1 == ~T6_E~0); 85101#L1457-1 assume !(1 == ~T7_E~0); 85102#L1462-1 assume !(1 == ~T8_E~0); 86657#L1467-1 assume !(1 == ~T9_E~0); 86677#L1472-1 assume !(1 == ~T10_E~0); 86678#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 86430#L1482-1 assume !(1 == ~T12_E~0); 86431#L1487-1 assume !(1 == ~T13_E~0); 85435#L1492-1 assume !(1 == ~E_M~0); 85436#L1497-1 assume !(1 == ~E_1~0); 85811#L1502-1 assume !(1 == ~E_2~0); 85812#L1507-1 assume !(1 == ~E_3~0); 85310#L1512-1 assume !(1 == ~E_4~0); 85311#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 86756#L1522-1 assume !(1 == ~E_6~0); 86061#L1527-1 assume !(1 == ~E_7~0); 86062#L1532-1 assume !(1 == ~E_8~0); 86984#L1537-1 assume !(1 == ~E_9~0); 86278#L1542-1 assume !(1 == ~E_10~0); 86090#L1547-1 assume !(1 == ~E_11~0); 86091#L1552-1 assume !(1 == ~E_12~0); 85007#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 85008#L1562-1 assume { :end_inline_reset_delta_events } true; 85618#L1928-2 [2024-11-08 00:35:59,090 INFO L747 eck$LassoCheckResult]: Loop: 85618#L1928-2 assume !false; 86127#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 85695#L1254-1 assume !false; 85934#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 85335#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 85336#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 85537#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 86742#L1067 assume !(0 != eval_~tmp~0#1); 86005#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 85595#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 85596#L1279-3 assume !(0 == ~M_E~0); 85834#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 85815#L1284-3 assume !(0 == ~T2_E~0); 85816#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 85795#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 85796#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 86198#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 86199#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 85675#L1314-3 assume !(0 == ~T8_E~0); 85676#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 86702#L1324-3 assume !(0 == ~T10_E~0); 85308#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 85309#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 86096#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 86097#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 86409#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 85658#L1354-3 assume !(0 == ~E_2~0); 85659#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 86417#L1364-3 assume !(0 == ~E_4~0); 86983#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 86856#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 85439#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 85440#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 85656#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 85657#L1394-3 assume !(0 == ~E_10~0); 85970#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 86866#L1404-3 assume !(0 == ~E_12~0); 86830#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 86831#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 86304#L628-45 assume !(1 == ~m_pc~0); 85968#L628-47 is_master_triggered_~__retres1~0#1 := 0; 85969#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 86494#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 85692#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 85693#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 86443#L647-45 assume 1 == ~t1_pc~0; 85257#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 85258#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 86216#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 85367#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 85368#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 85579#L666-45 assume !(1 == ~t2_pc~0); 85580#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 86081#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 86492#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 86493#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 86558#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 85117#L685-45 assume !(1 == ~t3_pc~0); 85119#L685-47 is_transmit3_triggered_~__retres1~3#1 := 0; 86211#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 86903#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 86754#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 86755#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 86913#L704-45 assume !(1 == ~t4_pc~0); 84987#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 84988#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 85863#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 86781#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 87032#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 86333#L723-45 assume 1 == ~t5_pc~0; 86335#L724-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 86842#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 86969#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 85670#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 85671#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 86724#L742-45 assume 1 == ~t6_pc~0; 86725#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 85942#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 86154#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 86155#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 86448#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 86537#L761-45 assume 1 == ~t7_pc~0; 86539#L762-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 85936#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 85937#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 85314#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 85315#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 86833#L780-45 assume !(1 == ~t8_pc~0); 85697#L780-47 is_transmit8_triggered_~__retres1~8#1 := 0; 85323#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 85324#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 86977#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 85294#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 85295#L799-45 assume !(1 == ~t9_pc~0); 85514#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 85515#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 86610#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 86483#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 86484#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 85235#L818-45 assume !(1 == ~t10_pc~0); 85237#L818-47 is_transmit10_triggered_~__retres1~10#1 := 0; 85352#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 86461#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 85860#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 85861#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 86586#L837-45 assume !(1 == ~t11_pc~0); 85787#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 85788#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 85304#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 85305#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 85376#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 85377#L856-45 assume !(1 == ~t12_pc~0); 85378#L856-47 is_transmit12_triggered_~__retres1~12#1 := 0; 85379#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 86642#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 86643#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 86214#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 86215#L875-45 assume 1 == ~t13_pc~0; 86182#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 86183#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 86245#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 86600#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 86878#L1695-47 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 86815#L1427-3 assume !(1 == ~M_E~0); 86006#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 86007#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 86545#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 86200#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 86201#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 85022#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 85023#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 86740#L1462-3 assume !(1 == ~T8_E~0); 86741#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 86597#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 86598#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 85278#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 85279#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 85422#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 85593#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 85594#L1502-3 assume !(1 == ~E_2~0); 86565#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 86700#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 85633#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 85318#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 85319#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 85285#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 85286#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 86418#L1542-3 assume !(1 == ~E_10~0); 86551#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 86185#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 86186#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 85491#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 85492#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 84910#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 85348#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 85349#L1947 assume !(0 == start_simulation_~tmp~3#1); 86322#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 86519#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 85552#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 84972#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 84973#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 86665#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 86666#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 86838#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 85618#L1928-2 [2024-11-08 00:35:59,091 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:59,091 INFO L85 PathProgramCache]: Analyzing trace with hash -1492429054, now seen corresponding path program 1 times [2024-11-08 00:35:59,091 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:59,091 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2094816479] [2024-11-08 00:35:59,091 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:59,091 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:59,103 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:59,144 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:59,144 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:59,144 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2094816479] [2024-11-08 00:35:59,144 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2094816479] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:59,144 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:59,144 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-08 00:35:59,144 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [812991735] [2024-11-08 00:35:59,144 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:59,145 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:35:59,145 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:59,145 INFO L85 PathProgramCache]: Analyzing trace with hash -2090864471, now seen corresponding path program 1 times [2024-11-08 00:35:59,145 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:59,145 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1817687787] [2024-11-08 00:35:59,145 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:59,145 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:59,159 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:59,211 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:59,212 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:59,212 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1817687787] [2024-11-08 00:35:59,212 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1817687787] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:59,212 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:59,212 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-08 00:35:59,212 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1731180621] [2024-11-08 00:35:59,212 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:59,212 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:35:59,213 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:35:59,213 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:35:59,213 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:35:59,213 INFO L87 Difference]: Start difference. First operand 3789 states and 5512 transitions. cyclomatic complexity: 1724 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:59,323 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:35:59,323 INFO L93 Difference]: Finished difference Result 7171 states and 10378 transitions. [2024-11-08 00:35:59,323 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7171 states and 10378 transitions. [2024-11-08 00:35:59,343 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6993 [2024-11-08 00:35:59,360 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7171 states to 7171 states and 10378 transitions. [2024-11-08 00:35:59,360 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7171 [2024-11-08 00:35:59,364 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7171 [2024-11-08 00:35:59,364 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7171 states and 10378 transitions. [2024-11-08 00:35:59,370 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:35:59,371 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7171 states and 10378 transitions. [2024-11-08 00:35:59,374 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7171 states and 10378 transitions. [2024-11-08 00:35:59,422 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7171 to 7167. [2024-11-08 00:35:59,429 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7167 states, 7167 states have (on average 1.4474675596483884) internal successors, (10374), 7166 states have internal predecessors, (10374), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:59,440 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7167 states to 7167 states and 10374 transitions. [2024-11-08 00:35:59,441 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7167 states and 10374 transitions. [2024-11-08 00:35:59,441 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:35:59,441 INFO L425 stractBuchiCegarLoop]: Abstraction has 7167 states and 10374 transitions. [2024-11-08 00:35:59,441 INFO L332 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2024-11-08 00:35:59,441 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7167 states and 10374 transitions. [2024-11-08 00:35:59,451 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6989 [2024-11-08 00:35:59,451 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:35:59,452 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:35:59,453 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:59,453 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:59,454 INFO L745 eck$LassoCheckResult]: Stem: 96207#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 96208#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 97210#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 97211#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 98021#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 96788#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 96789#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 96861#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 96862#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 97319#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 97320#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 96826#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 96628#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 96629#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 97098#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 97099#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 96972#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 96973#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 96603#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 96604#L1279 assume !(0 == ~M_E~0); 97909#L1279-2 assume !(0 == ~T1_E~0); 96229#L1284-1 assume !(0 == ~T2_E~0); 96230#L1289-1 assume !(0 == ~T3_E~0); 96969#L1294-1 assume !(0 == ~T4_E~0); 96970#L1299-1 assume !(0 == ~T5_E~0); 96981#L1304-1 assume !(0 == ~T6_E~0); 98020#L1309-1 assume !(0 == ~T7_E~0); 98022#L1314-1 assume !(0 == ~T8_E~0); 96152#L1319-1 assume !(0 == ~T9_E~0); 96153#L1324-1 assume !(0 == ~T10_E~0); 96328#L1329-1 assume !(0 == ~T11_E~0); 96329#L1334-1 assume !(0 == ~T12_E~0); 97809#L1339-1 assume !(0 == ~T13_E~0); 97896#L1344-1 assume !(0 == ~E_M~0); 97897#L1349-1 assume !(0 == ~E_1~0); 97166#L1354-1 assume !(0 == ~E_2~0); 97167#L1359-1 assume !(0 == ~E_3~0); 97607#L1364-1 assume !(0 == ~E_4~0); 96450#L1369-1 assume !(0 == ~E_5~0); 96451#L1374-1 assume !(0 == ~E_6~0); 97173#L1379-1 assume !(0 == ~E_7~0); 97174#L1384-1 assume !(0 == ~E_8~0); 97257#L1389-1 assume !(0 == ~E_9~0); 97834#L1394-1 assume !(0 == ~E_10~0); 97835#L1399-1 assume !(0 == ~E_11~0); 97945#L1404-1 assume !(0 == ~E_12~0); 96549#L1409-1 assume !(0 == ~E_13~0); 96550#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 97939#L628 assume !(1 == ~m_pc~0); 96449#L628-2 is_master_triggered_~__retres1~0#1 := 0; 96448#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 97042#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 97043#L1591 assume !(0 != activate_threads_~tmp~1#1); 97956#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 97022#L647 assume !(1 == ~t1_pc~0); 97023#L647-2 is_transmit1_triggered_~__retres1~1#1 := 0; 97077#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 97078#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 97566#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 97882#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 97883#L666 assume !(1 == ~t2_pc~0); 96228#L666-2 is_transmit2_triggered_~__retres1~2#1 := 0; 96390#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 96368#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 96369#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 97373#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 97374#L685 assume !(1 == ~t3_pc~0); 97476#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 97475#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 97550#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 97220#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 97221#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 96676#L704 assume 1 == ~t4_pc~0; 96677#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 97233#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 96018#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 96019#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 97075#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 97076#L723 assume !(1 == ~t5_pc~0); 97216#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 97448#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 97600#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 97352#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 97353#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 96432#L742 assume 1 == ~t6_pc~0; 96433#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 96592#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 96359#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 96122#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 96123#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 96512#L761 assume !(1 == ~t7_pc~0); 96513#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 96386#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 96387#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 97223#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 97224#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 96144#L780 assume 1 == ~t8_pc~0; 96145#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 96423#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 96424#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 97180#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 97181#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 97306#L799 assume 1 == ~t9_pc~0; 97415#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 96147#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 96148#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 96418#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 97521#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 97332#L818 assume !(1 == ~t10_pc~0); 95933#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 95934#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 97405#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 97335#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 97336#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 97382#L837 assume 1 == ~t11_pc~0; 97383#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 97208#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 97888#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 97299#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 97300#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 97031#L856 assume !(1 == ~t12_pc~0); 97032#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 97720#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 95951#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 95952#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 97695#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 97912#L875 assume 1 == ~t13_pc~0; 96979#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 96593#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 96594#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 96530#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 96531#L1695-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 97404#L1427 assume !(1 == ~M_E~0); 97389#L1427-2 assume !(1 == ~T1_E~0); 96498#L1432-1 assume !(1 == ~T2_E~0); 96499#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 97614#L1442-1 assume !(1 == ~T4_E~0); 97615#L1447-1 assume !(1 == ~T5_E~0); 97457#L1452-1 assume !(1 == ~T6_E~0); 96069#L1457-1 assume !(1 == ~T7_E~0); 96070#L1462-1 assume !(1 == ~T8_E~0); 97637#L1467-1 assume !(1 == ~T9_E~0); 97660#L1472-1 assume !(1 == ~T10_E~0); 97661#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 97400#L1482-1 assume !(1 == ~T12_E~0); 97401#L1487-1 assume !(1 == ~T13_E~0); 96398#L1492-1 assume !(1 == ~E_M~0); 96399#L1497-1 assume !(1 == ~E_1~0); 96770#L1502-1 assume !(1 == ~E_2~0); 96771#L1507-1 assume !(1 == ~E_3~0); 96278#L1512-1 assume !(1 == ~E_4~0); 96279#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 97742#L1522-1 assume !(1 == ~E_6~0); 97019#L1527-1 assume !(1 == ~E_7~0); 97020#L1532-1 assume !(1 == ~E_8~0); 97993#L1537-1 assume !(1 == ~E_9~0); 97240#L1542-1 assume !(1 == ~E_10~0); 97049#L1547-1 assume !(1 == ~E_11~0); 97050#L1552-1 assume !(1 == ~E_12~0); 95974#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 95975#L1562-1 assume { :end_inline_reset_delta_events } true; 96583#L1928-2 [2024-11-08 00:35:59,454 INFO L747 eck$LassoCheckResult]: Loop: 96583#L1928-2 assume !false; 98603#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 97765#L1254-1 assume !false; 98408#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 98400#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 98154#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 98155#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 98137#L1067 assume !(0 != eval_~tmp~0#1); 98138#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 101377#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 101376#L1279-3 assume !(0 == ~M_E~0); 101375#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 101374#L1284-3 assume !(0 == ~T2_E~0); 101373#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 101372#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 101371#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 101370#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 101369#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 101368#L1314-3 assume !(0 == ~T8_E~0); 101367#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 101366#L1324-3 assume !(0 == ~T10_E~0); 101365#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 101364#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 101363#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 97434#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 97379#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 96621#L1354-3 assume !(0 == ~E_2~0); 96622#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 97387#L1364-3 assume !(0 == ~E_4~0); 101359#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 101358#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 101357#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 101356#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 101355#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 101354#L1394-3 assume !(0 == ~E_10~0); 101353#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 101352#L1404-3 assume !(0 == ~E_12~0); 101351#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 101350#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 101349#L628-45 assume !(1 == ~m_pc~0); 96923#L628-47 is_master_triggered_~__retres1~0#1 := 0; 96924#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 97465#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 96654#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 96655#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 97413#L647-45 assume !(1 == ~t1_pc~0); 97414#L647-47 is_transmit1_triggered_~__retres1~1#1 := 0; 100050#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 100043#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 100034#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 100026#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 100018#L666-45 assume !(1 == ~t2_pc~0); 100010#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 100001#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 99994#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 99985#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 99977#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 99970#L685-45 assume 1 == ~t3_pc~0; 99961#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 99952#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 99945#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 99936#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 99928#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 99921#L704-45 assume 1 == ~t4_pc~0; 99913#L705-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 99903#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 99896#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 99887#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 99879#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 99872#L723-45 assume 1 == ~t5_pc~0; 99863#L724-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 99854#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 99847#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 99838#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 99830#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 99823#L742-45 assume !(1 == ~t6_pc~0); 99815#L742-47 is_transmit6_triggered_~__retres1~6#1 := 0; 99780#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 99769#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 99766#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 99764#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 99762#L761-45 assume !(1 == ~t7_pc~0); 99760#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 99757#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 99755#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 99752#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 99750#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 99748#L780-45 assume !(1 == ~t8_pc~0); 99745#L780-47 is_transmit8_triggered_~__retres1~8#1 := 0; 99742#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 99739#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 99737#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 99735#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 99733#L799-45 assume 1 == ~t9_pc~0; 99731#L800-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 99729#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 99728#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 98692#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 98689#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 98687#L818-45 assume !(1 == ~t10_pc~0); 98685#L818-47 is_transmit10_triggered_~__retres1~10#1 := 0; 98682#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 98680#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 98678#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 98675#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 98673#L837-45 assume !(1 == ~t11_pc~0); 98669#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 98667#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 98665#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 98662#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 98660#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 98658#L856-45 assume !(1 == ~t12_pc~0); 98656#L856-47 is_transmit12_triggered_~__retres1~12#1 := 0; 98653#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 98652#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 98651#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 98647#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 98645#L875-45 assume 1 == ~t13_pc~0; 98643#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 98641#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 98638#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 98637#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 98410#L1695-47 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 98261#L1427-3 assume !(1 == ~M_E~0); 98259#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 98256#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 98254#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 98252#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 98250#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 98247#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 98248#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 98880#L1462-3 assume !(1 == ~T8_E~0); 98878#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 98237#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 98234#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 98232#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 98233#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 98869#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 98867#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 98215#L1502-3 assume !(1 == ~E_2~0); 98212#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 98210#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 98208#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 98205#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 98203#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 98159#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 98151#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 98143#L1542-3 assume !(1 == ~E_10~0); 98134#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 98135#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 98121#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 98114#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 98115#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 98456#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 98455#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 98060#L1947 assume !(0 == start_simulation_~tmp~3#1); 98061#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 98626#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 98618#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 98616#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 98614#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 98610#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 98608#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 98606#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 96583#L1928-2 [2024-11-08 00:35:59,454 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:59,454 INFO L85 PathProgramCache]: Analyzing trace with hash -121367293, now seen corresponding path program 1 times [2024-11-08 00:35:59,455 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:59,455 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1776762905] [2024-11-08 00:35:59,455 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:59,455 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:59,464 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:59,508 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:59,508 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:59,508 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1776762905] [2024-11-08 00:35:59,508 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1776762905] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:59,508 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:59,508 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-08 00:35:59,508 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1501520257] [2024-11-08 00:35:59,508 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:59,509 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:35:59,509 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:59,509 INFO L85 PathProgramCache]: Analyzing trace with hash -393570519, now seen corresponding path program 1 times [2024-11-08 00:35:59,509 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:59,509 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1899272260] [2024-11-08 00:35:59,509 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:59,509 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:59,519 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:35:59,560 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:35:59,560 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:35:59,560 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1899272260] [2024-11-08 00:35:59,560 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1899272260] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:35:59,560 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:35:59,561 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-08 00:35:59,561 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1599952046] [2024-11-08 00:35:59,561 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:35:59,561 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:35:59,561 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:35:59,561 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-08 00:35:59,561 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-08 00:35:59,562 INFO L87 Difference]: Start difference. First operand 7167 states and 10374 transitions. cyclomatic complexity: 3209 Second operand has 5 states, 5 states have (on average 32.2) internal successors, (161), 5 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:59,844 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:35:59,844 INFO L93 Difference]: Finished difference Result 7350 states and 10557 transitions. [2024-11-08 00:35:59,844 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7350 states and 10557 transitions. [2024-11-08 00:35:59,861 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 7169 [2024-11-08 00:35:59,874 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7350 states to 7350 states and 10557 transitions. [2024-11-08 00:35:59,875 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7350 [2024-11-08 00:35:59,879 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7350 [2024-11-08 00:35:59,879 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7350 states and 10557 transitions. [2024-11-08 00:35:59,886 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:35:59,886 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7350 states and 10557 transitions. [2024-11-08 00:35:59,889 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7350 states and 10557 transitions. [2024-11-08 00:35:59,940 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7350 to 7350. [2024-11-08 00:35:59,946 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7350 states, 7350 states have (on average 1.4363265306122448) internal successors, (10557), 7349 states have internal predecessors, (10557), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:35:59,958 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7350 states to 7350 states and 10557 transitions. [2024-11-08 00:35:59,959 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7350 states and 10557 transitions. [2024-11-08 00:35:59,959 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-08 00:35:59,959 INFO L425 stractBuchiCegarLoop]: Abstraction has 7350 states and 10557 transitions. [2024-11-08 00:35:59,959 INFO L332 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2024-11-08 00:35:59,960 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7350 states and 10557 transitions. [2024-11-08 00:35:59,970 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 7169 [2024-11-08 00:35:59,970 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:35:59,970 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:35:59,972 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:59,973 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:35:59,973 INFO L745 eck$LassoCheckResult]: Stem: 110739#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 110740#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 111761#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 111762#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 112656#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 111323#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 111324#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 111397#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 111398#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 111872#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 111873#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 111361#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 111160#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 111161#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 111641#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 111642#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 111516#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 111517#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 111135#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 111136#L1279 assume !(0 == ~M_E~0); 112526#L1279-2 assume !(0 == ~T1_E~0); 110760#L1284-1 assume !(0 == ~T2_E~0); 110761#L1289-1 assume !(0 == ~T3_E~0); 111513#L1294-1 assume !(0 == ~T4_E~0); 111514#L1299-1 assume !(0 == ~T5_E~0); 111525#L1304-1 assume !(0 == ~T6_E~0); 112655#L1309-1 assume !(0 == ~T7_E~0); 112658#L1314-1 assume !(0 == ~T8_E~0); 110683#L1319-1 assume !(0 == ~T9_E~0); 110684#L1324-1 assume !(0 == ~T10_E~0); 110861#L1329-1 assume !(0 == ~T11_E~0); 110862#L1334-1 assume !(0 == ~T12_E~0); 112408#L1339-1 assume !(0 == ~T13_E~0); 112511#L1344-1 assume !(0 == ~E_M~0); 112512#L1349-1 assume !(0 == ~E_1~0); 111717#L1354-1 assume !(0 == ~E_2~0); 111718#L1359-1 assume !(0 == ~E_3~0); 112186#L1364-1 assume !(0 == ~E_4~0); 110984#L1369-1 assume !(0 == ~E_5~0); 110985#L1374-1 assume !(0 == ~E_6~0); 111725#L1379-1 assume !(0 == ~E_7~0); 111726#L1384-1 assume !(0 == ~E_8~0); 111809#L1389-1 assume !(0 == ~E_9~0); 112431#L1394-1 assume !(0 == ~E_10~0); 112432#L1399-1 assume !(0 == ~E_11~0); 112571#L1404-1 assume !(0 == ~E_12~0); 111083#L1409-1 assume !(0 == ~E_13~0); 111084#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 112562#L628 assume !(1 == ~m_pc~0); 110983#L628-2 is_master_triggered_~__retres1~0#1 := 0; 110982#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 111587#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 111588#L1591 assume !(0 != activate_threads_~tmp~1#1); 112584#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 111567#L647 assume !(1 == ~t1_pc~0); 111568#L647-2 is_transmit1_triggered_~__retres1~1#1 := 0; 111619#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 111620#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 112137#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 112498#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 112499#L666 assume !(1 == ~t2_pc~0); 110759#L666-2 is_transmit2_triggered_~__retres1~2#1 := 0; 110924#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 110902#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 110903#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 111930#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 111931#L685 assume !(1 == ~t3_pc~0); 112042#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 112113#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 112696#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 111770#L1615 assume !(0 != activate_threads_~tmp___2~0#1); 111771#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 111210#L704 assume 1 == ~t4_pc~0; 111211#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 111785#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 110546#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 110547#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 111617#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 111618#L723 assume !(1 == ~t5_pc~0); 111766#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 112012#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 112179#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 111907#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 111908#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 110966#L742 assume 1 == ~t6_pc~0; 110967#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 111123#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 110893#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 110653#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 110654#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 111045#L761 assume !(1 == ~t7_pc~0); 111046#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 110920#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 110921#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 111774#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 111775#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 110675#L780 assume 1 == ~t8_pc~0; 110676#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 110957#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 110958#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 111733#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 111734#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 111859#L799 assume 1 == ~t9_pc~0; 111976#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 110678#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 110679#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 110952#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 112088#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 111885#L818 assume !(1 == ~t10_pc~0); 110461#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 110462#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 111965#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 111890#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 111891#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 111941#L837 assume 1 == ~t11_pc~0; 111942#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 111759#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 112503#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 111849#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 111850#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 111576#L856 assume !(1 == ~t12_pc~0); 111577#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 112313#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 110479#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 110480#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 112280#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 112529#L875 assume 1 == ~t13_pc~0; 111523#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 111124#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 111125#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 111064#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 111065#L1695-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 111964#L1427 assume !(1 == ~M_E~0); 111949#L1427-2 assume !(1 == ~T1_E~0); 111031#L1432-1 assume !(1 == ~T2_E~0); 111032#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 112192#L1442-1 assume !(1 == ~T4_E~0); 112193#L1447-1 assume !(1 == ~T5_E~0); 112023#L1452-1 assume !(1 == ~T6_E~0); 110598#L1457-1 assume !(1 == ~T7_E~0); 110599#L1462-1 assume !(1 == ~T8_E~0); 112216#L1467-1 assume !(1 == ~T9_E~0); 112241#L1472-1 assume !(1 == ~T10_E~0); 112242#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 111960#L1482-1 assume !(1 == ~T12_E~0); 111961#L1487-1 assume !(1 == ~T13_E~0); 110932#L1492-1 assume !(1 == ~E_M~0); 110933#L1497-1 assume !(1 == ~E_1~0); 111305#L1502-1 assume !(1 == ~E_2~0); 111306#L1507-1 assume !(1 == ~E_3~0); 110808#L1512-1 assume !(1 == ~E_4~0); 110809#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 112336#L1522-1 assume !(1 == ~E_6~0); 111564#L1527-1 assume !(1 == ~E_7~0); 111565#L1532-1 assume !(1 == ~E_8~0); 112625#L1537-1 assume !(1 == ~E_9~0); 111792#L1542-1 assume !(1 == ~E_10~0); 111594#L1547-1 assume !(1 == ~E_11~0); 111595#L1552-1 assume !(1 == ~E_12~0); 110502#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 110503#L1562-1 assume { :end_inline_reset_delta_events } true; 111114#L1928-2 [2024-11-08 00:35:59,973 INFO L747 eck$LassoCheckResult]: Loop: 111114#L1928-2 assume !false; 111763#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 111430#L1254-1 assume !false; 111431#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 110835#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 110836#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 112350#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 112351#L1067 assume !(0 != eval_~tmp~0#1); 114172#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 115402#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 115400#L1279-3 assume !(0 == ~M_E~0); 115401#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 117752#L1284-3 assume !(0 == ~T2_E~0); 117751#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 117750#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 117749#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 117748#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 117747#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 117746#L1314-3 assume !(0 == ~T8_E~0); 117745#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 117744#L1324-3 assume !(0 == ~T10_E~0); 117743#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 117742#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 117741#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 117740#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 117739#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 117738#L1354-3 assume !(0 == ~E_2~0); 117737#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 117736#L1364-3 assume !(0 == ~E_4~0); 117735#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 117734#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 117733#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 117732#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 117731#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 117730#L1394-3 assume !(0 == ~E_10~0); 117729#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 117728#L1404-3 assume !(0 == ~E_12~0); 117727#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 117726#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 117725#L628-45 assume !(1 == ~m_pc~0); 117723#L628-47 is_master_triggered_~__retres1~0#1 := 0; 117722#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 117721#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 117720#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 117719#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 117718#L647-45 assume !(1 == ~t1_pc~0); 117717#L647-47 is_transmit1_triggered_~__retres1~1#1 := 0; 117716#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 117715#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 117714#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 117713#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 117711#L666-45 assume !(1 == ~t2_pc~0); 117710#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 117709#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 117708#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 117707#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 117706#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 117705#L685-45 assume !(1 == ~t3_pc~0); 117703#L685-47 is_transmit3_triggered_~__retres1~3#1 := 0; 117701#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 117699#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 117698#L1615-45 assume !(0 != activate_threads_~tmp___2~0#1); 117696#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 117695#L704-45 assume !(1 == ~t4_pc~0); 117693#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 117692#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 117691#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 117690#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 117689#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 117688#L723-45 assume !(1 == ~t5_pc~0); 117687#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 117685#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 117684#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 117683#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 117682#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 117681#L742-45 assume !(1 == ~t6_pc~0); 117680#L742-47 is_transmit6_triggered_~__retres1~6#1 := 0; 117678#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 117448#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 111981#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 111982#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 112075#L761-45 assume 1 == ~t7_pc~0; 112077#L762-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 111433#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 111434#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 110812#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 110813#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 112423#L780-45 assume !(1 == ~t8_pc~0); 111191#L780-47 is_transmit8_triggered_~__retres1~8#1 := 0; 110823#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 110824#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 112617#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 110792#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 110793#L799-45 assume !(1 == ~t9_pc~0); 111011#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 111012#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 112160#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 112024#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 112025#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 110734#L818-45 assume !(1 == ~t10_pc~0); 110736#L818-47 is_transmit10_triggered_~__retres1~10#1 := 0; 110854#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 111998#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 111356#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 111357#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 117376#L837-45 assume 1 == ~t11_pc~0; 117375#L838-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 117373#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 117372#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 112653#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 110876#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 110877#L856-45 assume 1 == ~t12_pc~0; 112523#L857-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 110879#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 112199#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 112200#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 111729#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 111730#L875-45 assume 1 == ~t13_pc~0; 111692#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 111693#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 111760#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 112151#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 112487#L1695-47 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 112406#L1427-3 assume !(1 == ~M_E~0); 111508#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 111509#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 112085#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 111715#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 111716#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 110519#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 110520#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 117247#L1462-3 assume !(1 == ~T8_E~0); 116003#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 115838#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 115370#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 115369#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 115368#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 115367#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 115366#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 112106#L1502-3 assume !(1 == ~E_2~0); 112107#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 112265#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 111128#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 111129#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 112592#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 110783#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 110784#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 111948#L1542-3 assume !(1 == ~E_10~0); 112543#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 115197#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 115196#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 115195#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 114799#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 114791#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 114789#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 114786#L1947 assume !(0 == start_simulation_~tmp~3#1); 114785#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 114469#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 114460#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 110469#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 110470#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 114250#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 112429#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 112430#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 111114#L1928-2 [2024-11-08 00:35:59,974 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:35:59,974 INFO L85 PathProgramCache]: Analyzing trace with hash -2061949307, now seen corresponding path program 1 times [2024-11-08 00:35:59,974 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:35:59,974 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [535791626] [2024-11-08 00:35:59,974 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:35:59,974 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:35:59,984 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:36:00,018 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:36:00,019 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:36:00,019 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [535791626] [2024-11-08 00:36:00,019 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [535791626] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:36:00,019 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:36:00,019 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-08 00:36:00,019 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2005209458] [2024-11-08 00:36:00,019 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:36:00,019 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:36:00,019 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:36:00,019 INFO L85 PathProgramCache]: Analyzing trace with hash -1463035220, now seen corresponding path program 1 times [2024-11-08 00:36:00,019 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:36:00,019 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [880883167] [2024-11-08 00:36:00,020 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:36:00,020 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:36:00,030 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:36:00,069 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:36:00,070 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:36:00,070 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [880883167] [2024-11-08 00:36:00,070 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [880883167] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:36:00,070 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:36:00,070 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-08 00:36:00,070 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1684539765] [2024-11-08 00:36:00,070 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:36:00,070 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:36:00,070 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:36:00,070 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:36:00,071 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:36:00,071 INFO L87 Difference]: Start difference. First operand 7350 states and 10557 transitions. cyclomatic complexity: 3209 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:36:00,168 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:36:00,168 INFO L93 Difference]: Finished difference Result 14052 states and 20097 transitions. [2024-11-08 00:36:00,169 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 14052 states and 20097 transitions. [2024-11-08 00:36:00,207 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 13860 [2024-11-08 00:36:00,239 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 14052 states to 14052 states and 20097 transitions. [2024-11-08 00:36:00,240 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14052 [2024-11-08 00:36:00,247 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14052 [2024-11-08 00:36:00,247 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14052 states and 20097 transitions. [2024-11-08 00:36:00,258 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:36:00,258 INFO L218 hiAutomatonCegarLoop]: Abstraction has 14052 states and 20097 transitions. [2024-11-08 00:36:00,267 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14052 states and 20097 transitions. [2024-11-08 00:36:00,422 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14052 to 14044. [2024-11-08 00:36:00,434 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14044 states, 14044 states have (on average 1.4304329250925663) internal successors, (20089), 14043 states have internal predecessors, (20089), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:36:00,456 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14044 states to 14044 states and 20089 transitions. [2024-11-08 00:36:00,457 INFO L240 hiAutomatonCegarLoop]: Abstraction has 14044 states and 20089 transitions. [2024-11-08 00:36:00,457 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:36:00,457 INFO L425 stractBuchiCegarLoop]: Abstraction has 14044 states and 20089 transitions. [2024-11-08 00:36:00,457 INFO L332 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2024-11-08 00:36:00,457 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14044 states and 20089 transitions. [2024-11-08 00:36:00,481 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 13852 [2024-11-08 00:36:00,482 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:36:00,482 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:36:00,483 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:36:00,483 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:36:00,484 INFO L745 eck$LassoCheckResult]: Stem: 132149#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 132150#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 133153#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 133154#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 133999#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 132729#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 132730#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 132803#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 132804#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 133260#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 133261#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 132769#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 132568#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 132569#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 133040#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 133041#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 132915#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 132916#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 132543#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 132544#L1279 assume !(0 == ~M_E~0); 133880#L1279-2 assume !(0 == ~T1_E~0); 132170#L1284-1 assume !(0 == ~T2_E~0); 132171#L1289-1 assume !(0 == ~T3_E~0); 132910#L1294-1 assume !(0 == ~T4_E~0); 132911#L1299-1 assume !(0 == ~T5_E~0); 132922#L1304-1 assume !(0 == ~T6_E~0); 133998#L1309-1 assume !(0 == ~T7_E~0); 134000#L1314-1 assume !(0 == ~T8_E~0); 132093#L1319-1 assume !(0 == ~T9_E~0); 132094#L1324-1 assume !(0 == ~T10_E~0); 132269#L1329-1 assume !(0 == ~T11_E~0); 132270#L1334-1 assume !(0 == ~T12_E~0); 133773#L1339-1 assume !(0 == ~T13_E~0); 133867#L1344-1 assume !(0 == ~E_M~0); 133868#L1349-1 assume !(0 == ~E_1~0); 133111#L1354-1 assume !(0 == ~E_2~0); 133112#L1359-1 assume !(0 == ~E_3~0); 133559#L1364-1 assume !(0 == ~E_4~0); 132392#L1369-1 assume !(0 == ~E_5~0); 132393#L1374-1 assume !(0 == ~E_6~0); 133118#L1379-1 assume !(0 == ~E_7~0); 133119#L1384-1 assume !(0 == ~E_8~0); 133199#L1389-1 assume !(0 == ~E_9~0); 133794#L1394-1 assume !(0 == ~E_10~0); 133795#L1399-1 assume !(0 == ~E_11~0); 133922#L1404-1 assume !(0 == ~E_12~0); 132491#L1409-1 assume !(0 == ~E_13~0); 132492#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 133911#L628 assume !(1 == ~m_pc~0); 132391#L628-2 is_master_triggered_~__retres1~0#1 := 0; 132390#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 132987#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 132988#L1591 assume !(0 != activate_threads_~tmp~1#1); 133933#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 132967#L647 assume !(1 == ~t1_pc~0); 132968#L647-2 is_transmit1_triggered_~__retres1~1#1 := 0; 133019#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 133020#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 133513#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 133852#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 133853#L666 assume !(1 == ~t2_pc~0); 132169#L666-2 is_transmit2_triggered_~__retres1~2#1 := 0; 132332#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 132310#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 132311#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 133319#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 133320#L685 assume !(1 == ~t3_pc~0); 133423#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 133491#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 133942#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 133162#L1615 assume !(0 != activate_threads_~tmp___2~0#1); 133163#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 132616#L704 assume !(1 == ~t4_pc~0); 132617#L704-2 is_transmit4_triggered_~__retres1~4#1 := 0; 133174#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 131957#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 131958#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 133017#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 133018#L723 assume !(1 == ~t5_pc~0); 133159#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 133392#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 133552#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 133297#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 133298#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 132374#L742 assume 1 == ~t6_pc~0; 132375#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 132532#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 132301#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 132061#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 132062#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 132453#L761 assume !(1 == ~t7_pc~0); 132454#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 132330#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 132331#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 133165#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 133166#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 132085#L780 assume 1 == ~t8_pc~0; 132086#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 132365#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 132366#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 133125#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 133126#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 133246#L799 assume 1 == ~t9_pc~0; 133360#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 132088#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 132089#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 132360#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 133468#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 133274#L818 assume !(1 == ~t10_pc~0); 131872#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 131873#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 133351#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 133277#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 133278#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 133327#L837 assume 1 == ~t11_pc~0; 133328#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 133152#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 133858#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 133239#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 133240#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 132976#L856 assume !(1 == ~t12_pc~0); 132977#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 133678#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 131890#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 131891#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 133649#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 133883#L875 assume 1 == ~t13_pc~0; 132920#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 132533#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 132534#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 132472#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 132473#L1695-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 133350#L1427 assume !(1 == ~M_E~0); 133334#L1427-2 assume !(1 == ~T1_E~0); 132440#L1432-1 assume !(1 == ~T2_E~0); 132441#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 133567#L1442-1 assume !(1 == ~T4_E~0); 133568#L1447-1 assume !(1 == ~T5_E~0); 133405#L1452-1 assume !(1 == ~T6_E~0); 132008#L1457-1 assume !(1 == ~T7_E~0); 132009#L1462-1 assume !(1 == ~T8_E~0); 133588#L1467-1 assume !(1 == ~T9_E~0); 133613#L1472-1 assume !(1 == ~T10_E~0); 133614#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 133346#L1482-1 assume !(1 == ~T12_E~0); 133347#L1487-1 assume !(1 == ~T13_E~0); 132340#L1492-1 assume !(1 == ~E_M~0); 132341#L1497-1 assume !(1 == ~E_1~0); 132711#L1502-1 assume !(1 == ~E_2~0); 132712#L1507-1 assume !(1 == ~E_3~0); 132218#L1512-1 assume !(1 == ~E_4~0); 132219#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 133705#L1522-1 assume !(1 == ~E_6~0); 132963#L1527-1 assume !(1 == ~E_7~0); 132964#L1532-1 assume !(1 == ~E_8~0); 133975#L1537-1 assume !(1 == ~E_9~0); 133181#L1542-1 assume !(1 == ~E_10~0); 132995#L1547-1 assume !(1 == ~E_11~0); 132996#L1552-1 assume !(1 == ~E_12~0); 131913#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 131914#L1562-1 assume { :end_inline_reset_delta_events } true; 132523#L1928-2 [2024-11-08 00:36:00,484 INFO L747 eck$LassoCheckResult]: Loop: 132523#L1928-2 assume !false; 141399#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 141394#L1254-1 assume !false; 133354#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 132243#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 132244#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 132442#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 133684#L1067 assume !(0 != eval_~tmp~0#1); 133685#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 144451#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 144450#L1279-3 assume !(0 == ~M_E~0); 144448#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 144446#L1284-3 assume !(0 == ~T2_E~0); 144444#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 144442#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 144440#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 144438#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 144436#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 144434#L1314-3 assume !(0 == ~T8_E~0); 144432#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 144429#L1324-3 assume !(0 == ~T10_E~0); 144427#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 144425#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 144423#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 144421#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 144419#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 144415#L1354-3 assume !(0 == ~E_2~0); 144413#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 144411#L1364-3 assume !(0 == ~E_4~0); 144409#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 144406#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 144404#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 144402#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 144400#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 144398#L1394-3 assume !(0 == ~E_10~0); 144396#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 144394#L1404-3 assume !(0 == ~E_12~0); 144392#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 144390#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 144387#L628-45 assume !(1 == ~m_pc~0); 144384#L628-47 is_master_triggered_~__retres1~0#1 := 0; 144382#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 144380#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 144378#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 144376#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 144373#L647-45 assume !(1 == ~t1_pc~0); 144371#L647-47 is_transmit1_triggered_~__retres1~1#1 := 0; 144369#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 144367#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 144365#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 144363#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 144357#L666-45 assume !(1 == ~t2_pc~0); 144355#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 144353#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 144351#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 144348#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 144346#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 144344#L685-45 assume 1 == ~t3_pc~0; 144342#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 144343#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 144456#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 144332#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 144330#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 144328#L704-45 assume !(1 == ~t4_pc~0); 144326#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 144324#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 144322#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 144319#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 144317#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 144316#L723-45 assume 1 == ~t5_pc~0; 144314#L724-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 144313#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 144312#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 144311#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 144310#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 144309#L742-45 assume 1 == ~t6_pc~0; 144307#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 144306#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 144305#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 144304#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 144303#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 144301#L761-45 assume 1 == ~t7_pc~0; 144298#L762-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 144297#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 144296#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 144295#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 144294#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 144293#L780-45 assume 1 == ~t8_pc~0; 144291#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 144290#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 144289#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 144288#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 144286#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 144283#L799-45 assume !(1 == ~t9_pc~0); 144280#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 144278#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 144276#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 144274#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 144272#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 144270#L818-45 assume 1 == ~t10_pc~0; 144267#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 144265#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 144263#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 144261#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 144258#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 144256#L837-45 assume 1 == ~t11_pc~0; 144254#L838-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 144251#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 144249#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 144247#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 144245#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 144242#L856-45 assume !(1 == ~t12_pc~0); 144240#L856-47 is_transmit12_triggered_~__retres1~12#1 := 0; 144237#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 144234#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 144232#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 144230#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 144228#L875-45 assume 1 == ~t13_pc~0; 144226#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 144223#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 144221#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 144219#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 144217#L1695-47 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 144137#L1427-3 assume !(1 == ~M_E~0); 144134#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 144132#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 144130#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 144128#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 144126#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 144124#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 144121#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 144119#L1462-3 assume !(1 == ~T8_E~0); 144117#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 144115#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 144113#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 144111#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 144108#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 144106#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 144104#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 144102#L1502-3 assume !(1 == ~E_2~0); 144100#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 144098#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 144095#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 144093#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 144091#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 144089#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 144087#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 144085#L1542-3 assume !(1 == ~E_10~0); 144082#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 144080#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 144078#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 144076#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 144042#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 144035#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 142491#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 134099#L1947 assume !(0 == start_simulation_~tmp~3#1); 133438#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 133439#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 132457#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 131880#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 131881#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 133599#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 133600#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 133793#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 132523#L1928-2 [2024-11-08 00:36:00,485 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:36:00,485 INFO L85 PathProgramCache]: Analyzing trace with hash 846336710, now seen corresponding path program 1 times [2024-11-08 00:36:00,485 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:36:00,485 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1393414649] [2024-11-08 00:36:00,485 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:36:00,485 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:36:00,495 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:36:00,531 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:36:00,531 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:36:00,531 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1393414649] [2024-11-08 00:36:00,531 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1393414649] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:36:00,531 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:36:00,532 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-08 00:36:00,532 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [666694426] [2024-11-08 00:36:00,532 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:36:00,532 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:36:00,532 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:36:00,532 INFO L85 PathProgramCache]: Analyzing trace with hash 1903947302, now seen corresponding path program 1 times [2024-11-08 00:36:00,532 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:36:00,532 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1975614287] [2024-11-08 00:36:00,532 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:36:00,532 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:36:00,543 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:36:00,569 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:36:00,571 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:36:00,571 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1975614287] [2024-11-08 00:36:00,571 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1975614287] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:36:00,571 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:36:00,572 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:36:00,572 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1488463438] [2024-11-08 00:36:00,572 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:36:00,572 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:36:00,572 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:36:00,572 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:36:00,572 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:36:00,573 INFO L87 Difference]: Start difference. First operand 14044 states and 20089 transitions. cyclomatic complexity: 6049 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:36:00,699 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:36:00,699 INFO L93 Difference]: Finished difference Result 26979 states and 38442 transitions. [2024-11-08 00:36:00,699 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 26979 states and 38442 transitions. [2024-11-08 00:36:00,801 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 26756 [2024-11-08 00:36:00,870 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 26979 states to 26979 states and 38442 transitions. [2024-11-08 00:36:00,870 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 26979 [2024-11-08 00:36:00,885 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 26979 [2024-11-08 00:36:00,885 INFO L73 IsDeterministic]: Start isDeterministic. Operand 26979 states and 38442 transitions. [2024-11-08 00:36:00,905 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:36:00,905 INFO L218 hiAutomatonCegarLoop]: Abstraction has 26979 states and 38442 transitions. [2024-11-08 00:36:00,921 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26979 states and 38442 transitions. [2024-11-08 00:36:01,177 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26979 to 26963. [2024-11-08 00:36:01,206 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 26963 states, 26963 states have (on average 1.4251381522827578) internal successors, (38426), 26962 states have internal predecessors, (38426), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:36:01,252 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26963 states to 26963 states and 38426 transitions. [2024-11-08 00:36:01,252 INFO L240 hiAutomatonCegarLoop]: Abstraction has 26963 states and 38426 transitions. [2024-11-08 00:36:01,253 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:36:01,253 INFO L425 stractBuchiCegarLoop]: Abstraction has 26963 states and 38426 transitions. [2024-11-08 00:36:01,253 INFO L332 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2024-11-08 00:36:01,253 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 26963 states and 38426 transitions. [2024-11-08 00:36:01,316 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 26740 [2024-11-08 00:36:01,317 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:36:01,317 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:36:01,319 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:36:01,319 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:36:01,319 INFO L745 eck$LassoCheckResult]: Stem: 173179#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 173180#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 174183#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 174184#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 175032#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 173758#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 173759#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 173829#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 173830#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 174293#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 174294#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 173793#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 173599#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 173600#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 174072#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 174073#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 173947#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 173948#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 173574#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 173575#L1279 assume !(0 == ~M_E~0); 174908#L1279-2 assume !(0 == ~T1_E~0); 173200#L1284-1 assume !(0 == ~T2_E~0); 173201#L1289-1 assume !(0 == ~T3_E~0); 173944#L1294-1 assume !(0 == ~T4_E~0); 173945#L1299-1 assume !(0 == ~T5_E~0); 173958#L1304-1 assume !(0 == ~T6_E~0); 175030#L1309-1 assume !(0 == ~T7_E~0); 175034#L1314-1 assume !(0 == ~T8_E~0); 173124#L1319-1 assume !(0 == ~T9_E~0); 173125#L1324-1 assume !(0 == ~T10_E~0); 173299#L1329-1 assume !(0 == ~T11_E~0); 173300#L1334-1 assume !(0 == ~T12_E~0); 174793#L1339-1 assume !(0 == ~T13_E~0); 174898#L1344-1 assume !(0 == ~E_M~0); 174899#L1349-1 assume !(0 == ~E_1~0); 174142#L1354-1 assume !(0 == ~E_2~0); 174143#L1359-1 assume !(0 == ~E_3~0); 174581#L1364-1 assume !(0 == ~E_4~0); 173423#L1369-1 assume !(0 == ~E_5~0); 173424#L1374-1 assume !(0 == ~E_6~0); 174149#L1379-1 assume !(0 == ~E_7~0); 174150#L1384-1 assume !(0 == ~E_8~0); 174229#L1389-1 assume !(0 == ~E_9~0); 174818#L1394-1 assume !(0 == ~E_10~0); 174819#L1399-1 assume !(0 == ~E_11~0); 174952#L1404-1 assume !(0 == ~E_12~0); 173521#L1409-1 assume !(0 == ~E_13~0); 173522#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 174941#L628 assume !(1 == ~m_pc~0); 173422#L628-2 is_master_triggered_~__retres1~0#1 := 0; 173421#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 174018#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 174019#L1591 assume !(0 != activate_threads_~tmp~1#1); 174963#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 173998#L647 assume !(1 == ~t1_pc~0); 173999#L647-2 is_transmit1_triggered_~__retres1~1#1 := 0; 174050#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 174051#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 174540#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 174884#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 174885#L666 assume !(1 == ~t2_pc~0); 173199#L666-2 is_transmit2_triggered_~__retres1~2#1 := 0; 173361#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 173339#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 173340#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 174346#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 174347#L685 assume !(1 == ~t3_pc~0); 174451#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 174519#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 174973#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 174193#L1615 assume !(0 != activate_threads_~tmp___2~0#1); 174194#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 173648#L704 assume !(1 == ~t4_pc~0); 173649#L704-2 is_transmit4_triggered_~__retres1~4#1 := 0; 174205#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 172987#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 172988#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 174048#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 174049#L723 assume !(1 == ~t5_pc~0); 174189#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 174420#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 174574#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 174324#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 174325#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 173406#L742 assume !(1 == ~t6_pc~0); 173407#L742-2 is_transmit6_triggered_~__retres1~6#1 := 0; 173563#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 173330#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 173093#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 173094#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 173483#L761 assume !(1 == ~t7_pc~0); 173484#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 173357#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 173358#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 174196#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 174197#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 173116#L780 assume 1 == ~t8_pc~0; 173117#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 173397#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 173398#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 174156#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 174157#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 174279#L799 assume 1 == ~t9_pc~0; 174387#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 173119#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 173120#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 173392#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 174496#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 174306#L818 assume !(1 == ~t10_pc~0); 172902#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 172903#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 174380#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 174309#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 174310#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 174356#L837 assume 1 == ~t11_pc~0; 174357#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 174181#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 174890#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 174272#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 174273#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 174007#L856 assume !(1 == ~t12_pc~0); 174008#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 174697#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 172920#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 172921#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 174671#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 174911#L875 assume 1 == ~t13_pc~0; 173954#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 173564#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 173565#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 173502#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 173503#L1695-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 174379#L1427 assume !(1 == ~M_E~0); 174364#L1427-2 assume !(1 == ~T1_E~0); 173470#L1432-1 assume !(1 == ~T2_E~0); 173471#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 174586#L1442-1 assume !(1 == ~T4_E~0); 174587#L1447-1 assume !(1 == ~T5_E~0); 174432#L1452-1 assume !(1 == ~T6_E~0); 173038#L1457-1 assume !(1 == ~T7_E~0); 173039#L1462-1 assume !(1 == ~T8_E~0); 174612#L1467-1 assume !(1 == ~T9_E~0); 174634#L1472-1 assume !(1 == ~T10_E~0); 174635#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 174375#L1482-1 assume !(1 == ~T12_E~0); 174376#L1487-1 assume !(1 == ~T13_E~0); 173370#L1492-1 assume !(1 == ~E_M~0); 173371#L1497-1 assume !(1 == ~E_1~0); 173741#L1502-1 assume !(1 == ~E_2~0); 173742#L1507-1 assume !(1 == ~E_3~0); 173249#L1512-1 assume !(1 == ~E_4~0); 173250#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 174721#L1522-1 assume !(1 == ~E_6~0); 173995#L1527-1 assume !(1 == ~E_7~0); 173996#L1532-1 assume !(1 == ~E_8~0); 175005#L1537-1 assume !(1 == ~E_9~0); 174212#L1542-1 assume !(1 == ~E_10~0); 174025#L1547-1 assume !(1 == ~E_11~0); 174026#L1552-1 assume !(1 == ~E_12~0); 172943#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 172944#L1562-1 assume { :end_inline_reset_delta_events } true; 173554#L1928-2 [2024-11-08 00:36:01,320 INFO L747 eck$LassoCheckResult]: Loop: 173554#L1928-2 assume !false; 182500#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 182494#L1254-1 assume !false; 182492#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 182440#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 182426#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 182420#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 182412#L1067 assume !(0 != eval_~tmp~0#1); 182413#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 187641#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 187640#L1279-3 assume !(0 == ~M_E~0); 187639#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 187638#L1284-3 assume !(0 == ~T2_E~0); 187637#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 187636#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 187635#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 187634#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 187633#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 187632#L1314-3 assume !(0 == ~T8_E~0); 187631#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 187630#L1324-3 assume !(0 == ~T10_E~0); 187629#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 187628#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 187627#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 187626#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 187625#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 187624#L1354-3 assume !(0 == ~E_2~0); 187623#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 187622#L1364-3 assume !(0 == ~E_4~0); 187621#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 187620#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 187619#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 187618#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 187617#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 187616#L1394-3 assume !(0 == ~E_10~0); 187615#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 187614#L1404-3 assume !(0 == ~E_12~0); 187613#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 187612#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 187611#L628-45 assume 1 == ~m_pc~0; 187610#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 187608#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 187607#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 187606#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 187605#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 187604#L647-45 assume !(1 == ~t1_pc~0); 187603#L647-47 is_transmit1_triggered_~__retres1~1#1 := 0; 187602#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 187601#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 187600#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 187599#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 187597#L666-45 assume !(1 == ~t2_pc~0); 187596#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 187595#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 187594#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 187593#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 187592#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 187591#L685-45 assume !(1 == ~t3_pc~0); 187590#L685-47 is_transmit3_triggered_~__retres1~3#1 := 0; 187588#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 187586#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 187584#L1615-45 assume !(0 != activate_threads_~tmp___2~0#1); 187582#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 187581#L704-45 assume !(1 == ~t4_pc~0); 187580#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 187579#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 187578#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 187577#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 187576#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 187575#L723-45 assume !(1 == ~t5_pc~0); 187574#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 187572#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 187571#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 187570#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 187569#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 187568#L742-45 assume !(1 == ~t6_pc~0); 187567#L742-47 is_transmit6_triggered_~__retres1~6#1 := 0; 187566#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 187565#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 187564#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 187563#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 187562#L761-45 assume 1 == ~t7_pc~0; 187560#L762-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 187559#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 187558#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 187556#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 187555#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 187554#L780-45 assume 1 == ~t8_pc~0; 187552#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 187551#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 187549#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 187546#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 187544#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 187542#L799-45 assume !(1 == ~t9_pc~0); 187539#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 187537#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 187535#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 187532#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 187530#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 187528#L818-45 assume !(1 == ~t10_pc~0); 187526#L818-47 is_transmit10_triggered_~__retres1~10#1 := 0; 187523#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 187520#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 187518#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 187516#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 187514#L837-45 assume !(1 == ~t11_pc~0); 187511#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 187509#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 187507#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 187504#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 187501#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 187498#L856-45 assume 1 == ~t12_pc~0; 187494#L857-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 187492#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 187490#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 187488#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 187486#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 187484#L875-45 assume 1 == ~t13_pc~0; 187482#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 187479#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 187477#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 187474#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 187472#L1695-47 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 187470#L1427-3 assume !(1 == ~M_E~0); 182881#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 187467#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 187465#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 187462#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 187460#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 187458#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 187456#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 187454#L1462-3 assume !(1 == ~T8_E~0); 187452#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 187449#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 187447#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 187445#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 187442#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 187438#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 187435#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 187431#L1502-3 assume !(1 == ~E_2~0); 187427#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 187413#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 187407#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 187401#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 187394#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 175408#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 175407#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 175406#L1542-3 assume !(1 == ~E_10~0); 175405#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 175404#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 175403#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 175402#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 175394#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 175386#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 175387#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 182782#L1947 assume !(0 == start_simulation_~tmp~3#1); 182779#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 182560#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 182552#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 182549#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 182547#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 182545#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 182528#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 182518#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 173554#L1928-2 [2024-11-08 00:36:01,321 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:36:01,321 INFO L85 PathProgramCache]: Analyzing trace with hash -995977081, now seen corresponding path program 1 times [2024-11-08 00:36:01,321 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:36:01,321 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [25480011] [2024-11-08 00:36:01,321 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:36:01,322 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:36:01,332 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:36:01,362 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:36:01,362 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:36:01,363 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [25480011] [2024-11-08 00:36:01,363 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [25480011] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:36:01,363 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:36:01,363 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-08 00:36:01,363 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1864397813] [2024-11-08 00:36:01,364 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:36:01,364 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:36:01,364 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:36:01,364 INFO L85 PathProgramCache]: Analyzing trace with hash 1127405867, now seen corresponding path program 1 times [2024-11-08 00:36:01,364 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:36:01,364 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [603227535] [2024-11-08 00:36:01,365 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:36:01,365 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:36:01,375 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:36:01,411 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:36:01,412 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:36:01,412 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [603227535] [2024-11-08 00:36:01,412 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [603227535] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:36:01,412 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:36:01,412 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-08 00:36:01,412 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1355251256] [2024-11-08 00:36:01,412 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:36:01,412 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:36:01,412 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:36:01,412 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:36:01,413 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:36:01,413 INFO L87 Difference]: Start difference. First operand 26963 states and 38426 transitions. cyclomatic complexity: 11471 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:36:01,787 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:36:01,787 INFO L93 Difference]: Finished difference Result 51902 states and 73699 transitions. [2024-11-08 00:36:01,787 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 51902 states and 73699 transitions. [2024-11-08 00:36:02,017 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 51600 [2024-11-08 00:36:02,201 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 51902 states to 51902 states and 73699 transitions. [2024-11-08 00:36:02,201 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 51902 [2024-11-08 00:36:02,239 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 51902 [2024-11-08 00:36:02,239 INFO L73 IsDeterministic]: Start isDeterministic. Operand 51902 states and 73699 transitions. [2024-11-08 00:36:02,292 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:36:02,292 INFO L218 hiAutomatonCegarLoop]: Abstraction has 51902 states and 73699 transitions. [2024-11-08 00:36:02,328 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 51902 states and 73699 transitions. [2024-11-08 00:36:02,863 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 51902 to 51870. [2024-11-08 00:36:02,914 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 51870 states, 51870 states have (on average 1.4202236360131097) internal successors, (73667), 51869 states have internal predecessors, (73667), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:36:03,112 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51870 states to 51870 states and 73667 transitions. [2024-11-08 00:36:03,112 INFO L240 hiAutomatonCegarLoop]: Abstraction has 51870 states and 73667 transitions. [2024-11-08 00:36:03,113 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:36:03,113 INFO L425 stractBuchiCegarLoop]: Abstraction has 51870 states and 73667 transitions. [2024-11-08 00:36:03,113 INFO L332 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2024-11-08 00:36:03,113 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 51870 states and 73667 transitions. [2024-11-08 00:36:03,209 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 51568 [2024-11-08 00:36:03,210 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:36:03,210 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:36:03,211 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:36:03,211 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:36:03,212 INFO L745 eck$LassoCheckResult]: Stem: 252050#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 252051#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 253046#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 253047#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 253859#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 252625#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 252626#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 252698#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 252699#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 253155#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 253156#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 252662#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 252464#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 252465#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 252933#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 252934#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 252810#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 252811#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 252439#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 252440#L1279 assume !(0 == ~M_E~0); 253742#L1279-2 assume !(0 == ~T1_E~0); 252071#L1284-1 assume !(0 == ~T2_E~0); 252072#L1289-1 assume !(0 == ~T3_E~0); 252807#L1294-1 assume !(0 == ~T4_E~0); 252808#L1299-1 assume !(0 == ~T5_E~0); 252819#L1304-1 assume !(0 == ~T6_E~0); 253858#L1309-1 assume !(0 == ~T7_E~0); 253861#L1314-1 assume !(0 == ~T8_E~0); 251995#L1319-1 assume !(0 == ~T9_E~0); 251996#L1324-1 assume !(0 == ~T10_E~0); 252171#L1329-1 assume !(0 == ~T11_E~0); 252172#L1334-1 assume !(0 == ~T12_E~0); 253638#L1339-1 assume !(0 == ~T13_E~0); 253732#L1344-1 assume !(0 == ~E_M~0); 253733#L1349-1 assume !(0 == ~E_1~0); 253001#L1354-1 assume !(0 == ~E_2~0); 253002#L1359-1 assume !(0 == ~E_3~0); 253445#L1364-1 assume !(0 == ~E_4~0); 252292#L1369-1 assume !(0 == ~E_5~0); 252293#L1374-1 assume !(0 == ~E_6~0); 253008#L1379-1 assume !(0 == ~E_7~0); 253009#L1384-1 assume !(0 == ~E_8~0); 253092#L1389-1 assume !(0 == ~E_9~0); 253662#L1394-1 assume !(0 == ~E_10~0); 253663#L1399-1 assume !(0 == ~E_11~0); 253781#L1404-1 assume !(0 == ~E_12~0); 252387#L1409-1 assume !(0 == ~E_13~0); 252388#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 253773#L628 assume !(1 == ~m_pc~0); 252291#L628-2 is_master_triggered_~__retres1~0#1 := 0; 252290#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 252880#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 252881#L1591 assume !(0 != activate_threads_~tmp~1#1); 253790#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 252860#L647 assume !(1 == ~t1_pc~0); 252861#L647-2 is_transmit1_triggered_~__retres1~1#1 := 0; 252912#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 252913#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 253399#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 253719#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 253720#L666 assume !(1 == ~t2_pc~0); 252070#L666-2 is_transmit2_triggered_~__retres1~2#1 := 0; 252233#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 252211#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 252212#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 253207#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 253208#L685 assume !(1 == ~t3_pc~0); 253308#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 253373#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 253797#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 253055#L1615 assume !(0 != activate_threads_~tmp___2~0#1); 253056#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 252514#L704 assume !(1 == ~t4_pc~0); 252515#L704-2 is_transmit4_triggered_~__retres1~4#1 := 0; 253068#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 251861#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 251862#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 252910#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 252911#L723 assume !(1 == ~t5_pc~0); 253051#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 253277#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 253438#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 253186#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 253187#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 252275#L742 assume !(1 == ~t6_pc~0); 252276#L742-2 is_transmit6_triggered_~__retres1~6#1 := 0; 252428#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 252202#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 251965#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 251966#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 252351#L761 assume !(1 == ~t7_pc~0); 252352#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 252229#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 252230#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 253058#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 253059#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 251988#L780 assume !(1 == ~t8_pc~0); 251989#L780-2 is_transmit8_triggered_~__retres1~8#1 := 0; 252266#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 252267#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 253015#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 253016#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 253141#L799 assume 1 == ~t9_pc~0; 253246#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 251990#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 251991#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 252261#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 253351#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 253168#L818 assume !(1 == ~t10_pc~0); 251776#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 251777#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 253239#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 253171#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 253172#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 253215#L837 assume 1 == ~t11_pc~0; 253216#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 253044#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 253724#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 253134#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 253135#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 252869#L856 assume !(1 == ~t12_pc~0); 252870#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 253555#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 251794#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 251795#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 253530#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 253745#L875 assume 1 == ~t13_pc~0; 252817#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 252429#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 252430#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 252369#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 252370#L1695-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 253238#L1427 assume !(1 == ~M_E~0); 253222#L1427-2 assume !(1 == ~T1_E~0); 252339#L1432-1 assume !(1 == ~T2_E~0); 252340#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 253451#L1442-1 assume !(1 == ~T4_E~0); 253452#L1447-1 assume !(1 == ~T5_E~0); 253288#L1452-1 assume !(1 == ~T6_E~0); 251912#L1457-1 assume !(1 == ~T7_E~0); 251913#L1462-1 assume !(1 == ~T8_E~0); 253472#L1467-1 assume !(1 == ~T9_E~0); 253496#L1472-1 assume !(1 == ~T10_E~0); 253497#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 253234#L1482-1 assume !(1 == ~T12_E~0); 253235#L1487-1 assume !(1 == ~T13_E~0); 252241#L1492-1 assume !(1 == ~E_M~0); 252242#L1497-1 assume !(1 == ~E_1~0); 252608#L1502-1 assume !(1 == ~E_2~0); 252609#L1507-1 assume !(1 == ~E_3~0); 252121#L1512-1 assume !(1 == ~E_4~0); 252122#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 253577#L1522-1 assume !(1 == ~E_6~0); 252856#L1527-1 assume !(1 == ~E_7~0); 252857#L1532-1 assume !(1 == ~E_8~0); 253829#L1537-1 assume !(1 == ~E_9~0); 253075#L1542-1 assume !(1 == ~E_10~0); 252887#L1547-1 assume !(1 == ~E_11~0); 252888#L1552-1 assume !(1 == ~E_12~0); 251817#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 251818#L1562-1 assume { :end_inline_reset_delta_events } true; 252419#L1928-2 [2024-11-08 00:36:03,212 INFO L747 eck$LassoCheckResult]: Loop: 252419#L1928-2 assume !false; 280241#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 280236#L1254-1 assume !false; 280234#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 280205#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 280196#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 280194#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 280192#L1067 assume !(0 != eval_~tmp~0#1); 280190#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 280188#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 280186#L1279-3 assume !(0 == ~M_E~0); 280184#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 280182#L1284-3 assume !(0 == ~T2_E~0); 280179#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 280177#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 280175#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 280173#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 280171#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 280169#L1314-3 assume !(0 == ~T8_E~0); 280167#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 280164#L1324-3 assume !(0 == ~T10_E~0); 280162#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 280160#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 280159#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 280156#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 280154#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 280152#L1354-3 assume !(0 == ~E_2~0); 280150#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 280148#L1364-3 assume !(0 == ~E_4~0); 280146#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 280144#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 280142#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 280140#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 280137#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 280135#L1394-3 assume !(0 == ~E_10~0); 280133#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 280113#L1404-3 assume !(0 == ~E_12~0); 280069#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 280053#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 280046#L628-45 assume !(1 == ~m_pc~0); 280038#L628-47 is_master_triggered_~__retres1~0#1 := 0; 280036#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 280034#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 280032#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 280029#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 280027#L647-45 assume !(1 == ~t1_pc~0); 280025#L647-47 is_transmit1_triggered_~__retres1~1#1 := 0; 280023#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 280021#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 280019#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 280017#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 280013#L666-45 assume !(1 == ~t2_pc~0); 280011#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 280009#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 280006#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 280004#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 280002#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 280000#L685-45 assume !(1 == ~t3_pc~0); 279996#L685-47 is_transmit3_triggered_~__retres1~3#1 := 0; 279994#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 279990#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 279988#L1615-45 assume !(0 != activate_threads_~tmp___2~0#1); 279985#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 279983#L704-45 assume !(1 == ~t4_pc~0); 279980#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 279978#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 279976#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 279974#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 279972#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 279970#L723-45 assume !(1 == ~t5_pc~0); 279968#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 279965#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 279963#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 279960#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 279958#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 279956#L742-45 assume !(1 == ~t6_pc~0); 279954#L742-47 is_transmit6_triggered_~__retres1~6#1 := 0; 279952#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 279950#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 279947#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 279945#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 279943#L761-45 assume 1 == ~t7_pc~0; 279940#L762-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 279938#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 279936#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 279933#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 279931#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 279929#L780-45 assume !(1 == ~t8_pc~0); 279928#L780-47 is_transmit8_triggered_~__retres1~8#1 := 0; 279905#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 279867#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 277862#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 277859#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 277857#L799-45 assume !(1 == ~t9_pc~0); 277854#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 277852#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 277313#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 277310#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 277308#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 277306#L818-45 assume 1 == ~t10_pc~0; 277303#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 277301#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 277299#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 277297#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 277295#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 277293#L837-45 assume !(1 == ~t11_pc~0); 277290#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 277288#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 277287#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 277284#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 277282#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 277280#L856-45 assume 1 == ~t12_pc~0; 277277#L857-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 277275#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 277273#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 277271#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 277268#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 277266#L875-45 assume 1 == ~t13_pc~0; 277264#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 277262#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 276952#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 276941#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 276933#L1695-47 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 276927#L1427-3 assume !(1 == ~M_E~0); 270122#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 276427#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 276424#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 276422#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 276420#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 276418#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 276416#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 276414#L1462-3 assume !(1 == ~T8_E~0); 276411#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 276409#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 276407#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 276405#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 276403#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 276386#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 276373#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 276365#L1502-3 assume !(1 == ~E_2~0); 276289#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 276277#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 276268#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 276261#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 276254#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 274652#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 274651#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 274650#L1542-3 assume !(1 == ~E_10~0); 274649#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 274648#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 274647#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 274646#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 274634#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 274627#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 274626#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 274624#L1947 assume !(0 == start_simulation_~tmp~3#1); 274625#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 280263#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 280255#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 280253#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 280251#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 280249#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 280246#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 280244#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 252419#L1928-2 [2024-11-08 00:36:03,213 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:36:03,213 INFO L85 PathProgramCache]: Analyzing trace with hash -618334264, now seen corresponding path program 1 times [2024-11-08 00:36:03,213 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:36:03,213 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1832578769] [2024-11-08 00:36:03,213 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:36:03,213 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:36:03,222 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:36:03,248 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:36:03,248 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:36:03,248 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1832578769] [2024-11-08 00:36:03,248 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1832578769] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:36:03,248 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:36:03,248 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-08 00:36:03,248 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1255414976] [2024-11-08 00:36:03,248 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:36:03,249 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:36:03,249 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:36:03,249 INFO L85 PathProgramCache]: Analyzing trace with hash 1422958444, now seen corresponding path program 1 times [2024-11-08 00:36:03,249 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:36:03,249 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [296475398] [2024-11-08 00:36:03,249 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:36:03,249 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:36:03,258 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:36:03,276 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:36:03,276 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:36:03,276 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [296475398] [2024-11-08 00:36:03,276 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [296475398] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:36:03,276 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:36:03,276 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:36:03,276 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [619909862] [2024-11-08 00:36:03,276 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:36:03,277 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:36:03,277 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:36:03,277 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:36:03,277 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:36:03,277 INFO L87 Difference]: Start difference. First operand 51870 states and 73667 transitions. cyclomatic complexity: 21813 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:36:03,602 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:36:03,602 INFO L93 Difference]: Finished difference Result 99901 states and 141392 transitions. [2024-11-08 00:36:03,602 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 99901 states and 141392 transitions. [2024-11-08 00:36:04,205 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 99408 [2024-11-08 00:36:04,624 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 99901 states to 99901 states and 141392 transitions. [2024-11-08 00:36:04,624 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 99901 [2024-11-08 00:36:04,693 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 99901 [2024-11-08 00:36:04,694 INFO L73 IsDeterministic]: Start isDeterministic. Operand 99901 states and 141392 transitions. [2024-11-08 00:36:04,855 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:36:04,855 INFO L218 hiAutomatonCegarLoop]: Abstraction has 99901 states and 141392 transitions. [2024-11-08 00:36:04,889 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 99901 states and 141392 transitions. [2024-11-08 00:36:05,510 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 99901 to 99837. [2024-11-08 00:36:05,598 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 99837 states, 99837 states have (on average 1.415587407474183) internal successors, (141328), 99836 states have internal predecessors, (141328), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:36:05,943 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 99837 states to 99837 states and 141328 transitions. [2024-11-08 00:36:05,944 INFO L240 hiAutomatonCegarLoop]: Abstraction has 99837 states and 141328 transitions. [2024-11-08 00:36:05,944 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:36:05,944 INFO L425 stractBuchiCegarLoop]: Abstraction has 99837 states and 141328 transitions. [2024-11-08 00:36:05,945 INFO L332 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2024-11-08 00:36:05,945 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 99837 states and 141328 transitions. [2024-11-08 00:36:06,136 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 99344 [2024-11-08 00:36:06,136 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:36:06,136 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:36:06,137 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:36:06,137 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:36:06,138 INFO L745 eck$LassoCheckResult]: Stem: 403829#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 403830#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 404852#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 404853#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 405772#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 404414#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 404415#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 404487#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 404488#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 404965#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 404966#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 404451#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 404248#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 404249#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 404732#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 404733#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 404601#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 404602#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 404223#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 404224#L1279 assume !(0 == ~M_E~0); 405623#L1279-2 assume !(0 == ~T1_E~0); 403850#L1284-1 assume !(0 == ~T2_E~0); 403851#L1289-1 assume !(0 == ~T3_E~0); 404594#L1294-1 assume !(0 == ~T4_E~0); 404595#L1299-1 assume !(0 == ~T5_E~0); 404610#L1304-1 assume !(0 == ~T6_E~0); 405770#L1309-1 assume !(0 == ~T7_E~0); 405773#L1314-1 assume !(0 == ~T8_E~0); 403774#L1319-1 assume !(0 == ~T9_E~0); 403775#L1324-1 assume !(0 == ~T10_E~0); 403950#L1329-1 assume !(0 == ~T11_E~0); 403951#L1334-1 assume !(0 == ~T12_E~0); 405503#L1339-1 assume !(0 == ~T13_E~0); 405609#L1344-1 assume !(0 == ~E_M~0); 405610#L1349-1 assume !(0 == ~E_1~0); 404804#L1354-1 assume !(0 == ~E_2~0); 404805#L1359-1 assume !(0 == ~E_3~0); 405269#L1364-1 assume !(0 == ~E_4~0); 404071#L1369-1 assume !(0 == ~E_5~0); 404072#L1374-1 assume !(0 == ~E_6~0); 404811#L1379-1 assume !(0 == ~E_7~0); 404812#L1384-1 assume !(0 == ~E_8~0); 404900#L1389-1 assume !(0 == ~E_9~0); 405530#L1394-1 assume !(0 == ~E_10~0); 405531#L1399-1 assume !(0 == ~E_11~0); 405662#L1404-1 assume !(0 == ~E_12~0); 404168#L1409-1 assume !(0 == ~E_13~0); 404169#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 405657#L628 assume !(1 == ~m_pc~0); 404070#L628-2 is_master_triggered_~__retres1~0#1 := 0; 404069#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 404674#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 404675#L1591 assume !(0 != activate_threads_~tmp~1#1); 405672#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 404651#L647 assume !(1 == ~t1_pc~0); 404652#L647-2 is_transmit1_triggered_~__retres1~1#1 := 0; 404711#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 404712#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 405224#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 405592#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 405593#L666 assume !(1 == ~t2_pc~0); 403849#L666-2 is_transmit2_triggered_~__retres1~2#1 := 0; 404012#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 403990#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 403991#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 405017#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 405018#L685 assume !(1 == ~t3_pc~0); 405125#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 405197#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 405687#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 404861#L1615 assume !(0 != activate_threads_~tmp___2~0#1); 404862#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 404299#L704 assume !(1 == ~t4_pc~0); 404300#L704-2 is_transmit4_triggered_~__retres1~4#1 := 0; 404874#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 403638#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 403639#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 404709#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 404710#L723 assume !(1 == ~t5_pc~0); 404857#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 405094#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 405262#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 404996#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 404997#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 404054#L742 assume !(1 == ~t6_pc~0); 404055#L742-2 is_transmit6_triggered_~__retres1~6#1 := 0; 404212#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 403981#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 403743#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 403744#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 404132#L761 assume !(1 == ~t7_pc~0); 404133#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 404008#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 404009#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 404864#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 404865#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 403767#L780 assume !(1 == ~t8_pc~0); 403768#L780-2 is_transmit8_triggered_~__retres1~8#1 := 0; 404045#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 404046#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 404819#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 404820#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 404951#L799 assume !(1 == ~t9_pc~0); 404269#L799-2 is_transmit9_triggered_~__retres1~9#1 := 0; 403769#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 403770#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 404040#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 405170#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 404978#L818 assume !(1 == ~t10_pc~0); 403554#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 403555#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 405053#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 404981#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 404982#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 405026#L837 assume 1 == ~t11_pc~0; 405027#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 404850#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 405597#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 404944#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 404945#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 404661#L856 assume !(1 == ~t12_pc~0); 404662#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 405397#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 403572#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 403573#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 405369#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 405628#L875 assume 1 == ~t13_pc~0; 404608#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 404213#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 404214#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 404150#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 404151#L1695-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 405052#L1427 assume !(1 == ~M_E~0); 405037#L1427-2 assume !(1 == ~T1_E~0); 404120#L1432-1 assume !(1 == ~T2_E~0); 404121#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 405276#L1442-1 assume !(1 == ~T4_E~0); 405277#L1447-1 assume !(1 == ~T5_E~0); 405106#L1452-1 assume !(1 == ~T6_E~0); 403689#L1457-1 assume !(1 == ~T7_E~0); 403690#L1462-1 assume !(1 == ~T8_E~0); 405301#L1467-1 assume !(1 == ~T9_E~0); 405330#L1472-1 assume !(1 == ~T10_E~0); 405331#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 405048#L1482-1 assume !(1 == ~T12_E~0); 405049#L1487-1 assume !(1 == ~T13_E~0); 404020#L1492-1 assume !(1 == ~E_M~0); 404021#L1497-1 assume !(1 == ~E_1~0); 404396#L1502-1 assume !(1 == ~E_2~0); 404397#L1507-1 assume !(1 == ~E_3~0); 403900#L1512-1 assume !(1 == ~E_4~0); 403901#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 405425#L1522-1 assume !(1 == ~E_6~0); 404647#L1527-1 assume !(1 == ~E_7~0); 404648#L1532-1 assume !(1 == ~E_8~0); 405728#L1537-1 assume !(1 == ~E_9~0); 404882#L1542-1 assume !(1 == ~E_10~0); 404681#L1547-1 assume !(1 == ~E_11~0); 404682#L1552-1 assume !(1 == ~E_12~0); 403594#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 403595#L1562-1 assume { :end_inline_reset_delta_events } true; 404203#L1928-2 [2024-11-08 00:36:06,138 INFO L747 eck$LassoCheckResult]: Loop: 404203#L1928-2 assume !false; 440724#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 440719#L1254-1 assume !false; 440717#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 440699#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 440690#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 440688#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 440685#L1067 assume !(0 != eval_~tmp~0#1); 440681#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 440679#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 440677#L1279-3 assume !(0 == ~M_E~0); 440675#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 440672#L1284-3 assume !(0 == ~T2_E~0); 440670#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 440668#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 440666#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 440664#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 440662#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 440660#L1314-3 assume !(0 == ~T8_E~0); 440658#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 440656#L1324-3 assume !(0 == ~T10_E~0); 440653#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 440651#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 440649#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 440647#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 440645#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 440643#L1354-3 assume !(0 == ~E_2~0); 440641#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 440639#L1364-3 assume !(0 == ~E_4~0); 440637#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 440635#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 440633#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 440631#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 440628#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 440626#L1394-3 assume !(0 == ~E_10~0); 440624#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 440622#L1404-3 assume !(0 == ~E_12~0); 440620#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 440618#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 440616#L628-45 assume 1 == ~m_pc~0; 440614#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 440611#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 440609#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 440607#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 440605#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 440603#L647-45 assume !(1 == ~t1_pc~0); 440601#L647-47 is_transmit1_triggered_~__retres1~1#1 := 0; 440599#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 440597#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 440595#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 440593#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 440588#L666-45 assume !(1 == ~t2_pc~0); 440586#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 440584#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 440582#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 440580#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 440577#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 440575#L685-45 assume 1 == ~t3_pc~0; 440573#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 440574#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 441163#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 440564#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 440561#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 440559#L704-45 assume !(1 == ~t4_pc~0); 440557#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 440555#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 440553#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 440551#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 440548#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 440546#L723-45 assume !(1 == ~t5_pc~0); 440544#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 440541#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 440539#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 440538#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 440534#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 440532#L742-45 assume !(1 == ~t6_pc~0); 440530#L742-47 is_transmit6_triggered_~__retres1~6#1 := 0; 440529#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 440526#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 440525#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 440524#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 440521#L761-45 assume 1 == ~t7_pc~0; 440516#L762-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 440512#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 440511#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 440510#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 440509#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 440508#L780-45 assume !(1 == ~t8_pc~0); 440507#L780-47 is_transmit8_triggered_~__retres1~8#1 := 0; 440506#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 440505#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 440504#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 440503#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 440502#L799-45 assume !(1 == ~t9_pc~0); 440501#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 440500#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 440499#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 440498#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 440497#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 440496#L818-45 assume 1 == ~t10_pc~0; 440494#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 440493#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 440492#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 440491#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 440490#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 440489#L837-45 assume !(1 == ~t11_pc~0); 440487#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 440486#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 440484#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 440483#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 440482#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 440481#L856-45 assume !(1 == ~t12_pc~0); 440480#L856-47 is_transmit12_triggered_~__retres1~12#1 := 0; 440478#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 440477#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 440475#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 440474#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 440473#L875-45 assume !(1 == ~t13_pc~0); 440471#L875-47 is_transmit13_triggered_~__retres1~13#1 := 0; 440470#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 440469#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 440468#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 440467#L1695-47 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 440466#L1427-3 assume !(1 == ~M_E~0); 440213#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 440464#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 440462#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 440460#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 440458#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 440456#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 440454#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 440452#L1462-3 assume !(1 == ~T8_E~0); 440450#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 440448#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 440446#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 440444#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 440442#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 440440#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 440438#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 440436#L1502-3 assume !(1 == ~E_2~0); 440434#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 440432#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 440430#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 440428#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 440426#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 440424#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 440422#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 440420#L1542-3 assume !(1 == ~E_10~0); 440418#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 440416#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 440414#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 440412#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 440392#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 440384#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 440382#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 440379#L1947 assume !(0 == start_simulation_~tmp~3#1); 440380#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 440747#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 440737#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 440733#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 440732#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 440731#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 440730#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 440728#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 404203#L1928-2 [2024-11-08 00:36:06,139 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:36:06,139 INFO L85 PathProgramCache]: Analyzing trace with hash -1649665079, now seen corresponding path program 1 times [2024-11-08 00:36:06,139 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:36:06,139 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1170942740] [2024-11-08 00:36:06,139 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:36:06,139 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:36:06,153 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:36:06,187 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:36:06,187 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:36:06,187 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1170942740] [2024-11-08 00:36:06,187 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1170942740] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:36:06,187 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:36:06,187 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-08 00:36:06,187 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1428197546] [2024-11-08 00:36:06,187 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:36:06,187 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:36:06,187 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:36:06,187 INFO L85 PathProgramCache]: Analyzing trace with hash 1697528170, now seen corresponding path program 1 times [2024-11-08 00:36:06,187 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:36:06,188 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2101925090] [2024-11-08 00:36:06,188 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:36:06,188 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:36:06,196 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:36:06,312 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:36:06,312 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:36:06,312 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2101925090] [2024-11-08 00:36:06,313 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2101925090] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:36:06,313 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:36:06,313 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:36:06,313 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [325732608] [2024-11-08 00:36:06,313 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:36:06,313 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:36:06,313 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:36:06,313 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-08 00:36:06,313 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-08 00:36:06,314 INFO L87 Difference]: Start difference. First operand 99837 states and 141328 transitions. cyclomatic complexity: 41523 Second operand has 5 states, 5 states have (on average 32.2) internal successors, (161), 5 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:36:06,764 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:36:06,764 INFO L93 Difference]: Finished difference Result 102336 states and 143827 transitions. [2024-11-08 00:36:06,764 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 102336 states and 143827 transitions. [2024-11-08 00:36:07,274 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 101840 [2024-11-08 00:36:07,687 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 102336 states to 102336 states and 143827 transitions. [2024-11-08 00:36:07,687 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 102336 [2024-11-08 00:36:07,737 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 102336 [2024-11-08 00:36:07,738 INFO L73 IsDeterministic]: Start isDeterministic. Operand 102336 states and 143827 transitions. [2024-11-08 00:36:07,777 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:36:07,777 INFO L218 hiAutomatonCegarLoop]: Abstraction has 102336 states and 143827 transitions. [2024-11-08 00:36:07,821 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 102336 states and 143827 transitions. [2024-11-08 00:36:08,346 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 102336 to 102336. [2024-11-08 00:36:08,434 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 102336 states, 102336 states have (on average 1.4054389462163852) internal successors, (143827), 102335 states have internal predecessors, (143827), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:36:08,759 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 102336 states to 102336 states and 143827 transitions. [2024-11-08 00:36:08,759 INFO L240 hiAutomatonCegarLoop]: Abstraction has 102336 states and 143827 transitions. [2024-11-08 00:36:08,760 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-08 00:36:08,760 INFO L425 stractBuchiCegarLoop]: Abstraction has 102336 states and 143827 transitions. [2024-11-08 00:36:08,760 INFO L332 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2024-11-08 00:36:08,760 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 102336 states and 143827 transitions. [2024-11-08 00:36:09,106 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 101840 [2024-11-08 00:36:09,107 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:36:09,107 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:36:09,109 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:36:09,109 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:36:09,109 INFO L745 eck$LassoCheckResult]: Stem: 606010#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 606011#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 607022#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 607023#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 607881#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 606590#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 606591#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 606664#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 606665#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 607128#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 607129#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 606630#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 606429#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 606430#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 606904#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 606905#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 606784#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 606785#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 606403#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 606404#L1279 assume !(0 == ~M_E~0); 607757#L1279-2 assume !(0 == ~T1_E~0); 606031#L1284-1 assume !(0 == ~T2_E~0); 606032#L1289-1 assume !(0 == ~T3_E~0); 606773#L1294-1 assume !(0 == ~T4_E~0); 606774#L1299-1 assume !(0 == ~T5_E~0); 606788#L1304-1 assume !(0 == ~T6_E~0); 607879#L1309-1 assume !(0 == ~T7_E~0); 607883#L1314-1 assume !(0 == ~T8_E~0); 605956#L1319-1 assume !(0 == ~T9_E~0); 605957#L1324-1 assume !(0 == ~T10_E~0); 606131#L1329-1 assume !(0 == ~T11_E~0); 606132#L1334-1 assume !(0 == ~T12_E~0); 607645#L1339-1 assume !(0 == ~T13_E~0); 607744#L1344-1 assume !(0 == ~E_M~0); 607745#L1349-1 assume !(0 == ~E_1~0); 606980#L1354-1 assume !(0 == ~E_2~0); 606981#L1359-1 assume !(0 == ~E_3~0); 607426#L1364-1 assume !(0 == ~E_4~0); 606253#L1369-1 assume !(0 == ~E_5~0); 606254#L1374-1 assume !(0 == ~E_6~0); 606987#L1379-1 assume !(0 == ~E_7~0); 606988#L1384-1 assume !(0 == ~E_8~0); 607067#L1389-1 assume !(0 == ~E_9~0); 607671#L1394-1 assume !(0 == ~E_10~0); 607672#L1399-1 assume !(0 == ~E_11~0); 607800#L1404-1 assume !(0 == ~E_12~0); 606352#L1409-1 assume !(0 == ~E_13~0); 606353#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 607787#L628 assume !(1 == ~m_pc~0); 606252#L628-2 is_master_triggered_~__retres1~0#1 := 0; 606251#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 606851#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 606852#L1591 assume !(0 != activate_threads_~tmp~1#1); 607810#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 606829#L647 assume !(1 == ~t1_pc~0); 606830#L647-2 is_transmit1_triggered_~__retres1~1#1 := 0; 606883#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 606884#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 607379#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 607731#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 607732#L666 assume !(1 == ~t2_pc~0); 606030#L666-2 is_transmit2_triggered_~__retres1~2#1 := 0; 606195#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 606173#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 606174#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 607183#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 607184#L685 assume !(1 == ~t3_pc~0); 607286#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 607354#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 607820#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 607031#L1615 assume !(0 != activate_threads_~tmp___2~0#1); 607032#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 606479#L704 assume !(1 == ~t4_pc~0); 606480#L704-2 is_transmit4_triggered_~__retres1~4#1 := 0; 607043#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 605821#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 605822#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 606881#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 606882#L723 assume !(1 == ~t5_pc~0); 607027#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 607258#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 607419#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 607164#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 607165#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 606236#L742 assume !(1 == ~t6_pc~0); 606237#L742-2 is_transmit6_triggered_~__retres1~6#1 := 0; 606392#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 606162#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 605928#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 605929#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 606315#L761 assume !(1 == ~t7_pc~0); 606316#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 606191#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 606192#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 607033#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 607034#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 605947#L780 assume !(1 == ~t8_pc~0); 605948#L780-2 is_transmit8_triggered_~__retres1~8#1 := 0; 606226#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 606227#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 606992#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 606993#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 607116#L799 assume !(1 == ~t9_pc~0); 606451#L799-2 is_transmit9_triggered_~__retres1~9#1 := 0; 605949#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 605950#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 606221#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 607335#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 607141#L818 assume !(1 == ~t10_pc~0); 605736#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 605737#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 607219#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 607144#L1671 assume !(0 != activate_threads_~tmp___9~0#1); 607145#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 607192#L837 assume 1 == ~t11_pc~0; 607193#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 607019#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 607735#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 607106#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 607107#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 606842#L856 assume !(1 == ~t12_pc~0); 606843#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 607545#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 605754#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 605755#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 607519#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 607760#L875 assume 1 == ~t13_pc~0; 606786#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 606393#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 606394#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 606333#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 606334#L1695-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 607216#L1427 assume !(1 == ~M_E~0); 607202#L1427-2 assume !(1 == ~T1_E~0); 606302#L1432-1 assume !(1 == ~T2_E~0); 606303#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 607434#L1442-1 assume !(1 == ~T4_E~0); 607435#L1447-1 assume !(1 == ~T5_E~0); 607268#L1452-1 assume !(1 == ~T6_E~0); 605872#L1457-1 assume !(1 == ~T7_E~0); 605873#L1462-1 assume !(1 == ~T8_E~0); 607454#L1467-1 assume !(1 == ~T9_E~0); 607479#L1472-1 assume !(1 == ~T10_E~0); 607480#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 607212#L1482-1 assume !(1 == ~T12_E~0); 607213#L1487-1 assume !(1 == ~T13_E~0); 606201#L1492-1 assume !(1 == ~E_M~0); 606202#L1497-1 assume !(1 == ~E_1~0); 606571#L1502-1 assume !(1 == ~E_2~0); 606572#L1507-1 assume !(1 == ~E_3~0); 606081#L1512-1 assume !(1 == ~E_4~0); 606082#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 607573#L1522-1 assume !(1 == ~E_6~0); 606827#L1527-1 assume !(1 == ~E_7~0); 606828#L1532-1 assume !(1 == ~E_8~0); 607851#L1537-1 assume !(1 == ~E_9~0); 607053#L1542-1 assume !(1 == ~E_10~0); 606859#L1547-1 assume !(1 == ~E_11~0); 606860#L1552-1 assume !(1 == ~E_12~0); 605779#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 605780#L1562-1 assume { :end_inline_reset_delta_events } true; 606382#L1928-2 [2024-11-08 00:36:09,110 INFO L747 eck$LassoCheckResult]: Loop: 606382#L1928-2 assume !false; 632010#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 632005#L1254-1 assume !false; 632003#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 631979#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 631970#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 631968#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 631964#L1067 assume !(0 != eval_~tmp~0#1); 631962#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 631960#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 631958#L1279-3 assume !(0 == ~M_E~0); 631956#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 631954#L1284-3 assume !(0 == ~T2_E~0); 631952#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 631950#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 631948#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 631946#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 631944#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 631942#L1314-3 assume !(0 == ~T8_E~0); 631939#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 631937#L1324-3 assume !(0 == ~T10_E~0); 631935#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 631933#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 631931#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 631929#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 631927#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 631925#L1354-3 assume !(0 == ~E_2~0); 631923#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 631921#L1364-3 assume !(0 == ~E_4~0); 631919#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 631917#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 631915#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 631913#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 631911#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 631909#L1394-3 assume !(0 == ~E_10~0); 631907#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 631903#L1404-3 assume !(0 == ~E_12~0); 631901#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 631899#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 631897#L628-45 assume !(1 == ~m_pc~0); 631893#L628-47 is_master_triggered_~__retres1~0#1 := 0; 631891#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 631889#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 631886#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 631884#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 631882#L647-45 assume !(1 == ~t1_pc~0); 631880#L647-47 is_transmit1_triggered_~__retres1~1#1 := 0; 631878#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 631876#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 631873#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 631871#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 631867#L666-45 assume !(1 == ~t2_pc~0); 631865#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 631863#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 631860#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 631858#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 631856#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 631854#L685-45 assume !(1 == ~t3_pc~0); 631850#L685-47 is_transmit3_triggered_~__retres1~3#1 := 0; 631849#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 631848#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 631844#L1615-45 assume !(0 != activate_threads_~tmp___2~0#1); 631841#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 631839#L704-45 assume !(1 == ~t4_pc~0); 631838#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 631835#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 631834#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 631833#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 631832#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 631831#L723-45 assume 1 == ~t5_pc~0; 631829#L724-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 631828#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 631827#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 631826#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 631825#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 631824#L742-45 assume !(1 == ~t6_pc~0); 631823#L742-47 is_transmit6_triggered_~__retres1~6#1 := 0; 631822#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 631821#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 631820#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 631819#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 631818#L761-45 assume !(1 == ~t7_pc~0); 631816#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 631814#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 631813#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 631812#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 631811#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 631810#L780-45 assume !(1 == ~t8_pc~0); 631809#L780-47 is_transmit8_triggered_~__retres1~8#1 := 0; 631807#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 631806#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 631805#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 631804#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 631803#L799-45 assume !(1 == ~t9_pc~0); 631801#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 631798#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 631796#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 631794#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 631792#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 631790#L818-45 assume !(1 == ~t10_pc~0); 631786#L818-47 is_transmit10_triggered_~__retres1~10#1 := 0; 631784#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 631782#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 631780#L1671-45 assume !(0 != activate_threads_~tmp___9~0#1); 631777#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 631775#L837-45 assume !(1 == ~t11_pc~0); 631771#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 631769#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 631767#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 631765#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 631763#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 631761#L856-45 assume !(1 == ~t12_pc~0); 631757#L856-47 is_transmit12_triggered_~__retres1~12#1 := 0; 631754#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 631752#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 631750#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 631747#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 631745#L875-45 assume 1 == ~t13_pc~0; 631743#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 631740#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 631738#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 631736#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 631734#L1695-47 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 631732#L1427-3 assume !(1 == ~M_E~0); 631316#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 631728#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 631726#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 631724#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 631722#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 631720#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 631718#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 631716#L1462-3 assume !(1 == ~T8_E~0); 631714#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 631712#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 631710#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 631708#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 631706#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 631703#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 631701#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 631699#L1502-3 assume !(1 == ~E_2~0); 631697#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 631695#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 631693#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 631691#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 631689#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 631687#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 631685#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 631683#L1542-3 assume !(1 == ~E_10~0); 631681#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 631679#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 631677#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 631675#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 631647#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 631638#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 631636#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 631633#L1947 assume !(0 == start_simulation_~tmp~3#1); 631634#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 632032#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 632024#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 632022#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 632020#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 632018#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 632016#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 632014#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 606382#L1928-2 [2024-11-08 00:36:09,110 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:36:09,110 INFO L85 PathProgramCache]: Analyzing trace with hash -1665183797, now seen corresponding path program 1 times [2024-11-08 00:36:09,110 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:36:09,110 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2099025480] [2024-11-08 00:36:09,111 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:36:09,111 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:36:09,122 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:36:09,173 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:36:09,174 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:36:09,174 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2099025480] [2024-11-08 00:36:09,174 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2099025480] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:36:09,174 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:36:09,174 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:36:09,174 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [86722623] [2024-11-08 00:36:09,174 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:36:09,175 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:36:09,175 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:36:09,175 INFO L85 PathProgramCache]: Analyzing trace with hash -2079641104, now seen corresponding path program 1 times [2024-11-08 00:36:09,175 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:36:09,175 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [386178499] [2024-11-08 00:36:09,175 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:36:09,175 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:36:09,187 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:36:09,228 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:36:09,229 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:36:09,229 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [386178499] [2024-11-08 00:36:09,229 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [386178499] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:36:09,229 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:36:09,229 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-08 00:36:09,229 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [785328603] [2024-11-08 00:36:09,229 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:36:09,229 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:36:09,229 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:36:09,229 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-08 00:36:09,230 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-08 00:36:09,230 INFO L87 Difference]: Start difference. First operand 102336 states and 143827 transitions. cyclomatic complexity: 41523 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:36:10,234 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:36:10,234 INFO L93 Difference]: Finished difference Result 283579 states and 396169 transitions. [2024-11-08 00:36:10,234 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 283579 states and 396169 transitions. [2024-11-08 00:36:11,462 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 281936 [2024-11-08 00:36:12,136 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 283579 states to 283579 states and 396169 transitions. [2024-11-08 00:36:12,136 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 283579 [2024-11-08 00:36:12,265 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 283579 [2024-11-08 00:36:12,265 INFO L73 IsDeterministic]: Start isDeterministic. Operand 283579 states and 396169 transitions. [2024-11-08 00:36:12,403 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:36:12,403 INFO L218 hiAutomatonCegarLoop]: Abstraction has 283579 states and 396169 transitions. [2024-11-08 00:36:12,532 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 283579 states and 396169 transitions. [2024-11-08 00:36:14,688 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 283579 to 281787. [2024-11-08 00:36:14,918 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 281787 states, 281787 states have (on average 1.397740137053874) internal successors, (393865), 281786 states have internal predecessors, (393865), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:36:15,345 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 281787 states to 281787 states and 393865 transitions. [2024-11-08 00:36:15,346 INFO L240 hiAutomatonCegarLoop]: Abstraction has 281787 states and 393865 transitions. [2024-11-08 00:36:15,346 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-08 00:36:15,346 INFO L425 stractBuchiCegarLoop]: Abstraction has 281787 states and 393865 transitions. [2024-11-08 00:36:15,346 INFO L332 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2024-11-08 00:36:15,346 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 281787 states and 393865 transitions. [2024-11-08 00:36:16,248 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 280528 [2024-11-08 00:36:16,248 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:36:16,248 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:36:16,249 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:36:16,250 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:36:16,250 INFO L745 eck$LassoCheckResult]: Stem: 991935#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 991936#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 992949#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 992950#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 993832#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 992517#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 992518#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 992590#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 992591#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 993052#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 993053#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 992552#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 992353#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 992354#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 992835#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 992836#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 992703#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 992704#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 992328#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 992329#L1279 assume !(0 == ~M_E~0); 993695#L1279-2 assume !(0 == ~T1_E~0); 991956#L1284-1 assume !(0 == ~T2_E~0); 991957#L1289-1 assume !(0 == ~T3_E~0); 992698#L1294-1 assume !(0 == ~T4_E~0); 992699#L1299-1 assume !(0 == ~T5_E~0); 992715#L1304-1 assume !(0 == ~T6_E~0); 993828#L1309-1 assume !(0 == ~T7_E~0); 993833#L1314-1 assume !(0 == ~T8_E~0); 991880#L1319-1 assume !(0 == ~T9_E~0); 991881#L1324-1 assume !(0 == ~T10_E~0); 992054#L1329-1 assume !(0 == ~T11_E~0); 992055#L1334-1 assume !(0 == ~T12_E~0); 993583#L1339-1 assume !(0 == ~T13_E~0); 993686#L1344-1 assume !(0 == ~E_M~0); 993687#L1349-1 assume !(0 == ~E_1~0); 992905#L1354-1 assume !(0 == ~E_2~0); 992906#L1359-1 assume !(0 == ~E_3~0); 993354#L1364-1 assume !(0 == ~E_4~0); 992177#L1369-1 assume !(0 == ~E_5~0); 992178#L1374-1 assume !(0 == ~E_6~0); 992912#L1379-1 assume !(0 == ~E_7~0); 992913#L1384-1 assume !(0 == ~E_8~0); 992995#L1389-1 assume !(0 == ~E_9~0); 993610#L1394-1 assume !(0 == ~E_10~0); 993611#L1399-1 assume !(0 == ~E_11~0); 993739#L1404-1 assume !(0 == ~E_12~0); 992274#L1409-1 assume !(0 == ~E_13~0); 992275#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 993733#L628 assume !(1 == ~m_pc~0); 992176#L628-2 is_master_triggered_~__retres1~0#1 := 0; 992175#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 992780#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 992781#L1591 assume !(0 != activate_threads_~tmp~1#1); 993749#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 992756#L647 assume !(1 == ~t1_pc~0); 992757#L647-2 is_transmit1_triggered_~__retres1~1#1 := 0; 992814#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 992815#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 993310#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 993667#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 993668#L666 assume !(1 == ~t2_pc~0); 991955#L666-2 is_transmit2_triggered_~__retres1~2#1 := 0; 992117#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 992095#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 992096#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 993112#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 993113#L685 assume !(1 == ~t3_pc~0); 993287#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 993288#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 993294#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 992958#L1615 assume !(0 != activate_threads_~tmp___2~0#1); 992959#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 992401#L704 assume !(1 == ~t4_pc~0); 992402#L704-2 is_transmit4_triggered_~__retres1~4#1 := 0; 992971#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 991747#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 991748#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 992812#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 992813#L723 assume !(1 == ~t5_pc~0); 992954#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 993187#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 993346#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 993089#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 993090#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 992160#L742 assume !(1 == ~t6_pc~0); 992161#L742-2 is_transmit6_triggered_~__retres1~6#1 := 0; 992317#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 992086#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 991852#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 991853#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 992238#L761 assume !(1 == ~t7_pc~0); 992239#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 992113#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 992114#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 992961#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 992962#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 991875#L780 assume !(1 == ~t8_pc~0); 991876#L780-2 is_transmit8_triggered_~__retres1~8#1 := 0; 992151#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 992152#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 992920#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 992921#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 993040#L799 assume !(1 == ~t9_pc~0); 992374#L799-2 is_transmit9_triggered_~__retres1~9#1 := 0; 991873#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 991874#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 992146#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 993263#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 993066#L818 assume !(1 == ~t10_pc~0); 991662#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 991663#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 993145#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 993069#L1671 assume !(0 != activate_threads_~tmp___9~0#1); 993070#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 993121#L837 assume !(1 == ~t11_pc~0); 992946#L837-2 is_transmit11_triggered_~__retres1~11#1 := 0; 992947#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 993674#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 993033#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 993034#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 992767#L856 assume !(1 == ~t12_pc~0); 992768#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 993486#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 991680#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 991681#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 993452#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 993698#L875 assume 1 == ~t13_pc~0; 992711#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 992318#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 992319#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 992255#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 992256#L1695-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 993144#L1427 assume !(1 == ~M_E~0); 993127#L1427-2 assume !(1 == ~T1_E~0); 992225#L1432-1 assume !(1 == ~T2_E~0); 992226#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 993361#L1442-1 assume !(1 == ~T4_E~0); 993362#L1447-1 assume !(1 == ~T5_E~0); 993198#L1452-1 assume !(1 == ~T6_E~0); 991798#L1457-1 assume !(1 == ~T7_E~0); 991799#L1462-1 assume !(1 == ~T8_E~0); 993385#L1467-1 assume !(1 == ~T9_E~0); 993411#L1472-1 assume !(1 == ~T10_E~0); 993412#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 993140#L1482-1 assume !(1 == ~T12_E~0); 993141#L1487-1 assume !(1 == ~T13_E~0); 992125#L1492-1 assume !(1 == ~E_M~0); 992126#L1497-1 assume !(1 == ~E_1~0); 992497#L1502-1 assume !(1 == ~E_2~0); 992498#L1507-1 assume !(1 == ~E_3~0); 992004#L1512-1 assume !(1 == ~E_4~0); 992005#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 993508#L1522-1 assume !(1 == ~E_6~0); 992753#L1527-1 assume !(1 == ~E_7~0); 992754#L1532-1 assume !(1 == ~E_8~0); 993804#L1537-1 assume !(1 == ~E_9~0); 992978#L1542-1 assume !(1 == ~E_10~0); 992787#L1547-1 assume !(1 == ~E_11~0); 992788#L1552-1 assume !(1 == ~E_12~0); 991703#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 991704#L1562-1 assume { :end_inline_reset_delta_events } true; 992307#L1928-2 [2024-11-08 00:36:16,250 INFO L747 eck$LassoCheckResult]: Loop: 992307#L1928-2 assume !false; 1103258#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1103252#L1254-1 assume !false; 1103249#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1103055#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1103039#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1103031#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1103019#L1067 assume !(0 != eval_~tmp~0#1); 1103009#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1102074#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1102071#L1279-3 assume !(0 == ~M_E~0); 1102069#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1102067#L1284-3 assume !(0 == ~T2_E~0); 1102065#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1102063#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1102061#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1102059#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1102057#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1102055#L1314-3 assume !(0 == ~T8_E~0); 1102053#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1102051#L1324-3 assume !(0 == ~T10_E~0); 1102049#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1102046#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 1102043#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 1102041#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1102039#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1102037#L1354-3 assume !(0 == ~E_2~0); 1102035#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1102033#L1364-3 assume !(0 == ~E_4~0); 1102031#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1102029#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1102027#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1102025#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1102023#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1102021#L1394-3 assume !(0 == ~E_10~0); 1102018#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1102016#L1404-3 assume !(0 == ~E_12~0); 1102014#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 1102012#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1101776#L628-45 assume !(1 == ~m_pc~0); 1101771#L628-47 is_master_triggered_~__retres1~0#1 := 0; 1101769#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1101767#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1101765#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1101762#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1101760#L647-45 assume !(1 == ~t1_pc~0); 1101758#L647-47 is_transmit1_triggered_~__retres1~1#1 := 0; 1101757#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1101755#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1101746#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1101738#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1101728#L666-45 assume !(1 == ~t2_pc~0); 1101721#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 1101712#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1101705#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1101698#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1101690#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1101683#L685-45 assume !(1 == ~t3_pc~0); 1101675#L685-47 is_transmit3_triggered_~__retres1~3#1 := 0; 1101667#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1101660#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1101653#L1615-45 assume !(0 != activate_threads_~tmp___2~0#1); 1101533#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1100059#L704-45 assume !(1 == ~t4_pc~0); 1100044#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 1100042#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1100040#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1100037#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1100035#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1100033#L723-45 assume 1 == ~t5_pc~0; 1100030#L724-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1100028#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1100026#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1100024#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 1100022#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1100020#L742-45 assume !(1 == ~t6_pc~0); 1100018#L742-47 is_transmit6_triggered_~__retres1~6#1 := 0; 1100016#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1100014#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1100012#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1100010#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1100008#L761-45 assume 1 == ~t7_pc~0; 1100005#L762-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1100003#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1100001#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1099999#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1099997#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1099995#L780-45 assume !(1 == ~t8_pc~0); 1099993#L780-47 is_transmit8_triggered_~__retres1~8#1 := 0; 1099991#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1099989#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1099987#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1099985#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1099983#L799-45 assume !(1 == ~t9_pc~0); 1099981#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 1099979#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1099977#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1099975#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1099973#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1099971#L818-45 assume 1 == ~t10_pc~0; 1099969#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1099970#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1100603#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1099959#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1099957#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1099955#L837-45 assume !(1 == ~t11_pc~0); 1099953#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 1099951#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1099949#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1099947#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1099945#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1099944#L856-45 assume 1 == ~t12_pc~0; 1099942#L857-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 1099939#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1099937#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1099935#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1099933#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1099931#L875-45 assume !(1 == ~t13_pc~0); 1099928#L875-47 is_transmit13_triggered_~__retres1~13#1 := 0; 1099924#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1099922#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1099920#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 1099918#L1695-47 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1099915#L1427-3 assume !(1 == ~M_E~0); 1099636#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1099912#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1099910#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1099908#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1099906#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1099904#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1099902#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1099900#L1462-3 assume !(1 == ~T8_E~0); 1099897#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1099895#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1099893#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1099891#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1099889#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 1099887#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1099885#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1099883#L1502-3 assume !(1 == ~E_2~0); 1099881#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1099879#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1099877#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1099875#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1099872#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1099870#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1099868#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1099866#L1542-3 assume !(1 == ~E_10~0); 1099864#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1099862#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 1099859#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 1099857#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1099808#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1099800#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1099798#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 1099795#L1947 assume !(0 == start_simulation_~tmp~3#1); 1099796#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1103340#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1103322#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1103321#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 1103319#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1103305#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1103294#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 1103285#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 992307#L1928-2 [2024-11-08 00:36:16,251 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:36:16,251 INFO L85 PathProgramCache]: Analyzing trace with hash 736341324, now seen corresponding path program 1 times [2024-11-08 00:36:16,251 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:36:16,251 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1410095667] [2024-11-08 00:36:16,251 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:36:16,251 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:36:16,259 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:36:16,282 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:36:16,282 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:36:16,282 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1410095667] [2024-11-08 00:36:16,282 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1410095667] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:36:16,282 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:36:16,282 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-08 00:36:16,282 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [370862926] [2024-11-08 00:36:16,282 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:36:16,283 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:36:16,283 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:36:16,283 INFO L85 PathProgramCache]: Analyzing trace with hash -343407252, now seen corresponding path program 1 times [2024-11-08 00:36:16,283 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:36:16,283 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1203250951] [2024-11-08 00:36:16,283 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:36:16,283 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:36:16,292 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:36:16,307 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:36:16,307 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:36:16,307 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1203250951] [2024-11-08 00:36:16,307 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1203250951] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:36:16,307 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:36:16,307 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:36:16,307 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [94958442] [2024-11-08 00:36:16,307 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:36:16,308 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:36:16,308 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:36:16,308 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-08 00:36:16,308 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-08 00:36:16,308 INFO L87 Difference]: Start difference. First operand 281787 states and 393865 transitions. cyclomatic complexity: 112142 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:36:18,490 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-08 00:36:18,490 INFO L93 Difference]: Finished difference Result 541610 states and 754806 transitions. [2024-11-08 00:36:18,490 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 541610 states and 754806 transitions. [2024-11-08 00:36:20,777 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 538880 [2024-11-08 00:36:21,995 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 541610 states to 541610 states and 754806 transitions. [2024-11-08 00:36:21,995 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 541610 [2024-11-08 00:36:22,266 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 541610 [2024-11-08 00:36:22,266 INFO L73 IsDeterministic]: Start isDeterministic. Operand 541610 states and 754806 transitions. [2024-11-08 00:36:22,523 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-08 00:36:22,524 INFO L218 hiAutomatonCegarLoop]: Abstraction has 541610 states and 754806 transitions. [2024-11-08 00:36:23,090 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 541610 states and 754806 transitions. [2024-11-08 00:36:26,715 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 541610 to 541226. [2024-11-08 00:36:27,093 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 541226 states, 541226 states have (on average 1.3939130788247422) internal successors, (754422), 541225 states have internal predecessors, (754422), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-08 00:36:28,608 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 541226 states to 541226 states and 754422 transitions. [2024-11-08 00:36:28,608 INFO L240 hiAutomatonCegarLoop]: Abstraction has 541226 states and 754422 transitions. [2024-11-08 00:36:28,608 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-08 00:36:28,609 INFO L425 stractBuchiCegarLoop]: Abstraction has 541226 states and 754422 transitions. [2024-11-08 00:36:28,609 INFO L332 stractBuchiCegarLoop]: ======== Iteration 27 ============ [2024-11-08 00:36:28,609 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 541226 states and 754422 transitions. [2024-11-08 00:36:30,179 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 538496 [2024-11-08 00:36:30,179 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-08 00:36:30,180 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-08 00:36:30,181 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:36:30,181 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-08 00:36:30,181 INFO L745 eck$LassoCheckResult]: Stem: 1815342#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 1815343#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 1816365#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1816366#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1817327#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 1815926#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1815927#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1815998#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1815999#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1816472#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1816473#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1815960#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1815760#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1815761#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1816239#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1816240#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1816114#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 1816115#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 1815735#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1815736#L1279 assume !(0 == ~M_E~0); 1817159#L1279-2 assume !(0 == ~T1_E~0); 1815363#L1284-1 assume !(0 == ~T2_E~0); 1815364#L1289-1 assume !(0 == ~T3_E~0); 1816111#L1294-1 assume !(0 == ~T4_E~0); 1816112#L1299-1 assume !(0 == ~T5_E~0); 1816122#L1304-1 assume !(0 == ~T6_E~0); 1817324#L1309-1 assume !(0 == ~T7_E~0); 1817328#L1314-1 assume !(0 == ~T8_E~0); 1815286#L1319-1 assume !(0 == ~T9_E~0); 1815287#L1324-1 assume !(0 == ~T10_E~0); 1815463#L1329-1 assume !(0 == ~T11_E~0); 1815464#L1334-1 assume !(0 == ~T12_E~0); 1817030#L1339-1 assume !(0 == ~T13_E~0); 1817147#L1344-1 assume !(0 == ~E_M~0); 1817148#L1349-1 assume !(0 == ~E_1~0); 1816316#L1354-1 assume !(0 == ~E_2~0); 1816317#L1359-1 assume !(0 == ~E_3~0); 1816786#L1364-1 assume !(0 == ~E_4~0); 1815587#L1369-1 assume !(0 == ~E_5~0); 1815588#L1374-1 assume !(0 == ~E_6~0); 1816323#L1379-1 assume !(0 == ~E_7~0); 1816324#L1384-1 assume !(0 == ~E_8~0); 1816412#L1389-1 assume !(0 == ~E_9~0); 1817060#L1394-1 assume !(0 == ~E_10~0); 1817061#L1399-1 assume !(0 == ~E_11~0); 1817208#L1404-1 assume !(0 == ~E_12~0); 1815681#L1409-1 assume !(0 == ~E_13~0); 1815682#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1817200#L628 assume !(1 == ~m_pc~0); 1815586#L628-2 is_master_triggered_~__retres1~0#1 := 0; 1815585#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1816184#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1816185#L1591 assume !(0 != activate_threads_~tmp~1#1); 1817217#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1816162#L647 assume !(1 == ~t1_pc~0); 1816163#L647-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1816218#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1816219#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1816739#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 1817127#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1817128#L666 assume !(1 == ~t2_pc~0); 1815362#L666-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1815526#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1815504#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1815505#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 1816529#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1816530#L685 assume !(1 == ~t3_pc~0); 1816712#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1816713#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1816720#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1816374#L1615 assume !(0 != activate_threads_~tmp___2~0#1); 1816375#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1815811#L704 assume !(1 == ~t4_pc~0); 1815812#L704-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1816387#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1815151#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1815152#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 1816216#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1816217#L723 assume !(1 == ~t5_pc~0); 1816370#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1816611#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1816778#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1816505#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 1816506#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1815569#L742 assume !(1 == ~t6_pc~0); 1815570#L742-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1815724#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1815495#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1815257#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 1815258#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1815646#L761 assume !(1 == ~t7_pc~0); 1815647#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1815522#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1815523#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1816377#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 1816378#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1815279#L780 assume !(1 == ~t8_pc~0); 1815280#L780-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1815560#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1815561#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1816330#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 1816331#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1816460#L799 assume !(1 == ~t9_pc~0); 1815783#L799-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1815281#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1815282#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1815555#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 1816686#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1816488#L818 assume !(1 == ~t10_pc~0); 1815066#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1815067#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1816566#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1816491#L1671 assume !(0 != activate_threads_~tmp___9~0#1); 1816492#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1816540#L837 assume !(1 == ~t11_pc~0); 1816362#L837-2 is_transmit11_triggered_~__retres1~11#1 := 0; 1816363#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1817132#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1816453#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 1816454#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1816172#L856 assume !(1 == ~t12_pc~0); 1816173#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 1816920#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1815084#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1815085#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 1816889#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1817165#L875 assume !(1 == ~t13_pc~0); 1817138#L875-2 is_transmit13_triggered_~__retres1~13#1 := 0; 1815725#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1815726#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1815663#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 1815664#L1695-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1816565#L1427 assume !(1 == ~M_E~0); 1816549#L1427-2 assume !(1 == ~T1_E~0); 1815634#L1432-1 assume !(1 == ~T2_E~0); 1815635#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1816795#L1442-1 assume !(1 == ~T4_E~0); 1816796#L1447-1 assume !(1 == ~T5_E~0); 1816622#L1452-1 assume !(1 == ~T6_E~0); 1815202#L1457-1 assume !(1 == ~T7_E~0); 1815203#L1462-1 assume !(1 == ~T8_E~0); 1816823#L1467-1 assume !(1 == ~T9_E~0); 1816852#L1472-1 assume !(1 == ~T10_E~0); 1816853#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1816561#L1482-1 assume !(1 == ~T12_E~0); 1816562#L1487-1 assume !(1 == ~T13_E~0); 1815535#L1492-1 assume !(1 == ~E_M~0); 1815536#L1497-1 assume !(1 == ~E_1~0); 1815906#L1502-1 assume !(1 == ~E_2~0); 1815907#L1507-1 assume !(1 == ~E_3~0); 1815412#L1512-1 assume !(1 == ~E_4~0); 1815413#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 1816948#L1522-1 assume !(1 == ~E_6~0); 1816159#L1527-1 assume !(1 == ~E_7~0); 1816160#L1532-1 assume !(1 == ~E_8~0); 1817285#L1537-1 assume !(1 == ~E_9~0); 1816395#L1542-1 assume !(1 == ~E_10~0); 1816191#L1547-1 assume !(1 == ~E_11~0); 1816192#L1552-1 assume !(1 == ~E_12~0); 1815107#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 1815108#L1562-1 assume { :end_inline_reset_delta_events } true; 1815715#L1928-2 [2024-11-08 00:36:30,182 INFO L747 eck$LassoCheckResult]: Loop: 1815715#L1928-2 assume !false; 1982388#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1982383#L1254-1 assume !false; 1982381#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1981481#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1981472#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1981469#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1981466#L1067 assume !(0 != eval_~tmp~0#1); 1981464#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1981462#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1981460#L1279-3 assume !(0 == ~M_E~0); 1981458#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1981456#L1284-3 assume !(0 == ~T2_E~0); 1981454#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1981452#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1981450#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1981448#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1981446#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1981444#L1314-3 assume !(0 == ~T8_E~0); 1981442#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1981440#L1324-3 assume !(0 == ~T10_E~0); 1981438#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1981436#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 1981432#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 1981430#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1981428#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1981426#L1354-3 assume !(0 == ~E_2~0); 1981423#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1981421#L1364-3 assume !(0 == ~E_4~0); 1981419#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1981417#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1981415#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1981413#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1981411#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1981409#L1394-3 assume !(0 == ~E_10~0); 1981407#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1981404#L1404-3 assume !(0 == ~E_12~0); 1981402#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 1981400#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1981398#L628-45 assume 1 == ~m_pc~0; 1981396#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1981393#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1981391#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1981389#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1981387#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1981385#L647-45 assume !(1 == ~t1_pc~0); 1981383#L647-47 is_transmit1_triggered_~__retres1~1#1 := 0; 1981382#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1981378#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1981376#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1981374#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1981372#L666-45 assume !(1 == ~t2_pc~0); 1981369#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 1981368#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1981367#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1981366#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1981365#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1981364#L685-45 assume !(1 == ~t3_pc~0); 1981363#L685-47 is_transmit3_triggered_~__retres1~3#1 := 0; 1981362#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1981360#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1981359#L1615-45 assume !(0 != activate_threads_~tmp___2~0#1); 1981358#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1981357#L704-45 assume !(1 == ~t4_pc~0); 1981356#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 1981355#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1981354#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1981352#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1981351#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1981350#L723-45 assume 1 == ~t5_pc~0; 1981348#L724-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1981347#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1981346#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1981345#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 1981344#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1981342#L742-45 assume !(1 == ~t6_pc~0); 1981339#L742-47 is_transmit6_triggered_~__retres1~6#1 := 0; 1981337#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1981335#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1981333#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1981331#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1981329#L761-45 assume 1 == ~t7_pc~0; 1981326#L762-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1981324#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1981322#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1981320#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1981318#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1981315#L780-45 assume !(1 == ~t8_pc~0); 1981313#L780-47 is_transmit8_triggered_~__retres1~8#1 := 0; 1981311#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1981309#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1981307#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1981305#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1981303#L799-45 assume !(1 == ~t9_pc~0); 1981301#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 1981299#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1981297#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1981295#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1981293#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1981291#L818-45 assume 1 == ~t10_pc~0; 1981289#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1981290#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1981353#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1981280#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1981278#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1981276#L837-45 assume !(1 == ~t11_pc~0); 1981273#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 1981271#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1981269#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1981267#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1981265#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1981263#L856-45 assume 1 == ~t12_pc~0; 1981260#L857-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 1981258#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1981256#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1981254#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1981252#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1981250#L875-45 assume !(1 == ~t13_pc~0); 1981247#L875-47 is_transmit13_triggered_~__retres1~13#1 := 0; 1981245#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1981243#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1981241#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 1981239#L1695-47 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1981237#L1427-3 assume !(1 == ~M_E~0); 1980862#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1981234#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1981232#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1981230#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1981228#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1981226#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1981224#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1981222#L1462-3 assume !(1 == ~T8_E~0); 1981220#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1981218#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1981216#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1981212#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1981210#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 1981208#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1981206#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1981203#L1502-3 assume !(1 == ~E_2~0); 1981201#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1981199#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1981197#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1981195#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1981193#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1981191#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1981189#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1981187#L1542-3 assume !(1 == ~E_10~0); 1981184#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1981182#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 1981180#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 1981178#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1981147#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1981137#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1981136#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 1981133#L1947 assume !(0 == start_simulation_~tmp~3#1); 1981134#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1982410#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1982402#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1982400#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 1982398#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1982395#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1982393#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 1982391#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 1815715#L1928-2 [2024-11-08 00:36:30,182 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:36:30,183 INFO L85 PathProgramCache]: Analyzing trace with hash 1787790413, now seen corresponding path program 1 times [2024-11-08 00:36:30,183 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:36:30,183 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [572919983] [2024-11-08 00:36:30,183 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:36:30,183 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:36:30,191 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:36:30,222 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:36:30,222 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:36:30,222 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [572919983] [2024-11-08 00:36:30,222 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [572919983] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:36:30,222 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:36:30,222 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:36:30,222 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [105273566] [2024-11-08 00:36:30,222 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:36:30,224 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-08 00:36:30,224 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-08 00:36:30,224 INFO L85 PathProgramCache]: Analyzing trace with hash 1436050859, now seen corresponding path program 1 times [2024-11-08 00:36:30,224 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-08 00:36:30,224 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [194693491] [2024-11-08 00:36:30,224 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-08 00:36:30,224 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-08 00:36:30,231 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-08 00:36:30,245 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-08 00:36:30,245 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-08 00:36:30,245 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [194693491] [2024-11-08 00:36:30,245 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [194693491] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-08 00:36:30,245 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-08 00:36:30,245 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-08 00:36:30,245 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1171075085] [2024-11-08 00:36:30,245 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-08 00:36:30,246 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-08 00:36:30,246 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-08 00:36:30,246 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-08 00:36:30,246 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-08 00:36:30,246 INFO L87 Difference]: Start difference. First operand 541226 states and 754422 transitions. cyclomatic complexity: 213324 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)