./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/bist_cell.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 023d838f Calling Ultimate with: /root/.sdkman/candidates/java/11.0.12-open/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/bist_cell.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash de455e90ef2ae1a82fb7a87bbcdb07831c7ef68e47976e1b2868a3e9de47a0a2 --- Real Ultimate output --- This is Ultimate 0.2.5-tmp.fs.icfgbuilder-eval-023d838-m [2024-11-10 23:18:56,643 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-10 23:18:56,711 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-11-10 23:18:56,715 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-10 23:18:56,715 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-10 23:18:56,716 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder.Remove goto edges from RCFG [2024-11-10 23:18:56,745 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-10 23:18:56,746 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-10 23:18:56,747 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-10 23:18:56,749 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-10 23:18:56,749 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-10 23:18:56,750 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-10 23:18:56,751 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-10 23:18:56,752 INFO L153 SettingsManager]: * Use SBE=true [2024-11-10 23:18:56,753 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-11-10 23:18:56,753 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-11-10 23:18:56,753 INFO L153 SettingsManager]: * Use old map elimination=false [2024-11-10 23:18:56,754 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-11-10 23:18:56,754 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-11-10 23:18:56,754 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-11-10 23:18:56,755 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-10 23:18:56,755 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-11-10 23:18:56,756 INFO L153 SettingsManager]: * sizeof long=4 [2024-11-10 23:18:56,756 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-10 23:18:56,756 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-11-10 23:18:56,757 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-10 23:18:56,757 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-11-10 23:18:56,758 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-11-10 23:18:56,758 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-11-10 23:18:56,758 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-11-10 23:18:56,759 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-11-10 23:18:56,759 INFO L153 SettingsManager]: * sizeof long double=12 [2024-11-10 23:18:56,759 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-10 23:18:56,760 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-11-10 23:18:56,760 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-10 23:18:56,760 INFO L151 SettingsManager]: Preferences of IcfgBuilder differ from their defaults: [2024-11-10 23:18:56,760 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-10 23:18:56,761 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-10 23:18:56,761 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-11-10 23:18:56,762 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-11-10 23:18:56,762 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> de455e90ef2ae1a82fb7a87bbcdb07831c7ef68e47976e1b2868a3e9de47a0a2 [2024-11-10 23:18:57,034 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-10 23:18:57,058 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-10 23:18:57,064 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-10 23:18:57,065 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-10 23:18:57,066 INFO L274 PluginConnector]: CDTParser initialized [2024-11-10 23:18:57,067 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/bist_cell.cil.c [2024-11-10 23:18:58,592 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-11-10 23:18:58,810 INFO L384 CDTParser]: Found 1 translation units. [2024-11-10 23:18:58,810 INFO L180 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/bist_cell.cil.c [2024-11-10 23:18:58,828 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/4b44d4646/6635ec1c40e642eeb1c147c4d4b388fa/FLAGdc696a5dc [2024-11-10 23:18:59,173 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/4b44d4646/6635ec1c40e642eeb1c147c4d4b388fa [2024-11-10 23:18:59,176 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-10 23:18:59,177 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-10 23:18:59,181 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-10 23:18:59,181 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-10 23:18:59,187 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-10 23:18:59,188 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 10.11 11:18:59" (1/1) ... [2024-11-10 23:18:59,189 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@5de03a6 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 11:18:59, skipping insertion in model container [2024-11-10 23:18:59,189 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 10.11 11:18:59" (1/1) ... [2024-11-10 23:18:59,228 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-10 23:18:59,490 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-10 23:18:59,508 INFO L200 MainTranslator]: Completed pre-run [2024-11-10 23:18:59,562 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-10 23:18:59,593 INFO L204 MainTranslator]: Completed translation [2024-11-10 23:18:59,593 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 11:18:59 WrapperNode [2024-11-10 23:18:59,593 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-10 23:18:59,595 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-10 23:18:59,595 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-10 23:18:59,595 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-10 23:18:59,602 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 11:18:59" (1/1) ... [2024-11-10 23:18:59,609 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 11:18:59" (1/1) ... [2024-11-10 23:18:59,633 INFO L138 Inliner]: procedures = 30, calls = 31, calls flagged for inlining = 26, calls inlined = 32, statements flattened = 343 [2024-11-10 23:18:59,634 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-10 23:18:59,635 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-10 23:18:59,635 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-10 23:18:59,635 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-10 23:18:59,645 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 11:18:59" (1/1) ... [2024-11-10 23:18:59,646 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 11:18:59" (1/1) ... [2024-11-10 23:18:59,649 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 11:18:59" (1/1) ... [2024-11-10 23:18:59,664 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-11-10 23:18:59,665 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 11:18:59" (1/1) ... [2024-11-10 23:18:59,665 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 11:18:59" (1/1) ... [2024-11-10 23:18:59,670 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 11:18:59" (1/1) ... [2024-11-10 23:18:59,672 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 11:18:59" (1/1) ... [2024-11-10 23:18:59,673 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 11:18:59" (1/1) ... [2024-11-10 23:18:59,674 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 11:18:59" (1/1) ... [2024-11-10 23:18:59,677 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-10 23:18:59,678 INFO L112 PluginConnector]: ------------------------IcfgBuilder---------------------------- [2024-11-10 23:18:59,678 INFO L270 PluginConnector]: Initializing IcfgBuilder... [2024-11-10 23:18:59,678 INFO L274 PluginConnector]: IcfgBuilder initialized [2024-11-10 23:18:59,680 INFO L184 PluginConnector]: Executing the observer IcfgBuilderObserver from plugin IcfgBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 11:18:59" (1/1) ... [2024-11-10 23:18:59,685 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-10 23:18:59,699 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-10 23:18:59,715 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-10 23:18:59,717 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-11-10 23:18:59,759 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-10 23:18:59,760 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-11-10 23:18:59,760 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-10 23:18:59,760 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-10 23:18:59,831 INFO L256 CfgBuilder]: Building ICFG [2024-11-10 23:18:59,832 INFO L286 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-10 23:19:00,270 INFO L? ?]: Removed 36 outVars from TransFormulas that were not future-live. [2024-11-10 23:19:00,270 INFO L307 CfgBuilder]: Performing block encoding [2024-11-10 23:19:00,286 INFO L331 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-10 23:19:00,287 INFO L336 CfgBuilder]: Removed 0 assume(true) statements. [2024-11-10 23:19:00,287 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 10.11 11:19:00 BoogieIcfgContainer [2024-11-10 23:19:00,287 INFO L131 PluginConnector]: ------------------------ END IcfgBuilder---------------------------- [2024-11-10 23:19:00,288 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-11-10 23:19:00,288 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-11-10 23:19:00,292 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-11-10 23:19:00,292 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-10 23:19:00,293 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 10.11 11:18:59" (1/3) ... [2024-11-10 23:19:00,293 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@6f883002 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 10.11 11:19:00, skipping insertion in model container [2024-11-10 23:19:00,294 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-10 23:19:00,294 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.11 11:18:59" (2/3) ... [2024-11-10 23:19:00,294 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@6f883002 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 10.11 11:19:00, skipping insertion in model container [2024-11-10 23:19:00,294 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-10 23:19:00,294 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 10.11 11:19:00" (3/3) ... [2024-11-10 23:19:00,295 INFO L332 chiAutomizerObserver]: Analyzing ICFG bist_cell.cil.c [2024-11-10 23:19:00,340 INFO L300 stractBuchiCegarLoop]: Interprodecural is true [2024-11-10 23:19:00,340 INFO L301 stractBuchiCegarLoop]: Hoare is None [2024-11-10 23:19:00,340 INFO L302 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-11-10 23:19:00,340 INFO L303 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-11-10 23:19:00,340 INFO L304 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-11-10 23:19:00,341 INFO L305 stractBuchiCegarLoop]: Difference is false [2024-11-10 23:19:00,341 INFO L306 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-11-10 23:19:00,341 INFO L310 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-11-10 23:19:00,345 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 128 states, 127 states have (on average 1.6220472440944882) internal successors, (206), 127 states have internal predecessors, (206), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-10 23:19:00,367 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 72 [2024-11-10 23:19:00,367 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-10 23:19:00,367 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-10 23:19:00,374 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-10 23:19:00,375 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-10 23:19:00,375 INFO L332 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-11-10 23:19:00,376 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 128 states, 127 states have (on average 1.6220472440944882) internal successors, (206), 127 states have internal predecessors, (206), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-10 23:19:00,385 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 72 [2024-11-10 23:19:00,388 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-10 23:19:00,388 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-10 23:19:00,390 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-10 23:19:00,391 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-10 23:19:00,400 INFO L745 eck$LassoCheckResult]: Stem: 112#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 28#ULTIMATE.init_returnLabel#1true assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 19#L490true assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 93#L212-1true assume !(1 == ~b0_req_up~0); 78#L219-1true assume !(1 == ~b1_req_up~0); 42#L226-1true assume !(1 == ~d0_req_up~0); 60#L233-1true assume !(1 == ~d1_req_up~0); 107#L240-1true assume !(1 == ~z_req_up~0); 76#L248-1true assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 18#L255true assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 128#L261true assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 81#L321-1true assume !(0 == ~b0_ev~0); 24#L326-1true assume !(0 == ~b1_ev~0); 29#L331-1true assume !(0 == ~d0_ev~0); 6#L336-1true assume !(0 == ~d1_ev~0); 122#L341-1true assume 0 == ~z_ev~0;~z_ev~0 := 1; 116#L347-1true assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 114#L107-1true assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 99#L121-1true assume true;is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 119#L130-1true assume true;activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 96#L390-1true assume !(0 != activate_threads_~tmp~1#1); 23#L396-1true assume true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41#L354-1true assume !(1 == ~b0_ev~0); 82#L359-1true assume !(1 == ~b1_ev~0); 40#L364-1true assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 46#L369-1true assume !(1 == ~d1_ev~0); 97#L374-1true assume !(1 == ~z_ev~0); 7#L380-1true assume true;assume { :end_inline_reset_delta_events } true; 83#L432true [2024-11-10 23:19:00,404 INFO L747 eck$LassoCheckResult]: Loop: 83#L432true assume true; 70#L432-1true assume !false;assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 110#L285true assume !true; 111#L293true assume true; 103#L314true assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 69#L212true assume !(1 == ~b0_req_up~0); 124#L219true assume !(1 == ~b1_req_up~0); 11#L226true assume !(1 == ~d0_req_up~0); 59#L233true assume !(1 == ~d1_req_up~0); 26#L240true assume !(1 == ~z_req_up~0); 125#L248true assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 61#L321true assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 32#L326true assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 10#L331true assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 77#L336true assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 84#L341true assume 0 == ~z_ev~0;~z_ev~0 := 1; 108#L347true assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 118#L107true assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 27#L121true assume true;is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 53#L130true assume true;activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 88#L390true assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 86#L396true assume true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 52#L354true assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 89#L359true assume 1 == ~b1_ev~0;~b1_ev~0 := 2; 121#L364true assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 37#L369true assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 129#L374true assume 1 == ~z_ev~0;~z_ev~0 := 2; 68#L380true assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 22#L268true assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 8#L270true assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 3#L276true assume true;stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1; 13#L407true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 117#L409true assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 104#L415true assume true;start_simulation_#t~ret8#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1; 66#L449true assume !(0 != start_simulation_~tmp~3#1); 83#L432true [2024-11-10 23:19:00,411 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-10 23:19:00,411 INFO L85 PathProgramCache]: Analyzing trace with hash 1453080336, now seen corresponding path program 1 times [2024-11-10 23:19:00,419 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-10 23:19:00,419 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [730621986] [2024-11-10 23:19:00,419 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-10 23:19:00,420 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-10 23:19:00,512 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-10 23:19:00,637 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-10 23:19:00,637 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-10 23:19:00,637 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [730621986] [2024-11-10 23:19:00,638 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [730621986] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-10 23:19:00,638 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-10 23:19:00,639 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-10 23:19:00,640 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [556092943] [2024-11-10 23:19:00,640 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-10 23:19:00,644 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-10 23:19:00,644 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-10 23:19:00,645 INFO L85 PathProgramCache]: Analyzing trace with hash 1604571376, now seen corresponding path program 1 times [2024-11-10 23:19:00,645 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-10 23:19:00,645 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2132592852] [2024-11-10 23:19:00,645 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-10 23:19:00,645 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-10 23:19:00,654 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-10 23:19:00,669 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-10 23:19:00,670 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-10 23:19:00,674 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2132592852] [2024-11-10 23:19:00,675 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2132592852] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-10 23:19:00,675 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-10 23:19:00,675 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-10 23:19:00,675 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [316756036] [2024-11-10 23:19:00,675 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-10 23:19:00,677 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-10 23:19:00,677 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-10 23:19:00,714 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-10 23:19:00,714 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-10 23:19:00,716 INFO L87 Difference]: Start difference. First operand has 128 states, 127 states have (on average 1.6220472440944882) internal successors, (206), 127 states have internal predecessors, (206), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 9.333333333333334) internal successors, (28), 3 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-10 23:19:00,752 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-10 23:19:00,752 INFO L93 Difference]: Finished difference Result 126 states and 198 transitions. [2024-11-10 23:19:00,754 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 126 states and 198 transitions. [2024-11-10 23:19:00,758 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 72 [2024-11-10 23:19:00,766 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 126 states to 118 states and 190 transitions. [2024-11-10 23:19:00,769 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 118 [2024-11-10 23:19:00,770 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 118 [2024-11-10 23:19:00,772 INFO L73 IsDeterministic]: Start isDeterministic. Operand 118 states and 190 transitions. [2024-11-10 23:19:00,774 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-10 23:19:00,774 INFO L218 hiAutomatonCegarLoop]: Abstraction has 118 states and 190 transitions. [2024-11-10 23:19:00,795 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 118 states and 190 transitions. [2024-11-10 23:19:00,806 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 118 to 118. [2024-11-10 23:19:00,808 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 118 states, 118 states have (on average 1.6101694915254237) internal successors, (190), 117 states have internal predecessors, (190), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-10 23:19:00,809 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 118 states to 118 states and 190 transitions. [2024-11-10 23:19:00,810 INFO L240 hiAutomatonCegarLoop]: Abstraction has 118 states and 190 transitions. [2024-11-10 23:19:00,811 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-10 23:19:00,817 INFO L425 stractBuchiCegarLoop]: Abstraction has 118 states and 190 transitions. [2024-11-10 23:19:00,817 INFO L332 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-11-10 23:19:00,817 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 118 states and 190 transitions. [2024-11-10 23:19:00,819 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 72 [2024-11-10 23:19:00,820 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-10 23:19:00,820 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-10 23:19:00,821 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-10 23:19:00,821 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-10 23:19:00,822 INFO L745 eck$LassoCheckResult]: Stem: 378#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 309#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 292#L490 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 293#L212-1 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 360#L137-1 assume !(~b0_val~0 != ~b0_val_t~0); 361#L143-1 ~b0_req_up~0 := 0; 349#L145-1 assume true;assume { :end_inline_update_b0 } true; 350#L219-1 assume !(1 == ~b1_req_up~0); 319#L226-1 assume !(1 == ~d0_req_up~0); 328#L233-1 assume !(1 == ~d1_req_up~0); 347#L240-1 assume !(1 == ~z_req_up~0); 331#L248-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 290#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 291#L261 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 363#L321-1 assume !(0 == ~b0_ev~0); 301#L326-1 assume !(0 == ~b1_ev~0); 302#L331-1 assume !(0 == ~d0_ev~0); 270#L336-1 assume !(0 == ~d1_ev~0); 271#L341-1 assume 0 == ~z_ev~0;~z_ev~0 := 1; 380#L347-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 379#L107-1 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 313#L121-1 assume true;is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 369#L130-1 assume true;activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 368#L390-1 assume !(0 != activate_threads_~tmp~1#1); 299#L396-1 assume true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 300#L354-1 assume !(1 == ~b0_ev~0); 326#L359-1 assume !(1 == ~b1_ev~0); 324#L364-1 assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 325#L369-1 assume !(1 == ~d1_ev~0); 329#L374-1 assume !(1 == ~z_ev~0); 272#L380-1 assume true;assume { :end_inline_reset_delta_events } true; 273#L432 [2024-11-10 23:19:00,822 INFO L747 eck$LassoCheckResult]: Loop: 273#L432 assume true; 357#L432-1 assume !false;assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 269#L285 assume true; 333#L285-1 assume !false;assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 334#L268-1 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 284#L270-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 285#L276-1 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 323#L290 assume !(0 != eval_~tmp___0~0#1); 377#L293 assume true; 371#L314 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 356#L212 assume !(1 == ~b0_req_up~0); 341#L219 assume !(1 == ~b1_req_up~0); 279#L226 assume !(1 == ~d0_req_up~0); 266#L233 assume !(1 == ~d1_req_up~0); 305#L240 assume !(1 == ~z_req_up~0); 307#L248 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 348#L321 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 314#L326 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 277#L331 assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 278#L336 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 362#L341 assume 0 == ~z_ev~0;~z_ev~0 := 1; 364#L347 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 376#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 296#L121 assume true;is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 308#L130 assume true;activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 339#L390 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 365#L396 assume true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 336#L354 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 337#L359 assume 1 == ~b1_ev~0;~b1_ev~0 := 2; 366#L364 assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 320#L369 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 321#L374 assume 1 == ~z_ev~0;~z_ev~0 := 2; 355#L380 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 298#L268 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 274#L270 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 263#L276 assume true;stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1; 264#L407 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 283#L409 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 372#L415 assume true;start_simulation_#t~ret8#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1; 353#L449 assume !(0 != start_simulation_~tmp~3#1); 273#L432 [2024-11-10 23:19:00,823 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-10 23:19:00,824 INFO L85 PathProgramCache]: Analyzing trace with hash 1671984624, now seen corresponding path program 1 times [2024-11-10 23:19:00,824 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-10 23:19:00,824 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1533143060] [2024-11-10 23:19:00,824 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-10 23:19:00,825 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-10 23:19:00,846 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-10 23:19:00,960 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-10 23:19:00,961 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-10 23:19:00,961 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1533143060] [2024-11-10 23:19:00,962 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1533143060] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-10 23:19:00,962 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-10 23:19:00,962 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-10 23:19:00,962 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [414692559] [2024-11-10 23:19:00,962 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-10 23:19:00,963 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-10 23:19:00,963 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-10 23:19:00,964 INFO L85 PathProgramCache]: Analyzing trace with hash -1332115255, now seen corresponding path program 1 times [2024-11-10 23:19:00,964 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-10 23:19:00,964 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1765793153] [2024-11-10 23:19:00,964 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-10 23:19:00,964 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-10 23:19:00,979 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-10 23:19:01,056 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-10 23:19:01,057 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-10 23:19:01,057 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1765793153] [2024-11-10 23:19:01,057 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1765793153] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-10 23:19:01,057 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-10 23:19:01,057 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-10 23:19:01,057 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [419812168] [2024-11-10 23:19:01,058 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-10 23:19:01,058 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-10 23:19:01,058 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-10 23:19:01,059 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-10 23:19:01,059 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-10 23:19:01,059 INFO L87 Difference]: Start difference. First operand 118 states and 190 transitions. cyclomatic complexity: 73 Second operand has 3 states, 3 states have (on average 10.333333333333334) internal successors, (31), 3 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-10 23:19:01,094 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-10 23:19:01,094 INFO L93 Difference]: Finished difference Result 118 states and 189 transitions. [2024-11-10 23:19:01,094 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 118 states and 189 transitions. [2024-11-10 23:19:01,096 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 72 [2024-11-10 23:19:01,101 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 118 states to 118 states and 189 transitions. [2024-11-10 23:19:01,102 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 118 [2024-11-10 23:19:01,102 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 118 [2024-11-10 23:19:01,102 INFO L73 IsDeterministic]: Start isDeterministic. Operand 118 states and 189 transitions. [2024-11-10 23:19:01,103 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-10 23:19:01,103 INFO L218 hiAutomatonCegarLoop]: Abstraction has 118 states and 189 transitions. [2024-11-10 23:19:01,103 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 118 states and 189 transitions. [2024-11-10 23:19:01,112 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 118 to 118. [2024-11-10 23:19:01,114 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 118 states, 118 states have (on average 1.6016949152542372) internal successors, (189), 117 states have internal predecessors, (189), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-10 23:19:01,115 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 118 states to 118 states and 189 transitions. [2024-11-10 23:19:01,115 INFO L240 hiAutomatonCegarLoop]: Abstraction has 118 states and 189 transitions. [2024-11-10 23:19:01,118 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-10 23:19:01,119 INFO L425 stractBuchiCegarLoop]: Abstraction has 118 states and 189 transitions. [2024-11-10 23:19:01,119 INFO L332 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-11-10 23:19:01,119 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 118 states and 189 transitions. [2024-11-10 23:19:01,120 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 72 [2024-11-10 23:19:01,120 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-10 23:19:01,120 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-10 23:19:01,123 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-10 23:19:01,123 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-10 23:19:01,123 INFO L745 eck$LassoCheckResult]: Stem: 623#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 554#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 537#L490 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 538#L212-1 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 605#L137-1 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 606#L143-1 ~b0_req_up~0 := 0; 594#L145-1 assume true;assume { :end_inline_update_b0 } true; 595#L219-1 assume !(1 == ~b1_req_up~0); 564#L226-1 assume !(1 == ~d0_req_up~0); 573#L233-1 assume !(1 == ~d1_req_up~0); 592#L240-1 assume !(1 == ~z_req_up~0); 576#L248-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 535#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 536#L261 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 608#L321-1 assume !(0 == ~b0_ev~0); 546#L326-1 assume !(0 == ~b1_ev~0); 547#L331-1 assume !(0 == ~d0_ev~0); 515#L336-1 assume !(0 == ~d1_ev~0); 516#L341-1 assume 0 == ~z_ev~0;~z_ev~0 := 1; 625#L347-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 624#L107-1 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 558#L121-1 assume true;is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 614#L130-1 assume true;activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 613#L390-1 assume !(0 != activate_threads_~tmp~1#1); 544#L396-1 assume true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 545#L354-1 assume !(1 == ~b0_ev~0); 571#L359-1 assume !(1 == ~b1_ev~0); 569#L364-1 assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 570#L369-1 assume !(1 == ~d1_ev~0); 574#L374-1 assume !(1 == ~z_ev~0); 517#L380-1 assume true;assume { :end_inline_reset_delta_events } true; 518#L432 [2024-11-10 23:19:01,126 INFO L747 eck$LassoCheckResult]: Loop: 518#L432 assume true; 602#L432-1 assume !false;assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 514#L285 assume true; 578#L285-1 assume !false;assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 579#L268-1 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 529#L270-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 530#L276-1 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 568#L290 assume !(0 != eval_~tmp___0~0#1); 622#L293 assume true; 616#L314 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 601#L212 assume !(1 == ~b0_req_up~0); 586#L219 assume !(1 == ~b1_req_up~0); 524#L226 assume !(1 == ~d0_req_up~0); 511#L233 assume !(1 == ~d1_req_up~0); 550#L240 assume !(1 == ~z_req_up~0); 552#L248 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 593#L321 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 559#L326 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 522#L331 assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 523#L336 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 607#L341 assume 0 == ~z_ev~0;~z_ev~0 := 1; 609#L347 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 621#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 541#L121 assume true;is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 553#L130 assume true;activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 584#L390 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 610#L396 assume true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 581#L354 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 582#L359 assume 1 == ~b1_ev~0;~b1_ev~0 := 2; 611#L364 assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 565#L369 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 566#L374 assume 1 == ~z_ev~0;~z_ev~0 := 2; 600#L380 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 543#L268 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 519#L270 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 508#L276 assume true;stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1; 509#L407 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 528#L409 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 617#L415 assume true;start_simulation_#t~ret8#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1; 598#L449 assume !(0 != start_simulation_~tmp~3#1); 518#L432 [2024-11-10 23:19:01,127 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-10 23:19:01,127 INFO L85 PathProgramCache]: Analyzing trace with hash 710370607, now seen corresponding path program 1 times [2024-11-10 23:19:01,127 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-10 23:19:01,127 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1729040254] [2024-11-10 23:19:01,127 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-10 23:19:01,127 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-10 23:19:01,146 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-10 23:19:01,204 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-10 23:19:01,205 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-10 23:19:01,205 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1729040254] [2024-11-10 23:19:01,205 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1729040254] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-10 23:19:01,205 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-10 23:19:01,205 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-10 23:19:01,205 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1725855942] [2024-11-10 23:19:01,206 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-10 23:19:01,206 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-10 23:19:01,206 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-10 23:19:01,207 INFO L85 PathProgramCache]: Analyzing trace with hash -1332115255, now seen corresponding path program 2 times [2024-11-10 23:19:01,207 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-10 23:19:01,207 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1962160968] [2024-11-10 23:19:01,207 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-10 23:19:01,207 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-10 23:19:01,223 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-10 23:19:01,295 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-10 23:19:01,296 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-10 23:19:01,297 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1962160968] [2024-11-10 23:19:01,297 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1962160968] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-10 23:19:01,297 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-10 23:19:01,298 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-10 23:19:01,299 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1807754998] [2024-11-10 23:19:01,299 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-10 23:19:01,299 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-10 23:19:01,300 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-10 23:19:01,300 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-10 23:19:01,300 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-10 23:19:01,301 INFO L87 Difference]: Start difference. First operand 118 states and 189 transitions. cyclomatic complexity: 72 Second operand has 3 states, 3 states have (on average 10.333333333333334) internal successors, (31), 3 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-10 23:19:01,322 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-10 23:19:01,322 INFO L93 Difference]: Finished difference Result 118 states and 188 transitions. [2024-11-10 23:19:01,323 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 118 states and 188 transitions. [2024-11-10 23:19:01,324 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 72 [2024-11-10 23:19:01,325 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 118 states to 118 states and 188 transitions. [2024-11-10 23:19:01,326 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 118 [2024-11-10 23:19:01,326 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 118 [2024-11-10 23:19:01,326 INFO L73 IsDeterministic]: Start isDeterministic. Operand 118 states and 188 transitions. [2024-11-10 23:19:01,327 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-10 23:19:01,327 INFO L218 hiAutomatonCegarLoop]: Abstraction has 118 states and 188 transitions. [2024-11-10 23:19:01,327 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 118 states and 188 transitions. [2024-11-10 23:19:01,334 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 118 to 118. [2024-11-10 23:19:01,335 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 118 states, 118 states have (on average 1.5932203389830508) internal successors, (188), 117 states have internal predecessors, (188), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-10 23:19:01,336 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 118 states to 118 states and 188 transitions. [2024-11-10 23:19:01,336 INFO L240 hiAutomatonCegarLoop]: Abstraction has 118 states and 188 transitions. [2024-11-10 23:19:01,338 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-10 23:19:01,338 INFO L425 stractBuchiCegarLoop]: Abstraction has 118 states and 188 transitions. [2024-11-10 23:19:01,339 INFO L332 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-11-10 23:19:01,339 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 118 states and 188 transitions. [2024-11-10 23:19:01,340 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 72 [2024-11-10 23:19:01,340 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-10 23:19:01,340 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-10 23:19:01,341 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-10 23:19:01,341 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-10 23:19:01,342 INFO L745 eck$LassoCheckResult]: Stem: 868#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 799#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 782#L490 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 783#L212-1 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 850#L137-1 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 851#L143-1 ~b0_req_up~0 := 0; 839#L145-1 assume true;assume { :end_inline_update_b0 } true; 840#L219-1 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 848#L152-1 assume !(~b1_val~0 != ~b1_val_t~0); 849#L158-1 ~b1_req_up~0 := 0; 808#L160-1 assume true;assume { :end_inline_update_b1 } true; 809#L226-1 assume !(1 == ~d0_req_up~0); 818#L233-1 assume !(1 == ~d1_req_up~0); 837#L240-1 assume !(1 == ~z_req_up~0); 821#L248-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 780#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 781#L261 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 853#L321-1 assume !(0 == ~b0_ev~0); 791#L326-1 assume !(0 == ~b1_ev~0); 792#L331-1 assume !(0 == ~d0_ev~0); 760#L336-1 assume !(0 == ~d1_ev~0); 761#L341-1 assume 0 == ~z_ev~0;~z_ev~0 := 1; 870#L347-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 869#L107-1 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 803#L121-1 assume true;is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 859#L130-1 assume true;activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 858#L390-1 assume !(0 != activate_threads_~tmp~1#1); 789#L396-1 assume true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 790#L354-1 assume !(1 == ~b0_ev~0); 816#L359-1 assume !(1 == ~b1_ev~0); 814#L364-1 assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 815#L369-1 assume !(1 == ~d1_ev~0); 819#L374-1 assume !(1 == ~z_ev~0); 762#L380-1 assume true;assume { :end_inline_reset_delta_events } true; 763#L432 [2024-11-10 23:19:01,342 INFO L747 eck$LassoCheckResult]: Loop: 763#L432 assume true; 847#L432-1 assume !false;assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 759#L285 assume true; 823#L285-1 assume !false;assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 824#L268-1 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 774#L270-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 775#L276-1 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 813#L290 assume !(0 != eval_~tmp___0~0#1); 867#L293 assume true; 861#L314 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 846#L212 assume !(1 == ~b0_req_up~0); 831#L219 assume !(1 == ~b1_req_up~0); 769#L226 assume !(1 == ~d0_req_up~0); 756#L233 assume !(1 == ~d1_req_up~0); 795#L240 assume !(1 == ~z_req_up~0); 797#L248 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 838#L321 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 804#L326 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 767#L331 assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 768#L336 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 852#L341 assume 0 == ~z_ev~0;~z_ev~0 := 1; 854#L347 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 866#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 786#L121 assume true;is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 798#L130 assume true;activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 829#L390 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 855#L396 assume true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 826#L354 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 827#L359 assume 1 == ~b1_ev~0;~b1_ev~0 := 2; 856#L364 assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 810#L369 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 811#L374 assume 1 == ~z_ev~0;~z_ev~0 := 2; 845#L380 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 788#L268 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 764#L270 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 753#L276 assume true;stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1; 754#L407 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 773#L409 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 862#L415 assume true;start_simulation_#t~ret8#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1; 843#L449 assume !(0 != start_simulation_~tmp~3#1); 763#L432 [2024-11-10 23:19:01,344 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-10 23:19:01,344 INFO L85 PathProgramCache]: Analyzing trace with hash -703410064, now seen corresponding path program 1 times [2024-11-10 23:19:01,344 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-10 23:19:01,344 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1800550847] [2024-11-10 23:19:01,344 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-10 23:19:01,345 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-10 23:19:01,363 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-10 23:19:01,474 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-10 23:19:01,474 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-10 23:19:01,474 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1800550847] [2024-11-10 23:19:01,474 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1800550847] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-10 23:19:01,475 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-10 23:19:01,475 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-10 23:19:01,475 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [528638266] [2024-11-10 23:19:01,475 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-10 23:19:01,475 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-10 23:19:01,476 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-10 23:19:01,476 INFO L85 PathProgramCache]: Analyzing trace with hash -1332115255, now seen corresponding path program 3 times [2024-11-10 23:19:01,476 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-10 23:19:01,476 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [469731792] [2024-11-10 23:19:01,476 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-10 23:19:01,477 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-10 23:19:01,496 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-10 23:19:01,545 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-10 23:19:01,545 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-10 23:19:01,546 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [469731792] [2024-11-10 23:19:01,546 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [469731792] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-10 23:19:01,546 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-10 23:19:01,546 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-10 23:19:01,546 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [790318222] [2024-11-10 23:19:01,546 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-10 23:19:01,547 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-10 23:19:01,547 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-10 23:19:01,547 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-10 23:19:01,548 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-10 23:19:01,548 INFO L87 Difference]: Start difference. First operand 118 states and 188 transitions. cyclomatic complexity: 71 Second operand has 4 states, 4 states have (on average 8.5) internal successors, (34), 4 states have internal predecessors, (34), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-10 23:19:01,604 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-10 23:19:01,604 INFO L93 Difference]: Finished difference Result 118 states and 187 transitions. [2024-11-10 23:19:01,605 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 118 states and 187 transitions. [2024-11-10 23:19:01,607 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 72 [2024-11-10 23:19:01,610 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 118 states to 118 states and 187 transitions. [2024-11-10 23:19:01,610 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 118 [2024-11-10 23:19:01,612 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 118 [2024-11-10 23:19:01,612 INFO L73 IsDeterministic]: Start isDeterministic. Operand 118 states and 187 transitions. [2024-11-10 23:19:01,612 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-10 23:19:01,613 INFO L218 hiAutomatonCegarLoop]: Abstraction has 118 states and 187 transitions. [2024-11-10 23:19:01,613 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 118 states and 187 transitions. [2024-11-10 23:19:01,620 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 118 to 118. [2024-11-10 23:19:01,621 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 118 states, 118 states have (on average 1.5847457627118644) internal successors, (187), 117 states have internal predecessors, (187), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-10 23:19:01,622 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 118 states to 118 states and 187 transitions. [2024-11-10 23:19:01,622 INFO L240 hiAutomatonCegarLoop]: Abstraction has 118 states and 187 transitions. [2024-11-10 23:19:01,625 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-10 23:19:01,626 INFO L425 stractBuchiCegarLoop]: Abstraction has 118 states and 187 transitions. [2024-11-10 23:19:01,626 INFO L332 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-11-10 23:19:01,626 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 118 states and 187 transitions. [2024-11-10 23:19:01,627 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 72 [2024-11-10 23:19:01,627 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-10 23:19:01,627 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-10 23:19:01,630 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-10 23:19:01,632 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-10 23:19:01,633 INFO L745 eck$LassoCheckResult]: Stem: 1116#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 1047#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 1030#L490 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1031#L212-1 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 1098#L137-1 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 1099#L143-1 ~b0_req_up~0 := 0; 1087#L145-1 assume true;assume { :end_inline_update_b0 } true; 1088#L219-1 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 1096#L152-1 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 1097#L158-1 ~b1_req_up~0 := 0; 1056#L160-1 assume true;assume { :end_inline_update_b1 } true; 1057#L226-1 assume !(1 == ~d0_req_up~0); 1066#L233-1 assume !(1 == ~d1_req_up~0); 1085#L240-1 assume !(1 == ~z_req_up~0); 1069#L248-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1028#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 1029#L261 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1101#L321-1 assume !(0 == ~b0_ev~0); 1039#L326-1 assume !(0 == ~b1_ev~0); 1040#L331-1 assume !(0 == ~d0_ev~0); 1008#L336-1 assume !(0 == ~d1_ev~0); 1009#L341-1 assume 0 == ~z_ev~0;~z_ev~0 := 1; 1118#L347-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 1117#L107-1 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 1051#L121-1 assume true;is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 1107#L130-1 assume true;activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 1106#L390-1 assume !(0 != activate_threads_~tmp~1#1); 1037#L396-1 assume true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1038#L354-1 assume !(1 == ~b0_ev~0); 1064#L359-1 assume !(1 == ~b1_ev~0); 1062#L364-1 assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 1063#L369-1 assume !(1 == ~d1_ev~0); 1067#L374-1 assume !(1 == ~z_ev~0); 1010#L380-1 assume true;assume { :end_inline_reset_delta_events } true; 1011#L432 [2024-11-10 23:19:01,633 INFO L747 eck$LassoCheckResult]: Loop: 1011#L432 assume true; 1095#L432-1 assume !false;assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 1007#L285 assume true; 1071#L285-1 assume !false;assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 1072#L268-1 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 1022#L270-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 1023#L276-1 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1061#L290 assume !(0 != eval_~tmp___0~0#1); 1115#L293 assume true; 1109#L314 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1094#L212 assume !(1 == ~b0_req_up~0); 1079#L219 assume !(1 == ~b1_req_up~0); 1017#L226 assume !(1 == ~d0_req_up~0); 1004#L233 assume !(1 == ~d1_req_up~0); 1043#L240 assume !(1 == ~z_req_up~0); 1045#L248 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1086#L321 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 1052#L326 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 1015#L331 assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 1016#L336 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 1100#L341 assume 0 == ~z_ev~0;~z_ev~0 := 1; 1102#L347 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 1114#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 1034#L121 assume true;is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 1046#L130 assume true;activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 1077#L390 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 1103#L396 assume true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1074#L354 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 1075#L359 assume 1 == ~b1_ev~0;~b1_ev~0 := 2; 1104#L364 assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 1058#L369 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 1059#L374 assume 1 == ~z_ev~0;~z_ev~0 := 2; 1093#L380 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 1036#L268 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 1012#L270 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 1001#L276 assume true;stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1; 1002#L407 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1021#L409 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1110#L415 assume true;start_simulation_#t~ret8#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1; 1091#L449 assume !(0 != start_simulation_~tmp~3#1); 1011#L432 [2024-11-10 23:19:01,634 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-10 23:19:01,634 INFO L85 PathProgramCache]: Analyzing trace with hash -734429871, now seen corresponding path program 1 times [2024-11-10 23:19:01,634 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-10 23:19:01,634 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1434068167] [2024-11-10 23:19:01,634 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-10 23:19:01,635 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-10 23:19:01,649 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-10 23:19:01,673 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-10 23:19:01,674 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-10 23:19:01,674 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1434068167] [2024-11-10 23:19:01,674 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1434068167] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-10 23:19:01,674 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-10 23:19:01,674 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-10 23:19:01,674 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [180135837] [2024-11-10 23:19:01,674 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-10 23:19:01,675 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-10 23:19:01,675 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-10 23:19:01,675 INFO L85 PathProgramCache]: Analyzing trace with hash -1332115255, now seen corresponding path program 4 times [2024-11-10 23:19:01,675 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-10 23:19:01,675 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1658692534] [2024-11-10 23:19:01,675 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-10 23:19:01,675 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-10 23:19:01,687 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-10 23:19:01,751 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-10 23:19:01,751 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-10 23:19:01,751 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1658692534] [2024-11-10 23:19:01,751 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1658692534] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-10 23:19:01,751 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-10 23:19:01,751 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-10 23:19:01,752 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [515476353] [2024-11-10 23:19:01,752 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-10 23:19:01,752 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-10 23:19:01,752 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-10 23:19:01,752 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-10 23:19:01,753 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-10 23:19:01,753 INFO L87 Difference]: Start difference. First operand 118 states and 187 transitions. cyclomatic complexity: 70 Second operand has 3 states, 3 states have (on average 11.333333333333334) internal successors, (34), 3 states have internal predecessors, (34), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-10 23:19:01,776 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-10 23:19:01,777 INFO L93 Difference]: Finished difference Result 118 states and 186 transitions. [2024-11-10 23:19:01,777 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 118 states and 186 transitions. [2024-11-10 23:19:01,778 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 72 [2024-11-10 23:19:01,779 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 118 states to 118 states and 186 transitions. [2024-11-10 23:19:01,779 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 118 [2024-11-10 23:19:01,779 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 118 [2024-11-10 23:19:01,781 INFO L73 IsDeterministic]: Start isDeterministic. Operand 118 states and 186 transitions. [2024-11-10 23:19:01,783 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-10 23:19:01,784 INFO L218 hiAutomatonCegarLoop]: Abstraction has 118 states and 186 transitions. [2024-11-10 23:19:01,784 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 118 states and 186 transitions. [2024-11-10 23:19:01,791 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 118 to 118. [2024-11-10 23:19:01,791 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 118 states, 118 states have (on average 1.576271186440678) internal successors, (186), 117 states have internal predecessors, (186), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-10 23:19:01,792 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 118 states to 118 states and 186 transitions. [2024-11-10 23:19:01,792 INFO L240 hiAutomatonCegarLoop]: Abstraction has 118 states and 186 transitions. [2024-11-10 23:19:01,795 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-10 23:19:01,796 INFO L425 stractBuchiCegarLoop]: Abstraction has 118 states and 186 transitions. [2024-11-10 23:19:01,796 INFO L332 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-11-10 23:19:01,796 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 118 states and 186 transitions. [2024-11-10 23:19:01,797 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 72 [2024-11-10 23:19:01,797 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-10 23:19:01,797 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-10 23:19:01,798 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-10 23:19:01,798 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-10 23:19:01,799 INFO L745 eck$LassoCheckResult]: Stem: 1361#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 1292#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 1275#L490 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1276#L212-1 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 1343#L137-1 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 1344#L143-1 ~b0_req_up~0 := 0; 1332#L145-1 assume true;assume { :end_inline_update_b0 } true; 1333#L219-1 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 1341#L152-1 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 1342#L158-1 ~b1_req_up~0 := 0; 1301#L160-1 assume true;assume { :end_inline_update_b1 } true; 1302#L226-1 assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true; 1310#L167-1 assume !(~d0_val~0 != ~d0_val_t~0); 1357#L173-1 ~d0_req_up~0 := 0; 1358#L175-1 assume true;assume { :end_inline_update_d0 } true; 1328#L233-1 assume !(1 == ~d1_req_up~0); 1330#L240-1 assume !(1 == ~z_req_up~0); 1313#L248-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1273#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 1274#L261 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1346#L321-1 assume !(0 == ~b0_ev~0); 1284#L326-1 assume !(0 == ~b1_ev~0); 1285#L331-1 assume !(0 == ~d0_ev~0); 1253#L336-1 assume !(0 == ~d1_ev~0); 1254#L341-1 assume 0 == ~z_ev~0;~z_ev~0 := 1; 1363#L347-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 1362#L107-1 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 1296#L121-1 assume true;is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 1352#L130-1 assume true;activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 1351#L390-1 assume !(0 != activate_threads_~tmp~1#1); 1282#L396-1 assume true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1283#L354-1 assume !(1 == ~b0_ev~0); 1309#L359-1 assume !(1 == ~b1_ev~0); 1307#L364-1 assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 1308#L369-1 assume !(1 == ~d1_ev~0); 1311#L374-1 assume !(1 == ~z_ev~0); 1255#L380-1 assume true;assume { :end_inline_reset_delta_events } true; 1256#L432 [2024-11-10 23:19:01,799 INFO L747 eck$LassoCheckResult]: Loop: 1256#L432 assume true; 1340#L432-1 assume !false;assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 1252#L285 assume true; 1315#L285-1 assume !false;assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 1316#L268-1 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 1267#L270-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 1268#L276-1 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1306#L290 assume !(0 != eval_~tmp___0~0#1); 1360#L293 assume true; 1354#L314 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1339#L212 assume !(1 == ~b0_req_up~0); 1323#L219 assume !(1 == ~b1_req_up~0); 1262#L226 assume !(1 == ~d0_req_up~0); 1249#L233 assume !(1 == ~d1_req_up~0); 1288#L240 assume !(1 == ~z_req_up~0); 1290#L248 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1331#L321 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 1297#L326 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 1260#L331 assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 1261#L336 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 1345#L341 assume 0 == ~z_ev~0;~z_ev~0 := 1; 1347#L347 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 1359#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 1279#L121 assume true;is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 1291#L130 assume true;activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 1321#L390 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 1348#L396 assume true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1318#L354 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 1319#L359 assume 1 == ~b1_ev~0;~b1_ev~0 := 2; 1349#L364 assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 1303#L369 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 1304#L374 assume 1 == ~z_ev~0;~z_ev~0 := 2; 1338#L380 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 1281#L268 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 1257#L270 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 1246#L276 assume true;stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1; 1247#L407 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1266#L409 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1355#L415 assume true;start_simulation_#t~ret8#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1; 1336#L449 assume !(0 != start_simulation_~tmp~3#1); 1256#L432 [2024-11-10 23:19:01,801 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-10 23:19:01,801 INFO L85 PathProgramCache]: Analyzing trace with hash 1140811823, now seen corresponding path program 1 times [2024-11-10 23:19:01,802 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-10 23:19:01,802 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1862856762] [2024-11-10 23:19:01,802 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-10 23:19:01,802 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-10 23:19:01,813 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-10 23:19:01,870 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-10 23:19:01,870 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-10 23:19:01,870 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1862856762] [2024-11-10 23:19:01,870 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1862856762] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-10 23:19:01,870 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-10 23:19:01,871 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-10 23:19:01,871 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1335887115] [2024-11-10 23:19:01,871 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-10 23:19:01,871 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-10 23:19:01,871 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-10 23:19:01,872 INFO L85 PathProgramCache]: Analyzing trace with hash -1332115255, now seen corresponding path program 5 times [2024-11-10 23:19:01,872 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-10 23:19:01,872 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1986972865] [2024-11-10 23:19:01,872 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-10 23:19:01,872 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-10 23:19:01,882 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-10 23:19:01,925 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-10 23:19:01,925 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-10 23:19:01,925 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1986972865] [2024-11-10 23:19:01,925 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1986972865] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-10 23:19:01,925 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-10 23:19:01,927 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-10 23:19:01,927 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1477435006] [2024-11-10 23:19:01,927 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-10 23:19:01,928 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-10 23:19:01,928 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-10 23:19:01,928 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-10 23:19:01,928 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-10 23:19:01,928 INFO L87 Difference]: Start difference. First operand 118 states and 186 transitions. cyclomatic complexity: 69 Second operand has 4 states, 4 states have (on average 9.25) internal successors, (37), 4 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-10 23:19:01,964 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-10 23:19:01,964 INFO L93 Difference]: Finished difference Result 118 states and 185 transitions. [2024-11-10 23:19:01,964 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 118 states and 185 transitions. [2024-11-10 23:19:01,967 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 72 [2024-11-10 23:19:01,967 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 118 states to 118 states and 185 transitions. [2024-11-10 23:19:01,968 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 118 [2024-11-10 23:19:01,968 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 118 [2024-11-10 23:19:01,969 INFO L73 IsDeterministic]: Start isDeterministic. Operand 118 states and 185 transitions. [2024-11-10 23:19:01,970 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-10 23:19:01,970 INFO L218 hiAutomatonCegarLoop]: Abstraction has 118 states and 185 transitions. [2024-11-10 23:19:01,970 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 118 states and 185 transitions. [2024-11-10 23:19:01,974 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 118 to 118. [2024-11-10 23:19:01,974 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 118 states, 118 states have (on average 1.5677966101694916) internal successors, (185), 117 states have internal predecessors, (185), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-10 23:19:01,975 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 118 states to 118 states and 185 transitions. [2024-11-10 23:19:01,975 INFO L240 hiAutomatonCegarLoop]: Abstraction has 118 states and 185 transitions. [2024-11-10 23:19:01,977 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-10 23:19:01,978 INFO L425 stractBuchiCegarLoop]: Abstraction has 118 states and 185 transitions. [2024-11-10 23:19:01,978 INFO L332 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-11-10 23:19:01,978 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 118 states and 185 transitions. [2024-11-10 23:19:01,979 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 72 [2024-11-10 23:19:01,979 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-10 23:19:01,979 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-10 23:19:01,980 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-10 23:19:01,980 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-10 23:19:01,982 INFO L745 eck$LassoCheckResult]: Stem: 1609#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 1540#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 1523#L490 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1524#L212-1 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 1591#L137-1 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 1592#L143-1 ~b0_req_up~0 := 0; 1580#L145-1 assume true;assume { :end_inline_update_b0 } true; 1581#L219-1 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 1589#L152-1 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 1590#L158-1 ~b1_req_up~0 := 0; 1549#L160-1 assume true;assume { :end_inline_update_b1 } true; 1550#L226-1 assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true; 1558#L167-1 assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0; 1605#L173-1 ~d0_req_up~0 := 0; 1606#L175-1 assume true;assume { :end_inline_update_d0 } true; 1576#L233-1 assume !(1 == ~d1_req_up~0); 1578#L240-1 assume !(1 == ~z_req_up~0); 1561#L248-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1521#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 1522#L261 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1594#L321-1 assume !(0 == ~b0_ev~0); 1532#L326-1 assume !(0 == ~b1_ev~0); 1533#L331-1 assume !(0 == ~d0_ev~0); 1501#L336-1 assume !(0 == ~d1_ev~0); 1502#L341-1 assume 0 == ~z_ev~0;~z_ev~0 := 1; 1611#L347-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 1610#L107-1 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 1544#L121-1 assume true;is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 1600#L130-1 assume true;activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 1599#L390-1 assume !(0 != activate_threads_~tmp~1#1); 1530#L396-1 assume true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1531#L354-1 assume !(1 == ~b0_ev~0); 1557#L359-1 assume !(1 == ~b1_ev~0); 1555#L364-1 assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 1556#L369-1 assume !(1 == ~d1_ev~0); 1559#L374-1 assume !(1 == ~z_ev~0); 1503#L380-1 assume true;assume { :end_inline_reset_delta_events } true; 1504#L432 [2024-11-10 23:19:01,983 INFO L747 eck$LassoCheckResult]: Loop: 1504#L432 assume true; 1588#L432-1 assume !false;assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 1500#L285 assume true; 1563#L285-1 assume !false;assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 1564#L268-1 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 1515#L270-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 1516#L276-1 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1554#L290 assume !(0 != eval_~tmp___0~0#1); 1608#L293 assume true; 1602#L314 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1587#L212 assume !(1 == ~b0_req_up~0); 1571#L219 assume !(1 == ~b1_req_up~0); 1510#L226 assume !(1 == ~d0_req_up~0); 1497#L233 assume !(1 == ~d1_req_up~0); 1536#L240 assume !(1 == ~z_req_up~0); 1538#L248 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1579#L321 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 1545#L326 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 1508#L331 assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 1509#L336 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 1593#L341 assume 0 == ~z_ev~0;~z_ev~0 := 1; 1595#L347 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 1607#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 1527#L121 assume true;is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 1539#L130 assume true;activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 1569#L390 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 1596#L396 assume true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1566#L354 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 1567#L359 assume 1 == ~b1_ev~0;~b1_ev~0 := 2; 1597#L364 assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 1551#L369 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 1552#L374 assume 1 == ~z_ev~0;~z_ev~0 := 2; 1586#L380 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 1529#L268 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 1505#L270 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 1494#L276 assume true;stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1; 1495#L407 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1514#L409 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1603#L415 assume true;start_simulation_#t~ret8#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1; 1584#L449 assume !(0 != start_simulation_~tmp~3#1); 1504#L432 [2024-11-10 23:19:01,983 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-10 23:19:01,983 INFO L85 PathProgramCache]: Analyzing trace with hash -1076946130, now seen corresponding path program 1 times [2024-11-10 23:19:01,983 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-10 23:19:01,984 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1192112322] [2024-11-10 23:19:01,984 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-10 23:19:01,984 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-10 23:19:02,006 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-10 23:19:02,038 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-10 23:19:02,039 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-10 23:19:02,039 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1192112322] [2024-11-10 23:19:02,039 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1192112322] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-10 23:19:02,039 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-10 23:19:02,039 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-10 23:19:02,039 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2036937340] [2024-11-10 23:19:02,039 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-10 23:19:02,040 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-10 23:19:02,040 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-10 23:19:02,040 INFO L85 PathProgramCache]: Analyzing trace with hash -1332115255, now seen corresponding path program 6 times [2024-11-10 23:19:02,040 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-10 23:19:02,040 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1354219149] [2024-11-10 23:19:02,040 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-10 23:19:02,041 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-10 23:19:02,047 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-10 23:19:02,094 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-10 23:19:02,094 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-10 23:19:02,095 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1354219149] [2024-11-10 23:19:02,095 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1354219149] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-10 23:19:02,095 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-10 23:19:02,095 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-10 23:19:02,095 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1778295700] [2024-11-10 23:19:02,095 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-10 23:19:02,095 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-10 23:19:02,096 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-10 23:19:02,096 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-10 23:19:02,096 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-10 23:19:02,096 INFO L87 Difference]: Start difference. First operand 118 states and 185 transitions. cyclomatic complexity: 68 Second operand has 3 states, 3 states have (on average 12.333333333333334) internal successors, (37), 3 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-10 23:19:02,110 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-10 23:19:02,110 INFO L93 Difference]: Finished difference Result 118 states and 184 transitions. [2024-11-10 23:19:02,110 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 118 states and 184 transitions. [2024-11-10 23:19:02,112 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 72 [2024-11-10 23:19:02,113 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 118 states to 118 states and 184 transitions. [2024-11-10 23:19:02,113 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 118 [2024-11-10 23:19:02,113 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 118 [2024-11-10 23:19:02,113 INFO L73 IsDeterministic]: Start isDeterministic. Operand 118 states and 184 transitions. [2024-11-10 23:19:02,114 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-10 23:19:02,114 INFO L218 hiAutomatonCegarLoop]: Abstraction has 118 states and 184 transitions. [2024-11-10 23:19:02,114 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 118 states and 184 transitions. [2024-11-10 23:19:02,121 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 118 to 118. [2024-11-10 23:19:02,122 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 118 states, 118 states have (on average 1.5593220338983051) internal successors, (184), 117 states have internal predecessors, (184), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-10 23:19:02,122 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 118 states to 118 states and 184 transitions. [2024-11-10 23:19:02,122 INFO L240 hiAutomatonCegarLoop]: Abstraction has 118 states and 184 transitions. [2024-11-10 23:19:02,123 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-10 23:19:02,124 INFO L425 stractBuchiCegarLoop]: Abstraction has 118 states and 184 transitions. [2024-11-10 23:19:02,126 INFO L332 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-11-10 23:19:02,126 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 118 states and 184 transitions. [2024-11-10 23:19:02,127 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 72 [2024-11-10 23:19:02,127 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-10 23:19:02,127 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-10 23:19:02,128 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-10 23:19:02,128 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-10 23:19:02,129 INFO L745 eck$LassoCheckResult]: Stem: 1854#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 1785#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 1768#L490 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1769#L212-1 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 1835#L137-1 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 1836#L143-1 ~b0_req_up~0 := 0; 1824#L145-1 assume true;assume { :end_inline_update_b0 } true; 1825#L219-1 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 1833#L152-1 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 1834#L158-1 ~b1_req_up~0 := 0; 1794#L160-1 assume true;assume { :end_inline_update_b1 } true; 1795#L226-1 assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true; 1803#L167-1 assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0; 1850#L173-1 ~d0_req_up~0 := 0; 1851#L175-1 assume true;assume { :end_inline_update_d0 } true; 1821#L233-1 assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true; 1822#L182-1 assume !(~d1_val~0 != ~d1_val_t~0); 1846#L188-1 ~d1_req_up~0 := 0; 1842#L190-1 assume true;assume { :end_inline_update_d1 } true; 1843#L240-1 assume !(1 == ~z_req_up~0); 1806#L248-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1766#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 1767#L261 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1838#L321-1 assume !(0 == ~b0_ev~0); 1777#L326-1 assume !(0 == ~b1_ev~0); 1778#L331-1 assume !(0 == ~d0_ev~0); 1746#L336-1 assume !(0 == ~d1_ev~0); 1747#L341-1 assume 0 == ~z_ev~0;~z_ev~0 := 1; 1856#L347-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 1855#L107-1 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 1789#L121-1 assume true;is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 1845#L130-1 assume true;activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 1844#L390-1 assume !(0 != activate_threads_~tmp~1#1); 1775#L396-1 assume true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1776#L354-1 assume !(1 == ~b0_ev~0); 1802#L359-1 assume !(1 == ~b1_ev~0); 1800#L364-1 assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 1801#L369-1 assume !(1 == ~d1_ev~0); 1804#L374-1 assume !(1 == ~z_ev~0); 1748#L380-1 assume true;assume { :end_inline_reset_delta_events } true; 1749#L432 [2024-11-10 23:19:02,129 INFO L747 eck$LassoCheckResult]: Loop: 1749#L432 assume true; 1832#L432-1 assume !false;assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 1745#L285 assume true; 1808#L285-1 assume !false;assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 1809#L268-1 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 1760#L270-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 1761#L276-1 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1799#L290 assume !(0 != eval_~tmp___0~0#1); 1853#L293 assume true; 1847#L314 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1831#L212 assume !(1 == ~b0_req_up~0); 1816#L219 assume !(1 == ~b1_req_up~0); 1755#L226 assume !(1 == ~d0_req_up~0); 1742#L233 assume !(1 == ~d1_req_up~0); 1781#L240 assume !(1 == ~z_req_up~0); 1783#L248 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1823#L321 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 1790#L326 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 1753#L331 assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 1754#L336 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 1837#L341 assume 0 == ~z_ev~0;~z_ev~0 := 1; 1839#L347 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 1852#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 1772#L121 assume true;is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 1784#L130 assume true;activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 1814#L390 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 1840#L396 assume true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1811#L354 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 1812#L359 assume 1 == ~b1_ev~0;~b1_ev~0 := 2; 1841#L364 assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 1796#L369 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 1797#L374 assume 1 == ~z_ev~0;~z_ev~0 := 2; 1830#L380 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 1774#L268 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 1750#L270 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 1739#L276 assume true;stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1; 1740#L407 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1759#L409 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1848#L415 assume true;start_simulation_#t~ret8#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1; 1828#L449 assume !(0 != start_simulation_~tmp~3#1); 1749#L432 [2024-11-10 23:19:02,129 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-10 23:19:02,129 INFO L85 PathProgramCache]: Analyzing trace with hash -559776271, now seen corresponding path program 1 times [2024-11-10 23:19:02,130 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-10 23:19:02,130 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [616298950] [2024-11-10 23:19:02,130 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-10 23:19:02,130 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-10 23:19:02,147 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-10 23:19:02,198 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-10 23:19:02,198 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-10 23:19:02,199 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [616298950] [2024-11-10 23:19:02,202 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [616298950] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-10 23:19:02,202 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-10 23:19:02,202 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-10 23:19:02,202 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1225310438] [2024-11-10 23:19:02,202 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-10 23:19:02,202 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-10 23:19:02,203 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-10 23:19:02,203 INFO L85 PathProgramCache]: Analyzing trace with hash -1332115255, now seen corresponding path program 7 times [2024-11-10 23:19:02,203 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-10 23:19:02,203 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1978486832] [2024-11-10 23:19:02,203 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-10 23:19:02,203 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-10 23:19:02,213 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-10 23:19:02,248 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-10 23:19:02,249 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-10 23:19:02,249 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1978486832] [2024-11-10 23:19:02,250 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1978486832] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-10 23:19:02,250 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-10 23:19:02,250 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-10 23:19:02,252 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1375892583] [2024-11-10 23:19:02,253 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-10 23:19:02,253 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-10 23:19:02,253 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-10 23:19:02,254 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-10 23:19:02,254 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-10 23:19:02,254 INFO L87 Difference]: Start difference. First operand 118 states and 184 transitions. cyclomatic complexity: 67 Second operand has 5 states, 5 states have (on average 8.0) internal successors, (40), 5 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-10 23:19:02,289 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-10 23:19:02,289 INFO L93 Difference]: Finished difference Result 123 states and 189 transitions. [2024-11-10 23:19:02,290 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 123 states and 189 transitions. [2024-11-10 23:19:02,291 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 77 [2024-11-10 23:19:02,291 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 123 states to 123 states and 189 transitions. [2024-11-10 23:19:02,292 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 123 [2024-11-10 23:19:02,292 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 123 [2024-11-10 23:19:02,292 INFO L73 IsDeterministic]: Start isDeterministic. Operand 123 states and 189 transitions. [2024-11-10 23:19:02,292 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-10 23:19:02,292 INFO L218 hiAutomatonCegarLoop]: Abstraction has 123 states and 189 transitions. [2024-11-10 23:19:02,293 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 123 states and 189 transitions. [2024-11-10 23:19:02,295 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 123 to 121. [2024-11-10 23:19:02,295 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 121 states, 121 states have (on average 1.5454545454545454) internal successors, (187), 120 states have internal predecessors, (187), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-10 23:19:02,296 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 121 states to 121 states and 187 transitions. [2024-11-10 23:19:02,296 INFO L240 hiAutomatonCegarLoop]: Abstraction has 121 states and 187 transitions. [2024-11-10 23:19:02,300 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-10 23:19:02,300 INFO L425 stractBuchiCegarLoop]: Abstraction has 121 states and 187 transitions. [2024-11-10 23:19:02,301 INFO L332 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-11-10 23:19:02,301 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 121 states and 187 transitions. [2024-11-10 23:19:02,301 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 75 [2024-11-10 23:19:02,302 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-10 23:19:02,302 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-10 23:19:02,302 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-10 23:19:02,302 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-10 23:19:02,303 INFO L745 eck$LassoCheckResult]: Stem: 2106#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 2036#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 2019#L490 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2020#L212-1 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 2087#L137-1 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 2088#L143-1 ~b0_req_up~0 := 0; 2075#L145-1 assume true;assume { :end_inline_update_b0 } true; 2076#L219-1 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 2085#L152-1 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 2086#L158-1 ~b1_req_up~0 := 0; 2045#L160-1 assume true;assume { :end_inline_update_b1 } true; 2046#L226-1 assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true; 2054#L167-1 assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0; 2102#L173-1 ~d0_req_up~0 := 0; 2103#L175-1 assume true;assume { :end_inline_update_d0 } true; 2072#L233-1 assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true; 2073#L182-1 assume !(~d1_val~0 != ~d1_val_t~0); 2098#L188-1 ~d1_req_up~0 := 0; 2094#L190-1 assume true;assume { :end_inline_update_d1 } true; 2095#L240-1 assume !(1 == ~z_req_up~0); 2057#L248-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2017#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 2018#L261 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2090#L321-1 assume !(0 == ~b0_ev~0); 2028#L326-1 assume !(0 == ~b1_ev~0); 2029#L331-1 assume !(0 == ~d0_ev~0); 1997#L336-1 assume !(0 == ~d1_ev~0); 1998#L341-1 assume 0 == ~z_ev~0;~z_ev~0 := 1; 2108#L347-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 2107#L107-1 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 2040#L121-1 assume true;is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 2097#L130-1 assume true;activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 2096#L390-1 assume !(0 != activate_threads_~tmp~1#1); 2026#L396-1 assume true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2027#L354-1 assume !(1 == ~b0_ev~0); 2053#L359-1 assume !(1 == ~b1_ev~0); 2051#L364-1 assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 2052#L369-1 assume !(1 == ~d1_ev~0); 2055#L374-1 assume !(1 == ~z_ev~0); 1999#L380-1 assume true;assume { :end_inline_reset_delta_events } true; 2000#L432 [2024-11-10 23:19:02,303 INFO L747 eck$LassoCheckResult]: Loop: 2000#L432 assume true; 2084#L432-1 assume !false;assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 1996#L285 assume true; 2059#L285-1 assume !false;assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 2060#L268-1 assume !(0 == ~comp_m1_st~0);exists_runnable_thread_~__retres1~1#1 := 0; 2079#L270-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 2110#L276-1 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2109#L290 assume !(0 != eval_~tmp___0~0#1); 2105#L293 assume true; 2099#L314 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2083#L212 assume !(1 == ~b0_req_up~0); 2067#L219 assume !(1 == ~b1_req_up~0); 2006#L226 assume !(1 == ~d0_req_up~0); 1993#L233 assume !(1 == ~d1_req_up~0); 2032#L240 assume !(1 == ~z_req_up~0); 2034#L248 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2074#L321 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 2041#L326 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 2004#L331 assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 2005#L336 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 2089#L341 assume 0 == ~z_ev~0;~z_ev~0 := 1; 2091#L347 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 2104#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 2023#L121 assume true;is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 2035#L130 assume true;activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 2065#L390 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 2092#L396 assume true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2062#L354 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 2063#L359 assume 1 == ~b1_ev~0;~b1_ev~0 := 2; 2093#L364 assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 2047#L369 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 2048#L374 assume 1 == ~z_ev~0;~z_ev~0 := 2; 2082#L380 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 2025#L268 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 2001#L270 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 1990#L276 assume true;stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1; 1991#L407 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2010#L409 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2100#L415 assume true;start_simulation_#t~ret8#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1; 2080#L449 assume !(0 != start_simulation_~tmp~3#1); 2000#L432 [2024-11-10 23:19:02,305 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-10 23:19:02,305 INFO L85 PathProgramCache]: Analyzing trace with hash -559776271, now seen corresponding path program 2 times [2024-11-10 23:19:02,305 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-10 23:19:02,306 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2105777625] [2024-11-10 23:19:02,306 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-10 23:19:02,306 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-10 23:19:02,316 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-10 23:19:02,375 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-10 23:19:02,375 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-10 23:19:02,375 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2105777625] [2024-11-10 23:19:02,375 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2105777625] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-10 23:19:02,375 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-10 23:19:02,375 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-10 23:19:02,376 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1459192897] [2024-11-10 23:19:02,376 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-10 23:19:02,376 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-10 23:19:02,376 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-10 23:19:02,376 INFO L85 PathProgramCache]: Analyzing trace with hash -1726482041, now seen corresponding path program 1 times [2024-11-10 23:19:02,376 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-10 23:19:02,377 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1361177662] [2024-11-10 23:19:02,377 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-10 23:19:02,377 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-10 23:19:02,392 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-10 23:19:02,392 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-10 23:19:02,399 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-10 23:19:02,429 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-10 23:19:02,835 INFO L204 LassoAnalysis]: Preferences: [2024-11-10 23:19:02,836 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-11-10 23:19:02,836 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-11-10 23:19:02,836 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-11-10 23:19:02,836 INFO L128 ssoRankerPreferences]: Use exernal solver: true [2024-11-10 23:19:02,836 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-10 23:19:02,836 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-11-10 23:19:02,836 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-11-10 23:19:02,837 INFO L132 ssoRankerPreferences]: Filename of dumped script: bist_cell.cil.c_Iteration9_Loop [2024-11-10 23:19:02,837 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-11-10 23:19:02,837 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-11-10 23:19:02,858 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:02,865 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:02,873 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:02,882 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:02,885 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:02,887 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:02,890 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:02,892 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:02,898 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:02,909 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:02,912 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:02,917 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:02,920 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:02,923 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:02,925 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:02,928 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:02,931 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:02,933 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:02,935 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:02,942 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:02,944 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:02,947 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:02,949 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:02,951 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:02,957 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:02,959 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:02,964 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:03,171 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-11-10 23:19:03,172 INFO L365 LassoAnalysis]: Checking for nontermination... [2024-11-10 23:19:03,173 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-10 23:19:03,173 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-10 23:19:03,175 INFO L229 MonitoredProcess]: Starting monitored process 2 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-10 23:19:03,176 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2024-11-10 23:19:03,177 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-10 23:19:03,177 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-10 23:19:03,194 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-10 23:19:03,195 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_stop_simulation_~__retres2~0#1=0} Honda state: {ULTIMATE.start_stop_simulation_~__retres2~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-10 23:19:03,212 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Forceful destruction successful, exit code 0 [2024-11-10 23:19:03,213 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-10 23:19:03,213 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-10 23:19:03,215 INFO L229 MonitoredProcess]: Starting monitored process 3 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-10 23:19:03,217 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2024-11-10 23:19:03,218 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-10 23:19:03,218 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-10 23:19:03,255 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Ended with exit code 0 [2024-11-10 23:19:03,255 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-10 23:19:03,255 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-10 23:19:03,257 INFO L229 MonitoredProcess]: Starting monitored process 4 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-10 23:19:03,263 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2024-11-10 23:19:03,264 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2024-11-10 23:19:03,264 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-10 23:19:03,290 INFO L405 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2024-11-10 23:19:03,320 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Ended with exit code 0 [2024-11-10 23:19:03,321 INFO L204 LassoAnalysis]: Preferences: [2024-11-10 23:19:03,321 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-11-10 23:19:03,321 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-11-10 23:19:03,321 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-11-10 23:19:03,321 INFO L128 ssoRankerPreferences]: Use exernal solver: false [2024-11-10 23:19:03,321 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-10 23:19:03,321 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-11-10 23:19:03,321 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-11-10 23:19:03,322 INFO L132 ssoRankerPreferences]: Filename of dumped script: bist_cell.cil.c_Iteration9_Loop [2024-11-10 23:19:03,322 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-11-10 23:19:03,322 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-11-10 23:19:03,324 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:03,342 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:03,345 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:03,352 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:03,372 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:03,379 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:03,382 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:03,387 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:03,390 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:03,396 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:03,402 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:03,407 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:03,410 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:03,413 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:03,415 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:03,418 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:03,421 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:03,424 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:03,427 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:03,430 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:03,437 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:03,441 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:03,444 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:03,446 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:03,448 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:03,451 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:03,458 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:03,633 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-11-10 23:19:03,639 INFO L451 LassoAnalysis]: Using template 'affine'. [2024-11-10 23:19:03,640 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-10 23:19:03,640 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-10 23:19:03,642 INFO L229 MonitoredProcess]: Starting monitored process 5 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-10 23:19:03,643 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2024-11-10 23:19:03,644 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-10 23:19:03,659 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-10 23:19:03,659 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-10 23:19:03,660 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-10 23:19:03,660 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-10 23:19:03,660 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-10 23:19:03,662 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-10 23:19:03,663 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-10 23:19:03,665 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-10 23:19:03,681 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Ended with exit code 0 [2024-11-10 23:19:03,686 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-10 23:19:03,687 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-10 23:19:03,689 INFO L229 MonitoredProcess]: Starting monitored process 6 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-10 23:19:03,691 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2024-11-10 23:19:03,693 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-10 23:19:03,706 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-10 23:19:03,706 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-10 23:19:03,707 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-10 23:19:03,707 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-10 23:19:03,707 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-10 23:19:03,709 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-10 23:19:03,709 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-10 23:19:03,710 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-10 23:19:03,729 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Ended with exit code 0 [2024-11-10 23:19:03,730 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-10 23:19:03,730 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-10 23:19:03,732 INFO L229 MonitoredProcess]: Starting monitored process 7 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-10 23:19:03,734 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2024-11-10 23:19:03,734 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-10 23:19:03,747 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-10 23:19:03,747 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-10 23:19:03,747 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-10 23:19:03,747 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-10 23:19:03,747 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-10 23:19:03,748 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-10 23:19:03,748 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-10 23:19:03,750 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-10 23:19:03,765 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Ended with exit code 0 [2024-11-10 23:19:03,765 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-10 23:19:03,765 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-10 23:19:03,767 INFO L229 MonitoredProcess]: Starting monitored process 8 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-10 23:19:03,768 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2024-11-10 23:19:03,770 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-10 23:19:03,782 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-10 23:19:03,783 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-10 23:19:03,783 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-10 23:19:03,783 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-10 23:19:03,783 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-10 23:19:03,784 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-10 23:19:03,784 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-10 23:19:03,787 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2024-11-10 23:19:03,793 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2024-11-10 23:19:03,794 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2024-11-10 23:19:03,795 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-10 23:19:03,795 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-10 23:19:03,814 INFO L229 MonitoredProcess]: Starting monitored process 9 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-10 23:19:03,815 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2024-11-10 23:19:03,816 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2024-11-10 23:19:03,817 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2024-11-10 23:19:03,817 INFO L474 LassoAnalysis]: Proved termination. [2024-11-10 23:19:03,817 INFO L476 LassoAnalysis]: Termination argument consisting of: Ranking function f(~z_ev~0) = -1*~z_ev~0 + 1 Supporting invariants [] [2024-11-10 23:19:03,832 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Ended with exit code 0 [2024-11-10 23:19:03,834 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2024-11-10 23:19:03,862 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-10 23:19:03,901 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-10 23:19:03,903 INFO L255 TraceCheckSpWp]: Trace formula consists of 179 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-11-10 23:19:03,905 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-10 23:19:04,007 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-10 23:19:04,008 INFO L255 TraceCheckSpWp]: Trace formula consists of 97 conjuncts, 4 conjuncts are in the unsatisfiable core [2024-11-10 23:19:04,009 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-10 23:19:04,131 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-10 23:19:04,136 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2024-11-10 23:19:04,138 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 121 states and 187 transitions. cyclomatic complexity: 67 Second operand has 5 states, 5 states have (on average 16.0) internal successors, (80), 5 states have internal predecessors, (80), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-10 23:19:04,212 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 121 states and 187 transitions. cyclomatic complexity: 67. Second operand has 5 states, 5 states have (on average 16.0) internal successors, (80), 5 states have internal predecessors, (80), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 277 states and 433 transitions. Complement of second has 5 states. [2024-11-10 23:19:04,214 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2024-11-10 23:19:04,214 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 16.0) internal successors, (80), 5 states have internal predecessors, (80), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-10 23:19:04,215 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 186 transitions. [2024-11-10 23:19:04,216 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 186 transitions. Stem has 40 letters. Loop has 40 letters. [2024-11-10 23:19:04,218 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-10 23:19:04,218 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 186 transitions. Stem has 80 letters. Loop has 40 letters. [2024-11-10 23:19:04,218 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-10 23:19:04,219 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 186 transitions. Stem has 40 letters. Loop has 80 letters. [2024-11-10 23:19:04,220 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-10 23:19:04,220 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 277 states and 433 transitions. [2024-11-10 23:19:04,223 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 150 [2024-11-10 23:19:04,224 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 277 states to 277 states and 433 transitions. [2024-11-10 23:19:04,225 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 197 [2024-11-10 23:19:04,225 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 200 [2024-11-10 23:19:04,225 INFO L73 IsDeterministic]: Start isDeterministic. Operand 277 states and 433 transitions. [2024-11-10 23:19:04,225 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-10 23:19:04,225 INFO L218 hiAutomatonCegarLoop]: Abstraction has 277 states and 433 transitions. [2024-11-10 23:19:04,226 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 277 states and 433 transitions. [2024-11-10 23:19:04,229 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 277 to 274. [2024-11-10 23:19:04,230 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 274 states, 274 states have (on average 1.562043795620438) internal successors, (428), 273 states have internal predecessors, (428), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-10 23:19:04,231 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 274 states to 274 states and 428 transitions. [2024-11-10 23:19:04,231 INFO L240 hiAutomatonCegarLoop]: Abstraction has 274 states and 428 transitions. [2024-11-10 23:19:04,231 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-10 23:19:04,231 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-10 23:19:04,232 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-10 23:19:04,232 INFO L87 Difference]: Start difference. First operand 274 states and 428 transitions. Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 4 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-10 23:19:04,262 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-10 23:19:04,262 INFO L93 Difference]: Finished difference Result 274 states and 427 transitions. [2024-11-10 23:19:04,262 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 274 states and 427 transitions. [2024-11-10 23:19:04,264 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 150 [2024-11-10 23:19:04,265 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 274 states to 274 states and 427 transitions. [2024-11-10 23:19:04,266 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 197 [2024-11-10 23:19:04,266 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 197 [2024-11-10 23:19:04,266 INFO L73 IsDeterministic]: Start isDeterministic. Operand 274 states and 427 transitions. [2024-11-10 23:19:04,266 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-10 23:19:04,266 INFO L218 hiAutomatonCegarLoop]: Abstraction has 274 states and 427 transitions. [2024-11-10 23:19:04,267 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 274 states and 427 transitions. [2024-11-10 23:19:04,282 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 274 to 274. [2024-11-10 23:19:04,288 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 274 states, 274 states have (on average 1.5583941605839415) internal successors, (427), 273 states have internal predecessors, (427), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-10 23:19:04,288 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 274 states to 274 states and 427 transitions. [2024-11-10 23:19:04,289 INFO L240 hiAutomatonCegarLoop]: Abstraction has 274 states and 427 transitions. [2024-11-10 23:19:04,289 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-10 23:19:04,289 INFO L425 stractBuchiCegarLoop]: Abstraction has 274 states and 427 transitions. [2024-11-10 23:19:04,289 INFO L332 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-11-10 23:19:04,290 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 274 states and 427 transitions. [2024-11-10 23:19:04,291 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 150 [2024-11-10 23:19:04,291 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-10 23:19:04,291 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-10 23:19:04,291 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-10 23:19:04,291 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-10 23:19:04,292 INFO L745 eck$LassoCheckResult]: Stem: 3405#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 3278#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 3249#L490 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3250#L212-1 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 3371#L137-1 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 3372#L143-1 ~b0_req_up~0 := 0; 3351#L145-1 assume true;assume { :end_inline_update_b0 } true; 3352#L219-1 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 3369#L152-1 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 3370#L158-1 ~b1_req_up~0 := 0; 3294#L160-1 assume true;assume { :end_inline_update_b1 } true; 3295#L226-1 assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true; 3307#L167-1 assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0; 3399#L173-1 ~d0_req_up~0 := 0; 3400#L175-1 assume true;assume { :end_inline_update_d0 } true; 3345#L233-1 assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true; 3346#L182-1 assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0; 3395#L188-1 ~d1_req_up~0 := 0; 3388#L190-1 assume true;assume { :end_inline_update_d1 } true; 3389#L240-1 assume !(1 == ~z_req_up~0); 3310#L248-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3247#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 3248#L261 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3375#L321-1 assume !(0 == ~b0_ev~0); 3268#L326-1 assume !(0 == ~b1_ev~0); 3269#L331-1 assume !(0 == ~d0_ev~0); 3213#L336-1 assume !(0 == ~d1_ev~0); 3214#L341-1 assume 0 == ~z_ev~0;~z_ev~0 := 1; 3407#L347-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 3406#L107-1 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 3287#L121-1 assume true;is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 3392#L130-1 assume true;activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 3390#L390-1 assume !(0 != activate_threads_~tmp~1#1); 3262#L396-1 assume true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3263#L354-1 assume !(1 == ~b0_ev~0); 3306#L359-1 assume !(1 == ~b1_ev~0); 3304#L364-1 assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 3305#L369-1 assume !(1 == ~d1_ev~0); 3308#L374-1 assume !(1 == ~z_ev~0); 3215#L380-1 assume true;assume { :end_inline_reset_delta_events } true; 3216#L432 assume true; 3365#L432-1 [2024-11-10 23:19:04,292 INFO L747 eck$LassoCheckResult]: Loop: 3365#L432-1 assume !false;assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 3209#L285 assume true; 3313#L285-1 assume !false;assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 3314#L268-1 assume !(0 == ~comp_m1_st~0);exists_runnable_thread_~__retres1~1#1 := 0; 3357#L270-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 3415#L276-1 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3414#L290 assume !(0 != eval_~tmp___0~0#1); 3403#L293 assume true; 3393#L314 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3363#L212 assume !(1 == ~b0_req_up~0); 3330#L219 assume !(1 == ~b1_req_up~0); 3382#L226 assume !(1 == ~d0_req_up~0); 3339#L233 assume !(1 == ~d1_req_up~0); 3270#L240 assume !(1 == ~z_req_up~0); 3272#L248 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3418#L321 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 3283#L326 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 3284#L331 assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 3417#L336 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 3376#L341 assume !(0 == ~z_ev~0); 3377#L347 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 3401#L107 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 3255#L121 assume true;is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 3276#L130 assume true;activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 3383#L390 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 3384#L396 assume true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3433#L354 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 3385#L359 assume 1 == ~b1_ev~0;~b1_ev~0 := 2; 3386#L364 assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 3432#L369 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 3410#L374 assume !(1 == ~z_ev~0); 3361#L380 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 3260#L268 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 3217#L270 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 3199#L276 assume true;stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1; 3200#L407 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3233#L409 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3396#L415 assume true;start_simulation_#t~ret8#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1; 3353#L449 assume !(0 != start_simulation_~tmp~3#1); 3354#L432 assume true; 3365#L432-1 [2024-11-10 23:19:04,296 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-10 23:19:04,297 INFO L85 PathProgramCache]: Analyzing trace with hash 1904014293, now seen corresponding path program 1 times [2024-11-10 23:19:04,297 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-10 23:19:04,297 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1658007712] [2024-11-10 23:19:04,297 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-10 23:19:04,297 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-10 23:19:04,301 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Ended with exit code 0 [2024-11-10 23:19:04,306 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-10 23:19:04,326 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-10 23:19:04,326 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-10 23:19:04,326 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1658007712] [2024-11-10 23:19:04,326 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1658007712] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-10 23:19:04,326 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-10 23:19:04,327 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-10 23:19:04,327 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2054447869] [2024-11-10 23:19:04,327 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-10 23:19:04,327 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-10 23:19:04,327 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-10 23:19:04,328 INFO L85 PathProgramCache]: Analyzing trace with hash 1401456347, now seen corresponding path program 1 times [2024-11-10 23:19:04,328 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-10 23:19:04,328 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [444743495] [2024-11-10 23:19:04,328 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-10 23:19:04,328 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-10 23:19:04,334 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-10 23:19:04,335 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-10 23:19:04,338 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-10 23:19:04,342 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-10 23:19:04,613 INFO L204 LassoAnalysis]: Preferences: [2024-11-10 23:19:04,613 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-11-10 23:19:04,613 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-11-10 23:19:04,613 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-11-10 23:19:04,613 INFO L128 ssoRankerPreferences]: Use exernal solver: true [2024-11-10 23:19:04,613 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-10 23:19:04,613 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-11-10 23:19:04,613 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-11-10 23:19:04,613 INFO L132 ssoRankerPreferences]: Filename of dumped script: bist_cell.cil.c_Iteration10_Loop [2024-11-10 23:19:04,614 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-11-10 23:19:04,614 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-11-10 23:19:04,615 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:04,622 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:04,626 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:04,628 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:04,631 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:04,633 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:04,636 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:04,639 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:04,641 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:04,644 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:04,649 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:04,652 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:04,654 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:04,656 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:04,658 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:04,659 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:04,662 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:04,667 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:04,669 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:04,674 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:04,676 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:04,678 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:04,682 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:04,686 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:04,688 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:04,692 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:04,694 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:04,865 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-11-10 23:19:04,865 INFO L365 LassoAnalysis]: Checking for nontermination... [2024-11-10 23:19:04,865 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-10 23:19:04,865 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-10 23:19:04,867 INFO L229 MonitoredProcess]: Starting monitored process 10 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-10 23:19:04,868 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Waiting until timeout for monitored process [2024-11-10 23:19:04,871 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-10 23:19:04,872 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-10 23:19:04,902 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Ended with exit code 0 [2024-11-10 23:19:04,903 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-10 23:19:04,903 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-10 23:19:04,904 INFO L229 MonitoredProcess]: Starting monitored process 11 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-10 23:19:04,905 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Waiting until timeout for monitored process [2024-11-10 23:19:04,906 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2024-11-10 23:19:04,906 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-10 23:19:04,918 INFO L405 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2024-11-10 23:19:04,930 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Forceful destruction successful, exit code 0 [2024-11-10 23:19:04,930 INFO L204 LassoAnalysis]: Preferences: [2024-11-10 23:19:04,931 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-11-10 23:19:04,931 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-11-10 23:19:04,931 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-11-10 23:19:04,931 INFO L128 ssoRankerPreferences]: Use exernal solver: false [2024-11-10 23:19:04,931 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-10 23:19:04,931 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-11-10 23:19:04,931 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-11-10 23:19:04,931 INFO L132 ssoRankerPreferences]: Filename of dumped script: bist_cell.cil.c_Iteration10_Loop [2024-11-10 23:19:04,931 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-11-10 23:19:04,931 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-11-10 23:19:04,933 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:04,936 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:04,941 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:04,946 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:04,948 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:04,952 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:04,956 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:04,960 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:04,962 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:04,964 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:04,967 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:04,969 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:04,971 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:04,973 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:04,975 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:04,982 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:04,984 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:04,989 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:04,991 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:04,992 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:04,997 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:04,999 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:05,001 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:05,005 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:05,007 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:05,012 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:05,016 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-10 23:19:05,184 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-11-10 23:19:05,184 INFO L451 LassoAnalysis]: Using template 'affine'. [2024-11-10 23:19:05,184 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-10 23:19:05,185 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-10 23:19:05,186 INFO L229 MonitoredProcess]: Starting monitored process 12 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-10 23:19:05,188 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Waiting until timeout for monitored process [2024-11-10 23:19:05,189 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-10 23:19:05,201 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-10 23:19:05,201 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-10 23:19:05,202 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-10 23:19:05,202 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-10 23:19:05,202 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-10 23:19:05,202 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-10 23:19:05,202 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-10 23:19:05,204 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-10 23:19:05,219 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Ended with exit code 0 [2024-11-10 23:19:05,219 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-10 23:19:05,220 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-10 23:19:05,222 INFO L229 MonitoredProcess]: Starting monitored process 13 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-10 23:19:05,223 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Waiting until timeout for monitored process [2024-11-10 23:19:05,224 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-10 23:19:05,236 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-10 23:19:05,236 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-10 23:19:05,237 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-10 23:19:05,237 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-10 23:19:05,237 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-10 23:19:05,238 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-10 23:19:05,238 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-10 23:19:05,241 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2024-11-10 23:19:05,243 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2024-11-10 23:19:05,243 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2024-11-10 23:19:05,243 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-10 23:19:05,244 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-10 23:19:05,245 INFO L229 MonitoredProcess]: Starting monitored process 14 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-10 23:19:05,247 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Waiting until timeout for monitored process [2024-11-10 23:19:05,247 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2024-11-10 23:19:05,247 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2024-11-10 23:19:05,248 INFO L474 LassoAnalysis]: Proved termination. [2024-11-10 23:19:05,248 INFO L476 LassoAnalysis]: Termination argument consisting of: Ranking function f(~d1_ev~0) = -1*~d1_ev~0 + 1 Supporting invariants [] [2024-11-10 23:19:05,260 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Forceful destruction successful, exit code 0 [2024-11-10 23:19:05,261 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2024-11-10 23:19:05,271 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-10 23:19:05,308 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-10 23:19:05,310 INFO L255 TraceCheckSpWp]: Trace formula consists of 183 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-11-10 23:19:05,311 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-10 23:19:05,395 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-10 23:19:05,396 INFO L255 TraceCheckSpWp]: Trace formula consists of 91 conjuncts, 4 conjuncts are in the unsatisfiable core [2024-11-10 23:19:05,397 INFO L278 TraceCheckSpWp]: Computing forward predicates... [2024-11-10 23:19:05,400 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Forceful destruction successful, exit code 0 [2024-11-10 23:19:05,522 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-10 23:19:05,523 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2024-11-10 23:19:05,523 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 274 states and 427 transitions. cyclomatic complexity: 156 Second operand has 5 states, 5 states have (on average 16.2) internal successors, (81), 5 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-10 23:19:05,576 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 274 states and 427 transitions. cyclomatic complexity: 156. Second operand has 5 states, 5 states have (on average 16.2) internal successors, (81), 5 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 743 states and 1167 transitions. Complement of second has 5 states. [2024-11-10 23:19:05,576 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2024-11-10 23:19:05,577 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 16.2) internal successors, (81), 5 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-10 23:19:05,577 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 188 transitions. [2024-11-10 23:19:05,577 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 188 transitions. Stem has 41 letters. Loop has 40 letters. [2024-11-10 23:19:05,578 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-10 23:19:05,578 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 188 transitions. Stem has 81 letters. Loop has 40 letters. [2024-11-10 23:19:05,578 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-10 23:19:05,578 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 188 transitions. Stem has 41 letters. Loop has 80 letters. [2024-11-10 23:19:05,579 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-10 23:19:05,579 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 743 states and 1167 transitions. [2024-11-10 23:19:05,584 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 300 [2024-11-10 23:19:05,588 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 743 states to 743 states and 1167 transitions. [2024-11-10 23:19:05,589 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 350 [2024-11-10 23:19:05,589 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 355 [2024-11-10 23:19:05,589 INFO L73 IsDeterministic]: Start isDeterministic. Operand 743 states and 1167 transitions. [2024-11-10 23:19:05,590 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-10 23:19:05,590 INFO L218 hiAutomatonCegarLoop]: Abstraction has 743 states and 1167 transitions. [2024-11-10 23:19:05,590 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 743 states and 1167 transitions. [2024-11-10 23:19:05,601 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 743 to 738. [2024-11-10 23:19:05,603 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 738 states, 738 states have (on average 1.5745257452574526) internal successors, (1162), 737 states have internal predecessors, (1162), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-10 23:19:05,605 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 738 states to 738 states and 1162 transitions. [2024-11-10 23:19:05,605 INFO L240 hiAutomatonCegarLoop]: Abstraction has 738 states and 1162 transitions. [2024-11-10 23:19:05,606 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-10 23:19:05,606 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-10 23:19:05,606 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-10 23:19:05,606 INFO L87 Difference]: Start difference. First operand 738 states and 1162 transitions. Second operand has 3 states, 3 states have (on average 13.666666666666666) internal successors, (41), 3 states have internal predecessors, (41), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-10 23:19:05,634 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-10 23:19:05,634 INFO L93 Difference]: Finished difference Result 918 states and 1407 transitions. [2024-11-10 23:19:05,634 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 918 states and 1407 transitions. [2024-11-10 23:19:05,641 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 380 [2024-11-10 23:19:05,646 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 918 states to 918 states and 1407 transitions. [2024-11-10 23:19:05,646 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 430 [2024-11-10 23:19:05,647 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 430 [2024-11-10 23:19:05,647 INFO L73 IsDeterministic]: Start isDeterministic. Operand 918 states and 1407 transitions. [2024-11-10 23:19:05,647 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-10 23:19:05,647 INFO L218 hiAutomatonCegarLoop]: Abstraction has 918 states and 1407 transitions. [2024-11-10 23:19:05,648 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 918 states and 1407 transitions. [2024-11-10 23:19:05,660 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 918 to 918. [2024-11-10 23:19:05,662 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 918 states, 918 states have (on average 1.5326797385620916) internal successors, (1407), 917 states have internal predecessors, (1407), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-10 23:19:05,666 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 918 states to 918 states and 1407 transitions. [2024-11-10 23:19:05,666 INFO L240 hiAutomatonCegarLoop]: Abstraction has 918 states and 1407 transitions. [2024-11-10 23:19:05,666 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-10 23:19:05,667 INFO L425 stractBuchiCegarLoop]: Abstraction has 918 states and 1407 transitions. [2024-11-10 23:19:05,667 INFO L332 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-11-10 23:19:05,667 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 918 states and 1407 transitions. [2024-11-10 23:19:05,671 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 380 [2024-11-10 23:19:05,671 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-10 23:19:05,671 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-10 23:19:05,672 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-10 23:19:05,672 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1] [2024-11-10 23:19:05,672 INFO L745 eck$LassoCheckResult]: Stem: 6341#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 6214#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 6185#L490 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6186#L212-1 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 6307#L137-1 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 6308#L143-1 ~b0_req_up~0 := 0; 6282#L145-1 assume true;assume { :end_inline_update_b0 } true; 6283#L219-1 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 6305#L152-1 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 6306#L158-1 ~b1_req_up~0 := 0; 6229#L160-1 assume true;assume { :end_inline_update_b1 } true; 6230#L226-1 assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true; 6243#L167-1 assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0; 6334#L173-1 ~d0_req_up~0 := 0; 6335#L175-1 assume true;assume { :end_inline_update_d0 } true; 6278#L233-1 assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true; 6279#L182-1 assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0; 6328#L188-1 ~d1_req_up~0 := 0; 6324#L190-1 assume true;assume { :end_inline_update_d1 } true; 6325#L240-1 assume !(1 == ~z_req_up~0); 6246#L248-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6183#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 6184#L261 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6311#L321-1 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 6200#L326-1 assume !(0 == ~b1_ev~0); 6201#L331-1 assume !(0 == ~d0_ev~0); 6149#L336-1 assume !(0 == ~d1_ev~0); 6150#L341-1 assume 0 == ~z_ev~0;~z_ev~0 := 1; 6343#L347-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 6342#L107-1 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 6220#L121-1 assume true;is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 6327#L130-1 assume true;activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 6326#L390-1 assume !(0 != activate_threads_~tmp~1#1); 6198#L396-1 assume true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6199#L354-1 assume !(1 == ~b0_ev~0); 6242#L359-1 assume !(1 == ~b1_ev~0); 6240#L364-1 assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 6241#L369-1 assume !(1 == ~d1_ev~0); 6244#L374-1 assume !(1 == ~z_ev~0); 6151#L380-1 assume true;assume { :end_inline_reset_delta_events } true; 6152#L432 assume true; 6592#L432-1 assume !false;assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 6593#L285 [2024-11-10 23:19:05,673 INFO L747 eck$LassoCheckResult]: Loop: 6593#L285 assume true; 6517#L285-1 assume !false;assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 6512#L268-1 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 6513#L270-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 6870#L276-1 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 6868#L290 assume 0 != eval_~tmp___0~0#1; 6502#L295 assume !(0 == ~comp_m1_st~0); 6593#L285 [2024-11-10 23:19:05,673 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-10 23:19:05,673 INFO L85 PathProgramCache]: Analyzing trace with hash -260627024, now seen corresponding path program 1 times [2024-11-10 23:19:05,673 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-10 23:19:05,673 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1485423657] [2024-11-10 23:19:05,673 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-10 23:19:05,673 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-10 23:19:05,681 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-10 23:19:05,698 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-10 23:19:05,698 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-10 23:19:05,698 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1485423657] [2024-11-10 23:19:05,698 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1485423657] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-10 23:19:05,698 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-10 23:19:05,698 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-10 23:19:05,698 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [875423958] [2024-11-10 23:19:05,699 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-10 23:19:05,699 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-10 23:19:05,699 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-10 23:19:05,699 INFO L85 PathProgramCache]: Analyzing trace with hash -965419658, now seen corresponding path program 1 times [2024-11-10 23:19:05,699 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-10 23:19:05,699 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [905331327] [2024-11-10 23:19:05,699 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-10 23:19:05,699 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-10 23:19:05,702 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-10 23:19:05,707 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-10 23:19:05,707 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-10 23:19:05,707 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [905331327] [2024-11-10 23:19:05,707 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [905331327] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-10 23:19:05,708 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-10 23:19:05,708 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-10 23:19:05,708 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [898494499] [2024-11-10 23:19:05,708 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-10 23:19:05,708 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-10 23:19:05,708 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-10 23:19:05,709 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-10 23:19:05,709 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-10 23:19:05,709 INFO L87 Difference]: Start difference. First operand 918 states and 1407 transitions. cyclomatic complexity: 498 Second operand has 3 states, 2 states have (on average 3.5) internal successors, (7), 3 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-10 23:19:05,736 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-10 23:19:05,737 INFO L93 Difference]: Finished difference Result 1129 states and 1696 transitions. [2024-11-10 23:19:05,737 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1129 states and 1696 transitions. [2024-11-10 23:19:05,743 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 460 [2024-11-10 23:19:05,749 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1129 states to 1129 states and 1696 transitions. [2024-11-10 23:19:05,749 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 534 [2024-11-10 23:19:05,750 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 534 [2024-11-10 23:19:05,750 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1129 states and 1696 transitions. [2024-11-10 23:19:05,750 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-10 23:19:05,750 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1129 states and 1696 transitions. [2024-11-10 23:19:05,751 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1129 states and 1696 transitions. [2024-11-10 23:19:05,763 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1129 to 1129. [2024-11-10 23:19:05,765 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1129 states, 1129 states have (on average 1.5022143489813995) internal successors, (1696), 1128 states have internal predecessors, (1696), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-10 23:19:05,768 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1129 states to 1129 states and 1696 transitions. [2024-11-10 23:19:05,768 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1129 states and 1696 transitions. [2024-11-10 23:19:05,769 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-10 23:19:05,769 INFO L425 stractBuchiCegarLoop]: Abstraction has 1129 states and 1696 transitions. [2024-11-10 23:19:05,769 INFO L332 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-11-10 23:19:05,769 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1129 states and 1696 transitions. [2024-11-10 23:19:05,774 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 460 [2024-11-10 23:19:05,774 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-10 23:19:05,774 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-10 23:19:05,775 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-10 23:19:05,775 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1] [2024-11-10 23:19:05,775 INFO L745 eck$LassoCheckResult]: Stem: 8409#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 8267#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 8239#L490 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8240#L212-1 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 8365#L137-1 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 8366#L143-1 ~b0_req_up~0 := 0; 8339#L145-1 assume true;assume { :end_inline_update_b0 } true; 8340#L219-1 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 8363#L152-1 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 8364#L158-1 ~b1_req_up~0 := 0; 8283#L160-1 assume true;assume { :end_inline_update_b1 } true; 8284#L226-1 assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true; 8298#L167-1 assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0; 8402#L173-1 ~d0_req_up~0 := 0; 8403#L175-1 assume true;assume { :end_inline_update_d0 } true; 8335#L233-1 assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true; 8336#L182-1 assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0; 8395#L188-1 ~d1_req_up~0 := 0; 8387#L190-1 assume true;assume { :end_inline_update_d1 } true; 8388#L240-1 assume !(1 == ~z_req_up~0); 8301#L248-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8236#L255 assume 1 == ~comp_m1_i~0;~comp_m1_st~0 := 0; 8237#L261 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8371#L321-1 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 8253#L326-1 assume !(0 == ~b1_ev~0); 8254#L331-1 assume !(0 == ~d0_ev~0); 8201#L336-1 assume !(0 == ~d1_ev~0); 8202#L341-1 assume 0 == ~z_ev~0;~z_ev~0 := 1; 8411#L347-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 8412#L107-1 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 9203#L121-1 assume true;is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 9202#L130-1 assume true;activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 9201#L390-1 assume !(0 != activate_threads_~tmp~1#1); 8251#L396-1 assume true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8252#L354-1 assume !(1 == ~b0_ev~0); 8297#L359-1 assume !(1 == ~b1_ev~0); 8372#L364-1 assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 8789#L369-1 assume !(1 == ~d1_ev~0); 8392#L374-1 assume !(1 == ~z_ev~0); 8203#L380-1 assume true;assume { :end_inline_reset_delta_events } true; 8204#L432 assume true; 8727#L432-1 assume !false;assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 8728#L285 [2024-11-10 23:19:05,776 INFO L747 eck$LassoCheckResult]: Loop: 8728#L285 assume true; 9067#L285-1 assume !false;assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 9066#L268-1 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 8760#L270-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 9064#L276-1 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 9063#L290 assume 0 != eval_~tmp___0~0#1; 9062#L295 assume 0 == ~comp_m1_st~0;havoc eval_#t~nondet5#1;eval_~tmp~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 8763#L299 assume !(0 != eval_~tmp~0#1); 8728#L285 [2024-11-10 23:19:05,776 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-10 23:19:05,776 INFO L85 PathProgramCache]: Analyzing trace with hash -471977937, now seen corresponding path program 1 times [2024-11-10 23:19:05,776 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-10 23:19:05,776 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1011780522] [2024-11-10 23:19:05,776 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-10 23:19:05,776 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-10 23:19:05,783 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-10 23:19:05,827 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-10 23:19:05,827 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-10 23:19:05,827 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1011780522] [2024-11-10 23:19:05,828 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1011780522] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-10 23:19:05,828 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-10 23:19:05,828 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-10 23:19:05,828 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [974505876] [2024-11-10 23:19:05,828 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-10 23:19:05,828 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-10 23:19:05,828 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-10 23:19:05,829 INFO L85 PathProgramCache]: Analyzing trace with hash 136761786, now seen corresponding path program 1 times [2024-11-10 23:19:05,829 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-10 23:19:05,829 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [409107359] [2024-11-10 23:19:05,829 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-10 23:19:05,829 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-10 23:19:05,832 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-10 23:19:05,832 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-10 23:19:05,833 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-10 23:19:05,835 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-10 23:19:05,859 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-10 23:19:05,859 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-10 23:19:05,859 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-10 23:19:05,860 INFO L87 Difference]: Start difference. First operand 1129 states and 1696 transitions. cyclomatic complexity: 576 Second operand has 4 states, 4 states have (on average 10.5) internal successors, (42), 4 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-10 23:19:05,884 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-10 23:19:05,884 INFO L93 Difference]: Finished difference Result 1115 states and 1669 transitions. [2024-11-10 23:19:05,885 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1115 states and 1669 transitions. [2024-11-10 23:19:05,892 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 460 [2024-11-10 23:19:05,898 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1115 states to 1115 states and 1669 transitions. [2024-11-10 23:19:05,898 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 520 [2024-11-10 23:19:05,899 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 520 [2024-11-10 23:19:05,899 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1115 states and 1669 transitions. [2024-11-10 23:19:05,899 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-10 23:19:05,900 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1115 states and 1669 transitions. [2024-11-10 23:19:05,900 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1115 states and 1669 transitions. [2024-11-10 23:19:05,911 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1115 to 1115. [2024-11-10 23:19:05,913 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1115 states, 1115 states have (on average 1.4968609865470852) internal successors, (1669), 1114 states have internal predecessors, (1669), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-10 23:19:05,916 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1115 states to 1115 states and 1669 transitions. [2024-11-10 23:19:05,917 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1115 states and 1669 transitions. [2024-11-10 23:19:05,918 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-10 23:19:05,918 INFO L425 stractBuchiCegarLoop]: Abstraction has 1115 states and 1669 transitions. [2024-11-10 23:19:05,918 INFO L332 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-11-10 23:19:05,918 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1115 states and 1669 transitions. [2024-11-10 23:19:05,923 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 460 [2024-11-10 23:19:05,923 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-10 23:19:05,923 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-10 23:19:05,923 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-10 23:19:05,924 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1] [2024-11-10 23:19:05,924 INFO L745 eck$LassoCheckResult]: Stem: 10659#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 10518#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 10490#L490 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10491#L212-1 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 10619#L137-1 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 10620#L143-1 ~b0_req_up~0 := 0; 10594#L145-1 assume true;assume { :end_inline_update_b0 } true; 10595#L219-1 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 10617#L152-1 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 10618#L158-1 ~b1_req_up~0 := 0; 10533#L160-1 assume true;assume { :end_inline_update_b1 } true; 10534#L226-1 assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true; 10549#L167-1 assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0; 10650#L173-1 ~d0_req_up~0 := 0; 10651#L175-1 assume true;assume { :end_inline_update_d0 } true; 10586#L233-1 assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true; 10587#L182-1 assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0; 10646#L188-1 ~d1_req_up~0 := 0; 10637#L190-1 assume true;assume { :end_inline_update_d1 } true; 10638#L240-1 assume !(1 == ~z_req_up~0); 10552#L248-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10488#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 10489#L261 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10623#L321-1 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 10508#L326-1 assume !(0 == ~b1_ev~0); 10509#L331-1 assume !(0 == ~d0_ev~0); 10454#L336-1 assume !(0 == ~d1_ev~0); 10455#L341-1 assume 0 == ~z_ev~0;~z_ev~0 := 1; 10661#L347-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 10660#L107-1 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 10524#L121-1 assume true;is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 10643#L130-1 assume true;activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 10639#L390-1 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 10502#L396-1 assume true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10503#L354-1 assume !(1 == ~b0_ev~0); 10548#L359-1 assume !(1 == ~b1_ev~0); 11029#L364-1 assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 11027#L369-1 assume !(1 == ~d1_ev~0); 10641#L374-1 assume !(1 == ~z_ev~0); 10456#L380-1 assume true;assume { :end_inline_reset_delta_events } true; 10457#L432 assume true; 10976#L432-1 assume !false;assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 10541#L285 [2024-11-10 23:19:05,924 INFO L747 eck$LassoCheckResult]: Loop: 10541#L285 assume true; 10655#L285-1 assume !false;assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 10596#L268-1 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 10476#L270-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 10477#L276-1 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 10544#L290 assume 0 != eval_~tmp___0~0#1; 10450#L295 assume 0 == ~comp_m1_st~0;havoc eval_#t~nondet5#1;eval_~tmp~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 10451#L299 assume !(0 != eval_~tmp~0#1); 10541#L285 [2024-11-10 23:19:05,924 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-10 23:19:05,924 INFO L85 PathProgramCache]: Analyzing trace with hash -64113519, now seen corresponding path program 1 times [2024-11-10 23:19:05,924 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-10 23:19:05,925 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1390883122] [2024-11-10 23:19:05,925 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-10 23:19:05,925 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-10 23:19:05,932 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-10 23:19:05,948 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-10 23:19:05,948 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-10 23:19:05,948 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1390883122] [2024-11-10 23:19:05,948 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1390883122] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-10 23:19:05,948 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-10 23:19:05,948 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-10 23:19:05,949 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1839659960] [2024-11-10 23:19:05,949 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-10 23:19:05,949 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-10 23:19:05,949 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-10 23:19:05,949 INFO L85 PathProgramCache]: Analyzing trace with hash 136761786, now seen corresponding path program 2 times [2024-11-10 23:19:05,949 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-10 23:19:05,950 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [993633387] [2024-11-10 23:19:05,950 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-10 23:19:05,950 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-10 23:19:05,953 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-10 23:19:05,953 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-10 23:19:05,954 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-10 23:19:05,956 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-10 23:19:05,976 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-10 23:19:05,976 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-10 23:19:05,977 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-10 23:19:05,977 INFO L87 Difference]: Start difference. First operand 1115 states and 1669 transitions. cyclomatic complexity: 563 Second operand has 3 states, 3 states have (on average 14.0) internal successors, (42), 3 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-10 23:19:06,004 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-10 23:19:06,004 INFO L93 Difference]: Finished difference Result 1412 states and 2070 transitions. [2024-11-10 23:19:06,004 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1412 states and 2070 transitions. [2024-11-10 23:19:06,012 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 592 [2024-11-10 23:19:06,019 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1412 states to 1412 states and 2070 transitions. [2024-11-10 23:19:06,019 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 652 [2024-11-10 23:19:06,020 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 652 [2024-11-10 23:19:06,020 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1412 states and 2070 transitions. [2024-11-10 23:19:06,020 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-10 23:19:06,020 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1412 states and 2070 transitions. [2024-11-10 23:19:06,021 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1412 states and 2070 transitions. [2024-11-10 23:19:06,035 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1412 to 1412. [2024-11-10 23:19:06,038 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1412 states, 1412 states have (on average 1.4660056657223797) internal successors, (2070), 1411 states have internal predecessors, (2070), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-10 23:19:06,042 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1412 states to 1412 states and 2070 transitions. [2024-11-10 23:19:06,042 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1412 states and 2070 transitions. [2024-11-10 23:19:06,042 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-10 23:19:06,043 INFO L425 stractBuchiCegarLoop]: Abstraction has 1412 states and 2070 transitions. [2024-11-10 23:19:06,043 INFO L332 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2024-11-10 23:19:06,043 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1412 states and 2070 transitions. [2024-11-10 23:19:06,049 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 592 [2024-11-10 23:19:06,049 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-10 23:19:06,049 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-10 23:19:06,049 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-10 23:19:06,049 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1] [2024-11-10 23:19:06,050 INFO L745 eck$LassoCheckResult]: Stem: 13189#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 13051#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 13023#L490 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13024#L212-1 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 13149#L137-1 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 13150#L143-1 ~b0_req_up~0 := 0; 13128#L145-1 assume true;assume { :end_inline_update_b0 } true; 13129#L219-1 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 13147#L152-1 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 13148#L158-1 ~b1_req_up~0 := 0; 13069#L160-1 assume true;assume { :end_inline_update_b1 } true; 13070#L226-1 assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true; 13085#L167-1 assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0; 13181#L173-1 ~d0_req_up~0 := 0; 13182#L175-1 assume true;assume { :end_inline_update_d0 } true; 13120#L233-1 assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true; 13121#L182-1 assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0; 13177#L188-1 ~d1_req_up~0 := 0; 13168#L190-1 assume true;assume { :end_inline_update_d1 } true; 13169#L240-1 assume !(1 == ~z_req_up~0); 13088#L248-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 13021#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 13022#L261 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13154#L321-1 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 13041#L326-1 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 13042#L331-1 assume !(0 == ~d0_ev~0); 12987#L336-1 assume !(0 == ~d1_ev~0); 12988#L341-1 assume 0 == ~z_ev~0;~z_ev~0 := 1; 13191#L347-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 13190#L107-1 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 13057#L121-1 assume true;is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 13174#L130-1 assume true;activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 13170#L390-1 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 13035#L396-1 assume true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13036#L354-1 assume !(1 == ~b0_ev~0); 13155#L359-1 assume !(1 == ~b1_ev~0); 13081#L364-1 assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 13082#L369-1 assume !(1 == ~d1_ev~0); 13086#L374-1 assume !(1 == ~z_ev~0); 12989#L380-1 assume true;assume { :end_inline_reset_delta_events } true; 12990#L432 assume true; 14156#L432-1 assume !false;assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 13076#L285 [2024-11-10 23:19:06,050 INFO L747 eck$LassoCheckResult]: Loop: 13076#L285 assume true; 13186#L285-1 assume !false;assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 14229#L268-1 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 13721#L270-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 14227#L276-1 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 14226#L290 assume 0 != eval_~tmp___0~0#1; 12983#L295 assume 0 == ~comp_m1_st~0;havoc eval_#t~nondet5#1;eval_~tmp~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 12984#L299 assume !(0 != eval_~tmp~0#1); 13076#L285 [2024-11-10 23:19:06,050 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-10 23:19:06,050 INFO L85 PathProgramCache]: Analyzing trace with hash 932958834, now seen corresponding path program 1 times [2024-11-10 23:19:06,050 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-10 23:19:06,050 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [127824736] [2024-11-10 23:19:06,050 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-10 23:19:06,050 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-10 23:19:06,056 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-10 23:19:06,089 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-10 23:19:06,090 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-10 23:19:06,090 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [127824736] [2024-11-10 23:19:06,090 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [127824736] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-10 23:19:06,090 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-10 23:19:06,090 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-10 23:19:06,090 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1512667738] [2024-11-10 23:19:06,090 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-10 23:19:06,090 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-10 23:19:06,091 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-10 23:19:06,091 INFO L85 PathProgramCache]: Analyzing trace with hash 136761786, now seen corresponding path program 3 times [2024-11-10 23:19:06,091 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-10 23:19:06,091 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1431606888] [2024-11-10 23:19:06,091 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-10 23:19:06,091 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-10 23:19:06,094 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-10 23:19:06,094 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-10 23:19:06,095 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-10 23:19:06,097 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-10 23:19:06,120 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-10 23:19:06,120 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-10 23:19:06,120 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-10 23:19:06,120 INFO L87 Difference]: Start difference. First operand 1412 states and 2070 transitions. cyclomatic complexity: 667 Second operand has 3 states, 3 states have (on average 14.0) internal successors, (42), 3 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-10 23:19:06,149 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-10 23:19:06,149 INFO L93 Difference]: Finished difference Result 1871 states and 2675 transitions. [2024-11-10 23:19:06,149 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1871 states and 2675 transitions. [2024-11-10 23:19:06,160 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 796 [2024-11-10 23:19:06,169 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1871 states to 1871 states and 2675 transitions. [2024-11-10 23:19:06,169 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 856 [2024-11-10 23:19:06,170 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 856 [2024-11-10 23:19:06,170 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1871 states and 2675 transitions. [2024-11-10 23:19:06,170 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-10 23:19:06,170 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1871 states and 2675 transitions. [2024-11-10 23:19:06,171 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1871 states and 2675 transitions. [2024-11-10 23:19:06,189 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1871 to 1871. [2024-11-10 23:19:06,192 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1871 states, 1871 states have (on average 1.4297167290219135) internal successors, (2675), 1870 states have internal predecessors, (2675), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-10 23:19:06,196 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1871 states to 1871 states and 2675 transitions. [2024-11-10 23:19:06,197 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1871 states and 2675 transitions. [2024-11-10 23:19:06,197 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-10 23:19:06,198 INFO L425 stractBuchiCegarLoop]: Abstraction has 1871 states and 2675 transitions. [2024-11-10 23:19:06,198 INFO L332 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2024-11-10 23:19:06,198 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1871 states and 2675 transitions. [2024-11-10 23:19:06,205 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 796 [2024-11-10 23:19:06,205 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-10 23:19:06,205 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-10 23:19:06,206 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-10 23:19:06,206 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1] [2024-11-10 23:19:06,206 INFO L745 eck$LassoCheckResult]: Stem: 16485#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 16345#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 16314#L490 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16315#L212-1 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 16450#L137-1 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 16451#L143-1 ~b0_req_up~0 := 0; 16423#L145-1 assume true;assume { :end_inline_update_b0 } true; 16424#L219-1 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 16448#L152-1 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 16449#L158-1 ~b1_req_up~0 := 0; 16364#L160-1 assume true;assume { :end_inline_update_b1 } true; 16365#L226-1 assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true; 16380#L167-1 assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0; 16478#L173-1 ~d0_req_up~0 := 0; 16479#L175-1 assume true;assume { :end_inline_update_d0 } true; 16417#L233-1 assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true; 16418#L182-1 assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0; 16472#L188-1 ~d1_req_up~0 := 0; 16466#L190-1 assume true;assume { :end_inline_update_d1 } true; 16467#L240-1 assume !(1 == ~z_req_up~0); 16383#L248-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16312#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 16313#L261 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16454#L321-1 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 16331#L326-1 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 16332#L331-1 assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 16276#L336-1 assume !(0 == ~d1_ev~0); 16277#L341-1 assume 0 == ~z_ev~0;~z_ev~0 := 1; 16487#L347-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 16486#L107-1 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 16351#L121-1 assume true;is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 16471#L130-1 assume true;activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 16469#L390-1 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 16329#L396-1 assume true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16330#L354-1 assume !(1 == ~b0_ev~0); 16379#L359-1 assume !(1 == ~b1_ev~0); 16455#L364-1 assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 17039#L369-1 assume !(1 == ~d1_ev~0); 17037#L374-1 assume !(1 == ~z_ev~0); 17035#L380-1 assume true;assume { :end_inline_reset_delta_events } true; 17032#L432 assume true; 17022#L432-1 assume !false;assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 17023#L285 [2024-11-10 23:19:06,206 INFO L747 eck$LassoCheckResult]: Loop: 17023#L285 assume true; 17964#L285-1 assume !false;assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 17938#L268-1 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 17354#L270-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 17931#L276-1 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 17929#L290 assume 0 != eval_~tmp___0~0#1; 17927#L295 assume 0 == ~comp_m1_st~0;havoc eval_#t~nondet5#1;eval_~tmp~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 17357#L299 assume !(0 != eval_~tmp~0#1); 17023#L285 [2024-11-10 23:19:06,206 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-10 23:19:06,207 INFO L85 PathProgramCache]: Analyzing trace with hash -420350863, now seen corresponding path program 1 times [2024-11-10 23:19:06,207 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-10 23:19:06,207 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [806955487] [2024-11-10 23:19:06,207 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-10 23:19:06,207 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-10 23:19:06,213 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-10 23:19:06,227 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-10 23:19:06,227 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-10 23:19:06,227 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [806955487] [2024-11-10 23:19:06,228 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [806955487] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-10 23:19:06,228 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-10 23:19:06,228 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-10 23:19:06,228 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1118225412] [2024-11-10 23:19:06,228 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-10 23:19:06,228 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-10 23:19:06,228 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-10 23:19:06,229 INFO L85 PathProgramCache]: Analyzing trace with hash 136761786, now seen corresponding path program 4 times [2024-11-10 23:19:06,229 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-10 23:19:06,229 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [897934891] [2024-11-10 23:19:06,229 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-10 23:19:06,229 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-10 23:19:06,232 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-10 23:19:06,233 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-10 23:19:06,234 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-10 23:19:06,237 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-10 23:19:06,257 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-10 23:19:06,258 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-10 23:19:06,258 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-10 23:19:06,258 INFO L87 Difference]: Start difference. First operand 1871 states and 2675 transitions. cyclomatic complexity: 813 Second operand has 3 states, 3 states have (on average 14.0) internal successors, (42), 3 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-10 23:19:06,294 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-10 23:19:06,294 INFO L93 Difference]: Finished difference Result 2084 states and 2948 transitions. [2024-11-10 23:19:06,294 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2084 states and 2948 transitions. [2024-11-10 23:19:06,305 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 938 [2024-11-10 23:19:06,315 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2084 states to 2084 states and 2948 transitions. [2024-11-10 23:19:06,315 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 998 [2024-11-10 23:19:06,316 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 998 [2024-11-10 23:19:06,316 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2084 states and 2948 transitions. [2024-11-10 23:19:06,316 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-10 23:19:06,316 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2084 states and 2948 transitions. [2024-11-10 23:19:06,318 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2084 states and 2948 transitions. [2024-11-10 23:19:06,337 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2084 to 2084. [2024-11-10 23:19:06,340 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2084 states, 2084 states have (on average 1.4145873320537428) internal successors, (2948), 2083 states have internal predecessors, (2948), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-10 23:19:06,345 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2084 states to 2084 states and 2948 transitions. [2024-11-10 23:19:06,346 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2084 states and 2948 transitions. [2024-11-10 23:19:06,346 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-10 23:19:06,346 INFO L425 stractBuchiCegarLoop]: Abstraction has 2084 states and 2948 transitions. [2024-11-10 23:19:06,347 INFO L332 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2024-11-10 23:19:06,347 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2084 states and 2948 transitions. [2024-11-10 23:19:06,352 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 938 [2024-11-10 23:19:06,352 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-10 23:19:06,353 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-10 23:19:06,353 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-10 23:19:06,353 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1] [2024-11-10 23:19:06,353 INFO L745 eck$LassoCheckResult]: Stem: 20455#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 20305#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 20275#L490 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20276#L212-1 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 20415#L137-1 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 20416#L143-1 ~b0_req_up~0 := 0; 20389#L145-1 assume true;assume { :end_inline_update_b0 } true; 20390#L219-1 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 20413#L152-1 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 20414#L158-1 ~b1_req_up~0 := 0; 20326#L160-1 assume true;assume { :end_inline_update_b1 } true; 20327#L226-1 assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true; 20342#L167-1 assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0; 20448#L173-1 ~d0_req_up~0 := 0; 20449#L175-1 assume true;assume { :end_inline_update_d0 } true; 20385#L233-1 assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true; 20386#L182-1 assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0; 20442#L188-1 ~d1_req_up~0 := 0; 20432#L190-1 assume true;assume { :end_inline_update_d1 } true; 20433#L240-1 assume !(1 == ~z_req_up~0); 20346#L248-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 20273#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 20274#L261 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20419#L321-1 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 20291#L326-1 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 20292#L331-1 assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 20237#L336-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 20238#L341-1 assume 0 == ~z_ev~0;~z_ev~0 := 1; 20457#L347-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 20456#L107-1 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 20311#L121-1 assume true;is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 20441#L130-1 assume true;activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 20435#L390-1 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 20436#L396-1 assume true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21235#L354-1 assume !(1 == ~b0_ev~0); 21234#L359-1 assume !(1 == ~b1_ev~0); 20339#L364-1 assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 20340#L369-1 assume !(1 == ~d1_ev~0); 20716#L374-1 assume !(1 == ~z_ev~0); 20714#L380-1 assume true;assume { :end_inline_reset_delta_events } true; 20711#L432 assume true; 20704#L432-1 assume !false;assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 20705#L285 [2024-11-10 23:19:06,353 INFO L747 eck$LassoCheckResult]: Loop: 20705#L285 assume true; 20942#L285-1 assume !false;assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 20940#L268-1 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 20875#L270-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 20935#L276-1 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 20931#L290 assume 0 != eval_~tmp___0~0#1; 20930#L295 assume 0 == ~comp_m1_st~0;havoc eval_#t~nondet5#1;eval_~tmp~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 20878#L299 assume !(0 != eval_~tmp~0#1); 20705#L285 [2024-11-10 23:19:06,354 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-10 23:19:06,354 INFO L85 PathProgramCache]: Analyzing trace with hash 90183314, now seen corresponding path program 1 times [2024-11-10 23:19:06,354 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-10 23:19:06,354 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [523836539] [2024-11-10 23:19:06,354 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-10 23:19:06,354 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-10 23:19:06,360 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-10 23:19:06,382 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-10 23:19:06,382 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-10 23:19:06,382 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [523836539] [2024-11-10 23:19:06,383 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [523836539] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-10 23:19:06,383 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-10 23:19:06,383 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-10 23:19:06,383 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [544339363] [2024-11-10 23:19:06,383 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-10 23:19:06,383 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-10 23:19:06,383 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-10 23:19:06,384 INFO L85 PathProgramCache]: Analyzing trace with hash 136761786, now seen corresponding path program 5 times [2024-11-10 23:19:06,384 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-10 23:19:06,384 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [722698006] [2024-11-10 23:19:06,384 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-10 23:19:06,384 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-10 23:19:06,386 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-10 23:19:06,387 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-10 23:19:06,388 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-10 23:19:06,389 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-10 23:19:06,413 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-10 23:19:06,413 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-10 23:19:06,413 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-10 23:19:06,413 INFO L87 Difference]: Start difference. First operand 2084 states and 2948 transitions. cyclomatic complexity: 873 Second operand has 3 states, 3 states have (on average 14.0) internal successors, (42), 3 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-10 23:19:06,448 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-10 23:19:06,448 INFO L93 Difference]: Finished difference Result 4135 states and 5817 transitions. [2024-11-10 23:19:06,448 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4135 states and 5817 transitions. [2024-11-10 23:19:06,466 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 1876 [2024-11-10 23:19:06,483 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4135 states to 3462 states and 4890 transitions. [2024-11-10 23:19:06,483 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1972 [2024-11-10 23:19:06,485 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1978 [2024-11-10 23:19:06,485 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3462 states and 4890 transitions. [2024-11-10 23:19:06,487 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-10 23:19:06,487 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3462 states and 4890 transitions. [2024-11-10 23:19:06,490 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3462 states and 4890 transitions. [2024-11-10 23:19:06,517 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3462 to 2114. [2024-11-10 23:19:06,520 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2114 states, 2114 states have (on average 1.413434247871334) internal successors, (2988), 2113 states have internal predecessors, (2988), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-10 23:19:06,525 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2114 states to 2114 states and 2988 transitions. [2024-11-10 23:19:06,526 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2114 states and 2988 transitions. [2024-11-10 23:19:06,526 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-10 23:19:06,526 INFO L425 stractBuchiCegarLoop]: Abstraction has 2114 states and 2988 transitions. [2024-11-10 23:19:06,527 INFO L332 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2024-11-10 23:19:06,527 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2114 states and 2988 transitions. [2024-11-10 23:19:06,532 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 938 [2024-11-10 23:19:06,532 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-10 23:19:06,532 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-10 23:19:06,532 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-10 23:19:06,532 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1] [2024-11-10 23:19:06,533 INFO L745 eck$LassoCheckResult]: Stem: 26689#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 26536#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 26500#L490 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 26501#L212-1 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 26642#L137-1 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 26643#L143-1 ~b0_req_up~0 := 0; 26618#L145-1 assume true;assume { :end_inline_update_b0 } true; 26619#L219-1 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 26640#L152-1 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 26641#L158-1 ~b1_req_up~0 := 0; 26553#L160-1 assume true;assume { :end_inline_update_b1 } true; 26554#L226-1 assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true; 26570#L167-1 assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0; 26682#L173-1 ~d0_req_up~0 := 0; 26683#L175-1 assume true;assume { :end_inline_update_d0 } true; 26612#L233-1 assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true; 26613#L182-1 assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0; 26677#L188-1 ~d1_req_up~0 := 0; 26661#L190-1 assume true;assume { :end_inline_update_d1 } true; 26662#L240-1 assume !(1 == ~z_req_up~0); 26684#L248-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 26702#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 26699#L261 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 26647#L321-1 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 26648#L326-1 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 26537#L331-1 assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 26538#L336-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 26695#L341-1 assume !(0 == ~z_ev~0); 26691#L347-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 26690#L107-1 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 26543#L121-1 assume true;is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 26693#L130-1 assume true;activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 26694#L390-1 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 26516#L396-1 assume true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26517#L354-1 assume !(1 == ~b0_ev~0); 26649#L359-1 assume !(1 == ~b1_ev~0); 26650#L364-1 assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 26705#L369-1 assume !(1 == ~d1_ev~0); 26706#L374-1 assume !(1 == ~z_ev~0); 26464#L380-1 assume true;assume { :end_inline_reset_delta_events } true; 26465#L432 assume true; 26907#L432-1 assume !false;assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 26561#L285 [2024-11-10 23:19:06,533 INFO L747 eck$LassoCheckResult]: Loop: 26561#L285 assume true; 26577#L285-1 assume !false;assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 26578#L268-1 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 26624#L270-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 28407#L276-1 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 26692#L290 assume 0 != eval_~tmp___0~0#1; 26458#L295 assume 0 == ~comp_m1_st~0;havoc eval_#t~nondet5#1;eval_~tmp~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 26459#L299 assume !(0 != eval_~tmp~0#1); 26561#L285 [2024-11-10 23:19:06,533 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-10 23:19:06,533 INFO L85 PathProgramCache]: Analyzing trace with hash 1597735123, now seen corresponding path program 1 times [2024-11-10 23:19:06,533 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-10 23:19:06,533 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [160374166] [2024-11-10 23:19:06,533 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-10 23:19:06,534 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-10 23:19:06,539 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-10 23:19:06,552 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-10 23:19:06,553 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-10 23:19:06,553 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [160374166] [2024-11-10 23:19:06,553 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [160374166] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-10 23:19:06,553 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-10 23:19:06,553 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-10 23:19:06,553 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1358496458] [2024-11-10 23:19:06,553 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-10 23:19:06,553 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-10 23:19:06,554 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-10 23:19:06,554 INFO L85 PathProgramCache]: Analyzing trace with hash 136761786, now seen corresponding path program 6 times [2024-11-10 23:19:06,554 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-10 23:19:06,554 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [242160841] [2024-11-10 23:19:06,554 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-10 23:19:06,554 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-10 23:19:06,557 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-10 23:19:06,557 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-10 23:19:06,558 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-10 23:19:06,559 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-10 23:19:06,589 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-10 23:19:06,590 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-10 23:19:06,590 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-10 23:19:06,590 INFO L87 Difference]: Start difference. First operand 2114 states and 2988 transitions. cyclomatic complexity: 880 Second operand has 3 states, 3 states have (on average 14.0) internal successors, (42), 3 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-10 23:19:06,620 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-10 23:19:06,620 INFO L93 Difference]: Finished difference Result 2289 states and 3212 transitions. [2024-11-10 23:19:06,621 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2289 states and 3212 transitions. [2024-11-10 23:19:06,661 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1020 [2024-11-10 23:19:06,671 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2289 states to 2289 states and 3212 transitions. [2024-11-10 23:19:06,671 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1111 [2024-11-10 23:19:06,672 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1111 [2024-11-10 23:19:06,672 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2289 states and 3212 transitions. [2024-11-10 23:19:06,673 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-10 23:19:06,676 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2289 states and 3212 transitions. [2024-11-10 23:19:06,678 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2289 states and 3212 transitions. [2024-11-10 23:19:06,699 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2289 to 2289. [2024-11-10 23:19:06,703 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2289 states, 2289 states have (on average 1.4032328527741371) internal successors, (3212), 2288 states have internal predecessors, (3212), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-10 23:19:06,708 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2289 states to 2289 states and 3212 transitions. [2024-11-10 23:19:06,709 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2289 states and 3212 transitions. [2024-11-10 23:19:06,709 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-10 23:19:06,710 INFO L425 stractBuchiCegarLoop]: Abstraction has 2289 states and 3212 transitions. [2024-11-10 23:19:06,710 INFO L332 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2024-11-10 23:19:06,710 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2289 states and 3212 transitions. [2024-11-10 23:19:06,716 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1020 [2024-11-10 23:19:06,716 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-10 23:19:06,716 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-10 23:19:06,717 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-10 23:19:06,717 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1] [2024-11-10 23:19:06,717 INFO L745 eck$LassoCheckResult]: Stem: 31110#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 30947#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 30912#L490 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 30913#L212-1 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 31055#L137-1 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 31056#L143-1 ~b0_req_up~0 := 0; 31029#L145-1 assume true;assume { :end_inline_update_b0 } true; 31030#L219-1 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 31053#L152-1 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 31054#L158-1 ~b1_req_up~0 := 0; 30961#L160-1 assume true;assume { :end_inline_update_b1 } true; 30962#L226-1 assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true; 30978#L167-1 assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0; 31101#L173-1 ~d0_req_up~0 := 0; 31102#L175-1 assume true;assume { :end_inline_update_d0 } true; 31022#L233-1 assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true; 31023#L182-1 assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0; 31097#L188-1 ~d1_req_up~0 := 0; 31080#L190-1 assume true;assume { :end_inline_update_d1 } true; 31081#L240-1 assume !(1 == ~z_req_up~0); 31103#L248-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 31132#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 31129#L261 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 31063#L321-1 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 31064#L326-1 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 30948#L331-1 assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 30949#L336-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 31123#L341-1 assume !(0 == ~z_ev~0); 31113#L347-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 31114#L107-1 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 31092#L121-1 assume true;is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 31093#L130-1 assume true;activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 31084#L390-1 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 31085#L396-1 assume true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 31142#L354-1 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 31143#L359-1 assume !(1 == ~b1_ev~0); 31138#L364-1 assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 31139#L369-1 assume !(1 == ~d1_ev~0); 31087#L374-1 assume !(1 == ~z_ev~0); 31088#L380-1 assume true;assume { :end_inline_reset_delta_events } true; 32203#L432 assume true; 31694#L432-1 assume !false;assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 30969#L285 [2024-11-10 23:19:06,717 INFO L747 eck$LassoCheckResult]: Loop: 30969#L285 assume true; 33132#L285-1 assume !false;assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 33131#L268-1 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 32758#L270-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 33130#L276-1 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 33129#L290 assume 0 != eval_~tmp___0~0#1; 30867#L295 assume 0 == ~comp_m1_st~0;havoc eval_#t~nondet5#1;eval_~tmp~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 30868#L299 assume !(0 != eval_~tmp~0#1); 30969#L285 [2024-11-10 23:19:06,717 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-10 23:19:06,717 INFO L85 PathProgramCache]: Analyzing trace with hash -145075212, now seen corresponding path program 1 times [2024-11-10 23:19:06,718 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-10 23:19:06,718 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1347118264] [2024-11-10 23:19:06,718 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-10 23:19:06,718 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-10 23:19:06,723 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-10 23:19:06,738 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-10 23:19:06,738 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-10 23:19:06,738 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1347118264] [2024-11-10 23:19:06,738 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1347118264] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-10 23:19:06,738 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-10 23:19:06,738 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-10 23:19:06,738 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1803561687] [2024-11-10 23:19:06,738 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-10 23:19:06,739 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-10 23:19:06,739 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-10 23:19:06,739 INFO L85 PathProgramCache]: Analyzing trace with hash 136761786, now seen corresponding path program 7 times [2024-11-10 23:19:06,739 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-10 23:19:06,739 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1803021515] [2024-11-10 23:19:06,739 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-10 23:19:06,739 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-10 23:19:06,742 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-10 23:19:06,742 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-10 23:19:06,743 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-10 23:19:06,744 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-10 23:19:06,762 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-10 23:19:06,763 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-10 23:19:06,763 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-10 23:19:06,763 INFO L87 Difference]: Start difference. First operand 2289 states and 3212 transitions. cyclomatic complexity: 929 Second operand has 3 states, 3 states have (on average 14.0) internal successors, (42), 3 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-10 23:19:06,787 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-10 23:19:06,787 INFO L93 Difference]: Finished difference Result 2582 states and 3615 transitions. [2024-11-10 23:19:06,787 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2582 states and 3615 transitions. [2024-11-10 23:19:06,797 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1148 [2024-11-10 23:19:06,808 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2582 states to 2582 states and 3615 transitions. [2024-11-10 23:19:06,808 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1241 [2024-11-10 23:19:06,809 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1241 [2024-11-10 23:19:06,810 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2582 states and 3615 transitions. [2024-11-10 23:19:06,810 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-10 23:19:06,810 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2582 states and 3615 transitions. [2024-11-10 23:19:06,812 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2582 states and 3615 transitions. [2024-11-10 23:19:06,839 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2582 to 2582. [2024-11-10 23:19:06,843 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2582 states, 2582 states have (on average 1.4000774593338496) internal successors, (3615), 2581 states have internal predecessors, (3615), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-10 23:19:06,849 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2582 states to 2582 states and 3615 transitions. [2024-11-10 23:19:06,850 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2582 states and 3615 transitions. [2024-11-10 23:19:06,850 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-10 23:19:06,850 INFO L425 stractBuchiCegarLoop]: Abstraction has 2582 states and 3615 transitions. [2024-11-10 23:19:06,850 INFO L332 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2024-11-10 23:19:06,850 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2582 states and 3615 transitions. [2024-11-10 23:19:06,858 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1148 [2024-11-10 23:19:06,858 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-10 23:19:06,858 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-10 23:19:06,858 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-10 23:19:06,859 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1] [2024-11-10 23:19:06,859 INFO L745 eck$LassoCheckResult]: Stem: 35982#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 35819#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 35787#L490 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 35788#L212-1 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 35930#L137-1 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 35931#L143-1 ~b0_req_up~0 := 0; 35901#L145-1 assume true;assume { :end_inline_update_b0 } true; 35902#L219-1 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 35928#L152-1 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 35929#L158-1 ~b1_req_up~0 := 0; 35838#L160-1 assume true;assume { :end_inline_update_b1 } true; 35839#L226-1 assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true; 35854#L167-1 assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0; 35972#L173-1 ~d0_req_up~0 := 0; 35973#L175-1 assume true;assume { :end_inline_update_d0 } true; 35896#L233-1 assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true; 35897#L182-1 assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0; 35965#L188-1 ~d1_req_up~0 := 0; 35951#L190-1 assume true;assume { :end_inline_update_d1 } true; 35952#L240-1 assume !(1 == ~z_req_up~0); 35974#L248-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 36000#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 35995#L261 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 35937#L321-1 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 35938#L326-1 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 35820#L331-1 assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 35821#L336-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 35992#L341-1 assume !(0 == ~z_ev~0); 35985#L347-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 35986#L107-1 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 35963#L121-1 assume true;is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 35964#L130-1 assume true;activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 35955#L390-1 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 35956#L396-1 assume true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36014#L354-1 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 36011#L359-1 assume 1 == ~b1_ev~0;~b1_ev~0 := 2; 36010#L364-1 assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 36008#L369-1 assume !(1 == ~d1_ev~0); 36009#L374-1 assume !(1 == ~z_ev~0); 35750#L380-1 assume true;assume { :end_inline_reset_delta_events } true; 35751#L432 assume true; 36420#L432-1 assume !false;assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 35846#L285 [2024-11-10 23:19:06,859 INFO L747 eck$LassoCheckResult]: Loop: 35846#L285 assume true; 35860#L285-1 assume !false;assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 35861#L268-1 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 35773#L270-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 35774#L276-1 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 35849#L290 assume 0 != eval_~tmp___0~0#1; 35744#L295 assume 0 == ~comp_m1_st~0;havoc eval_#t~nondet5#1;eval_~tmp~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 35745#L299 assume !(0 != eval_~tmp~0#1); 35846#L285 [2024-11-10 23:19:06,859 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-10 23:19:06,860 INFO L85 PathProgramCache]: Analyzing trace with hash -1032578893, now seen corresponding path program 1 times [2024-11-10 23:19:06,860 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-10 23:19:06,860 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [337126684] [2024-11-10 23:19:06,860 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-10 23:19:06,860 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-10 23:19:06,866 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-10 23:19:06,886 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-10 23:19:06,887 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-10 23:19:06,887 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [337126684] [2024-11-10 23:19:06,887 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [337126684] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-10 23:19:06,887 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-10 23:19:06,887 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-10 23:19:06,887 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1193106685] [2024-11-10 23:19:06,887 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-10 23:19:06,887 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-10 23:19:06,888 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-10 23:19:06,888 INFO L85 PathProgramCache]: Analyzing trace with hash 136761786, now seen corresponding path program 8 times [2024-11-10 23:19:06,888 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-10 23:19:06,888 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2080180191] [2024-11-10 23:19:06,888 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-10 23:19:06,888 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-10 23:19:06,891 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-10 23:19:06,892 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-10 23:19:06,893 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-10 23:19:06,894 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-10 23:19:06,913 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-10 23:19:06,914 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-10 23:19:06,914 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-10 23:19:06,914 INFO L87 Difference]: Start difference. First operand 2582 states and 3615 transitions. cyclomatic complexity: 1039 Second operand has 3 states, 3 states have (on average 14.0) internal successors, (42), 3 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-10 23:19:06,948 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-10 23:19:06,948 INFO L93 Difference]: Finished difference Result 3042 states and 4231 transitions. [2024-11-10 23:19:06,949 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3042 states and 4231 transitions. [2024-11-10 23:19:06,961 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1252 [2024-11-10 23:19:06,975 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3042 states to 2894 states and 4014 transitions. [2024-11-10 23:19:06,975 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1349 [2024-11-10 23:19:06,976 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1349 [2024-11-10 23:19:06,976 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2894 states and 4014 transitions. [2024-11-10 23:19:06,977 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-10 23:19:06,977 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2894 states and 4014 transitions. [2024-11-10 23:19:06,979 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2894 states and 4014 transitions. [2024-11-10 23:19:07,008 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2894 to 2894. [2024-11-10 23:19:07,013 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2894 states, 2894 states have (on average 1.387007601935038) internal successors, (4014), 2893 states have internal predecessors, (4014), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-10 23:19:07,019 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2894 states to 2894 states and 4014 transitions. [2024-11-10 23:19:07,019 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2894 states and 4014 transitions. [2024-11-10 23:19:07,019 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-10 23:19:07,020 INFO L425 stractBuchiCegarLoop]: Abstraction has 2894 states and 4014 transitions. [2024-11-10 23:19:07,020 INFO L332 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2024-11-10 23:19:07,020 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2894 states and 4014 transitions. [2024-11-10 23:19:07,028 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1252 [2024-11-10 23:19:07,028 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-10 23:19:07,028 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-10 23:19:07,029 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-10 23:19:07,029 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1] [2024-11-10 23:19:07,029 INFO L745 eck$LassoCheckResult]: Stem: 41610#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0; 41454#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0; 41418#L490 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 41419#L212-1 assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true; 41558#L137-1 assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0; 41559#L143-1 ~b0_req_up~0 := 0; 41533#L145-1 assume true;assume { :end_inline_update_b0 } true; 41534#L219-1 assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true; 41556#L152-1 assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0; 41557#L158-1 ~b1_req_up~0 := 0; 41470#L160-1 assume true;assume { :end_inline_update_b1 } true; 41471#L226-1 assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true; 41486#L167-1 assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0; 41601#L173-1 ~d0_req_up~0 := 0; 41602#L175-1 assume true;assume { :end_inline_update_d0 } true; 41531#L233-1 assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true; 41532#L182-1 assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0; 41596#L188-1 ~d1_req_up~0 := 0; 41582#L190-1 assume true;assume { :end_inline_update_d1 } true; 41583#L240-1 assume !(1 == ~z_req_up~0); 41603#L248-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 41634#L255 assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2; 41629#L261 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 41563#L321-1 assume 0 == ~b0_ev~0;~b0_ev~0 := 1; 41564#L326-1 assume 0 == ~b1_ev~0;~b1_ev~0 := 1; 41455#L331-1 assume 0 == ~d0_ev~0;~d0_ev~0 := 1; 41456#L336-1 assume 0 == ~d1_ev~0;~d1_ev~0 := 1; 41623#L341-1 assume !(0 == ~z_ev~0); 41613#L347-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1; 41614#L107-1 assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1; 41594#L121-1 assume true;is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1; 41595#L130-1 assume true;activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1; 41586#L390-1 assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0; 41587#L396-1 assume true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41649#L354-1 assume 1 == ~b0_ev~0;~b0_ev~0 := 2; 41645#L359-1 assume 1 == ~b1_ev~0;~b1_ev~0 := 2; 41646#L364-1 assume 1 == ~d0_ev~0;~d0_ev~0 := 2; 41641#L369-1 assume 1 == ~d1_ev~0;~d1_ev~0 := 2; 41642#L374-1 assume !(1 == ~z_ev~0); 41380#L380-1 assume true;assume { :end_inline_reset_delta_events } true; 41381#L432 assume true; 42996#L432-1 assume !false;assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1; 42160#L285 [2024-11-10 23:19:07,029 INFO L747 eck$LassoCheckResult]: Loop: 42160#L285 assume true; 42316#L285-1 assume !false;assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1; 42309#L268-1 assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1; 42025#L270-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1; 42241#L276-1 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 42234#L290 assume 0 != eval_~tmp___0~0#1; 42230#L295 assume 0 == ~comp_m1_st~0;havoc eval_#t~nondet5#1;eval_~tmp~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 42046#L299 assume !(0 != eval_~tmp~0#1); 42160#L285 [2024-11-10 23:19:07,029 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-10 23:19:07,030 INFO L85 PathProgramCache]: Analyzing trace with hash -1033502414, now seen corresponding path program 1 times [2024-11-10 23:19:07,030 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-10 23:19:07,030 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [777468176] [2024-11-10 23:19:07,030 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-10 23:19:07,030 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-10 23:19:07,037 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-10 23:19:07,037 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-10 23:19:07,042 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-10 23:19:07,048 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-10 23:19:07,049 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-10 23:19:07,050 INFO L85 PathProgramCache]: Analyzing trace with hash 136761786, now seen corresponding path program 9 times [2024-11-10 23:19:07,050 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-10 23:19:07,050 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [240035498] [2024-11-10 23:19:07,050 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-10 23:19:07,050 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-10 23:19:07,053 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-10 23:19:07,053 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-10 23:19:07,055 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-10 23:19:07,056 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-10 23:19:07,057 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-10 23:19:07,057 INFO L85 PathProgramCache]: Analyzing trace with hash -1441459733, now seen corresponding path program 1 times [2024-11-10 23:19:07,057 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-10 23:19:07,057 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [72493063] [2024-11-10 23:19:07,057 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-10 23:19:07,057 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-10 23:19:07,064 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-10 23:19:07,064 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-10 23:19:07,069 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-10 23:19:07,074 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-10 23:19:07,988 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-10 23:19:07,989 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-10 23:19:08,002 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-10 23:19:08,121 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 10.11 11:19:08 BoogieIcfgContainer [2024-11-10 23:19:08,121 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2024-11-10 23:19:08,122 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2024-11-10 23:19:08,122 INFO L270 PluginConnector]: Initializing Witness Printer... [2024-11-10 23:19:08,122 INFO L274 PluginConnector]: Witness Printer initialized [2024-11-10 23:19:08,123 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 10.11 11:19:00" (3/4) ... [2024-11-10 23:19:08,125 INFO L140 WitnessPrinter]: Generating witness for non-termination counterexample [2024-11-10 23:19:08,191 INFO L149 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2024-11-10 23:19:08,191 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2024-11-10 23:19:08,192 INFO L158 Benchmark]: Toolchain (without parser) took 9014.85ms. Allocated memory was 144.7MB in the beginning and 270.5MB in the end (delta: 125.8MB). Free memory was 90.9MB in the beginning and 185.1MB in the end (delta: -94.2MB). Peak memory consumption was 33.7MB. Max. memory is 16.1GB. [2024-11-10 23:19:08,192 INFO L158 Benchmark]: CDTParser took 0.21ms. Allocated memory is still 144.7MB. Free memory is still 104.5MB. There was no memory consumed. Max. memory is 16.1GB. [2024-11-10 23:19:08,193 INFO L158 Benchmark]: CACSL2BoogieTranslator took 413.02ms. Allocated memory is still 144.7MB. Free memory was 90.5MB in the beginning and 74.2MB in the end (delta: 16.3MB). Peak memory consumption was 14.7MB. Max. memory is 16.1GB. [2024-11-10 23:19:08,193 INFO L158 Benchmark]: Boogie Procedure Inliner took 39.54ms. Allocated memory is still 144.7MB. Free memory was 74.2MB in the beginning and 72.0MB in the end (delta: 2.2MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2024-11-10 23:19:08,193 INFO L158 Benchmark]: Boogie Preprocessor took 42.60ms. Allocated memory is still 144.7MB. Free memory was 72.0MB in the beginning and 69.9MB in the end (delta: 2.2MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2024-11-10 23:19:08,193 INFO L158 Benchmark]: IcfgBuilder took 609.38ms. Allocated memory is still 144.7MB. Free memory was 69.5MB in the beginning and 97.5MB in the end (delta: -27.9MB). Peak memory consumption was 12.3MB. Max. memory is 16.1GB. [2024-11-10 23:19:08,194 INFO L158 Benchmark]: BuchiAutomizer took 7833.14ms. Allocated memory was 144.7MB in the beginning and 270.5MB in the end (delta: 125.8MB). Free memory was 97.5MB in the beginning and 191.4MB in the end (delta: -93.9MB). Peak memory consumption was 31.9MB. Max. memory is 16.1GB. [2024-11-10 23:19:08,194 INFO L158 Benchmark]: Witness Printer took 69.50ms. Allocated memory is still 270.5MB. Free memory was 191.4MB in the beginning and 185.1MB in the end (delta: 6.3MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. [2024-11-10 23:19:08,196 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.21ms. Allocated memory is still 144.7MB. Free memory is still 104.5MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 413.02ms. Allocated memory is still 144.7MB. Free memory was 90.5MB in the beginning and 74.2MB in the end (delta: 16.3MB). Peak memory consumption was 14.7MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 39.54ms. Allocated memory is still 144.7MB. Free memory was 74.2MB in the beginning and 72.0MB in the end (delta: 2.2MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * Boogie Preprocessor took 42.60ms. Allocated memory is still 144.7MB. Free memory was 72.0MB in the beginning and 69.9MB in the end (delta: 2.2MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * IcfgBuilder took 609.38ms. Allocated memory is still 144.7MB. Free memory was 69.5MB in the beginning and 97.5MB in the end (delta: -27.9MB). Peak memory consumption was 12.3MB. Max. memory is 16.1GB. * BuchiAutomizer took 7833.14ms. Allocated memory was 144.7MB in the beginning and 270.5MB in the end (delta: 125.8MB). Free memory was 97.5MB in the beginning and 191.4MB in the end (delta: -93.9MB). Peak memory consumption was 31.9MB. Max. memory is 16.1GB. * Witness Printer took 69.50ms. Allocated memory is still 270.5MB. Free memory was 191.4MB in the beginning and 185.1MB in the end (delta: 6.3MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 21 terminating modules (19 trivial, 2 deterministic, 0 nondeterministic) and one nonterminating remainder module.One deterministic module has affine ranking function (((long long) -1 * z_ev) + 1) and consists of 3 locations. One deterministic module has affine ranking function (((long long) -1 * d1_ev) + 1) and consists of 3 locations. 19 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 2894 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 7.6s and 20 iterations. TraceHistogramMax:1. Analysis of lassos took 5.3s. Construction of modules took 0.3s. Büchi inclusion checks took 1.7s. Highest rank in rank-based complementation 3. Minimization of det autom 8. Minimization of nondet autom 13. Automata minimization 0.4s AutomataMinimizationTime, 21 MinimizatonAttempts, 1358 StatesRemovedByMinimization, 4 NontrivialMinimizations. Non-live state removal took 0.2s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [2, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 948 SdHoareTripleChecker+Valid, 0.4s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 946 mSDsluCounter, 8141 SdHoareTripleChecker+Invalid, 0.3s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 4303 mSDsCounter, 60 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 282 IncrementalHoareTripleChecker+Invalid, 342 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 60 mSolverCounterUnsat, 3838 mSDtfsCounter, 282 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI0 SFLT0 conc0 concLT0 SILN8 SILU0 SILI9 SILT2 lasso0 LassoPreprocessingBenchmarks: Lassos: inital60 mio100 ax100 hnf100 lsp15 ukn100 mio100 lsp100 div100 bol100 ite100 ukn100 eq184 hnf97 smp100 dnf152 smp86 tf109 neg100 sie116 LassoTerminationAnalysisBenchmarks: ConstraintsSatisfiability: unsat Degree: 0 Time: 25ms VariablesStem: 0 VariablesLoop: 0 DisjunctsStem: 1 DisjunctsLoop: 1 SupportingInvariants: 0 MotzkinApplications: 2 LassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 1 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 2 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.1s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 285]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L24] int b0_val ; [L25] int b0_val_t ; [L26] int b0_ev ; [L27] int b0_req_up ; [L28] int b1_val ; [L29] int b1_val_t ; [L30] int b1_ev ; [L31] int b1_req_up ; [L32] int d0_val ; [L33] int d0_val_t ; [L34] int d0_ev ; [L35] int d0_req_up ; [L36] int d1_val ; [L37] int d1_val_t ; [L38] int d1_ev ; [L39] int d1_req_up ; [L40] int z_val ; [L41] int z_val_t ; [L42] int z_ev ; [L43] int z_req_up ; [L44] int comp_m1_st ; [L45] int comp_m1_i ; VAL [b0_ev=0, b0_req_up=0, b0_val=0, b0_val_t=0, b1_ev=0, b1_req_up=0, b1_val=0, b1_val_t=0, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=0, d0_val=0, d0_val_t=0, d1_ev=0, d1_req_up=0, d1_val=0, d1_val_t=0, z_ev=0, z_req_up=0, z_val=0, z_val_t=0] [L494] int __retres1 ; [L498] CALL init_model() [L465] b0_val = 0 [L466] b0_ev = 2 [L467] b0_req_up = 0 [L468] b1_val = 0 [L469] b1_ev = 2 [L470] b1_req_up = 0 [L471] d0_val = 0 [L472] d0_ev = 2 [L473] d0_req_up = 0 [L474] d1_val = 0 [L475] d1_ev = 2 [L476] d1_req_up = 0 [L477] z_val = 0 [L478] z_ev = 2 [L479] z_req_up = 0 [L480] b0_val_t = 1 [L481] b0_req_up = 1 [L482] b1_val_t = 1 [L483] b1_req_up = 1 [L484] d0_val_t = 1 [L485] d0_req_up = 1 [L486] d1_val_t = 1 [L487] d1_req_up = 1 [L488] comp_m1_i = 0 VAL [b0_ev=2, b0_req_up=1, b0_val=0, b0_val_t=1, b1_ev=2, b1_req_up=1, b1_val=0, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=1, d0_val=0, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L498] RET init_model() [L499] CALL start_simulation() [L419] int kernel_st ; [L420] int tmp ; [L424] kernel_st = 0 [L425] CALL update_channels() [L212] COND TRUE (int )b0_req_up == 1 [L214] CALL update_b0() [L137] COND TRUE (int )b0_val != (int )b0_val_t [L138] b0_val = b0_val_t [L139] b0_ev = 0 VAL [b0_ev=0, b0_req_up=1, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=1, b1_val=0, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=1, d0_val=0, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L143] b0_req_up = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=1, b1_val=0, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=1, d0_val=0, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L214] RET update_b0() [L219] COND TRUE (int )b1_req_up == 1 [L221] CALL update_b1() [L152] COND TRUE (int )b1_val != (int )b1_val_t [L153] b1_val = b1_val_t [L154] b1_ev = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=1, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=1, d0_val=0, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L158] b1_req_up = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=1, d0_val=0, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L221] RET update_b1() [L226] COND TRUE (int )d0_req_up == 1 [L228] CALL update_d0() [L167] COND TRUE (int )d0_val != (int )d0_val_t [L168] d0_val = d0_val_t [L169] d0_ev = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=1, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L173] d0_req_up = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L228] RET update_d0() [L233] COND TRUE (int )d1_req_up == 1 [L235] CALL update_d1() [L182] COND TRUE (int )d1_val != (int )d1_val_t [L183] d1_val = d1_val_t [L184] d1_ev = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=1, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L188] d1_req_up = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L235] RET update_d1() [L240] COND FALSE !((int )z_req_up == 1) VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L425] RET update_channels() [L426] CALL init_threads() [L255] COND FALSE !((int )comp_m1_i == 1) [L258] comp_m1_st = 2 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L426] RET init_threads() [L427] CALL fire_delta_events() [L321] COND TRUE (int )b0_ev == 0 [L322] b0_ev = 1 VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L326] COND TRUE (int )b1_ev == 0 [L327] b1_ev = 1 VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L331] COND TRUE (int )d0_ev == 0 [L332] d0_ev = 1 VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L336] COND TRUE (int )d1_ev == 0 [L337] d1_ev = 1 VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L341] COND FALSE !((int )z_ev == 0) VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L427] RET fire_delta_events() [L428] CALL activate_threads() [L384] int tmp ; [L388] CALL, EXPR is_method1_triggered() [L104] int __retres1 ; VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L107] COND TRUE (int )b0_ev == 1 [L108] __retres1 = 1 VAL [__retres1=1, b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L130] return (__retres1); VAL [\result=1, b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L388] RET, EXPR is_method1_triggered() [L388] tmp = is_method1_triggered() [L390] COND TRUE \read(tmp) [L391] comp_m1_st = 0 VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L428] RET activate_threads() [L429] CALL reset_delta_events() [L354] COND TRUE (int )b0_ev == 1 [L355] b0_ev = 2 VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L359] COND TRUE (int )b1_ev == 1 [L360] b1_ev = 2 VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L364] COND TRUE (int )d0_ev == 1 [L365] d0_ev = 2 VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L369] COND TRUE (int )d1_ev == 1 [L370] d1_ev = 2 VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L374] COND FALSE !((int )z_ev == 1) VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L429] RET reset_delta_events() [L432] COND TRUE 1 [L435] kernel_st = 1 [L436] CALL eval() [L280] int tmp ; [L281] int tmp___0 ; VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] Loop: [L285] COND TRUE 1 [L288] CALL, EXPR exists_runnable_thread() [L265] int __retres1 ; [L268] COND TRUE (int )comp_m1_st == 0 [L269] __retres1 = 1 [L276] return (__retres1); [L288] RET, EXPR exists_runnable_thread() [L288] tmp___0 = exists_runnable_thread() [L290] COND TRUE \read(tmp___0) [L295] COND TRUE (int )comp_m1_st == 0 [L297] tmp = __VERIFIER_nondet_int() [L299] COND FALSE !(\read(tmp)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 285]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L24] int b0_val ; [L25] int b0_val_t ; [L26] int b0_ev ; [L27] int b0_req_up ; [L28] int b1_val ; [L29] int b1_val_t ; [L30] int b1_ev ; [L31] int b1_req_up ; [L32] int d0_val ; [L33] int d0_val_t ; [L34] int d0_ev ; [L35] int d0_req_up ; [L36] int d1_val ; [L37] int d1_val_t ; [L38] int d1_ev ; [L39] int d1_req_up ; [L40] int z_val ; [L41] int z_val_t ; [L42] int z_ev ; [L43] int z_req_up ; [L44] int comp_m1_st ; [L45] int comp_m1_i ; VAL [b0_ev=0, b0_req_up=0, b0_val=0, b0_val_t=0, b1_ev=0, b1_req_up=0, b1_val=0, b1_val_t=0, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=0, d0_val=0, d0_val_t=0, d1_ev=0, d1_req_up=0, d1_val=0, d1_val_t=0, z_ev=0, z_req_up=0, z_val=0, z_val_t=0] [L494] int __retres1 ; [L498] CALL init_model() [L465] b0_val = 0 [L466] b0_ev = 2 [L467] b0_req_up = 0 [L468] b1_val = 0 [L469] b1_ev = 2 [L470] b1_req_up = 0 [L471] d0_val = 0 [L472] d0_ev = 2 [L473] d0_req_up = 0 [L474] d1_val = 0 [L475] d1_ev = 2 [L476] d1_req_up = 0 [L477] z_val = 0 [L478] z_ev = 2 [L479] z_req_up = 0 [L480] b0_val_t = 1 [L481] b0_req_up = 1 [L482] b1_val_t = 1 [L483] b1_req_up = 1 [L484] d0_val_t = 1 [L485] d0_req_up = 1 [L486] d1_val_t = 1 [L487] d1_req_up = 1 [L488] comp_m1_i = 0 VAL [b0_ev=2, b0_req_up=1, b0_val=0, b0_val_t=1, b1_ev=2, b1_req_up=1, b1_val=0, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=1, d0_val=0, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L498] RET init_model() [L499] CALL start_simulation() [L419] int kernel_st ; [L420] int tmp ; [L424] kernel_st = 0 [L425] CALL update_channels() [L212] COND TRUE (int )b0_req_up == 1 [L214] CALL update_b0() [L137] COND TRUE (int )b0_val != (int )b0_val_t [L138] b0_val = b0_val_t [L139] b0_ev = 0 VAL [b0_ev=0, b0_req_up=1, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=1, b1_val=0, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=1, d0_val=0, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L143] b0_req_up = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=1, b1_val=0, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=1, d0_val=0, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L214] RET update_b0() [L219] COND TRUE (int )b1_req_up == 1 [L221] CALL update_b1() [L152] COND TRUE (int )b1_val != (int )b1_val_t [L153] b1_val = b1_val_t [L154] b1_ev = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=1, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=1, d0_val=0, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L158] b1_req_up = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=1, d0_val=0, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L221] RET update_b1() [L226] COND TRUE (int )d0_req_up == 1 [L228] CALL update_d0() [L167] COND TRUE (int )d0_val != (int )d0_val_t [L168] d0_val = d0_val_t [L169] d0_ev = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=1, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L173] d0_req_up = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L228] RET update_d0() [L233] COND TRUE (int )d1_req_up == 1 [L235] CALL update_d1() [L182] COND TRUE (int )d1_val != (int )d1_val_t [L183] d1_val = d1_val_t [L184] d1_ev = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=1, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L188] d1_req_up = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L235] RET update_d1() [L240] COND FALSE !((int )z_req_up == 1) VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L425] RET update_channels() [L426] CALL init_threads() [L255] COND FALSE !((int )comp_m1_i == 1) [L258] comp_m1_st = 2 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L426] RET init_threads() [L427] CALL fire_delta_events() [L321] COND TRUE (int )b0_ev == 0 [L322] b0_ev = 1 VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L326] COND TRUE (int )b1_ev == 0 [L327] b1_ev = 1 VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L331] COND TRUE (int )d0_ev == 0 [L332] d0_ev = 1 VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L336] COND TRUE (int )d1_ev == 0 [L337] d1_ev = 1 VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L341] COND FALSE !((int )z_ev == 0) VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L427] RET fire_delta_events() [L428] CALL activate_threads() [L384] int tmp ; [L388] CALL, EXPR is_method1_triggered() [L104] int __retres1 ; VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L107] COND TRUE (int )b0_ev == 1 [L108] __retres1 = 1 VAL [__retres1=1, b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L130] return (__retres1); VAL [\result=1, b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L388] RET, EXPR is_method1_triggered() [L388] tmp = is_method1_triggered() [L390] COND TRUE \read(tmp) [L391] comp_m1_st = 0 VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L428] RET activate_threads() [L429] CALL reset_delta_events() [L354] COND TRUE (int )b0_ev == 1 [L355] b0_ev = 2 VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L359] COND TRUE (int )b1_ev == 1 [L360] b1_ev = 2 VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L364] COND TRUE (int )d0_ev == 1 [L365] d0_ev = 2 VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L369] COND TRUE (int )d1_ev == 1 [L370] d1_ev = 2 VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L374] COND FALSE !((int )z_ev == 1) VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L429] RET reset_delta_events() [L432] COND TRUE 1 [L435] kernel_st = 1 [L436] CALL eval() [L280] int tmp ; [L281] int tmp___0 ; VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] Loop: [L285] COND TRUE 1 [L288] CALL, EXPR exists_runnable_thread() [L265] int __retres1 ; [L268] COND TRUE (int )comp_m1_st == 0 [L269] __retres1 = 1 [L276] return (__retres1); [L288] RET, EXPR exists_runnable_thread() [L288] tmp___0 = exists_runnable_thread() [L290] COND TRUE \read(tmp___0) [L295] COND TRUE (int )comp_m1_st == 0 [L297] tmp = __VERIFIER_nondet_int() [L299] COND FALSE !(\read(tmp)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2024-11-10 23:19:08,230 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)